update

src/docs/asciidoc/BPI-CM4-datasheet.adoc-bk

@@ -0,0 +1,647 @@
+= Banana Pi Compute Module 4
+:outlinelevels: 3
+Hulk Wang
+:example-caption!:
+ifndef::imagesdir[:imagesdir: images]
+
+<<<
+toc::[]
+
+== Chapter 1. Introduction
+
+=== 1.1 Introduction
+
+image::BPI-CM4.jpg[scaledwidth=75%, title="The BPI-CM4"]
+
+The Banana Pi Compute Module 4(CM4)is a System on Module(SoM) containing processor,DRAM, eMMC Flash and supporting power circuitry. These modules allow a designer touse the Banana Pi hardware and software stack in their own custom systems and formfactors. And, These modules offer additional IO interfaces beyond what is provided on Banana Pi boards, providing designers with more options.
+
+The design of the CM4 is loosely based on the Amlogic A311D, Quad core ARM Cortex-A73 and dual core ARM Cortex-A53 CPU , ARM G52MP4(6EE) GPU,NPU for AI at 5.0 TOPS, support Camera and MIPI-CSI interface ,HDMI output,2 Gigabit port . 4G RAM and 16 GB eMMC flash.
+
+for A311D chip PIN limited . just support 1 HDMI ,1 CSI and 1 DSI , Raspberry Pi support 2 HDMI ,2 CSI and 2 DSI , Other is Pin2Pin . you can use Raspberry Pi CM4 baseboard.
+
+NOTE: for A311D chip PIN limited . just support 1 HDMI ,1 CSI and 1 DSI , Raspberry Pi support 2 HDMI ,2 CSI and 2 DSI , Other is Pin2Pin . you can use Raspberry Pi CM4 baseboard.
+
+<<<
+
+=== 1.2 Key Feature
+
+Key feature of the BPI-CM4 are as follows:
+
+* Amlogic A311D  Quad core ARM Cortex-A73 and dual core ARM Cortex-A53,ARM G52 MP4(6EE) GPU
+* NPU for AI  Next generation, deep-neural-network applications, at 5.0 TOPS 
+* OpenGL ES 3.2, Vulkan 1.1 and OpenCL 2.0 support
+* 4GB LPDDR4 RAM 
+* 16GB eMMC flash (Max 128G) 
+* MIPI DSI :
+** 1x4-Lane MIPI DSI Display Interface 
+* MIPI CSI :
+** 1x4-Lane MIPI CSI Camera Interface
+* PCIe Interface:
+** 1xPCIe 1-Lane Host,Gen 2(5Gbps)
+* HDMI Interface:
+** 1xHDMI 2.1 Output Interface(up tp 4Kx2K@60)
+* Gigabit Ethernet PHY supporting
+* GPIOs:
+** PCM
+** IIC
+** IIS
+** SPI
+** UART
+** PWM
+** ...
+* Single +5V PSU Input
+* Support Android and Linux system
+* Size: 55x40mm
+
+
+== Chapter 2. Interfaces
+
+=== 2.1 Wireless
+
+The BPI-CM4 supports an onboard wireless module based on Realtek RTL8822CS,supports both
+
+* 2.4GHz & 5GHz IEEE 802.11 a/b/g/n/ac 2x2 MIMO wireless
+* Bluetooth 5.0 BR/EDR/LE
+
+These wireless interfaces can be individually enabled or disabled as required via CPU GPIO. In the case of many application environments, a service engineer can enable wireless operation and then disable it when done.
+
+The CPU can also turn on the wireless by itself for data communication, and turn ff the wireless after completion to reduce power consumption.
+
+The BPI-CM4 has two standard IPEX-1G connector on the module, If you want to use 2x2 MIMO, need to connect 2x 2.4G&5G antenna.
+
+Banana Pi Ltd has an antenna kit which is certified to be used with the BPI-CM4. If a different antenna is used then separate certification will be required.
+
+=== 2.2 Ethernet
+
+The BPI-CM4 has an onboard Gigabit Ethernet PHY - the https://www.realtek.com/en/products/connected-media-ics/item/rtl8211f-i-cg[REALTEK RTL8211F] - some of the major features of this PHY include;
+
+* IEEE 802.3az-2010
+* Built-in Wake-on-LAN
+* Crossover Detection & Auto-Correction
+
+A standard RJ45 connector is necessary to provid an Ethernet connection to the BPI-CM4.Can be see in link:#EthSch[Figure 2]
+
+[#EthSch]
+image::EthernetSch.jpg[title="Ethernet Schematic", alt=EthSch]
+
+The differential Ethernet signals should be routed as 100Ω differential pairs, with suitable clearances. Length matching between pairs should be better than 50mm, so in the typical case no length matching is required. However the signals within a pair need to be length matched, ideally to better than 0.15mm.
+
+The PHY also supports up to 2 LEDs to give user status feedback, these are low active. These LEDs can have a range of functions, and you should consult your OS driver to see which functions are supported by your driver.
+
+=== 2.3 PCIe(Gen2 x1)
+
+The BPI-CM4 has an internal PCIe2.0 x1 host controller. Connecting a PCIe device follows the standard PCIe convention.The CM4 has onboard AC coupling capacitors for *PCIe_CLK* and *PCIe_TX* signals.However the *PCIe_RX* signals need external coupling capacitors close to the driving source (the device *TX*), if you are using an external PCIe/NVMe cards these capacitors will be onboard. The PCIe conversion is that if you are wiring directly to an IC then the TX and RX pairs need to be swapped (TX->RX, RX->TX). If you are wiring to a connector then this is typically labelled from the host post of view and so TX RX swaps aren’t required. Additionally the *PCIECK_REQN* must be connected to ensure the CM4 produces a clock signal, and the *PERST0_N* should also be connected to ensure the device is correctly reset when required. The differential PCIe signals should be routed as 100Ω differential pairs, with suitable clearances. There is no need to match the lengths between pairs, only the signals within a Pair need to be length matched ideally to better than 0.1mm
+
+TIP: 5.10 kernel and .......
+
+=== 2.4 USB 2.0(HS)/3.0(SS)
+
+The USB 2.0 interface supports up to 480MBps signalling. The differential pair should be routed as a 90Ω differential pair. The P N signals should ideally be matched to better than 0.15mm.
+
+.USB 3.0 or PCIe 2.0 x1
+IMPORTANT: *USB 3.0* multiplexed with *PCIe 2.0 x1*. *USB30_RX_P/N* multiplexed with *PCIe_RX_P/N* and *USB30_TX_P/N* multiplexed with *PCIe_TX_P/N*.
+
+BPI-CM4 has two full-speed USB channels, one of which (USB_A) can be USB2.0 x1+ PCIe2.0 x1 or USB3.0 x1, or can use FE1.1s chip (USB 2.0 HUB chip) or VL807 (USB 3.0 HUB chip) Expanded to four-way USB.The other one (USB_B) interface also has OTG(On-The-Go) function at the same time.
+
+=== 2.5 GPIO
+
+BPI-CM4 has 17 pins available for general purpose I/O (GPIO),corresponding to the first half of the standard 40 pins of other BananaPi development boards.These pins have access to internal peripherals;PCM, IIC, UART and PWM. https://drive.google.com/file/d/1IXXok1P2OLiW3p8tavkbfEPTGTrM3b-R/view?usp=sharing[BPI-CM4 Sch  ^] describes these features in detail, and the multiplexing options available. The drive strength and slew rate should ideally be set as low as possible to reduce any EMC issues.GPIOX_17 and GPIOX_18 have 2.2K pull up resistors.
+
+By default, GPIO bank is powered by 3V3, but GPIOX_x GPIOs can be changed to powered by 1.8V.
+
+NOTE: *GPIOX_x* Power Bank depending on the selected WiFi module, PCIe WiFi or RTL WiFi (default) is powered by 3.3V, and AMPAK 6275s WiFi is powered by 1.8V.
+
+image::GPIO.jpg[title="GPIO", alt=GPIO]
+
+==== 2.5.1 Alternative Function Assignments
+
+.GPIO Alternative Function Assignments
+[.autowidth.stretch, cols="^2,3,2,2,6,5"]
+|===
+|Num|GPIOx_x |PD/PU |ALT0 |ALT1 |ALT2
+
+|3 |GPIOX_17 |PU |GPIO |I2C_EE_M2_SDA |BT_EN
+|5 |GPIOX_18 |PU |GPIO |I2C_EE_M2_SCL |BT_WAKE_HOST
+|7 |GPIOH_5 |PU |GPIO |SPDIF_IN |
+|8 |GPIOX_6 |PU |GPIO |UART_B_TX |WIFI_PWREN
+|10 |GPIOx_7 |PU |GPIO |UART_B_RX |WIFI_WAKE_HOST
+|11 |GPIOAO_10 |PD |GPIO | | 
+|12 |GPIOA_1 |PU |GPIO |I2SB_SCLK | 
+|13 |GPIOH_4 |PD |GPIO |SPDIF_OUT |
+|15 |GPIOAO_5 |PU |GPIO |IR_IN |
+|16 |GPIOA_0 |PU |GPIO |I2S_MCLK |
+|18 |GPIOA_2 |PD |GPIO |I2SB_LRCLK |
+|19 |GPIOX_8 |PU |GPIO |SPI_A_MOSI |BTPCM_DIN
+|21 |GPIOX_9 |PU |GPIO |SPI_A_MISO |BTPCM_DOUT
+|22 |GPIOA-7 |PU |GPIO |I2SC_DOUT_DIN_3 |
+|23 |GPIOX_11 |PU |GPIO |SPI_A_CLK |BTPCM_CLK
+|24 |GPIOX_10 |PU |GPIO |SPI_A_SS0 |BTPCM_SYNC
+|26 |GPIOA_3 |PU |GPIO |I2SB_DOUT_DIN_0 |
+|===
+
+=== 2.6 HDMI
+
+The BPI-CM4 supports one HDMI 2.1 interface, it capable of driving 4Kx2K 60fps output.
+
+HDMI signals should be routed as 100Ω differential pairs, each signal within a pair should ideally be matched to better than 0.15mm.Pairs don’t typically need any extra matching as they only have to be matched to 25mm.
+
+CEC, Dynamic HDR and HDCP 2.2 supported. CEC internal 27K pullup resistor and *HDMI_SDA*/*HDMI_SCL* internal 27K pullup resistor is included in the BPI-CM4.
+
+The BPI-CM4 need extra ESD protection maybe required.
+
+=== 2.7 CSI(MIPI Serial Camera)
+
+The BPI-CM4 supports one camera ports(4 lanes); CSI signals should be routed as 100Ω differential pairs, each signal within a pair should ideally be matched to better than 0.15mm.
+
+The documentation around the CSI interface can be found on the https://wiki.banana-pi.org/BPI-CM4_Computer_module_and_development_Kit[BananaPi Wiki] website while Linux kernel drivers can be found on https://github.com/BPI-SINOVOIP/BPI-M2S-bsp[Github].
+
+NOTE: Camera sensors supported by the official BananaPi firmware are;ShenZhenShi HongJia OS08A10 V11(sensor: OS08A20). no security device is required on Compute Module devices to use these camera sensors.
+
+=== 2.8 DSI(MIPI Serial Display)
+
+The BPI-CM4 supports one display ports(4 lanes); supports a maximum of data rate per lane of 1Gbit/s.
+
+The DSI interface only supported by offical BananaPi firmware are supported DSI Displays, more infomation can see https://wiki.banana-pi.org/BPI-CM4_Computer_module_and_development_Kit[BananaPi Wiki] website.DSI signals should be routed as 100Ω differential pairs, each signal within a pair should ideally be matched to better than 0.15mm.
+
+NOTE: BananaPi firmware only supports officially recommended DSI displays, but add and compile your own driver.
+
+=== 2.9 IIC(GPIO Pin3&Pin5)
+
+This IIC bus is not shared with CSI or DSI and can be used arbitrarily.
+
+=== 2.10 IIC(CAM0_SCK/SDA)
+
+This IIC bus(GPIOH_7/GPIOH_6) is used by default for MIPI CSI(Camera sensor), If you don't use, it can also be used for general purpose I/O or to connect other IIC devices.
+
+=== 2.11 IIC(TP_SCK/SDA)
+
+This IIC bus(GPIOA_15/GPIOA_14) is used by default for MIPI DSI Touch Panel(capacitive touch panel), If you don't use, it can also be used for general purpose I/O or to connect other IIC devices.
+
+NOTE: All IIC buses have 2K2 pull-up resistors on BPI-CM4
+
+=== 2.12 SDIO/eMMC()
+
+The BPI-CM4 supported 16GB eMMC flash (option up to 128GB). The *TF_VDD_EN* signal is used to enable an external power switch to turn on power to the TF_Card. If booting from TF_Card is required then a pullup resistor must also be fitted to default the power to be on. 
+
+image::TF_Card.jpg[title="TF Card", alt=TF_CARD]
+
+=== 2.13 Analog(SARADC_CH2/CH3)
+
+These are the two ADC pins straight out of the CPU.No onboard filtering, 100K pull-up resistors on BPI-CM4.
+
+NOTE: If you need to use these two ADC pins, you need to consider adding filtering, the recommended value is 1000pF ~ 0.1uF
+
+=== 2.14 *CPU_RST*
+
+Pulling this pin low places BPI-CM4 in reset. Removing the pull-down state allows the BPI-CM4 to reset and run again.
+
+TIP: To reset BPI-CM4, the *CPU_RST* pin needs to be pulled low for at least 0ms.T~CPU_RST_L~>0ms.
+
+=== 2.15 *SYS_LED*
+
+This pin is designed to drive an LED to show the BPI-CM4 operating status. If an error occurs during startup, it will blink with the *SYS_LED2* beyond expectations to help the user easily determine the status.
+
+=== 2.16 *SYS_LED2*
+
+This pin is designed to drive an LED to show the BPI-CM4 operating status. If an error occurs during startup, it will blink with the *SYS_LED2* beyond expectations to help the user easily determine the status.
+
+<<<
+
+
+== Chapter 3. Electrical and Mechanical
+
+=== 3.1 Mechanical
+
+The BPI-CM4 is a compact 40 × 55mm module. The Module is 4.1mm deep, but usually the height after connection is 4.4mm.
+
+TIP: The height of 4.4mm after connection is the minimum height between the connector and the fixing stud recommended by bpi. If other connectors and fixing studs of the corresponding height are used, the height needs to be actually measured.
+
+. 4 × M3 Mounting holes (inset about 4mm from module edge)
+. PCB thickness 1.2mm ± 10%
+. https://drive.google.com/file/d/1SRAY_RDxKhw819uyo9H13zNN2wlG6LDq/view?usp=sharing[Amlogic A311D] SoC height including solder balls 1.0 ± 0.11mm
+. Stacking height either:
+.. 1.5mm with mating connector (clearance under CM4 0mm) : DF40C-100DS-0.4v
+.. 3.0mm with mating connector (clearance under CM4 1.5mm): DF40HC(3.0)-100DS-0.4v
+
+If the wireless antenna is used  it must be orientated towards the edge of the plastic enclosure and any close by metal must have cut outs or the wireless performance will be degraded.It is recommended to fix the antenna outside the case.
+
+image::Mechanical.jpg[title="Mechanical", alt=Mechanical, width=75%]
+
+NOTE: The location and arrangement of components on the Compute Module may change slightly over time due to revisions for cost and manufacturing considerations; however the maximum component heights and PCB thickness will be kept as specified.
+
+=== 3.2 Thermal
+
+The BPI-CM4 has less passive cooling due to its smaller size, so it may run hotter.In order to ensure the life of BPI-CM4, the core temperature of the main control chip(Amlogic A311D) should be kept below 85 degrees Celsius as much as possible.If the core temperature is found to be higher than 85 degrees Celsius, you can reduce the clock frequency or add additional active and passive cooling methods.
+
+It is important that thermal solution chosen keeps the ambient temperature for the other silicon devices on the CM4 within the operating temperature range.
+
+Operating temperature range: -20°C - +85°C Non-condensing. 
+
+=== 3.3  Electrical Specification
+
+WARNING: Stresses above those listed in Table 3 may cause permanent damage to the device. This is a stress rating only; functional operation of the device under these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
+
+.Absolute maximum ratings
+[.autowidth.stretch, cols="2,4,2,2,2"]
+|===
+|Symbol |Parameter |Min. |Max. |Unit 
+
+|V~IN~ |+5V_Input |-0.5 |6 |V
+|V~GPIO_ref~ |GPIO Voltage |-0.5 |3.6 |V
+|V~GPIO~ |GPIO INPUT Voltage |-0.5 |V~GPIO_ref~+0.5 |V
+|===
+
+==== DC Electrical Characteristics
+
+.Normal GPIO Specifications (For DIO)
+[.autowidth.stretch,cols="2,4,2,2,2,1"]
+|===
+|Symbol |Parameter |Min. |Typ. |Max. |Unit
+
+|V~IH(gpio)~ |High-level Input Voltage |*IOVREF*/2+0.3 | |VDDIO+0.3 |V
+|V~IL(gpio)~ |Low-level Input Voltage |-0.3 | |*IOVREF*/2-0.3 |V
+|R~PU/PD~ |Built-in pull Up/Down resistor | |60K | |ohm
+|IoH/IoL |GPIO driving capability |4^1)^ | |6^2)^ |mA
+|VOH |Output high level with 4 mA loading |VDDIO-0.5 | | |V
+|VOL |Output low level with 4 mA loading | | |0.4 |V
+|===
+
+NOTE: Minimal driving capability applies when VDDIO LV 1.71V, or VDDIO HV 3.0V, VOL<0.4V
+Maximal driving capability only applies to applications such as driving LED when VOL<0.6V.
+
+.Open Drain GPIO Specifications (For DIO_OD)
+[.autowidth.stretch,cols="2,4,2,2,2,1"]
+|===
+|Symbol |Parameter |Min. |Typ. |Max. |Unit
+
+|V~IH(OD5V)~ |High-level Input Voltage |2.2 | |5.5 |V
+|V~IL(OD5V)~ |Low-level Input Voltage |-0.3 | |0.8 |V
+|V~IH(OD3.3V)~ |High-level Input Voltage |2.2 | |3.6 |V
+|V~IL(OD3.3V)~ |Low-level Input Voltage |-0.3 | |0.8 |V
+|R~PU/PD~ |No built-in pull up/down resistor on OD IO |- |- |- |ohm
+|Io |OD IO driving low capability |4^1)^ | |6^2)^ |mA
+|VOL |Output low level with mini Io loading | | |0.4 |V
+|===
+
+NOTE: Minimal driving capability applies when VDDIO LV 1.71V, or VDDIO HV 3.0V, VOL<0.4V
+Maximal driving capability only applies to applications such as driving LED when VOL<0.6V.
+
+== Chapter 4. Pin Out
+
+=== 4.1 Pin out define
+
+.Pin out define of BPI-CM4
+[cols="^1,3,9"]
+|===
+|Pin Num |Signal |Description
+
+| 1   | GND                     | Ground (0V)
+| 2   | GND                     | Ground (0V)
+| 3   | NAT0_MDI3p              | Ethernet MDI 3 Positive (connect to Transformer or RJ45 Connector)
+| 4   | NAT0_MDI1p              | Ethernet MDI 1 Positive (connect to Transformer or RJ45 Connector)
+| 5   | NAT0_MDI3n              | Ethernet MDI 3 Negative (connect to Transformer or RJ45 Connector)
+| 6   | NAT0_MDI1n              | Ethernet MDI 1 Negative (connect to Transformer or RJ45 Connector)
+| 7   | GND                     | Ground (0V)
+| 8   | GND                     | Ground (0V)
+| 9   | NAT0_MDI2n              | Ethernet MDI 2 Negative (connect to Transformer or RJ45 Connector)
+| 10  | NAT0_MDI0n              | Ethernet MDI 0 Negative (connect to Transformer or RJ45 Connector)
+| 11  | NAT0_MDI2p              | Ethernet MDI 2 Positive (connect to Transformer or RJ45 Connector)
+| 12  | NAT0_MDI0p              | Ethernet MDI 0 Positive (connect to Transformer or RJ45 Connector)
+| 13  | GND                     | Ground (0V)
+| 14  | GND                     | Ground (0V)
+| 15  | Ethernet_LED2/1G_Active | Low Active Ethernet Activity indicator (3.3V signal) Typically a Yellow LED is connected to this pin.Represents the negotiated rate
+| 16  | LINUX_Debug_RX          | Debug Uart RX.Usually under Linux system
+| 17  | Ethernet_LED1/Link      | Low Active Ethernet Activity indicator (3.3V signal) Typically a Green LED is connected to this pin.Represents the link state
+| 18  | LINUX_Debug_TX          | Debug Uart TX.Usually under Linux system
+| 19  | Ethernet_0_LED0/CFG_EXT | Reserved.From PHY chip    
+| 20  | NC                      | No connection pin.
+| 21  | SYS_LED2                | Low Active Pi Activity LED.Max 3.3V tolerant (VOL<0.4V). Default drives the Green LED
+| 22  | GND                     | Ground (0V)
+| 23  | GND                     | Ground (0V)
+| 24  | GPIOA_0                 | General purpose input/output bank A signal 0.Typically a 3.3V signal
+| 25  | GPIOA_3                 | General purpose input/output bank A signal 3.Typically a 3.3V signal
+| 26  | GPIOA_2                 | General purpose input/output bank A signal 2.Typically a 3.3V signal
+| 27  | GPIOA_4                 | General purpose input/output bank A signal 4.Typically a 3.3V signal
+| 28  | GPIOA_7                 | General purpose input/output bank A signal 7.Typically a 3.3V signal
+| 29  | GPIOAO_11               | General purpose input/output bank AO signal 11.Typically a 3.3V signal
+| 30  | GPIOAO_10               | General purpose input/output bank AO signal 10.Typically a 3.3V signal
+| 31  | GPIOH_5                 | General purpose input/output bank H signal 5.Typically a 3.3V signal
+| 32  | GND                     | Ground (0V)
+| 33  | GND                     | Ground (0V)
+| 34  | GPIOH_4                 | General purpose input/output bank H signal 4.Typically a 3.3V signal
+| 35  | GPIOA_15                | General purpose input/output bank A signal 15.Typically a 3.3V signal
+| 36  | GPIOA_14                | General purpose input/output bank A signal 14.Typically a 3.3V signal
+| 37  | GPIOAO_5                | General purpose input/output bank AO signal 5.Typically a 3.3V signal
+| 38  | GPIOX_11                | General purpose input/output bank X signal 11.Typically a 3.3V signal
+| 39  | GPIOX_10                | General purpose input/output bank X signal 10.Typically a 3.3V signal
+| 40  | GPIOX_9                 | General purpose input/output bank X signal 9.Typically a 3.3V signal
+| 41  | GPIOA_11                | General purpose input/output bank A signal 11.Typically a 3.3V signal
+| 42  | GND                     | Ground (0V)
+| 43  | GND                     | Ground (0V)
+| 44  | GPIOX_8                 | General purpose input/output bank X signal 8.Typically a 3.3V signal
+| 45  | GPIOA_12                | General purpose input/output bank A signal 12.Typically a 3.3V signal
+| 46  | GPIOA_5                 | General purpose input/output bank A signal 5.Typically a 3.3V signal
+| 47  | GPIOA_13                | General purpose input/output bank A signal 13.Typically a 3.3V signal
+| 48  | GPIOA_6                 | General purpose input/output bank A signal 6.Typically a 3.3V signal
+| 49  | GPIOA_1                 | General purpose input/output bank A signal 1.Typically a 3.3V signal
+| 50  | GPIOA_9                 | General purpose input/output bank A signal 9.Typically a 3.3V signal
+| 51  | GPIOX_7                 | General purpose input/output bank X signal 7.Typically a 3.3V signal
+| 52  | GND                     | Ground (0V)
+| 53  | GND                     | Ground (0V)
+| 54  | GPIOA_10                | General purpose input/output bank A signal 10.Typically a 3.3V signal.
+| 55  | GPIOX_6                 | General purpose input/output bank X signal 6.Typically a 3.3V signal.
+| 56  | GPIOX_18                | General purpose input/output bank X signal 18.Typically a 3.3V signal.
+| 57  | SD_CLK_B                | SDCARD Clock signal.
+| 58  | GPIOX_17                | General purpose input/output bank X signal 17.Typically a 3.3V signal.
+| 59  | GND                     | Ground (0V)
+| 60  | GND                     | Ground (0V)
+| 61  | SD_D3_B                 | SDCARD Data3 signal.
+| 62  | SD_CMD_B                | SDCARD Command signal.
+| 63  | SD_D0_B                 | SDCARD Data0 signal.
+| 64  | NC                      | No connection pin.
+| 65  | GND                     | Ground (0V)
+| 66  | GND                     | Ground (0V)
+| 67  | SD_D1_B                 | SDCARD Data1 signal.
+| 68  | NC                      | No connection pin.
+| 69  | SD_D2_B                 | SDCARD Data2 signal.
+| 70  | NC                      | No connection pin.
+| 71  | GND                     | Ground (0V)
+| 72  | NC                      | No connection pin.
+| 73  | NC                      | No connection pin.
+| 74  | GND                     | Ground (0V)
+| 75  | TF_VDD_EN               | Output to Power switch for the SDCARD. The CM4 sets this pin High (3.3V) to signal that Power to the SDCARD should be turned on. If booting from the SDCARD is required then a pullup should also be fitted so the power defaults to on.
+| 76  | CARD_DET                | SDCARD detection signal.
+| 77  | +5V_Input               | 4.75V-5.25V Main power input
+| 78  | NC                      | No connection pin.
+| 79  | +5V_Input               | 4.75V-5.25V Main power input.
+| 80  | GPIOH_7                 | General purpose input/output bank H signal 7.Typically a 3.3V signal.
+| 81  | +5V_Input               | 4.75V-5.25V Main power input.
+| 82  | GPIOH_6                 | General purpose input/output bank H signal 6.Typically a 3.3V signal.
+| 83  | +5V_Input               | 4.75V-5.25V Main power input..
+| 84  | CM4_3V3_OUTPUT          | 3.3V +/-2.5% Power Output.Usually not used as an extended power supply it can be used as a reference potential.
+| 85  | +5V_Input               | 4.75V-5.25V Main power input.
+| 86  | CM4_3V3_OUTPUT          | 3.3V +/-2.5% Power Output.Usually not used as an extended power supply it can be used as a reference potential.
+| 87  | +5V_Input               | 4.75V-5.25V Main power input.
+| 88  | CM4_1V8_OUTPUT          | 1.8V +/-2.5% Power Output.Usually not used as an extended power supply it can be used as a reference potential.
+| 89  | NC                      | No connection pin.
+| 90  | CM4_1V8_OUTPUT          | 1.8V +/-2.5% Power Output.Usually not used as an extended power supply it can be used as a reference potential.
+| 91  | NC                      | No connection pin.
+| 92  | CPU_RST                 | System reset input.Pull low to reset the system.
+| 93  | NC                      | No connection pin.
+| 94  | SARADC_CH3              | ADC channel 3 input.In the official firmware this pin is used as Hardware ID.
+| 95  | SYS_LED                 | Low active Output to drive Power On LED.
+| 96  | ADC_KEY                 | ADC channel 2 input.In the official firmware this pin is used as AD_KEY.
+| 97  | NC                      | No connection pin.
+| 98  | GND                     | Ground (0V)
+| 99  | NC                      | No connection pin.
+| 100 | GPIOH_8                 | General purpose input/output bank H signal 8.Typically a 3.3V signal.
+| 101 | USBOTG_B_ID             | USB OTG mini-receptacle identifier.
+| 102 | PCIECK_REQN             | request-acknowledge communication between PCIe devices.
+| 103 | USBOTG_B_DM             | USB 2.0 Port B negative data signal(OTG).
+| 104 | USB_A_DP                | USB 2.0 Port A positive data signal(HOST only).
+| 105 | USBOTG_B_DP             | USB 2.0 Port B positive data signal(OTG).
+| 106 | USB_A_DM                | USB 2.0 Port A negative data signal(HOST only).
+| 107 | GND                     | Ground (0V)
+| 108 | GND                     | Ground (0V)
+| 109 | PERST0_N                | Used to control the reset operation of PCIe devices.
+| 110 | PCIE_CLKP               | PCIE reference clock positive signal.
+| 111 | NC                      | No connection pin.
+| 112 | PCIE_CLKN               | PCIE reference clock negative signal.
+| 113 | GND                     | Ground (0V)
+| 114 | GND                     | Ground (0V)
+| 115 | MIPI_CSI_D0N            | MIPI CSI data 0 negative input
+| 116 | PCIE_SOC_RXP            | PCIE or USB3.0 input positive signal
+| 117 | MIPI_CSI_D0P            | MIPI CSI data 0 positive input
+| 118 | PCIE_SOC_RXN            | PCIE or USB3.0 input negative signal
+| 119 | GND                     | Ground (0V)
+| 120 | GND                     | Ground (0V)
+| 121 | MIPI_CSI_D1N            | MIPI CSI data 1 negative input
+| 122 | PCIE_TX0_P              | PCIE or USB3.0 output positive signal
+| 123 | MIPI_CSI_D1P            | MIPI CSI data 1 positive input
+| 124 | PCIE_TX0_N              | PCIE or USB3.0 input negative signal
+| 125 | GND                     | Ground (0V)
+| 126 | GND                     | Ground (0V)
+| 127 | MIPI_CSI_CLKAN          | MIPI CSI CLK negative input for channel A
+| 128 | NC                      | No connection pin.
+| 129 | MIPI_CSI_CLKAP          | MIPI CSI CLK positive input for channel A
+| 130 | NC                      | No connection pin.
+| 131 | GND                     | Ground (0V)
+| 132 | GND                     | Ground (0V)
+| 133 | MIPI_CSI_D2N            | MIPI CSI data 2 negative input
+| 134 | NC                      | No connection pin.
+| 135 | MIPI_CSI_D2P            | MIPI CSI data 2 positive input
+| 136 | NC                      | No connection pin.
+| 137 | GND                     | Ground (0V)
+| 138 | GND                     | Ground (0V)
+| 139 | MIPI_CSI_D3N            | MIPI CSI data 3 negative input
+| 140 | MIPI_CSI_CLKBN          | MIPI CSI CLK negative input for channel B
+| 141 | MIPI_CSI_D3P            | MIPI CSI data 3 positive input
+| 142 | MIPI_CSI_CLKBP          | MIPI CSI CLK negative input for channel B
+| 143 | NC                      | No connection pin.
+| 144 | GND                     | Ground (0V)
+| 145 | NC                      | No connection pin.
+| 146 | NC                      | No connection pin.
+| 147 | NC                      | No connection pin.
+| 148 | NC                      | No connection pin.
+| 149 | NC                      | No connection pin.
+| 150 | GND                     | Ground (0V)
+| 151 | HDMI_TXCEC              | HDMI CEC signal.
+| 152 | NC                      | No connection pin.
+| 153 | HDMI_HPDC               | HDMI Hot Plugin Detection
+| 154 | NC                      | No connection pin.
+| 155 | GND                     | Ground (0V)
+| 156 | GND                     | Ground (0V)
+| 157 | NC                      | No connection pin.
+| 158 | NC                      | No connection pin.
+| 159 | NC                      | No connection pin.
+| 160 | NC                      | No connection pin.
+| 161 | GND                     | Ground (0V)
+| 162 | GND                     | Ground (0V)
+| 163 | NC                      | No connection pin.
+| 164 | NC                      | No connection pin.
+| 165 | NC                      | No connection pin.
+| 166 | NC                      | No connection pin.
+| 167 | GND                     | Ground (0V)
+| 168 | GND                     | Ground (0V)
+| 169 | Reserved                | Reserved.Audio DAC line-out right channel positive signal
+| 170 | HDMI_TX2P               | HDMI TMDS data 2 positive output
+| 171 | Reserved                | Reserved.Audio DAC line-out left channel positive signal
+| 172 | HDMI_TX2N               | HDMI TMDS data 2 negative output
+| 173 | GND                     | Ground (0V)
+| 174 | GND                     | Ground (0V)
+| 175 | MIPI_D0_N               | MIPI DSI data 0 negative output or Bidirectional in LP mode.
+| 176 | HDMI_TX1P               | HDMI TMDS data 1 positive output.
+| 177 | MIPI_D0_P               | MIPI DSI data 0 positive output or Bidirectional in LP mode.
+| 178 | HDMI_TX1N               | HDMI TMDS data 1 negative output.
+| 179 | GND                     | Ground (0V)
+| 180 | GND                     | Ground (0V)
+| 181 | MIPI_D1_N               | MIPI DSI data 1 negative output.
+| 182 | HDMI_TX0P               | HDMI TMDS data 0 positive output.
+| 183 | MIPI_D1_P               | MIPI DSI data 1 positive output.
+| 184 | HDMI_TX0N               | HDMI TMDS data 0 negative output.
+| 185 | GND                     | Ground (0V)
+| 186 | GND                     | Ground (0V)
+| 187 | MIPI_CLK_N              | MIPI DSI clock negative output.
+| 188 | HDMI_TXCP               | HDMI TMDS clock positive output.
+| 189 | MIPI_CLK_P              | MIPI DSI clock positive output.
+| 190 | HDMI_TXCN               | HDMI TMDS clock negative output.
+| 191 | GND                     | Ground (0V)
+| 192 | GND                     | Ground (0V)
+| 193 | MIPI_D2_N               | MIPI DSI data 2 negative output.
+| 194 | MIPI_D3_N               | MIPI DSI data 3 negative output.
+| 195 | MIPI_D2_P               | MIPI DSI data 2 positive output.
+| 196 | MIPI_D3_P               | MIPI DSI data 3 positive output.
+| 197 | GND                     | Ground (0V)
+| 198 | GND                     | Ground (0V)
+| 199 | HDMI_SDA                | HDMI SDA(IIC) signal. 2.2K pull-up resistors on BPI-CM4
+| 200 | HDMI_SCL                | HDMI SCL(IIC) signal. 2.2K pull-up resistors on BPI-CM4
+|===
+
+<<<
+
+=== 4.2 Pin comparison between BPI-CM4 and  Raspberry Pi Compute Module 4
+
+.Pin comparison between BPI-CM4 and  Raspberry Pi Compute Module 4
+[cols="3,3,^1,^1,3,3"]
+|===
+|RPI CM4                   |BPI-CM4                  |Pin Num |Pin Num            |BPI-CM4 |RPI CM4
+
+| GND                      | GND                     | 1   | 2   | GND            | GND                
+| Ethernet_Pair3_P         | NAT0_MDI3p              | 3   | 4   | NAT0_MDI1p     | Ethernet_Pair1_P   
+| Ethernet_Pair3_N         | NAT0_MDI3n              | 5   | 6   | NAT0_MDI1n     | Ethernet_Pair1_N   
+| GND                      | GND                     | 7   | 8   | GND            | GND                
+| Ethernet_Pair2_N         | NAT0_MDI2n              | 9   | 10  | NAT0_MDI0n     | Ethernet_Pair0_N   
+| Ethernet_Pair2_P         | NAT0_MDI2p              | 11  | 12  | NAT0_MDI0p     | Ethernet_Pair0_P   
+| GND                      | GND                     | 13  | 14  | GND            | GND                
+| Ethernet_nLED3_1G-Active | Ethernet_LED2/1G_Active | 15  | 16  | LINUX_Debug_RX | Ethernet_SYNC_IN   
+| Ethernet_nLED2_1G-Link   | Ethernet_LED1/Link      | 17  | 18  | LINUX_Debug_TX | Ethernet_SYNC_OUT  
+| Ethernet_nLED1_Y         | Ethernet_0_LED0/CFG_EXT | 19  | 20  | NC             | EEPROM_nWP         
+| Pi_nLED_Activity         | SYS_LED2                | 21  | 22  | GND            | GND                
+| GND                      | GND                     | 23  | 24  | GPIOA_0        | I2S_MCLK/GPIO26    
+| GPIO21/I2S_DO            | GPIOA_3                 | 25  | 26  | GPIOA_2        | I2S_LRCLK/GPIO19   
+| GPIO20/I2S_DI            | GPIOA_4                 | 27  | 28  | GPIOA_7        | GPIO13             
+| GPIO16                   | GPIOAO_11               | 29  | 30  | GPIOAO_10      | GPIO6              
+| GPIO12                   | GPIOH_5                 | 31  | 32  | GND            | GND                
+| GND                      | GND                     | 33  | 34  | GPIOH_4        | GPIO5              
+| ID_SC                    | GPIOA_15                | 35  | 36  | GPIOA_14       | ID_SD              
+| GPIO7/SPI-CE1            | GPIOAO_5                | 37  | 38  | GPIOX_11       | SPI-CLK/GPIO11     
+| GPIO8/SPI-CE0            | GPIOX_10                | 39  | 40  | GPIOX_9        | SPI-MISO/GPIO9     
+| GPIO25                   | GPIOA_11                | 41  | 42  | GND            | GND                
+| GND                      | GND                     | 43  | 44  | GPIOX_8        | SPI-MOSI/GPIO10    
+| GPIO24/UART0-CTS         | GPIOA_12                | 45  | 46  | GPIOA_5        | GPIO22             
+| GPIO23/UART0-RTS         | GPIOA_13                | 47  | 48  | GPIOA_6        | UART1-RXD/GPIO27   
+| GPIO18/I2S_SCLK          | GPIOA_1                 | 49  | 50  | GPIOA_9        | UART1-TXD/GPIO17   
+| GPIO15/UART0-RXD         | GPIOX_7                 | 51  | 52  | GND            | GND                
+| GND                      | GND                     | 53  | 54  | GPIOA_10       | PWM/GPIO4          
+| GPIO14/UART0-TXD         | GPIOX_6                 | 55  | 56  | GPIOX_18       | SCL/GPIO3          
+| SD_CLK                   | SD_CLK_B                | 57  | 58  | GPIOX_17       | SDA/GPIO2          
+| GND                      | GND                     | 59  | 60  | GND            | GND                
+| SD_DAT3                  | SD_D3_B                 | 61  | 62  | SD_CMD_B       | SD_CMD             
+| SD_DAT0                  | SD_D0_B                 | 63  | 64  | NC             | SD_DAT5            
+| GND                      | GND                     | 65  | 66  | GND            | GND                
+| SD_DAT1                  | SD_D1_B                 | 67  | 68  | NC             | SD_DAT4            
+| SD_DAT2                  | SD_D2_B                 | 69  | 70  | NC             | SD_DAT7            
+| GND                      | GND                     | 71  | 72  | NC             | SD_DAT6            
+| SD_VDD_Override          | NC                      | 73  | 74  | GND            | GND                
+| SD_PWR_ON                | TF_VDD_EN               | 75  | 76  | CARD_DET       | Reserved/SD_DET    
+| +5V_Input                | +5V_Input               | 77  | 78  | NC             | GPIO_VREF          
+| +5V_Input                | +5V_Input               | 79  | 80  | GPIOH_7        | SCL0_Camera_3V3    
+| +5V_Input                | +5V_Input               | 81  | 82  | GPIOH_6        | SDA0_Camera_3V3    
+| +5V_Input                | +5V_Input               | 83  | 84  | CM4_3V3_OUTPUT | CM4_3V3_OUTPUT     
+| +5V_Input                | +5V_Input               | 85  | 86  | CM4_3V3_OUTPUT | CM4_3V3_OUTPUT     
+| +5V_Input                | +5V_Input               | 87  | 88  | CM4_1V8_OUTPUT | CM4_1V8_OUTPUT     
+| /WL_nDisable_3V3         | NC                      | 89  | 90  | CM4_1V8_OUTPUT | CM4_1V8_OUTPUT     
+| /BT_nDisable_3V3         | NC                      | 91  | 92  | CPU_RST        | RUN_PG/Reset_3V3   
+| /nRPIBOOT_3V3            | NC                      | 93  | 94  | SARADC_CH3     | AnalogIP1/USBC_CC2 
+| PI_LED_nPWR              | SYS_LED                 | 95  | 96  | ADC_KEY        | AnalogIP0/USBC_CC1 
+| Camera_PWD_GPIO          | NC                      | 97  | 98  | GND            | GND                
+| GLOBAL_EN_5V             | NC                      | 99  | 100 | GPIOH_8        | nEXTRST            
+| USB_OTG_ID_3V3           | USBOTG_B_ID             | 101 | 102 | PCIECK_REQN    | PCIe_CLK_nREQ_3V3  
+| USB_N                    | USBOTG_B_DM             | 103 | 104 | USB_A_DP       | Reserved           
+| USB_P                    | USBOTG_B_DP             | 105 | 106 | USB_A_DM       | Reserved           
+| GND                      | GND                     | 107 | 108 | GND            | GND                
+| PCIe_nRST_3V3            | PERST0_N                | 109 | 110 | PCIE_CLKP      | PCIe_CLK_P         
+| VDAC_COMP_TV             | NC                      | 111 | 112 | PCIE_CLKN      | PCIe_CLK_N         
+| GND                      | GND                     | 113 | 114 | GND            | GND                
+| CAM1_D0_N                | MIPI_CSI_D0N            | 115 | 116 | PCIE_SOC_RXP   | PCIe_RX_P          
+| CAM1_D0_P                | MIPI_CSI_D0P            | 117 | 118 | PCIE_SOC_RXN   | PCIe_RX_N          
+| GND                      | GND                     | 119 | 120 | GND            | GND                
+| CAM1_D1_N                | MIPI_CSI_D1N            | 121 | 122 | PCIE_TX0_P     | PCIe_TX_P          
+| CAM1_D1_P                | MIPI_CSI_D1P            | 123 | 124 | PCIE_TX0_N     | PCIe_TX_N          
+| GND                      | GND                     | 125 | 126 | GND            | GND                
+| CAM1_C_N                 | MIPI_CSI_CLKAN          | 127 | 128 | NC             | CAM0_D0_N          
+| CAM1_C_P                 | MIPI_CSI_CLKAP          | 129 | 130 | NC             | CAM0_D0_P          
+| GND                      | GND                     | 131 | 132 | GND            | GND                
+| CAM1_D2_N                | MIPI_CSI_D2N            | 133 | 134 | NC             | CAM0_D1_N          
+| CAM1_D2_P                | MIPI_CSI_D2P            | 135 | 136 | NC             | CAM0_D1_P          
+| GND                      | GND                     | 137 | 138 | GND            | GND                
+| CAM1_D3_N                | MIPI_CSI_D3N            | 139 | 140 | MIPI_CSI_CLKBN | CAM0_C_N           
+| CAM1_D3_P                | MIPI_CSI_D3P            | 141 | 142 | MIPI_CSI_CLKBP | CAM0_C_P           
+| HDMI1_HOTPLUG_5V         | NC                      | 143 | 144 | GND            | GND                
+| HDMI1_SDA_5V             | NC                      | 145 | 146 | NC             | HDMI1_TX2_P        
+| HDMI1_SCL_5V             | NC                      | 147 | 148 | NC             | HDMI1_TX2_N        
+| HDMI1_CEC_5V             | NC                      | 149 | 150 | GND            | GND                
+| HDMI0_CEC_5V             | HDMI_TXCEC              | 151 | 152 | NC             | HDMI1_TX1_P        
+| HDMI0_HOTPLUG_5V         | HDMI_HPDC               | 153 | 154 | NC             | HDMI1_TX1_N        
+| GND                      | GND                     | 155 | 156 | GND            | GND                
+| DSI0_D0_N                | NC                      | 157 | 158 | NC             | HDMI1_TX0_P        
+| DSI0_D0_P                | NC                      | 159 | 160 | NC             | HDMI1_TX0_N        
+| GND                      | GND                     | 161 | 162 | GND            | GND                
+| DSI0_D1_N                | NC                      | 163 | 164 | NC             | HDMI1_CLK_P        
+| DSI0_D1_P                | NC                      | 165 | 166 | NC             | HDMI1_CLK_N        
+| GND                      | GND                     | 167 | 168 | GND            | GND                
+| DSI0_C_N                 | NC                      | 169 | 170 | HDMI_TX2P      | HDMI0_TX2_P        
+| DSI0_C_P                 | NC                      | 171 | 172 | HDMI_TX2N      | HDMI0_TX2_N        
+| GND                      | GND                     | 173 | 174 | GND            | GNF                
+| DSI1_D0_N                | MIPI_D0_N               | 175 | 176 | HDMI_TX1P      | HDMI0_TX1_P        
+| DSI1_D0_P                | MIPI_D0_P               | 177 | 178 | HDMI_TX1N      | HDMI0_TX1_N        
+| GND                      | GND                     | 179 | 180 | GND            | GND                
+| DSI1_D1_N                | MIPI_D1_N               | 181 | 182 | HDMI_TX0P      | HDMI0_TX0_P        
+| DSI1_D1_P                | MIPI_D1_P               | 183 | 184 | HDMI_TX0N      | HDMI0_TX0_N        
+| GND                      | GND                     | 185 | 186 | GND            | GND                
+| DSI1_C_N                 | MIPI_CLK_N              | 187 | 188 | HDMI_TXCP      | HDMI0_CLK_P        
+| DSI1_C_P                 | MIPI_CLK_P              | 189 | 190 | HDMI_TXCN      | HDMI0_CLK_N        
+| GND                      | GND                     | 191 | 192 | GND            | GND                
+| DSI1_D2_N                | MIPI_D2_N               | 193 | 194 | MIPI_D3_N      | DSI1_D3_N          
+| DSI1_D2_P                | MIPI_D2_P               | 195 | 196 | MIPI_D3_P      | DSI1_D3_P          
+| GND                      | GND                     | 197 | 198 | GND            | GND                
+| HDMI0_SDA_5V             | HDMI_SDA                | 199 | 200 | HDMI_SCL       | HDMI0_SCL_5V       
+|===
+
+All ground pins should be connected.Attention should be paid to mechanical stability when designing expansion boards.
+
+Strict attention should be paid to the IO level to avoid damage to the chip.and do not input reverse voltage.
+
+== Chapter 5. Power
+
+=== 5.1 Power up sequencing
+
+The BPI-CM4 requires a single +5V supply, and it is not recommended to use the +3.3V and +1.8V output of the core board to power peripheral devices.
+
+All pins should not have any power applied to them before the +5V rail is applied.
+
++5V should rise monotonically to 4.75V and stay above 4.75V for the entire operation of the BPI-CM4.
+
+System operation begins when both +5V rails are above 4.75V and CPU_RST is high. CPU_RST has an internal RC delay on the core board to make it rise after +5V rises.The order of events is as follows
+
+. +5V rises
+. CPU_RST rises
+. +1.8V rises
+. +3.3V rises
+
+=== 5.2 Power down sequencing
+
+The Operating System should be shut down to ensure that the file system remains consistent, before the power is removed. If this can't be achieved, then a filesystem like btrfs, f2fs or overlayfs should be considered.
+
+Once the Operating System has shutdown the +5V rail can be removed.
+
+During the shutdown sequence the +3.3v will be discharged before the +1.8v rail.
+
+== Appendix A: Official Support
+
+
+
+* Official wiki Getting Started: https://wiki.banana-pi.org/Getting_Started_with_CM4[Getting Started with CM4] 
+* Official wiki Products: https://wiki.banana-pi.org/BPI-CM4_Computer_module_and_development_Kit[BPI-CM4 Computer module and development Kit]
+* Official Forum (EN): https://forum.banana-pi.org/c/Banana-Pi-BPI-M5[BPI-CM4 Forum(EN)]
+* Official Forum (CN): https://forum.banana-pi.org.cn/c/bpi-m5/144[BPI-CM4 Forum(CN)]

src/docs/asciidoc/BPI-H618_pre-edit_CN.adoc

@@ -0,0 +1,291 @@
+= BPI-H618 预编
+:outlinelevels: 3
+用于嵌入式应用的 Banana Pi SBC
+:example-caption!:
+ifndef::imagesdir[:imagesdir: images]
+
+toc::[]
+
+== 第1章 介绍
+
+=== 1.1 介绍
+
+BPI-H618 开发板作为一款强大的单板计算机（SBC），充分挖掘了全志 H618 系统级芯片（SoC）的功能，为开发人员提供了令人印象深刻的性能和丰富的特性。与树莓派 4b 类似，BPI-H618 能够展现与之相匹敌的CPU性能，支持LPDDR4内存，集成WiFi和蓝牙功能，并拥有熟悉的40-pin接头布局，还有4个USB接口和一个GbE RJ45端口。
+
+它不仅配备了一个标准的SD卡插槽供操作系统使用，还集成了高性能的8GB eMMC闪存。这一增强功能显著加速了系统的读写速度，加快了开发和调试过程，从而为项目提供了更稳定、高效的基础。
+
+BPI-H618 开发板的标志性特点之一是其出色的成像和解码能力。配备全尺寸的HDMI 2.0a接口，支持高达60Hz的4K分辨率输出。具备卓越的解码能力，适应各种视频格式，包括但不限于H.265 4K@60fps、6K@30fps、VP9 4K@30fps、AVS2 4K@60fps以及H.264 4K@30fps。此外，BPI-H618 还拥有H.264 4K@25fps的编码性能，使其成为涉及流媒体、娱乐和视觉处理应用的理想选择。
+
+BPI-H618的设计灵活性使其非常适合硬件领域的多种应用场景。其与树莓派兼容的40-pin接头便于与各种传感器、扩展板和设备连接。此外，提供4个USB接口，便于连接各种USB外设，进一步扩展其实用性。GbE RJ45接口提供了快速的高速有线网络连接，2.4G/5G WiFi和蓝牙满足大部分主流无线设备的通信需求，使BPI-H618成为网络应用和物联网（IoT）项目的最佳选择。
+
+BPI-H618 开发板，以其强大的性能、多功能特点和卓越的图像处理能力为特点，是嵌入式和计算行业专业人员的理想 SBC 开发平台。配备 8GB eMMC 闪存、高性能的解码和编码能力以及一系列的接口选项，它满足了广泛的使用需求，包括媒体处理、IoT 和娱乐等应用领域。无论是对初学者还是经验丰富的开发者，BPI-H618 开发板都提供了一个理想的工具集，以支持用户实现创意愿景和项目目标。
+
+=== 1.2 特性
+
+==== 硬件与接口
+
+* 全志H618，四核ARM Cortex™-A53处理器，64位，最高1.5GHz
+* 每核32KB L1 I-cache缓存 + 32KB L1 D-cache缓存和 1MB L2缓存
+* ARM Mali G31图形处理器
+* WIFI & 蓝牙
+* 2G LPDDR4 RAM
+* 8G eMMC闪存
+* 1x MicroSD卡插槽
+* 1x USB2.0 Type-C OTG，5V供电
+* 4x USB2.0 Type-A接口
+* 1x HDMI 2.0a接口
+* 1x 3.5mm音频 & TVE插槽
+* 1x GbE以太网端口（通过额外的PoE HAT支持PoE供电）
+* 1x 调试UART接口
+* 40-pin 接头，包含28个GPIO针脚
+** UART、SPI、TWI/I²C、PWM、PCM/I²S
+* 1x CIR 红外接收器
+
+==== 解码与编码
+
+
+*解码器*
+
+* H.265 Main10@L5.1 最高支持 4K@60fps，或 6K@30fps
+* VP9 Profile 2 最高支持 4K@30fps
+* AVS2 JiZhun 10bit Profile 最高支持 4K@60fps
+* H.264 BP/MP/HP@L4.2 最高支持 4K@30fps
+
+*编码器*
+
+* H.264编码的最大分辨率为1600万像素（4096x 4096）
+* H.264编码能力：4K@25fps
+* JPEG快照性能独立为1080p@60fps
+* 支持恒定比特率（CBR）/变量比特率（VBR）控制模式，范围从256 kbit/s到100Mbit/s。
+
+
+== 第2章 机械规格
+
+== 第3章 外设
+
+=== 3.1 GPIO 接口
+
+BPI-H618 通过标准 2.54 毫米间距 40-pin接头提供 28 个 H618 GPIO。
+
+==== 3.1.1 GPIO 引脚分配
+
+image::GPIO.png[GPIO,title="40-pin接头原理图", alt=GPIO]
+
+除了用于基本软件控制的输入和输出操作，和可编程上拉下拉功能之外，GPIO 引脚还能够重新配置（多路复用）为由专用外设模块，例如 TWI/I2C、UART 和 SPI。
+
+<<<
+
+==== 3.1.2 GPIO 可选功能
+
+*Pin Num*: 在40-pin接头中的针脚编号。
+
+*Pin Name*: 针脚名称。
+
+*Ball Reset State*: 复位时针脚的状态。 PU：拉起； PD：下拉； Z：高阻抗。
+
+[options="header",cols="^.^,^.^,^.^,^.^,^.^,^.^,^.^",frame="all",stripes="odd",width="100%"]
+.GPIO 可选功能分配
+|================================================================================================
+| Pin Num | Pin Name | Ball Reset State | ALT0         | ALT1         | ALT2      | ALT3         
+
+| 1       | 3.3V     |                  |              |              |           |              
+| 2       | 5V       |                  |              |              |           |              
+| 3       | PG16     | PU               | UART2_RX     |              |           | TWI4_SDA     
+| 4       | 5V       |                  |              |              |           |              
+| 5       | PG15     | PU               | UART2_TX     |              |           | TWI4_SCK     
+| 6       | GND      |                  |              |              |           |              
+| 7       | PG19     | Z                |              |              | PWM1      |              
+| 8       | PG6      | Z                | UART1_TX     |              |           |              
+| 9       | GND      |                  |              |              |           |              
+| 10      | PG7      | Z                | UART1_RX     |              |           |              
+| 11      | PH2      | Z                | UART5_TX     |              | PWM2      |              
+| 12      | PG11     | Z                | H_I2S2_BCLK  |              |           |              
+| 13      | PH3      | Z                | UART5_RX     |              | PWM1      |              
+| 14      | GND      |                  |              |              |           |              
+| 15      | PG2      | PU               |              |              |           |              
+| 16      | PG8      | Z                | UART1_RTS    |              |           |              
+| 17      | 3.3V     |                  |              |              |           |              
+| 18      | PG9      | Z                | UART1_CTS    |              |           |              
+| 19      | PH7      | Z                | UART2_RTS    | H_I2S3_LRCK  | SPI1_MOSI |              
+| 20      | GND      |                  |              |              |           |              
+| 21      | PH8      | Z                | UART2_CTS    | H_I2S3_DOUT0 | SPI1_MISO | H_I2S3_DIN1  
+| 22      | PG1      | PU               |              |              |           |              
+| 23      | PH6      | Z                | UART2_RX     | H_I2S3_BCLK  | SPI1_CLK  |              
+| 24      | PH5      | Z                | UART2_TX     | H_I2S3_MCLK  | SPI1_CS0  |              
+| 25      | GND      |                  |              |              |           |              
+| 26      | PH9      | Z                |              | H_I2S3_DIN0  | SPI1_CS1  | H_I2S3_DOUT1 
+| 27      | PG18     | PU               | UART2_CTS    |              |           | TWI3_SDA     
+| 28      | PG17     | PU               | UART2_RTS    |              |           | TWI3_SCK     
+| 29      | PG3      | PU               |              |              |           |              
+| 30      | GND      |                  |              |              |           |              
+| 31      | PG4      | PU               |              |              |           |              
+| 32      | PG0      | Z                |              |              |           |              
+| 33      | PG5      | PU               |              |              |           |              
+| 34      | GND      |                  |              |              |           |              
+| 35      | PG12     | Z                | H_I2S2_LRCK  |              |           |              
+| 36      | PH4      | Z                |              |              |           |              
+| 37      | PG10     | Z                | H_I2S2_MCLK  |              |           |              
+| 38      | PG14     | Z                | H_I2S2_DIN0  | H_I2S2_DOUT1 |           |              
+| 39      | GND      |                  |              |              |           |              
+| 40      | PG13     | Z                | H_I2S2_DOUT0 | H_I2S2_DIN1  |           |              
+|================================================================================================
+
+<<<
+
+==== 3.1.3 详细信号描述
+
+*Signal Name*：每个信号的名称。
+
+*Description*：每个信号的详细功能描述。
+
+*Type*：表示信号方向：
+
+* I (输入)
+* O (输出)
+* I/O(输入/输出)
+
+[options="header",cols="^.^2,^.^2,^.^1",frame="all",stripes="odd",width="90%"]
+.详细信号描述
+|=================================================================================
+| Signal Name          | Description                                        | Type
+
+| UART[1/2/5]_TX       | UART[1/2/5] Data Transmit                          | O   
+| UART[1/2/5]_RX       | UART[1/2/5] Data Receive                           | I   
+| UART[1/2]_CTS        | UART[1/2] Data Clear to Send                       | I   
+| UART[1/2]_RTS        | UART[1/2] Data Request to Send                     | O   
+| SPI1_CS0             | SPI1 Chip Select0 Signal, Low Active               | I/O 
+| SPI1_CS1             | SPI1 Chip Select1 Signal, Low Active               | I/O 
+| SPI1_CLK             | SPI1 Clock Signal                                  | I/O 
+| SPI1_MOSI            | SPI1 Master Data Out, Slave Data In                | I/O 
+| SPI1_MISO            | SPI1 Master Data In, Slave Data Out                | I/O 
+| TWI[3/4]_SCK         | TWI[3/4] Serial Clock Signal                       | I/O 
+| TWI[3/4]_SDA         | TWI[3/4] Serial Data Signal                        | I/O 
+| PWM[1/2]             | Pulse Width Modulation Output Channel [1/2]        | I/O 
+| H_I2S[2/3]_MCLK      | I2S[2/3] Master Clock                              | O   
+| H_I2S[2/3]_LRCK      | I2S[2/3]/PCM[2/3] Sample Rate Clock/Sync           | I/O 
+| H_I2S[2/3]_BCLK      | I2S[2/3]/PCM[2/3] Sample Rate Clock                | I/O 
+| H_I2S[2/3]_DOUT[1/2] | I2S[2/3]/PCM[2/3] Serial Data Output Channel [1/2] | O   
+| H_I2S[2/3]_DIN[1/2]  | I2S[2/3]/PCM[2/3] Serial Data Input Channel [1/2]  | I   
+
+|=================================================================================
+
+=== 3.2 调试UART接口
+
+通过独立的 2.54mm 间距 3-pin 接头提供调试 UART，带有 TX、RX 和 GND。
+
+默认波特率为 *115200 bps*。
+
+=== 3.3 USB 2.0 OTG & 供电
+
+开发板需要能够提供 5V@3A 的优质 USB Type-C 电源。
+
+如果连接的下游设备消耗小于 500mA 或没有设备，则可以使用 5V@2A 电源。
+
+USB Type-C 插座提供 USB 2.0 OTG，以及集成的 USB 2.0 模拟 PHY。
+
+兼容USB 2.0规范。
+
+在主机模式下支持高速（HS，480 Mbit/s）、全速（FS，12 Mbit/s）和低速（LS，1.5 Mbit/s）。
+
+在设备模式下支持高速（HS，480 Mbit/s）、全速（FS，12 Mbit/s）。
+
+与主机模式的增强型主机控制器接口 (EHCI) 规范 1.0 版和开放式主机控制器接口 (OHCI) 规范 1.0a 版兼容。
+
+多达 8 个用户可配置端点 (EP)，用于批量、同步和中断双向传输。
+
+支持所有EP（包括EP0）的（4KB+64Bytes）FIFO。
+
+支持主机和外设模式下的点对点和点对多点传输。
+
+=== 3.4 USB 2.0 HOST
+
+通过板载 USB HUB 提供 4 个 USB 2.0 Type-A 插座。
+
+与增强型主机控制器接口 (EHCI) 规范 1.0 版和开放式主机控制器接口 (OHCI) 规范 1.0a 版兼容。
+
+支持高速（HS，480 Mbit/s）、全速（FS，12 Mbit/s）和低速（LS，1.5 Mbit/s）设备。
+
+通过独立的 2.54mm 间距 2-pin 接头提供另一个 USB 2.0 主机端口，支持 USB 待机。
+
+=== 3.5 Micro SD 卡
+
+提供一个Micro SD卡插槽，4位总线宽度，支持SD3.0。
+
+=== 3.6 CIR 消费级红外接收器
+
+支持NEC格式红外数据。
+
+支持CIR远程控制或无线键盘。
+
+=== 3.7 HDMI
+
+提供全尺寸HDMI2.0a端口。 兼容HDCP 2.2和HDCP 1.4，支持DDC和SCDC，集成CEC硬件引擎。
+
+视频支持：
+
+* 2D视频：4K/1080P/1080I/720P/576P/480P/576I/480I，高达4K@60fps
+* -3D视频：4K/1080P/720P/576P/480P，最高4K@30fps
+* 支持RGB888/YUV444/YUV422输出
+* 颜色深度：8/10 位
+* HDR10：符合CTA-861.3和SMPTE ST 2048
+
+音频支持：
+
+* 未压缩音频格式：IEC60985 L-PCM 音频样本，高达 192 kHz
+* 压缩音频格式：IEC61937 压缩音频，最高 1536 kHz
+
+=== 3.8 音频和 TVE
+
+为音频和 TVE 提供 3.5 毫米插孔。
+
+image::AV1.png[AV1,title="音频和 TVE 插孔原理图"]
+
+1 个单端 LINEOUTL/R 音频输出。
+
+2 个音频 DAC 通道。
+
+支持 16 位和 20 位采样分辨率。
+
+8 kHz 至 192 kHz DAC 采样率。
+
+95±2dB SNR@A-weight，-80±3dB THD+N，输出电平大于0.55Vrms。
+
+image::AV2.png[AV2,250,title="3.5mm转3RCA线",align=center]
+
+使用 3.5mm转3RCA线 获得电视 CVBS 输出。
+
+支持NTSC和PAL模式，自动检测插头状态。
+
+=== 3.9 按钮
+
+*RESET 按钮*，按下时重置。
+
+*FEL 按钮*，boot选择按钮，按住不放，然后复位板子，板子就会进入强制升级进程。
+
+*USER 按钮*，用户可编程按钮，按下时GPIO PC7 为低电平，反之为高电平。
+
+所有按键均配有ESD静电防护。
+
+=== 3.10 以太网
+
+提供千兆以太网RJ45端口。
+
+符合 IEEE 802.3-2002 标准。
+
+支持全双工和半双工操作。
+
+通过附加 PoE HAT 模块可支持 PoE。
+
+=== 3.11 WiFi 和蓝牙
+
+通过 WIFI+BT 组合模块提供 2.4G/5G WiFi 和蓝牙 4.2。
+
+通过 IPEX-1 RF 连接器连接天线。
+
+* 2.4G WIFI：2.412~2.472GHz
+* 5G WIFI：5.18 ~ 5.24GHz / 5.745 ~ 5.825GHz
+* 蓝牙：2.402~2.48GHz
+* IEEE 802.11a/b/g/n/ac(1T1R)
+* 无线数据速率可达433.3Mbps
+* 支持蓝牙低功耗
+

src/docs/asciidoc/BPI-H618_pre-edit_EN.adoc

@@ -0,0 +1,293 @@
+= BPI-H618 pre-edit
+:outlinelevels: 3
+A Banana Pi SBC for embedded applica
+:example-caption!:
+ifndef::imagesdir[:imagesdir: images]
+
+toc::[]
+
+== Chapter 1. Introduction
+
+=== 1.1 Introduction
+
+The BPI-H618 development board stands as a powerful Single Board Computer (SBC), harnessing the capabilities of the Allwinner H618 System-on-Chip (SoC) to provide developers with impressive performance and a wealth of features. Similar to the Raspberry Pi 4b, the BPI-H618 boasts comparable CPU prowess, LPDDR4 memory support, integrated WiFi and Bluetooth functionalities, and a familiar 40-pin header layout, alongside 4 USB interfaces and a GbE RJ45 port. 
+
+It not only features a standard SD card slot for operating systems but also integrates a high-performance 8GB eMMC flash memory. This enhancement brings forth significantly accelerated system read and write speeds, expediting development and debugging processes, thereby furnishing a more stable and efficient foundation for project endeavors.
+
+One of the flagship traits of the BPI-H618 development board is its exceptional imaging and decoding capabilities. Equipped with a full-size HDMI 2.0a interface, it supports 4K resolution output at refresh rates of up to 60Hz. This empowers users with remarkable decoding capabilities, accommodating various video formats, including but not limited to, H.265 4K@60fps, 6K@30fps, VP9 4K@30fps, AVS2 4K@60fps, and H.264 4K@30fps. Furthermore, the BPI-H618 also boasts H.264 4K@25fps encoding performance, rendering it an ideal choice for applications encompassing streaming, entertainment, and visual processing.
+
+The BPI-H618's design flexibility makes it well-suited for diverse application scenarios within the hardware realm. Its Raspberry Pi-compatible 40-pin header facilitates seamless interfacing with a variety of sensors, expansion boards, and devices. Moreover, the availability of 4 USB interfaces facilitates connection to external peripherals, further extending its utility. The GbE RJ45 interface offers expedient high-speed network connectivity, 2.4G/5G WiFi and Bluetooth meet the communication needs of most mainstream wireless devices, positioning the BPI-H618 as an optimal selection for networking applications and Internet of Things (IoT) projects.
+
+The BPI-H618 development board, characterized by its robust performance, versatile features, and remarkable image processing capabilities, stands as an exemplary SBC development platform for professionals within the embedded and computing industries. Equipped with 8GB eMMC flash storage, high-performance decoding and encoding capabilities, and an array of interface options, it caters to a wide spectrum of application domains, including media processing, IoT, and entertainment. Whether catering to novices or seasoned developers, the BPI-H618 development board offers an ideal toolset for realizing creative visions and project objectives.
+
+=== 1.2 Features
+
+==== Hardware and Interface
+
+* Allwinner H618, Quad-core ARM Cortex™-A53 processor, 64-bit, up to 1.5GHz
+* 32KB L1 I-cache + 32KB L1 D-cache per core and 1MB L2 cache
+* ARM Mali G31 GPU
+* WIFI & Bluetooth
+* 2G LPDDR4 RAM
+* 8G eMMC flash memory
+* 1x MicroSD card slot
+* 1x USB2.0 Type-C OTG, 5V power supply
+* 4x USB2.0 Type-A
+* 1x HDMI 2.0a
+* 1x 3.5mm Audio & TVE jack socket
+* 1x GbE Ethernet port (supports PoE with add-on PoE HAT)
+* 1x Debug UART
+* 40-pin header, 28-pin GPIO
+** UART, SPI, TWI/I²C, PWM, PCM/I²S
+* 1x CIR
+
+
+==== Decoder and Encoder
+
+*Decoder*
+
+* H.265 Main10@L5.1 up to 4K@60fps, or 6K@30fps
+* VP9 Profile 2 up to 4K@ 30fps
+* AVS2 JiZhun 10bit Profile up to 4K@ 60fps
+* H.264 BP/MP/HP@L4.2 up to 4K@30fps
+
+*Encoder*
+
+* Maximum 16-megapixel (4096x 4096) resolution for H.264 encoding 
+* H.264 encoding capability: 4K@25fps
+* JPEG snapshot performance of 1080p@60fps independently
+* Supports the constant bit rate (CBR)/variable bit rate (VBR) bit rate control mode, ranging from 256 kbit/s to 100Mbit/s
+
+== Chapter 2. Mechanical Specification
+
+== Chapter 3. Peripherals
+
+=== 3.1 GPIO Interface
+
+The BPI-H618 makes 28 H618 GPIOs available via a standard 2.54mm pitch 40-pin header. 
+
+==== 3.1.1 GPIO Pin Assignments
+
+image::GPIO.png[GPIO,title="40-pin header schematic", alt=GPIO]
+
+In addition to their utility for basic software-controlled input and output operations, which includes programmable pull functionalities, GPIO pins possess the capability to be reconfigured (multiplexed) into diverse operational modes supported by specialized peripheral blocks such as TWI/I2C, UART, and SPI.
+
+<<<
+
+==== 3.1.2 GPIO Alternate Functions
+
+*Pin Num*: The number among the 40-pin header.
+
+*Pin Name*: The name of the pin.
+
+*Ball Reset State*: The state of the terminal at reset. PU: pull up; PD: pull down; Z: high impedance.
+
+[options="header",cols="^.^,^.^,^.^,^.^,^.^,^.^,^.^",frame="all",stripes="odd",width="100%"]
+.GPIO Alternative Function Assignments
+|================================================================================================
+| Pin Num | Pin Name | Ball Reset State | ALT0         | ALT1         | ALT2      | ALT3         
+
+| 1       | 3.3V     |                  |              |              |           |              
+| 2       | 5V       |                  |              |              |           |              
+| 3       | PG16     | PU               | UART2_RX     |              |           | TWI4_SDA     
+| 4       | 5V       |                  |              |              |           |              
+| 5       | PG15     | PU               | UART2_TX     |              |           | TWI4_SCK     
+| 6       | GND      |                  |              |              |           |              
+| 7       | PG19     | Z                |              |              | PWM1      |              
+| 8       | PG6      | Z                | UART1_TX     |              |           |              
+| 9       | GND      |                  |              |              |           |              
+| 10      | PG7      | Z                | UART1_RX     |              |           |              
+| 11      | PH2      | Z                | UART5_TX     |              | PWM2      |              
+| 12      | PG11     | Z                | H_I2S2_BCLK  |              |           |              
+| 13      | PH3      | Z                | UART5_RX     |              | PWM1      |              
+| 14      | GND      |                  |              |              |           |              
+| 15      | PG2      | PU               |              |              |           |              
+| 16      | PG8      | Z                | UART1_RTS    |              |           |              
+| 17      | 3.3V     |                  |              |              |           |              
+| 18      | PG9      | Z                | UART1_CTS    |              |           |              
+| 19      | PH7      | Z                | UART2_RTS    | H_I2S3_LRCK  | SPI1_MOSI |              
+| 20      | GND      |                  |              |              |           |              
+| 21      | PH8      | Z                | UART2_CTS    | H_I2S3_DOUT0 | SPI1_MISO | H_I2S3_DIN1  
+| 22      | PG1      | PU               |              |              |           |              
+| 23      | PH6      | Z                | UART2_RX     | H_I2S3_BCLK  | SPI1_CLK  |              
+| 24      | PH5      | Z                | UART2_TX     | H_I2S3_MCLK  | SPI1_CS0  |              
+| 25      | GND      |                  |              |              |           |              
+| 26      | PH9      | Z                |              | H_I2S3_DIN0  | SPI1_CS1  | H_I2S3_DOUT1 
+| 27      | PG18     | PU               | UART2_CTS    |              |           | TWI3_SDA     
+| 28      | PG17     | PU               | UART2_RTS    |              |           | TWI3_SCK     
+| 29      | PG3      | PU               |              |              |           |              
+| 30      | GND      |                  |              |              |           |              
+| 31      | PG4      | PU               |              |              |           |              
+| 32      | PG0      | Z                |              |              |           |              
+| 33      | PG5      | PU               |              |              |           |              
+| 34      | GND      |                  |              |              |           |              
+| 35      | PG12     | Z                | H_I2S2_LRCK  |              |           |              
+| 36      | PH4      | Z                |              |              |           |              
+| 37      | PG10     | Z                | H_I2S2_MCLK  |              |           |              
+| 38      | PG14     | Z                | H_I2S2_DIN0  | H_I2S2_DOUT1 |           |              
+| 39      | GND      |                  |              |              |           |              
+| 40      | PG13     | Z                | H_I2S2_DOUT0 | H_I2S2_DIN1  |           |              
+|================================================================================================
+
+<<<
+
+==== 3.1.3 Detailed Signal Description
+
+*Signal Name*: The name of every signal.
+
+*Description*: The detailed function description of every signal.
+
+*Type*: Denotes the signal direction:
+
+* I (Input)
+* O (Output)
+* I/O(Input/Output)
+
+[options="header",cols="^.^2,^.^2,^.^1",frame="all",stripes="odd",width="90%"]
+.Detailed Signal Description
+|=================================================================================
+| Signal Name          | Description                                        | Type
+
+| UART[1/2/5]_TX       | UART[1/2/5] Data Transmit                          | O   
+| UART[1/2/5]_RX       | UART[1/2/5] Data Receive                           | I   
+| UART[1/2]_CTS        | UART[1/2] Data Clear to Send                       | I   
+| UART[1/2]_RTS        | UART[1/2] Data Request to Send                     | O   
+| SPI1_CS0             | SPI1 Chip Select0 Signal, Low Active               | I/O 
+| SPI1_CS1             | SPI1 Chip Select1 Signal, Low Active               | I/O 
+| SPI1_CLK             | SPI1 Clock Signal                                  | I/O 
+| SPI1_MOSI            | SPI1 Master Data Out, Slave Data In                | I/O 
+| SPI1_MISO            | SPI1 Master Data In, Slave Data Out                | I/O 
+| TWI[3/4]_SCK         | TWI[3/4] Serial Clock Signal                       | I/O 
+| TWI[3/4]_SDA         | TWI[3/4] Serial Data Signal                        | I/O 
+| PWM[1/2]             | Pulse Width Modulation Output Channel [1/2]        | I/O 
+| H_I2S[2/3]_MCLK      | I2S[2/3] Master Clock                              | O   
+| H_I2S[2/3]_LRCK      | I2S[2/3]/PCM[2/3] Sample Rate Clock/Sync           | I/O 
+| H_I2S[2/3]_BCLK      | I2S[2/3]/PCM[2/3] Sample Rate Clock                | I/O 
+| H_I2S[2/3]_DOUT[1/2] | I2S[2/3]/PCM[2/3] Serial Data Output Channel [1/2] | O   
+| H_I2S[2/3]_DIN[1/2]  | I2S[2/3]/PCM[2/3] Serial Data Input Channel [1/2]  | I   
+
+|=================================================================================
+
+=== 3.2 Debug UART
+
+Provide a Debug UART via a separate 2.54mm pitch 3-pin header, with TX、RX and GND.
+
+The default baud rate is *115200 bps*.
+
+=== 3.3 USB 2.0 OTG & Power Supply
+
+The board requires a good quality USB Type-C power supply capable of delivering 5V@3A.
+
+If attached downstream devices consume less than 500mA or none device, a 5V@2A supply may be used.
+
+The USB Type-C sockets provide USB 2.0 OTG, with integrated USB 2.0 analog PHY.
+
+Compatible with USB 2.0 Specification.
+
+Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s) and Low-Speed (LS, 1.5 Mbit/s) in host mode.
+
+Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s) in device mode.
+
+Compatible with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0, and the Open Host Controller Interface (OHCI) Specification, Version 1.0a for host mode.
+
+Up to 8 User-Configurable Endpoints (EPs) for Bulk, Isochronous and Interrupt bi-directional transfers.
+
+Supports (4KB+64Bytes) FIFO for all EPs (including EP0).
+
+Supports point-to-point and point-to-multipoint transfer in both host and peripheral mode.
+
+=== 3.4 USB 2.0 HOST
+
+Provide 4 USB 2.0 Type-A sockets through the onboard USB HUB.
+
+Compatible with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0, and the Open Host Controller Interface (OHCI) Specification, Version 1.0a.
+
+Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s) and Low-Speed (LS, 1.5 Mbit/s) device.
+
+Provide another USB 2.0 host port via a separate 2.54mm pitch 2-pin header, supports USB standby.
+
+=== 3.5 Micro SD card
+
+Provide a Micro SD card slot, 4-bit bus width, support SD3.0.
+
+=== 3.6 CIR
+
+Provide a Consumer Infrared Receiver.
+
+Supports NEC format infrared data.
+
+Supports CIR for remote control or wireless keyboard.
+
+=== 3.7 HDMI
+
+Provides a full-size HDMI2.0a port. Compatible with HDCP 2.2 and HDCP 1.4, supports DDC and SCDC, integrated CEC hardware engine.
+
+Video support:
+
+* 2D Video: 4K/1080P/1080I/720P/576P/480P/576I/480I, up to 4K@60fps
+* -3D Video: 4K/1080P/720P/576P/480P, up to 4K@30fps
+* Supports RGB888/YUV444/YUV422 output
+* Color depth: 8/10-bit
+* HDR10: compliant with CTA-861.3 and SMPTE ST 2048
+
+Audio support:
+
+* Uncompressed audio formats: IEC60985 L-PCM audio samples, up to 192 kHz
+* Compressed audio formats: IEC61937 compressed audio, up to 1536 kHz
+
+=== 3.8 Audio & TVE
+
+Provides a 3.5mm jack socket for Audio & TVE .
+
+image::AV1.png[AV1,title="Audio & TVE jack socket schematic"]
+
+One single-ended LINEOUTL/R audio output.
+
+Two audio digital-to-analog (DAC) channels.
+
+Supports 16-bit and 20-bit sample resolution.
+
+8 kHz to 192 kHz DAC sample rate.
+
+95±2dB SNR@A-weight, -80±3dB THD+N, output Level more than 0.55Vrms.
+
+image::AV2.png[AV2,250,title="3.5mm To 3 RCA Cable",align=center]
+
+Use 3.5mm To 3 RCA Cable to get the TV CVBS output.
+
+Supports NTSC and PAL mode, plug status auto detecting.
+
+=== 3.9 Buttons
+
+*RESET Button*, reset when pressed.
+
+*FEL Button*, boot select button, when press it and hold it down, then reset the board, the board will enter into the mandatory upgrade process.
+
+*USER Button*, user-programmable button, when pressed, GPIO PC7 will get low level, otherwise it will get a high level.
+
+All buttons are equipped with ESD electrostatic protection.
+
+=== 3.10 Ethernet
+
+Provides a Gigabit Ethernet RJ45 port.
+
+Compliant with IEEE 802.3-2002 standard.
+
+Supports both full-duplex and half-duplex operation.
+
+Supports PoE with add-on PoE HAT.
+
+=== 3.11 WiFi & Bluetooth
+
+Provides 2.4G/5G WiFi and Bluetooth 4.2 via an WIFI+BT Combo Module.
+
+Connect the antenna via IPEX-1 RF connector.
+
+* 2.4G WIFI:2.412~2.472GHz
+* 5G WIFI: 5.18 ~ 5.24GHz / 5.745 ~ 5.825GHz
+* BT:2.402~2.48GHz
+* IEEE 802.11a/b/g/n/ac(1T1R)
+* Wireless data rate can reach up to 433.3Mbps 
+* Bluetooth Low Energy Support 
+
+

src/docs/asciidoc/example-manual.adoc

@@ -1,129 +0,0 @@
-= Banana Pi Compute Module 4
-:outlinelevels: 3
-A Banana Pi for deeply embedded applica
-:example-caption!:
-ifndef::imagesdir[:imagesdir: images]
-
-== Colophon
-
-法律信息及版权信息
-
-<<<
-toc::[]
-
-== Chapter 1. Introduction
-
-=== 1.1 Introduction
-
-image::BPI-CM4.jpg[scaledwidth=75%, title="The BPI-CM4"]
-
-The Banana Pi Compute Module 4(CM4)is a System on Module(SoM) containing processor,DRAM, eMMC Flash and supporting power circuitry. These modules allow a designer touse the Banana Pi hardware and software stack in their own custom systems and formfactors. And, These modules offer additional IO interfaces beyond what is provided on Banana Pi boards, providing designers with more options.
-
-The design of the CM4 is loosely based on the Amlogic A311D, Quad core ARM Cortex-A73 and dual core ARM Cortex-A53 CPU , ARM G52MP4(6EE) GPU,NPU for AI at 5.0 TOPS, support Camera and MIPI-CSI interface ,HDMI output,2 Gigabit port . 4G RAM and 16 GB eMMC flash.
-
-for A311D chip PIN limited . just support 1 HDMI ,1 CSI and 1 DSI , Raspberry Pi support 2 HDMI ,2 CSI and 2 DSI , Other is Pin2Pin . you can use Raspberry Pi CM4 baseboard.
-
-NOTE: for A311D chip PIN limited . just support 1 HDMI ,1 CSI and 1 DSI , Raspberry Pi support 2 HDMI ,2 CSI and 2 DSI , Other is Pin2Pin . you can use Raspberry Pi CM4 baseboard.
-
-<<<
-
-=== 1.2 Key Feature
-
-Key feature of the BPI-CM4 are as follows:
-
-* Amlogic A311D  Quad core ARM Cortex-A73 and dual core ARM Cortex-A53,ARM G52 MP4(6EE) GPU
-* NPU for AI  Next generation, deep-neural-network applications, at 5.0 TOPS 
-* OpenGL ES 3.2, Vulkan 1.1 and OpenCL 2.0 support
-* 4GB LPDDR4 RAM 
-* 16GB eMMC flash (Max 128G) 
-* MIPI DSI :
-** 1x4-Lane MIPI DSI Display Interface 
-* MIPI CSI :
-** 1x4-Lane MIPI CSI Camera Interface
-* PCIe Interface:
-** 1xPCIe 1-Lane Host,Gen 2(5Gbps)
-* HDMI Interface:
-** 1xHDMI 2.1 Output Interface(up tp 4Kx2K@60)
-* Gigabit Ethernet PHY supporting
-* 26 PIN GPIO:
-** 1x PCM
-** 1x IIC
-** 1x UART
-** 1x PWM
-* Single +5V PSU Input
-* Support Android and Linux system
-* Size: 55x40mm
-
-
-== Chapter 2. Interfaces
-
-=== 2.1 Wireless
-
-The BPI-CM4 supports an onboard wireless module based on Realtek RTL8822CS,supports both
-
-* 2.4GHz & 5GHz IEEE 802.11 a/b/g/n/ac 2x2 MIMO wireless
-* Bluetooth 5.0 BR/EDR/LE
-
-These wireless interfaces can be individually enabled or disabled as required via CPU GPIO. In the case of many application environments, a service engineer can enable wireless operation and then disable it when done.
-
-The CPU can also turn on the wireless by itself for data communication, and turn ff the wireless after completion to reduce power consumption.
-
-The BPI-CM4 has two standard IPEX-1G connector on the module, If you want to use 2x2 MIMO, need to connect 2x 2.4G&5G antenna.
-
-Banana Pi Ltd has an antenna kit which is certified to be used with the BPI-CM4. If a different antenna is used then separate certification will be required.
-
-=== 2.2 Ethernet
-
-The BPI-CM4 has an onboard Gigabit Ethernet PHY - the https://www.realtek.com/en/products/connected-media-ics/item/rtl8211f-i-cg[REALTEK RTL8211F] - some of the major features of this PHY include;
-
-* IEEE 802.3az-2010
-* Built-in Wake-on-LAN
-* Crossover Detection & Auto-Correction
-
-A standard RJ45 connector is necessary to provid an Ethernet connection to the BPI-CM4.Can be see in link:#EthSch[Figure 2]
-
-[#EthSch]
-image::EthernetSch.jpg[title="Ethernet Schematic", alt=EthSch]
-
-The differential Ethernet signals should be routed as 100Ω differential pairs, with suitable clearances. Length matching between pairs should be better than 50mm, so in the typical case no length matching is required. However the signals within a pair need to be length matched, ideally to better than 0.15mm.
-
-The PHY also supports up to 2 LEDs to give user status feedback, these are low active. These LEDs can have a range of functions, and you should consult your OS driver to see which functions are supported by your driver.
-
-=== 2.3 PCIe(Gen2 x1)
-
-The BPI-CM4 has an internal PCIe2.0 x1 host controller. Connecting a PCIe device follows the standard PCIe convention.The CM4 has onboard AC coupling capacitors for *PCIe_CLK* and *PCIe_TX* signals.However the *PCIe_RX* signals need external coupling capacitors close to the driving source (the device *TX*), if you are using an external PCIe/NVMe cards these capacitors will be onboard. The PCIe conversion is that if you are wiring directly to an IC then the TX and RX pairs need to be swapped ( ie. TX->RX, RX->TX ). If you are wiring to a connector then this is typically labelled from the host post of view and so TX RX swaps aren’t required. Additionally the *PCIECK_REQN* must be connected to ensure the CM4 produces a clock signal, and the *PERST0_N* should also be connected to ensure the device is correctly reset when required. The differential PCIe signals should be routed as 100Ω differential pairs, with suitable clearances. There is no need to match the lengths between pairs, only the signals within a Pair need to be length matched ideally to better than 0.1mm
-
-TIP: 5.10 kernel and .......
-
-=== 2.4 USB 2.0(Highspeed)
-
-The USB 2.0 interface supports up to 480MBps signalling. The differential pair should be routed as a 90Ω differential pair. The P N signals should ideally be matched to better than 0.15mm.
-
-
-
-<<<
-
-
-
-== Build
-
-This page was built by the following command:
-
- $ mvn
-
-=== Attributes
-
-.Built-in
-asciidoctor-version:: {asciidoctor-version}
-safe-mode-name:: {safe-mode-name}
-docdir:: {docdir}
-docfile:: {docfile}
-imagesdir:: {imagesdir}
-
-.Custom
-sourcedir:: {sourcedir}
-
-== Includes
-
-WARNING: Includes can be tricky!
-

target/generated-docs-custom-theme/BPI-CM4-datasheet.adoc-bk

@@ -0,0 +1,647 @@
+= Banana Pi Compute Module 4
+:outlinelevels: 3
+Hulk Wang
+:example-caption!:
+ifndef::imagesdir[:imagesdir: images]
+
+<<<
+toc::[]
+
+== Chapter 1. Introduction
+
+=== 1.1 Introduction
+
+image::BPI-CM4.jpg[scaledwidth=75%, title="The BPI-CM4"]
+
+The Banana Pi Compute Module 4(CM4)is a System on Module(SoM) containing processor,DRAM, eMMC Flash and supporting power circuitry. These modules allow a designer touse the Banana Pi hardware and software stack in their own custom systems and formfactors. And, These modules offer additional IO interfaces beyond what is provided on Banana Pi boards, providing designers with more options.
+
+The design of the CM4 is loosely based on the Amlogic A311D, Quad core ARM Cortex-A73 and dual core ARM Cortex-A53 CPU , ARM G52MP4(6EE) GPU,NPU for AI at 5.0 TOPS, support Camera and MIPI-CSI interface ,HDMI output,2 Gigabit port . 4G RAM and 16 GB eMMC flash.
+
+for A311D chip PIN limited . just support 1 HDMI ,1 CSI and 1 DSI , Raspberry Pi support 2 HDMI ,2 CSI and 2 DSI , Other is Pin2Pin . you can use Raspberry Pi CM4 baseboard.
+
+NOTE: for A311D chip PIN limited . just support 1 HDMI ,1 CSI and 1 DSI , Raspberry Pi support 2 HDMI ,2 CSI and 2 DSI , Other is Pin2Pin . you can use Raspberry Pi CM4 baseboard.
+
+<<<
+
+=== 1.2 Key Feature
+
+Key feature of the BPI-CM4 are as follows:
+
+* Amlogic A311D  Quad core ARM Cortex-A73 and dual core ARM Cortex-A53,ARM G52 MP4(6EE) GPU
+* NPU for AI  Next generation, deep-neural-network applications, at 5.0 TOPS 
+* OpenGL ES 3.2, Vulkan 1.1 and OpenCL 2.0 support
+* 4GB LPDDR4 RAM 
+* 16GB eMMC flash (Max 128G) 
+* MIPI DSI :
+** 1x4-Lane MIPI DSI Display Interface 
+* MIPI CSI :
+** 1x4-Lane MIPI CSI Camera Interface
+* PCIe Interface:
+** 1xPCIe 1-Lane Host,Gen 2(5Gbps)
+* HDMI Interface:
+** 1xHDMI 2.1 Output Interface(up tp 4Kx2K@60)
+* Gigabit Ethernet PHY supporting
+* GPIOs:
+** PCM
+** IIC
+** IIS
+** SPI
+** UART
+** PWM
+** ...
+* Single +5V PSU Input
+* Support Android and Linux system
+* Size: 55x40mm
+
+
+== Chapter 2. Interfaces
+
+=== 2.1 Wireless
+
+The BPI-CM4 supports an onboard wireless module based on Realtek RTL8822CS,supports both
+
+* 2.4GHz & 5GHz IEEE 802.11 a/b/g/n/ac 2x2 MIMO wireless
+* Bluetooth 5.0 BR/EDR/LE
+
+These wireless interfaces can be individually enabled or disabled as required via CPU GPIO. In the case of many application environments, a service engineer can enable wireless operation and then disable it when done.
+
+The CPU can also turn on the wireless by itself for data communication, and turn ff the wireless after completion to reduce power consumption.
+
+The BPI-CM4 has two standard IPEX-1G connector on the module, If you want to use 2x2 MIMO, need to connect 2x 2.4G&5G antenna.
+
+Banana Pi Ltd has an antenna kit which is certified to be used with the BPI-CM4. If a different antenna is used then separate certification will be required.
+
+=== 2.2 Ethernet
+
+The BPI-CM4 has an onboard Gigabit Ethernet PHY - the https://www.realtek.com/en/products/connected-media-ics/item/rtl8211f-i-cg[REALTEK RTL8211F] - some of the major features of this PHY include;
+
+* IEEE 802.3az-2010
+* Built-in Wake-on-LAN
+* Crossover Detection & Auto-Correction
+
+A standard RJ45 connector is necessary to provid an Ethernet connection to the BPI-CM4.Can be see in link:#EthSch[Figure 2]
+
+[#EthSch]
+image::EthernetSch.jpg[title="Ethernet Schematic", alt=EthSch]
+
+The differential Ethernet signals should be routed as 100Ω differential pairs, with suitable clearances. Length matching between pairs should be better than 50mm, so in the typical case no length matching is required. However the signals within a pair need to be length matched, ideally to better than 0.15mm.
+
+The PHY also supports up to 2 LEDs to give user status feedback, these are low active. These LEDs can have a range of functions, and you should consult your OS driver to see which functions are supported by your driver.
+
+=== 2.3 PCIe(Gen2 x1)
+
+The BPI-CM4 has an internal PCIe2.0 x1 host controller. Connecting a PCIe device follows the standard PCIe convention.The CM4 has onboard AC coupling capacitors for *PCIe_CLK* and *PCIe_TX* signals.However the *PCIe_RX* signals need external coupling capacitors close to the driving source (the device *TX*), if you are using an external PCIe/NVMe cards these capacitors will be onboard. The PCIe conversion is that if you are wiring directly to an IC then the TX and RX pairs need to be swapped (TX->RX, RX->TX). If you are wiring to a connector then this is typically labelled from the host post of view and so TX RX swaps aren’t required. Additionally the *PCIECK_REQN* must be connected to ensure the CM4 produces a clock signal, and the *PERST0_N* should also be connected to ensure the device is correctly reset when required. The differential PCIe signals should be routed as 100Ω differential pairs, with suitable clearances. There is no need to match the lengths between pairs, only the signals within a Pair need to be length matched ideally to better than 0.1mm
+
+TIP: 5.10 kernel and .......
+
+=== 2.4 USB 2.0(HS)/3.0(SS)
+
+The USB 2.0 interface supports up to 480MBps signalling. The differential pair should be routed as a 90Ω differential pair. The P N signals should ideally be matched to better than 0.15mm.
+
+.USB 3.0 or PCIe 2.0 x1
+IMPORTANT: *USB 3.0* multiplexed with *PCIe 2.0 x1*. *USB30_RX_P/N* multiplexed with *PCIe_RX_P/N* and *USB30_TX_P/N* multiplexed with *PCIe_TX_P/N*.
+
+BPI-CM4 has two full-speed USB channels, one of which (USB_A) can be USB2.0 x1+ PCIe2.0 x1 or USB3.0 x1, or can use FE1.1s chip (USB 2.0 HUB chip) or VL807 (USB 3.0 HUB chip) Expanded to four-way USB.The other one (USB_B) interface also has OTG(On-The-Go) function at the same time.
+
+=== 2.5 GPIO
+
+BPI-CM4 has 17 pins available for general purpose I/O (GPIO),corresponding to the first half of the standard 40 pins of other BananaPi development boards.These pins have access to internal peripherals;PCM, IIC, UART and PWM. https://drive.google.com/file/d/1IXXok1P2OLiW3p8tavkbfEPTGTrM3b-R/view?usp=sharing[BPI-CM4 Sch  ^] describes these features in detail, and the multiplexing options available. The drive strength and slew rate should ideally be set as low as possible to reduce any EMC issues.GPIOX_17 and GPIOX_18 have 2.2K pull up resistors.
+
+By default, GPIO bank is powered by 3V3, but GPIOX_x GPIOs can be changed to powered by 1.8V.
+
+NOTE: *GPIOX_x* Power Bank depending on the selected WiFi module, PCIe WiFi or RTL WiFi (default) is powered by 3.3V, and AMPAK 6275s WiFi is powered by 1.8V.
+
+image::GPIO.jpg[title="GPIO", alt=GPIO]
+
+==== 2.5.1 Alternative Function Assignments
+
+.GPIO Alternative Function Assignments
+[.autowidth.stretch, cols="^2,3,2,2,6,5"]
+|===
+|Num|GPIOx_x |PD/PU |ALT0 |ALT1 |ALT2
+
+|3 |GPIOX_17 |PU |GPIO |I2C_EE_M2_SDA |BT_EN
+|5 |GPIOX_18 |PU |GPIO |I2C_EE_M2_SCL |BT_WAKE_HOST
+|7 |GPIOH_5 |PU |GPIO |SPDIF_IN |
+|8 |GPIOX_6 |PU |GPIO |UART_B_TX |WIFI_PWREN
+|10 |GPIOx_7 |PU |GPIO |UART_B_RX |WIFI_WAKE_HOST
+|11 |GPIOAO_10 |PD |GPIO | | 
+|12 |GPIOA_1 |PU |GPIO |I2SB_SCLK | 
+|13 |GPIOH_4 |PD |GPIO |SPDIF_OUT |
+|15 |GPIOAO_5 |PU |GPIO |IR_IN |
+|16 |GPIOA_0 |PU |GPIO |I2S_MCLK |
+|18 |GPIOA_2 |PD |GPIO |I2SB_LRCLK |
+|19 |GPIOX_8 |PU |GPIO |SPI_A_MOSI |BTPCM_DIN
+|21 |GPIOX_9 |PU |GPIO |SPI_A_MISO |BTPCM_DOUT
+|22 |GPIOA-7 |PU |GPIO |I2SC_DOUT_DIN_3 |
+|23 |GPIOX_11 |PU |GPIO |SPI_A_CLK |BTPCM_CLK
+|24 |GPIOX_10 |PU |GPIO |SPI_A_SS0 |BTPCM_SYNC
+|26 |GPIOA_3 |PU |GPIO |I2SB_DOUT_DIN_0 |
+|===
+
+=== 2.6 HDMI
+
+The BPI-CM4 supports one HDMI 2.1 interface, it capable of driving 4Kx2K 60fps output.
+
+HDMI signals should be routed as 100Ω differential pairs, each signal within a pair should ideally be matched to better than 0.15mm.Pairs don’t typically need any extra matching as they only have to be matched to 25mm.
+
+CEC, Dynamic HDR and HDCP 2.2 supported. CEC internal 27K pullup resistor and *HDMI_SDA*/*HDMI_SCL* internal 27K pullup resistor is included in the BPI-CM4.
+
+The BPI-CM4 need extra ESD protection maybe required.
+
+=== 2.7 CSI(MIPI Serial Camera)
+
+The BPI-CM4 supports one camera ports(4 lanes); CSI signals should be routed as 100Ω differential pairs, each signal within a pair should ideally be matched to better than 0.15mm.
+
+The documentation around the CSI interface can be found on the https://wiki.banana-pi.org/BPI-CM4_Computer_module_and_development_Kit[BananaPi Wiki] website while Linux kernel drivers can be found on https://github.com/BPI-SINOVOIP/BPI-M2S-bsp[Github].
+
+NOTE: Camera sensors supported by the official BananaPi firmware are;ShenZhenShi HongJia OS08A10 V11(sensor: OS08A20). no security device is required on Compute Module devices to use these camera sensors.
+
+=== 2.8 DSI(MIPI Serial Display)
+
+The BPI-CM4 supports one display ports(4 lanes); supports a maximum of data rate per lane of 1Gbit/s.
+
+The DSI interface only supported by offical BananaPi firmware are supported DSI Displays, more infomation can see https://wiki.banana-pi.org/BPI-CM4_Computer_module_and_development_Kit[BananaPi Wiki] website.DSI signals should be routed as 100Ω differential pairs, each signal within a pair should ideally be matched to better than 0.15mm.
+
+NOTE: BananaPi firmware only supports officially recommended DSI displays, but add and compile your own driver.
+
+=== 2.9 IIC(GPIO Pin3&Pin5)
+
+This IIC bus is not shared with CSI or DSI and can be used arbitrarily.
+
+=== 2.10 IIC(CAM0_SCK/SDA)
+
+This IIC bus(GPIOH_7/GPIOH_6) is used by default for MIPI CSI(Camera sensor), If you don't use, it can also be used for general purpose I/O or to connect other IIC devices.
+
+=== 2.11 IIC(TP_SCK/SDA)
+
+This IIC bus(GPIOA_15/GPIOA_14) is used by default for MIPI DSI Touch Panel(capacitive touch panel), If you don't use, it can also be used for general purpose I/O or to connect other IIC devices.
+
+NOTE: All IIC buses have 2K2 pull-up resistors on BPI-CM4
+
+=== 2.12 SDIO/eMMC()
+
+The BPI-CM4 supported 16GB eMMC flash (option up to 128GB). The *TF_VDD_EN* signal is used to enable an external power switch to turn on power to the TF_Card. If booting from TF_Card is required then a pullup resistor must also be fitted to default the power to be on. 
+
+image::TF_Card.jpg[title="TF Card", alt=TF_CARD]
+
+=== 2.13 Analog(SARADC_CH2/CH3)
+
+These are the two ADC pins straight out of the CPU.No onboard filtering, 100K pull-up resistors on BPI-CM4.
+
+NOTE: If you need to use these two ADC pins, you need to consider adding filtering, the recommended value is 1000pF ~ 0.1uF
+
+=== 2.14 *CPU_RST*
+
+Pulling this pin low places BPI-CM4 in reset. Removing the pull-down state allows the BPI-CM4 to reset and run again.
+
+TIP: To reset BPI-CM4, the *CPU_RST* pin needs to be pulled low for at least 0ms.T~CPU_RST_L~>0ms.
+
+=== 2.15 *SYS_LED*
+
+This pin is designed to drive an LED to show the BPI-CM4 operating status. If an error occurs during startup, it will blink with the *SYS_LED2* beyond expectations to help the user easily determine the status.
+
+=== 2.16 *SYS_LED2*
+
+This pin is designed to drive an LED to show the BPI-CM4 operating status. If an error occurs during startup, it will blink with the *SYS_LED2* beyond expectations to help the user easily determine the status.
+
+<<<
+
+
+== Chapter 3. Electrical and Mechanical
+
+=== 3.1 Mechanical
+
+The BPI-CM4 is a compact 40 × 55mm module. The Module is 4.1mm deep, but usually the height after connection is 4.4mm.
+
+TIP: The height of 4.4mm after connection is the minimum height between the connector and the fixing stud recommended by bpi. If other connectors and fixing studs of the corresponding height are used, the height needs to be actually measured.
+
+. 4 × M3 Mounting holes (inset about 4mm from module edge)
+. PCB thickness 1.2mm ± 10%
+. https://drive.google.com/file/d/1SRAY_RDxKhw819uyo9H13zNN2wlG6LDq/view?usp=sharing[Amlogic A311D] SoC height including solder balls 1.0 ± 0.11mm
+. Stacking height either:
+.. 1.5mm with mating connector (clearance under CM4 0mm) : DF40C-100DS-0.4v
+.. 3.0mm with mating connector (clearance under CM4 1.5mm): DF40HC(3.0)-100DS-0.4v
+
+If the wireless antenna is used  it must be orientated towards the edge of the plastic enclosure and any close by metal must have cut outs or the wireless performance will be degraded.It is recommended to fix the antenna outside the case.
+
+image::Mechanical.jpg[title="Mechanical", alt=Mechanical, width=75%]
+
+NOTE: The location and arrangement of components on the Compute Module may change slightly over time due to revisions for cost and manufacturing considerations; however the maximum component heights and PCB thickness will be kept as specified.
+
+=== 3.2 Thermal
+
+The BPI-CM4 has less passive cooling due to its smaller size, so it may run hotter.In order to ensure the life of BPI-CM4, the core temperature of the main control chip(Amlogic A311D) should be kept below 85 degrees Celsius as much as possible.If the core temperature is found to be higher than 85 degrees Celsius, you can reduce the clock frequency or add additional active and passive cooling methods.
+
+It is important that thermal solution chosen keeps the ambient temperature for the other silicon devices on the CM4 within the operating temperature range.
+
+Operating temperature range: -20°C - +85°C Non-condensing. 
+
+=== 3.3  Electrical Specification
+
+WARNING: Stresses above those listed in Table 3 may cause permanent damage to the device. This is a stress rating only; functional operation of the device under these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
+
+.Absolute maximum ratings
+[.autowidth.stretch, cols="2,4,2,2,2"]
+|===
+|Symbol |Parameter |Min. |Max. |Unit 
+
+|V~IN~ |+5V_Input |-0.5 |6 |V
+|V~GPIO_ref~ |GPIO Voltage |-0.5 |3.6 |V
+|V~GPIO~ |GPIO INPUT Voltage |-0.5 |V~GPIO_ref~+0.5 |V
+|===
+
+==== DC Electrical Characteristics
+
+.Normal GPIO Specifications (For DIO)
+[.autowidth.stretch,cols="2,4,2,2,2,1"]
+|===
+|Symbol |Parameter |Min. |Typ. |Max. |Unit
+
+|V~IH(gpio)~ |High-level Input Voltage |*IOVREF*/2+0.3 | |VDDIO+0.3 |V
+|V~IL(gpio)~ |Low-level Input Voltage |-0.3 | |*IOVREF*/2-0.3 |V
+|R~PU/PD~ |Built-in pull Up/Down resistor | |60K | |ohm
+|IoH/IoL |GPIO driving capability |4^1)^ | |6^2)^ |mA
+|VOH |Output high level with 4 mA loading |VDDIO-0.5 | | |V
+|VOL |Output low level with 4 mA loading | | |0.4 |V
+|===
+
+NOTE: Minimal driving capability applies when VDDIO LV 1.71V, or VDDIO HV 3.0V, VOL<0.4V
+Maximal driving capability only applies to applications such as driving LED when VOL<0.6V.
+
+.Open Drain GPIO Specifications (For DIO_OD)
+[.autowidth.stretch,cols="2,4,2,2,2,1"]
+|===
+|Symbol |Parameter |Min. |Typ. |Max. |Unit
+
+|V~IH(OD5V)~ |High-level Input Voltage |2.2 | |5.5 |V
+|V~IL(OD5V)~ |Low-level Input Voltage |-0.3 | |0.8 |V
+|V~IH(OD3.3V)~ |High-level Input Voltage |2.2 | |3.6 |V
+|V~IL(OD3.3V)~ |Low-level Input Voltage |-0.3 | |0.8 |V
+|R~PU/PD~ |No built-in pull up/down resistor on OD IO |- |- |- |ohm
+|Io |OD IO driving low capability |4^1)^ | |6^2)^ |mA
+|VOL |Output low level with mini Io loading | | |0.4 |V
+|===
+
+NOTE: Minimal driving capability applies when VDDIO LV 1.71V, or VDDIO HV 3.0V, VOL<0.4V
+Maximal driving capability only applies to applications such as driving LED when VOL<0.6V.
+
+== Chapter 4. Pin Out
+
+=== 4.1 Pin out define
+
+.Pin out define of BPI-CM4
+[cols="^1,3,9"]
+|===
+|Pin Num |Signal |Description
+
+| 1   | GND                     | Ground (0V)
+| 2   | GND                     | Ground (0V)
+| 3   | NAT0_MDI3p              | Ethernet MDI 3 Positive (connect to Transformer or RJ45 Connector)
+| 4   | NAT0_MDI1p              | Ethernet MDI 1 Positive (connect to Transformer or RJ45 Connector)
+| 5   | NAT0_MDI3n              | Ethernet MDI 3 Negative (connect to Transformer or RJ45 Connector)
+| 6   | NAT0_MDI1n              | Ethernet MDI 1 Negative (connect to Transformer or RJ45 Connector)
+| 7   | GND                     | Ground (0V)
+| 8   | GND                     | Ground (0V)
+| 9   | NAT0_MDI2n              | Ethernet MDI 2 Negative (connect to Transformer or RJ45 Connector)
+| 10  | NAT0_MDI0n              | Ethernet MDI 0 Negative (connect to Transformer or RJ45 Connector)
+| 11  | NAT0_MDI2p              | Ethernet MDI 2 Positive (connect to Transformer or RJ45 Connector)
+| 12  | NAT0_MDI0p              | Ethernet MDI 0 Positive (connect to Transformer or RJ45 Connector)
+| 13  | GND                     | Ground (0V)
+| 14  | GND                     | Ground (0V)
+| 15  | Ethernet_LED2/1G_Active | Low Active Ethernet Activity indicator (3.3V signal) Typically a Yellow LED is connected to this pin.Represents the negotiated rate
+| 16  | LINUX_Debug_RX          | Debug Uart RX.Usually under Linux system
+| 17  | Ethernet_LED1/Link      | Low Active Ethernet Activity indicator (3.3V signal) Typically a Green LED is connected to this pin.Represents the link state
+| 18  | LINUX_Debug_TX          | Debug Uart TX.Usually under Linux system
+| 19  | Ethernet_0_LED0/CFG_EXT | Reserved.From PHY chip    
+| 20  | NC                      | No connection pin.
+| 21  | SYS_LED2                | Low Active Pi Activity LED.Max 3.3V tolerant (VOL<0.4V). Default drives the Green LED
+| 22  | GND                     | Ground (0V)
+| 23  | GND                     | Ground (0V)
+| 24  | GPIOA_0                 | General purpose input/output bank A signal 0.Typically a 3.3V signal
+| 25  | GPIOA_3                 | General purpose input/output bank A signal 3.Typically a 3.3V signal
+| 26  | GPIOA_2                 | General purpose input/output bank A signal 2.Typically a 3.3V signal
+| 27  | GPIOA_4                 | General purpose input/output bank A signal 4.Typically a 3.3V signal
+| 28  | GPIOA_7                 | General purpose input/output bank A signal 7.Typically a 3.3V signal
+| 29  | GPIOAO_11               | General purpose input/output bank AO signal 11.Typically a 3.3V signal
+| 30  | GPIOAO_10               | General purpose input/output bank AO signal 10.Typically a 3.3V signal
+| 31  | GPIOH_5                 | General purpose input/output bank H signal 5.Typically a 3.3V signal
+| 32  | GND                     | Ground (0V)
+| 33  | GND                     | Ground (0V)
+| 34  | GPIOH_4                 | General purpose input/output bank H signal 4.Typically a 3.3V signal
+| 35  | GPIOA_15                | General purpose input/output bank A signal 15.Typically a 3.3V signal
+| 36  | GPIOA_14                | General purpose input/output bank A signal 14.Typically a 3.3V signal
+| 37  | GPIOAO_5                | General purpose input/output bank AO signal 5.Typically a 3.3V signal
+| 38  | GPIOX_11                | General purpose input/output bank X signal 11.Typically a 3.3V signal
+| 39  | GPIOX_10                | General purpose input/output bank X signal 10.Typically a 3.3V signal
+| 40  | GPIOX_9                 | General purpose input/output bank X signal 9.Typically a 3.3V signal
+| 41  | GPIOA_11                | General purpose input/output bank A signal 11.Typically a 3.3V signal
+| 42  | GND                     | Ground (0V)
+| 43  | GND                     | Ground (0V)
+| 44  | GPIOX_8                 | General purpose input/output bank X signal 8.Typically a 3.3V signal
+| 45  | GPIOA_12                | General purpose input/output bank A signal 12.Typically a 3.3V signal
+| 46  | GPIOA_5                 | General purpose input/output bank A signal 5.Typically a 3.3V signal
+| 47  | GPIOA_13                | General purpose input/output bank A signal 13.Typically a 3.3V signal
+| 48  | GPIOA_6                 | General purpose input/output bank A signal 6.Typically a 3.3V signal
+| 49  | GPIOA_1                 | General purpose input/output bank A signal 1.Typically a 3.3V signal
+| 50  | GPIOA_9                 | General purpose input/output bank A signal 9.Typically a 3.3V signal
+| 51  | GPIOX_7                 | General purpose input/output bank X signal 7.Typically a 3.3V signal
+| 52  | GND                     | Ground (0V)
+| 53  | GND                     | Ground (0V)
+| 54  | GPIOA_10                | General purpose input/output bank A signal 10.Typically a 3.3V signal.
+| 55  | GPIOX_6                 | General purpose input/output bank X signal 6.Typically a 3.3V signal.
+| 56  | GPIOX_18                | General purpose input/output bank X signal 18.Typically a 3.3V signal.
+| 57  | SD_CLK_B                | SDCARD Clock signal.
+| 58  | GPIOX_17                | General purpose input/output bank X signal 17.Typically a 3.3V signal.
+| 59  | GND                     | Ground (0V)
+| 60  | GND                     | Ground (0V)
+| 61  | SD_D3_B                 | SDCARD Data3 signal.
+| 62  | SD_CMD_B                | SDCARD Command signal.
+| 63  | SD_D0_B                 | SDCARD Data0 signal.
+| 64  | NC                      | No connection pin.
+| 65  | GND                     | Ground (0V)
+| 66  | GND                     | Ground (0V)
+| 67  | SD_D1_B                 | SDCARD Data1 signal.
+| 68  | NC                      | No connection pin.
+| 69  | SD_D2_B                 | SDCARD Data2 signal.
+| 70  | NC                      | No connection pin.
+| 71  | GND                     | Ground (0V)
+| 72  | NC                      | No connection pin.
+| 73  | NC                      | No connection pin.
+| 74  | GND                     | Ground (0V)
+| 75  | TF_VDD_EN               | Output to Power switch for the SDCARD. The CM4 sets this pin High (3.3V) to signal that Power to the SDCARD should be turned on. If booting from the SDCARD is required then a pullup should also be fitted so the power defaults to on.
+| 76  | CARD_DET                | SDCARD detection signal.
+| 77  | +5V_Input               | 4.75V-5.25V Main power input
+| 78  | NC                      | No connection pin.
+| 79  | +5V_Input               | 4.75V-5.25V Main power input.
+| 80  | GPIOH_7                 | General purpose input/output bank H signal 7.Typically a 3.3V signal.
+| 81  | +5V_Input               | 4.75V-5.25V Main power input.
+| 82  | GPIOH_6                 | General purpose input/output bank H signal 6.Typically a 3.3V signal.
+| 83  | +5V_Input               | 4.75V-5.25V Main power input..
+| 84  | CM4_3V3_OUTPUT          | 3.3V +/-2.5% Power Output.Usually not used as an extended power supply it can be used as a reference potential.
+| 85  | +5V_Input               | 4.75V-5.25V Main power input.
+| 86  | CM4_3V3_OUTPUT          | 3.3V +/-2.5% Power Output.Usually not used as an extended power supply it can be used as a reference potential.
+| 87  | +5V_Input               | 4.75V-5.25V Main power input.
+| 88  | CM4_1V8_OUTPUT          | 1.8V +/-2.5% Power Output.Usually not used as an extended power supply it can be used as a reference potential.
+| 89  | NC                      | No connection pin.
+| 90  | CM4_1V8_OUTPUT          | 1.8V +/-2.5% Power Output.Usually not used as an extended power supply it can be used as a reference potential.
+| 91  | NC                      | No connection pin.
+| 92  | CPU_RST                 | System reset input.Pull low to reset the system.
+| 93  | NC                      | No connection pin.
+| 94  | SARADC_CH3              | ADC channel 3 input.In the official firmware this pin is used as Hardware ID.
+| 95  | SYS_LED                 | Low active Output to drive Power On LED.
+| 96  | ADC_KEY                 | ADC channel 2 input.In the official firmware this pin is used as AD_KEY.
+| 97  | NC                      | No connection pin.
+| 98  | GND                     | Ground (0V)
+| 99  | NC                      | No connection pin.
+| 100 | GPIOH_8                 | General purpose input/output bank H signal 8.Typically a 3.3V signal.
+| 101 | USBOTG_B_ID             | USB OTG mini-receptacle identifier.
+| 102 | PCIECK_REQN             | request-acknowledge communication between PCIe devices.
+| 103 | USBOTG_B_DM             | USB 2.0 Port B negative data signal(OTG).
+| 104 | USB_A_DP                | USB 2.0 Port A positive data signal(HOST only).
+| 105 | USBOTG_B_DP             | USB 2.0 Port B positive data signal(OTG).
+| 106 | USB_A_DM                | USB 2.0 Port A negative data signal(HOST only).
+| 107 | GND                     | Ground (0V)
+| 108 | GND                     | Ground (0V)
+| 109 | PERST0_N                | Used to control the reset operation of PCIe devices.
+| 110 | PCIE_CLKP               | PCIE reference clock positive signal.
+| 111 | NC                      | No connection pin.
+| 112 | PCIE_CLKN               | PCIE reference clock negative signal.
+| 113 | GND                     | Ground (0V)
+| 114 | GND                     | Ground (0V)
+| 115 | MIPI_CSI_D0N            | MIPI CSI data 0 negative input
+| 116 | PCIE_SOC_RXP            | PCIE or USB3.0 input positive signal
+| 117 | MIPI_CSI_D0P            | MIPI CSI data 0 positive input
+| 118 | PCIE_SOC_RXN            | PCIE or USB3.0 input negative signal
+| 119 | GND                     | Ground (0V)
+| 120 | GND                     | Ground (0V)
+| 121 | MIPI_CSI_D1N            | MIPI CSI data 1 negative input
+| 122 | PCIE_TX0_P              | PCIE or USB3.0 output positive signal
+| 123 | MIPI_CSI_D1P            | MIPI CSI data 1 positive input
+| 124 | PCIE_TX0_N              | PCIE or USB3.0 input negative signal
+| 125 | GND                     | Ground (0V)
+| 126 | GND                     | Ground (0V)
+| 127 | MIPI_CSI_CLKAN          | MIPI CSI CLK negative input for channel A
+| 128 | NC                      | No connection pin.
+| 129 | MIPI_CSI_CLKAP          | MIPI CSI CLK positive input for channel A
+| 130 | NC                      | No connection pin.
+| 131 | GND                     | Ground (0V)
+| 132 | GND                     | Ground (0V)
+| 133 | MIPI_CSI_D2N            | MIPI CSI data 2 negative input
+| 134 | NC                      | No connection pin.
+| 135 | MIPI_CSI_D2P            | MIPI CSI data 2 positive input
+| 136 | NC                      | No connection pin.
+| 137 | GND                     | Ground (0V)
+| 138 | GND                     | Ground (0V)
+| 139 | MIPI_CSI_D3N            | MIPI CSI data 3 negative input
+| 140 | MIPI_CSI_CLKBN          | MIPI CSI CLK negative input for channel B
+| 141 | MIPI_CSI_D3P            | MIPI CSI data 3 positive input
+| 142 | MIPI_CSI_CLKBP          | MIPI CSI CLK negative input for channel B
+| 143 | NC                      | No connection pin.
+| 144 | GND                     | Ground (0V)
+| 145 | NC                      | No connection pin.
+| 146 | NC                      | No connection pin.
+| 147 | NC                      | No connection pin.
+| 148 | NC                      | No connection pin.
+| 149 | NC                      | No connection pin.
+| 150 | GND                     | Ground (0V)
+| 151 | HDMI_TXCEC              | HDMI CEC signal.
+| 152 | NC                      | No connection pin.
+| 153 | HDMI_HPDC               | HDMI Hot Plugin Detection
+| 154 | NC                      | No connection pin.
+| 155 | GND                     | Ground (0V)
+| 156 | GND                     | Ground (0V)
+| 157 | NC                      | No connection pin.
+| 158 | NC                      | No connection pin.
+| 159 | NC                      | No connection pin.
+| 160 | NC                      | No connection pin.
+| 161 | GND                     | Ground (0V)
+| 162 | GND                     | Ground (0V)
+| 163 | NC                      | No connection pin.
+| 164 | NC                      | No connection pin.
+| 165 | NC                      | No connection pin.
+| 166 | NC                      | No connection pin.
+| 167 | GND                     | Ground (0V)
+| 168 | GND                     | Ground (0V)
+| 169 | Reserved                | Reserved.Audio DAC line-out right channel positive signal
+| 170 | HDMI_TX2P               | HDMI TMDS data 2 positive output
+| 171 | Reserved                | Reserved.Audio DAC line-out left channel positive signal
+| 172 | HDMI_TX2N               | HDMI TMDS data 2 negative output
+| 173 | GND                     | Ground (0V)
+| 174 | GND                     | Ground (0V)
+| 175 | MIPI_D0_N               | MIPI DSI data 0 negative output or Bidirectional in LP mode.
+| 176 | HDMI_TX1P               | HDMI TMDS data 1 positive output.
+| 177 | MIPI_D0_P               | MIPI DSI data 0 positive output or Bidirectional in LP mode.
+| 178 | HDMI_TX1N               | HDMI TMDS data 1 negative output.
+| 179 | GND                     | Ground (0V)
+| 180 | GND                     | Ground (0V)
+| 181 | MIPI_D1_N               | MIPI DSI data 1 negative output.
+| 182 | HDMI_TX0P               | HDMI TMDS data 0 positive output.
+| 183 | MIPI_D1_P               | MIPI DSI data 1 positive output.
+| 184 | HDMI_TX0N               | HDMI TMDS data 0 negative output.
+| 185 | GND                     | Ground (0V)
+| 186 | GND                     | Ground (0V)
+| 187 | MIPI_CLK_N              | MIPI DSI clock negative output.
+| 188 | HDMI_TXCP               | HDMI TMDS clock positive output.
+| 189 | MIPI_CLK_P              | MIPI DSI clock positive output.
+| 190 | HDMI_TXCN               | HDMI TMDS clock negative output.
+| 191 | GND                     | Ground (0V)
+| 192 | GND                     | Ground (0V)
+| 193 | MIPI_D2_N               | MIPI DSI data 2 negative output.
+| 194 | MIPI_D3_N               | MIPI DSI data 3 negative output.
+| 195 | MIPI_D2_P               | MIPI DSI data 2 positive output.
+| 196 | MIPI_D3_P               | MIPI DSI data 3 positive output.
+| 197 | GND                     | Ground (0V)
+| 198 | GND                     | Ground (0V)
+| 199 | HDMI_SDA                | HDMI SDA(IIC) signal. 2.2K pull-up resistors on BPI-CM4
+| 200 | HDMI_SCL                | HDMI SCL(IIC) signal. 2.2K pull-up resistors on BPI-CM4
+|===
+
+<<<
+
+=== 4.2 Pin comparison between BPI-CM4 and  Raspberry Pi Compute Module 4
+
+.Pin comparison between BPI-CM4 and  Raspberry Pi Compute Module 4
+[cols="3,3,^1,^1,3,3"]
+|===
+|RPI CM4                   |BPI-CM4                  |Pin Num |Pin Num            |BPI-CM4 |RPI CM4
+
+| GND                      | GND                     | 1   | 2   | GND            | GND                
+| Ethernet_Pair3_P         | NAT0_MDI3p              | 3   | 4   | NAT0_MDI1p     | Ethernet_Pair1_P   
+| Ethernet_Pair3_N         | NAT0_MDI3n              | 5   | 6   | NAT0_MDI1n     | Ethernet_Pair1_N   
+| GND                      | GND                     | 7   | 8   | GND            | GND                
+| Ethernet_Pair2_N         | NAT0_MDI2n              | 9   | 10  | NAT0_MDI0n     | Ethernet_Pair0_N   
+| Ethernet_Pair2_P         | NAT0_MDI2p              | 11  | 12  | NAT0_MDI0p     | Ethernet_Pair0_P   
+| GND                      | GND                     | 13  | 14  | GND            | GND                
+| Ethernet_nLED3_1G-Active | Ethernet_LED2/1G_Active | 15  | 16  | LINUX_Debug_RX | Ethernet_SYNC_IN   
+| Ethernet_nLED2_1G-Link   | Ethernet_LED1/Link      | 17  | 18  | LINUX_Debug_TX | Ethernet_SYNC_OUT  
+| Ethernet_nLED1_Y         | Ethernet_0_LED0/CFG_EXT | 19  | 20  | NC             | EEPROM_nWP         
+| Pi_nLED_Activity         | SYS_LED2                | 21  | 22  | GND            | GND                
+| GND                      | GND                     | 23  | 24  | GPIOA_0        | I2S_MCLK/GPIO26    
+| GPIO21/I2S_DO            | GPIOA_3                 | 25  | 26  | GPIOA_2        | I2S_LRCLK/GPIO19   
+| GPIO20/I2S_DI            | GPIOA_4                 | 27  | 28  | GPIOA_7        | GPIO13             
+| GPIO16                   | GPIOAO_11               | 29  | 30  | GPIOAO_10      | GPIO6              
+| GPIO12                   | GPIOH_5                 | 31  | 32  | GND            | GND                
+| GND                      | GND                     | 33  | 34  | GPIOH_4        | GPIO5              
+| ID_SC                    | GPIOA_15                | 35  | 36  | GPIOA_14       | ID_SD              
+| GPIO7/SPI-CE1            | GPIOAO_5                | 37  | 38  | GPIOX_11       | SPI-CLK/GPIO11     
+| GPIO8/SPI-CE0            | GPIOX_10                | 39  | 40  | GPIOX_9        | SPI-MISO/GPIO9     
+| GPIO25                   | GPIOA_11                | 41  | 42  | GND            | GND                
+| GND                      | GND                     | 43  | 44  | GPIOX_8        | SPI-MOSI/GPIO10    
+| GPIO24/UART0-CTS         | GPIOA_12                | 45  | 46  | GPIOA_5        | GPIO22             
+| GPIO23/UART0-RTS         | GPIOA_13                | 47  | 48  | GPIOA_6        | UART1-RXD/GPIO27   
+| GPIO18/I2S_SCLK          | GPIOA_1                 | 49  | 50  | GPIOA_9        | UART1-TXD/GPIO17   
+| GPIO15/UART0-RXD         | GPIOX_7                 | 51  | 52  | GND            | GND                
+| GND                      | GND                     | 53  | 54  | GPIOA_10       | PWM/GPIO4          
+| GPIO14/UART0-TXD         | GPIOX_6                 | 55  | 56  | GPIOX_18       | SCL/GPIO3          
+| SD_CLK                   | SD_CLK_B                | 57  | 58  | GPIOX_17       | SDA/GPIO2          
+| GND                      | GND                     | 59  | 60  | GND            | GND                
+| SD_DAT3                  | SD_D3_B                 | 61  | 62  | SD_CMD_B       | SD_CMD             
+| SD_DAT0                  | SD_D0_B                 | 63  | 64  | NC             | SD_DAT5            
+| GND                      | GND                     | 65  | 66  | GND            | GND                
+| SD_DAT1                  | SD_D1_B                 | 67  | 68  | NC             | SD_DAT4            
+| SD_DAT2                  | SD_D2_B                 | 69  | 70  | NC             | SD_DAT7            
+| GND                      | GND                     | 71  | 72  | NC             | SD_DAT6            
+| SD_VDD_Override          | NC                      | 73  | 74  | GND            | GND                
+| SD_PWR_ON                | TF_VDD_EN               | 75  | 76  | CARD_DET       | Reserved/SD_DET    
+| +5V_Input                | +5V_Input               | 77  | 78  | NC             | GPIO_VREF          
+| +5V_Input                | +5V_Input               | 79  | 80  | GPIOH_7        | SCL0_Camera_3V3    
+| +5V_Input                | +5V_Input               | 81  | 82  | GPIOH_6        | SDA0_Camera_3V3    
+| +5V_Input                | +5V_Input               | 83  | 84  | CM4_3V3_OUTPUT | CM4_3V3_OUTPUT     
+| +5V_Input                | +5V_Input               | 85  | 86  | CM4_3V3_OUTPUT | CM4_3V3_OUTPUT     
+| +5V_Input                | +5V_Input               | 87  | 88  | CM4_1V8_OUTPUT | CM4_1V8_OUTPUT     
+| /WL_nDisable_3V3         | NC                      | 89  | 90  | CM4_1V8_OUTPUT | CM4_1V8_OUTPUT     
+| /BT_nDisable_3V3         | NC                      | 91  | 92  | CPU_RST        | RUN_PG/Reset_3V3   
+| /nRPIBOOT_3V3            | NC                      | 93  | 94  | SARADC_CH3     | AnalogIP1/USBC_CC2 
+| PI_LED_nPWR              | SYS_LED                 | 95  | 96  | ADC_KEY        | AnalogIP0/USBC_CC1 
+| Camera_PWD_GPIO          | NC                      | 97  | 98  | GND            | GND                
+| GLOBAL_EN_5V             | NC                      | 99  | 100 | GPIOH_8        | nEXTRST            
+| USB_OTG_ID_3V3           | USBOTG_B_ID             | 101 | 102 | PCIECK_REQN    | PCIe_CLK_nREQ_3V3  
+| USB_N                    | USBOTG_B_DM             | 103 | 104 | USB_A_DP       | Reserved           
+| USB_P                    | USBOTG_B_DP             | 105 | 106 | USB_A_DM       | Reserved           
+| GND                      | GND                     | 107 | 108 | GND            | GND                
+| PCIe_nRST_3V3            | PERST0_N                | 109 | 110 | PCIE_CLKP      | PCIe_CLK_P         
+| VDAC_COMP_TV             | NC                      | 111 | 112 | PCIE_CLKN      | PCIe_CLK_N         
+| GND                      | GND                     | 113 | 114 | GND            | GND                
+| CAM1_D0_N                | MIPI_CSI_D0N            | 115 | 116 | PCIE_SOC_RXP   | PCIe_RX_P          
+| CAM1_D0_P                | MIPI_CSI_D0P            | 117 | 118 | PCIE_SOC_RXN   | PCIe_RX_N          
+| GND                      | GND                     | 119 | 120 | GND            | GND                
+| CAM1_D1_N                | MIPI_CSI_D1N            | 121 | 122 | PCIE_TX0_P     | PCIe_TX_P          
+| CAM1_D1_P                | MIPI_CSI_D1P            | 123 | 124 | PCIE_TX0_N     | PCIe_TX_N          
+| GND                      | GND                     | 125 | 126 | GND            | GND                
+| CAM1_C_N                 | MIPI_CSI_CLKAN          | 127 | 128 | NC             | CAM0_D0_N          
+| CAM1_C_P                 | MIPI_CSI_CLKAP          | 129 | 130 | NC             | CAM0_D0_P          
+| GND                      | GND                     | 131 | 132 | GND            | GND                
+| CAM1_D2_N                | MIPI_CSI_D2N            | 133 | 134 | NC             | CAM0_D1_N          
+| CAM1_D2_P                | MIPI_CSI_D2P            | 135 | 136 | NC             | CAM0_D1_P          
+| GND                      | GND                     | 137 | 138 | GND            | GND                
+| CAM1_D3_N                | MIPI_CSI_D3N            | 139 | 140 | MIPI_CSI_CLKBN | CAM0_C_N           
+| CAM1_D3_P                | MIPI_CSI_D3P            | 141 | 142 | MIPI_CSI_CLKBP | CAM0_C_P           
+| HDMI1_HOTPLUG_5V         | NC                      | 143 | 144 | GND            | GND                
+| HDMI1_SDA_5V             | NC                      | 145 | 146 | NC             | HDMI1_TX2_P        
+| HDMI1_SCL_5V             | NC                      | 147 | 148 | NC             | HDMI1_TX2_N        
+| HDMI1_CEC_5V             | NC                      | 149 | 150 | GND            | GND                
+| HDMI0_CEC_5V             | HDMI_TXCEC              | 151 | 152 | NC             | HDMI1_TX1_P        
+| HDMI0_HOTPLUG_5V         | HDMI_HPDC               | 153 | 154 | NC             | HDMI1_TX1_N        
+| GND                      | GND                     | 155 | 156 | GND            | GND                
+| DSI0_D0_N                | NC                      | 157 | 158 | NC             | HDMI1_TX0_P        
+| DSI0_D0_P                | NC                      | 159 | 160 | NC             | HDMI1_TX0_N        
+| GND                      | GND                     | 161 | 162 | GND            | GND                
+| DSI0_D1_N                | NC                      | 163 | 164 | NC             | HDMI1_CLK_P        
+| DSI0_D1_P                | NC                      | 165 | 166 | NC             | HDMI1_CLK_N        
+| GND                      | GND                     | 167 | 168 | GND            | GND                
+| DSI0_C_N                 | NC                      | 169 | 170 | HDMI_TX2P      | HDMI0_TX2_P        
+| DSI0_C_P                 | NC                      | 171 | 172 | HDMI_TX2N      | HDMI0_TX2_N        
+| GND                      | GND                     | 173 | 174 | GND            | GNF                
+| DSI1_D0_N                | MIPI_D0_N               | 175 | 176 | HDMI_TX1P      | HDMI0_TX1_P        
+| DSI1_D0_P                | MIPI_D0_P               | 177 | 178 | HDMI_TX1N      | HDMI0_TX1_N        
+| GND                      | GND                     | 179 | 180 | GND            | GND                
+| DSI1_D1_N                | MIPI_D1_N               | 181 | 182 | HDMI_TX0P      | HDMI0_TX0_P        
+| DSI1_D1_P                | MIPI_D1_P               | 183 | 184 | HDMI_TX0N      | HDMI0_TX0_N        
+| GND                      | GND                     | 185 | 186 | GND            | GND                
+| DSI1_C_N                 | MIPI_CLK_N              | 187 | 188 | HDMI_TXCP      | HDMI0_CLK_P        
+| DSI1_C_P                 | MIPI_CLK_P              | 189 | 190 | HDMI_TXCN      | HDMI0_CLK_N        
+| GND                      | GND                     | 191 | 192 | GND            | GND                
+| DSI1_D2_N                | MIPI_D2_N               | 193 | 194 | MIPI_D3_N      | DSI1_D3_N          
+| DSI1_D2_P                | MIPI_D2_P               | 195 | 196 | MIPI_D3_P      | DSI1_D3_P          
+| GND                      | GND                     | 197 | 198 | GND            | GND                
+| HDMI0_SDA_5V             | HDMI_SDA                | 199 | 200 | HDMI_SCL       | HDMI0_SCL_5V       
+|===
+
+All ground pins should be connected.Attention should be paid to mechanical stability when designing expansion boards.
+
+Strict attention should be paid to the IO level to avoid damage to the chip.and do not input reverse voltage.
+
+== Chapter 5. Power
+
+=== 5.1 Power up sequencing
+
+The BPI-CM4 requires a single +5V supply, and it is not recommended to use the +3.3V and +1.8V output of the core board to power peripheral devices.
+
+All pins should not have any power applied to them before the +5V rail is applied.
+
++5V should rise monotonically to 4.75V and stay above 4.75V for the entire operation of the BPI-CM4.
+
+System operation begins when both +5V rails are above 4.75V and CPU_RST is high. CPU_RST has an internal RC delay on the core board to make it rise after +5V rises.The order of events is as follows
+
+. +5V rises
+. CPU_RST rises
+. +1.8V rises
+. +3.3V rises
+
+=== 5.2 Power down sequencing
+
+The Operating System should be shut down to ensure that the file system remains consistent, before the power is removed. If this can't be achieved, then a filesystem like btrfs, f2fs or overlayfs should be considered.
+
+Once the Operating System has shutdown the +5V rail can be removed.
+
+During the shutdown sequence the +3.3v will be discharged before the +1.8v rail.
+
+== Appendix A: Official Support
+
+
+
+* Official wiki Getting Started: https://wiki.banana-pi.org/Getting_Started_with_CM4[Getting Started with CM4] 
+* Official wiki Products: https://wiki.banana-pi.org/BPI-CM4_Computer_module_and_development_Kit[BPI-CM4 Computer module and development Kit]
+* Official Forum (EN): https://forum.banana-pi.org/c/Banana-Pi-BPI-M5[BPI-CM4 Forum(EN)]
+* Official Forum (CN): https://forum.banana-pi.org.cn/c/bpi-m5/144[BPI-CM4 Forum(CN)]