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fix(fvp): fix SPIs for IOMMU with GICv5

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The SPIs described in the DT for the IOMMU were wrongly offset by
32. Update them to correctly describe the hardware with GICv5 as
found in the docs:
https://developer.arm.com/documentation/110379/1131/Base-Platform/FVP-Base-RevC-2xAEMvA-GICv5-platform-interrupt-assignments?lang=en

Change-Id: Id6cc342a7533ac58e1170eab1c7c632a89e315a3
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
This commit is contained in:
Boyan Karatotev 2026-04-17 09:03:30 +01:00
parent 2cd4773356
commit 7a617d8ec2
1 changed files with 4 additions and 4 deletions
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8
fdts/fvp-base-gicv5.dtsi
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@ -151,10 +151,10 @@
msi-map = <0x0 &its0 0x0 0x10000>;
};
smmu: iommu@2b400000 {
interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 111 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 107 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 109 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
msi-parent = <&its0 0x10000>;
};
#endif /* ENABLE_RMM */