BPI/arm-trusted-firmware
5
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

feat(stm32mp2): add watchdog support

Browse Source 
Add the private functions to read OTP and update shadow (without
locking them).
Initialize the watchdog driver and refresh it after the security
setup.

Change-Id: Ic12952a0a8c80fe7e0c732bd5eb539f9e8fefdc9
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This commit is contained in:
Antonio Borneo 2023-07-12 10:37:55 +02:00 committed by Yann Gautier
parent c53dd82558
commit 9529933b3b
3 changed files with 64 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
plat/st/stm32mp2/bl2_plat_setup.c
View File

@ -14,6 +14,7 @@
#include <drivers/clk.h>
#include <drivers/mmc.h>
#include <drivers/st/regulator_fixed.h>
#include <drivers/st/stm32_iwdg.h>
#include <drivers/st/stm32_rifsc.h>
#include <drivers/st/stm32_rng.h>
#include <drivers/st/stm32mp2_ddr_helpers.h>
@ -190,6 +191,12 @@ void bl2_plat_arch_setup(void)
mmio_write_32(RISAB3_BASE + RISAB_CR, RISAB_CR_SRWIAD);
#endif
if (stm32_iwdg_init() < 0) {
panic();
}
stm32_iwdg_refresh();
stm32_save_boot_info(boot_context);
if (stm32mp_uart_console_setup() != 0) {

6
plat/st/stm32mp2/stm32mp2_def.h
View File

@ -408,9 +408,9 @@ enum ddr_type {
#define PACKAGE_OTP_PKG_SHIFT U(0)
/* IWDG OTP */
#define HCONF1_OTP_IWDG_HW_POS U(0)
#define HCONF1_OTP_IWDG_FZ_STOP_POS U(1)
#define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2)
#define HCONF1_OTP_IWDG_HW_MASK(i) BIT_32((i) * 3U)
#define HCONF1_OTP_IWDG_FZ_STOP_MASK(i) BIT_32((i) * 3U + 1U)
#define HCONF1_OTP_IWDG_FZ_STANDBY_MASK(i) BIT_32((i) * 3U + 2U)
/* NAND OTP */
/* NAND parameter storage flag */

54
plat/st/stm32mp2/stm32mp2_private.c
View File

@ -7,6 +7,7 @@
#include <assert.h>
#include <errno.h>
#include <drivers/st/stm32_iwdg.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <platform_def.h>
@ -531,6 +532,59 @@ bool stm32mp_is_auth_supported(void)
return supported;
}
uint32_t stm32_iwdg_get_instance(uintptr_t base)
{
uint32_t instance = UINT32_MAX;
switch (base) {
case IWDG1_BASE:
instance = IWDG1_INST;
break;
case IWDG2_BASE:
instance = IWDG2_INST;
break;
default:
break;
}
if (instance == UINT32_MAX) {
panic();
}
return instance;
}
uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst)
{
uint32_t iwdg_cfg = 0U;
uint32_t otp_value;
if (stm32_get_otp_value(HCONF1_OTP, &otp_value) != 0U) {
panic();
}
if ((otp_value & HCONF1_OTP_IWDG_HW_MASK(iwdg_inst)) != 0U) {
iwdg_cfg |= IWDG_HW_ENABLED;
}
if ((otp_value & HCONF1_OTP_IWDG_FZ_STOP_MASK(iwdg_inst)) != 0U) {
iwdg_cfg |= IWDG_DISABLE_ON_STOP;
}
if ((otp_value & HCONF1_OTP_IWDG_FZ_STANDBY_MASK(iwdg_inst)) != 0U) {
iwdg_cfg |= IWDG_DISABLE_ON_STANDBY;
}
return iwdg_cfg;
}
#if defined(IMAGE_BL2)
uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags)
{
return BSEC_OK;
}
#endif
bool stm32mp_is_wakeup_from_standby(void)
{
/* TODO add source code to determine if platform is waking up from standby mode */