Merge "fix(imx93): remove the unused platform helper code" into integration
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commit
d629b4af36
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/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <cortex_a55.h>
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#include <platform_def.h>
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_calc_core_pos
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.globl platform_mem_init
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/* ------------------------------------------------------
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* Helper macro that reads the part number of the current
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* CPU and jumps to the given label if it matches the CPU
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* MIDR provided.
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*
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* Clobbers x0.
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* ------------------------------------------------------
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*/
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.macro jump_if_cpu_midr _cpu_midr, _label
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mrs x0, midr_el1
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ubfx x0, x0, MIDR_PN_SHIFT, #12
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cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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b.eq \_label
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.endm
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/* ----------------------------------------------
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* unsigned int plat_is_my_cpu_primary(void);
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* This function checks if this is the primary CPU
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* ----------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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mov_imm x1, MPIDR_AFFINITY_MASK
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and x0, x0, x1
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cmp x0, #PLAT_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* ----------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the plat_calc_core_pos()
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* to get the index of the calling CPU.
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* ----------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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mov x1, #MPIDR_AFFLVL_MASK
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and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
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ret
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endfunc plat_my_core_pos
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/*
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* unsigned int plat_calc_core_pos(uint64_t mpidr)
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* helper function to calculate the core position.
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* With this function.
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*/
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func plat_calc_core_pos
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mov x1, #MPIDR_AFFLVL_MASK
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and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
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ret
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endfunc plat_calc_core_pos
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func platform_mem_init
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ret
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endfunc platform_mem_init
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@ -1,39 +0,0 @@
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/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <plat/common/platform.h>
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const unsigned char imx_power_domain_tree_desc[] = {
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PWR_DOMAIN_AT_MAX_LVL,
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PLATFORM_CLUSTER_COUNT,
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PLATFORM_CLUSTER0_CORE_COUNT,
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};
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return imx_power_domain_tree_desc;
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}
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/*
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* Only one cluster is planned for i.MX9 family, no need
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* to consider the cluster id
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*/
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int cpu_id;
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mpidr &= MPIDR_AFFINITY_MASK;
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if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) {
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return -1;
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}
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cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
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return cpu_id;
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}
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