arm64: sun60iw2: add dt-bindings and move BPI-M8 overlay path

Kconfig

@@ -30,3 +30,5 @@ source "lib/Kconfig"
 source "lib/Kconfig.debug"
 
 source "Documentation/Kconfig"
+
+source "bsp/Kconfig"

include/dt-bindings/clock/sun60iw2-ccu.h

@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
+/*
+ * Copyright (C) 2023 rengaomin@allwinnertech.com
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN60IW2_H_
+#define _DT_BINDINGS_CLK_SUN60IW2_H_
+
+#define CLK_PLL_REF		0
+#define CLK_PLL_DDR		1
+#define CLK_PLL_PERI0		2
+#define CLK_PLL_PERI0_2X	3
+#define CLK_PLL_PERI0_800M	4
+#define CLK_PLL_PERI0_480M	5
+#define CLK_PLL_PERI0_600M	6
+#define CLK_PLL_PERI0_400M	7
+#define CLK_PLL_PERI0_300M	8
+#define CLK_PLL_PERI0_200M	9
+#define CLK_PLL_PERI0_160M	10
+#define CLK_PLL_PERI0_150M	11
+#define CLK_PLL_PERI1		12
+#define CLK_PLL_PERI1_2X	13
+#define CLK_PLL_PERI1_800M	14
+#define CLK_PLL_PERI1_480M	15
+#define CLK_PLL_PERI1_600M	16
+#define CLK_PLL_PERI1_400M	17
+#define CLK_PLL_PERI1_300M	18
+#define CLK_PLL_PERI1_200M	19
+#define CLK_PLL_PERI1_160M	20
+#define CLK_PLL_PERI1_150M	21
+#define CLK_HDMI_CEC_32K	22
+#define CLK_PLL_GPU0		23
+#define CLK_PLL_VIDEO0		24
+#define CLK_PLL_VIDEO0_4X	25
+#define CLK_PLL_VIDEO0_3X	26
+#define CLK_PLL_VIDEO1		27
+#define CLK_PLL_VIDEO1_4X	28
+#define CLK_PLL_VIDEO1_3X	29
+#define CLK_PLL_VIDEO2		30
+#define CLK_PLL_VIDEO2_4X	31
+#define CLK_PLL_VIDEO2_3X	32
+#define CLK_PLL_VE0		33
+#define CLK_PLL_VE1		34
+#define CLK_PLL_AUDIO0_4X	35
+#define CLK_PLL_AUDIO1		36
+#define CLK_PLL_AUDIO1_DIV2	37
+#define CLK_PLL_AUDIO1_DIV5	38
+#define CLK_PLL_NPU		39
+#define CLK_PLL_DE		40
+#define CLK_PLL_DE_4X		41
+#define CLK_PLL_DE_3X		42
+#define CLK_AHB			43
+#define CLK_APB0		44
+#define CLK_APB1		45
+#define CLK_APB_UART		46
+#define CLK_TRACE		47
+#define CLK_GIC			48
+#define CLK_CPU_PERI		49
+#define CLK_ITS_PCIE0_A		50
+#define CLK_NSI			51
+#define CLK_NSI_CFG		52
+#define CLK_MBUS		53
+#define CLK_IOMMU0_SYS_H	54
+#define CLK_IOMMU0_SYS_P	55
+#define CLK_IOMMU0_SYS_MBUS	56
+#define CLK_MSI_LITE0		57
+#define CLK_MSI_LITE1		58
+#define CLK_MSI_LITE2		59
+#define CLK_IOMMU1_SYS_H	60
+#define CLK_IOMMU1_SYS_P	61
+#define CLK_IOMMU1_SYS_MBUS	62
+#define CLK_CPUS_HCLK_GATE	63
+#define CLK_STORE_AHB_GATE	64
+#define CLK_MSILITE0_AHB_GATE	65
+#define CLK_USB_SYS_AHB_GATE	66
+#define CLK_SERDES_AHB_GATE	67
+#define CLK_GPU0_AHB_GATE	68
+#define CLK_NPU_AHB_GATE	69
+#define CLK_DE_AHB_GATE		70
+#define CLK_VID_OUT1_AHB_GATE	71
+#define CLK_VID_OUT0_AHB_GATE	72
+#define CLK_VID_IN_AHB_GATE	73
+#define CLK_VE_ENC_AHB_GATE	74
+#define CLK_VE_AHB_GATE		75
+#define CLK_MBUS_MSILITE2_GATE	76
+#define CLK_MBUS_STORE_GATE	77
+#define CLK_MBUS_MSILITE0_GATE	78
+#define CLK_MBUS_SERDES_GATE	79
+#define CLK_MBUS_VID_IN_GATE	80
+#define CLK_MBUS_NPU_GATE	81
+#define CLK_MBUS_GPU0_GATE	82
+#define CLK_DEC_MBUS_GATE	83
+#define CLK_MBUS_VE_GATE	84
+#define CLK_MBUS_DESYS_GATE	85
+#define CLK_IOMMU1_MBUS_GATE	86
+#define CLK_IOMMU0_MBUS_GATE	87
+#define CLK_VE_DEC_MBUS		88
+#define CLK_GMAC1_MBUS		89
+#define CLK_GMAC0_MBUS		90
+#define CLK_ISP_MBUS		91
+#define CLK_CSI_MBUS		92
+#define CLK_NAND_MBUS		93
+#define CLK_DMA1_MBUS		94
+#define CLK_MBUS_CE		95
+#define CLK_MBUS_VE		96
+#define CLK_MBUS_DMA0		97
+#define CLK_DMA0		98
+#define CLK_DMA1		99
+#define CLK_SPINLOCK		100
+#define CLK_MSGBOX0		101
+#define CLK_PWM0		102
+#define CLK_PWM1		103
+#define CLK_DBGSYS		104
+#define CLK_SYSDAP		105
+#define CLK_TIMER0		106
+#define CLK_TIMER1		107
+#define CLK_TIMER2		108
+#define CLK_TIMER3		109
+#define CLK_TIMER4		110
+#define CLK_TIMER5		111
+#define CLK_TIMER6		112
+#define CLK_TIMER7		113
+#define CLK_TIMER8		114
+#define CLK_TIMER9		115
+#define CLK_BUS_TIMER		116
+#define CLK_AVS			117
+#define CLK_DE0			118
+#define CLK_BUS_DE0		119
+#define CLK_DI			120
+#define CLK_DI_GATE		121
+#define CLK_G2D			122
+#define CLK_G2D_GATE		123
+#define CLK_EINK		124
+#define CLK_EINK_PANEL		125
+#define CLK_EINK_GATE		126
+#define CLK_VE_ENC0		127
+#define CLK_VE_DEC		128
+#define CLK_BUS_VE_DEC		129
+#define CLK_BUS_VE_ENC		130
+#define CLK_CE			131
+#define CLK_CE_SYS		132
+#define CLK_BUS_CE		133
+#define CLK_NPU			134
+#define CLK_BUS_NPU		135
+#define CLK_GPU0		136
+#define CLK_BUS_GPU0		137
+#define CLK_DRAM0		138
+#define CLK_BUS_DRAM0		139
+#define CLK_NAND0_CLK0		140
+#define CLK_NAND0_CLK1		141
+#define CLK_BUS_NAND0		142
+#define CLK_SMHC0		143
+#define CLK_BUS_SMHC0		144
+#define CLK_SMHC1		145
+#define CLK_BUS_SMHC1		146
+#define CLK_SMHC2		147
+#define CLK_BUS_SMHC2		148
+#define CLK_SMHC3		149
+#define CLK_BUS_SMHC3		150
+#define CLK_UFS_AXI		151
+#define CLK_UFS_CFG		152
+#define CLK_UFS			153
+#define CLK_UART0		154
+#define CLK_UART1		155
+#define CLK_UART2		156
+#define CLK_UART3		157
+#define CLK_UART4		158
+#define CLK_UART5		159
+#define CLK_UART6		160
+#define CLK_TWI0		161
+#define CLK_TWI1		162
+#define CLK_TWI2		163
+#define CLK_TWI3		164
+#define CLK_TWI4		165
+#define CLK_TWI5		166
+#define CLK_TWI6		167
+#define CLK_TWI7		168
+#define CLK_TWI8		169
+#define CLK_TWI9		170
+#define CLK_TWI10		171
+#define CLK_TWI11		172
+#define CLK_TWI12		173
+#define CLK_SPI0		174
+#define CLK_BUS_SPI0		175
+#define CLK_SPI1		176
+#define CLK_BUS_SPI1		177
+#define CLK_SPI2		178
+#define CLK_BUS_SPI2		179
+#define CLK_SPIF		180
+#define CLK_BUS_SPIF		181
+#define CLK_SPI3		182
+#define CLK_BUS_SPI3		183
+#define CLK_SPI4		184
+#define CLK_BUS_SPI4		185
+#define CLK_GPADC0_24M		186
+#define CLK_GPADC0		187
+#define CLK_THS0		188
+#define CLK_IRRX		189
+#define CLK_IRRX_GATE		190
+#define CLK_IRTX		191
+#define CLK_IRTX_GATE		192
+#define CLK_LRADC		193
+#define CLK_SGPIO		194
+#define CLK_BUS_SGPIO		195
+#define CLK_LPC			196
+#define CLK_BUS_LPC		197
+#define CLK_I2SPCM0		198
+#define CLK_BUS_I2SPCM0		199
+#define CLK_I2SPCM1		200
+#define CLK_BUS_I2SPCM1		201
+#define CLK_I2SPCM2		202
+#define CLK_I2SPCM2_ASRC	203
+#define CLK_BUS_I2SPCM2		204
+#define CLK_I2SPCM3		205
+#define CLK_BUS_I2SPCM3		206
+#define CLK_I2SPCM4		207
+#define CLK_BUS_I2SPCM4		208
+#define CLK_OWA_TX		209
+#define CLK_OWA_RX		210
+#define CLK_BUS_OWA		211
+#define CLK_DMIC		212
+#define CLK_BUS_DMIC		213
+#define CLK_USB			214
+#define CLK_USB0_DEVICE		215
+#define CLK_USB0_EHCI		216
+#define CLK_USB0_OHCI		217
+#define CLK_USB1		218
+#define CLK_USB1_EHCI		219
+#define CLK_USB1_OHCI		220
+#define CLK_USB_REF		221
+#define CLK_USB2_U2_REF		222
+#define CLK_USB2_SUSPEND	223
+#define CLK_USB2_MF		224
+#define CLK_USB2_U3_UTMI	225
+#define CLK_USB2_U2_PIPE	226
+#define CLK_PCIE0_AUX		227
+#define CLK_PCIE0_AXI_SLV	228
+#define CLK_SERDES_PHY_CFG	229
+#define CLK_GMAC_PTP		230
+#define CLK_GMAC0_PHY		231
+#define CLK_GMAC0		232
+#define CLK_GMAC1_PHY		233
+#define CLK_GMAC1		234
+#define CLK_VO0_TCONLCD0	235
+#define CLK_BUS_VO0_TCONLCD0	236
+#define CLK_VO0_TCONLCD1	237
+#define CLK_BUS_VO0_TCONLCD1	238
+#define CLK_VO0_TCONLCD2	239
+#define CLK_BUS_VO0_TCONLCD2	240
+#define CLK_DSI0		241
+#define CLK_BUS_DSI0		242
+#define CLK_DSI1		243
+#define CLK_BUS_DSI1		244
+#define CLK_COMBPHY0		245
+#define CLK_COMBPHY1		246
+#define CLK_TCONTV0		247
+#define CLK_TCONTV1		248
+#define CLK_EDP_TV		249
+#define CLK_EDP			250
+#define CLK_HDMI_REF		251
+#define CLK_HDMI_TV		252
+#define CLK_HDMI		253
+#define CLK_HDMI_SFR		254
+#define CLK_HDCP_ESM		255
+#define CLK_DPSS_TOP0		256
+#define CLK_DPSS_TOP1		257
+#define CLK_LEDC		258
+#define CLK_BUS_LEDC		259
+#define CLK_DSC			260
+#define CLK_CSI_MASTER0		261
+#define CLK_CSI_MASTER1		262
+#define CLK_CSI_MASTER2		263
+#define CLK_CSI			264
+#define CLK_BUS_CSI		265
+#define CLK_ISP			266
+#define CLK_RES_DCAP_24M	267
+#define CLK_APB2JTAG		268
+#define CLK_FANOUT_25M		269
+#define CLK_FANOUT_16M		270
+#define CLK_FANOUT_12M		271
+#define CLK_FANOUT_24M		272
+#define CLK_CLK27M_FANOUT	273
+#define CLK_CLK_FANOUT		274
+#define CLK_SYS_12M		275
+#define CLK_PLL_PERI0_16M	276
+#define CLK_PLL_PERI0_25M	277
+#define CLK_FANOUT3		278
+#define CLK_FANOUT2		279
+#define CLK_FANOUT1		280
+#define CLK_FANOUT0		281
+#define CLK_BUS_DEBUG		282
+#define CLK_PLL_DDR_AUTO	283
+#define CLK_PLL_PERI0_2X_AUTO	284
+#define CLK_PLL_PERI0_800M_AUTO	285
+#define CLK_PLL_PERI0_600M_AUTO	286
+#define CLK_PLL_PERI0_480M_ALL_AUTO	287
+#define CLK_PLL_PERI0_480M_AUTO	288
+#define CLK_PLL_PERI0_160M_AUTO	289
+#define CLK_PLL_PERI0_300M_ALL_AUTO	290
+#define CLK_PLL_PERI0_300M_AUTO	291
+#define CLK_PLL_PERI0_150M_AUTO	292
+#define CLK_PLL_PERI0_400M_ALL_AUTO	293
+#define CLK_PLL_PERI0_400M_AUTO	294
+#define CLK_PLL_PERI0_200M_AUTO	295
+#define CLK_PLL_PERI1_800M_AUTO	296
+#define CLK_PLL_PERI1_600M_ALL_AUTO	297
+#define CLK_PLL_PERI1_600M_AUTO	298
+#define CLK_PLL_PERI1_480M_ALL_AUTO	299
+#define CLK_PLL_PERI1_480M_AUTO	300
+#define CLK_PLL_PERI1_160M_AUTO	301
+#define CLK_PLL_PERI1_300M_ALL_AUTO	302
+#define CLK_PLL_PERI1_300M_AUTO	303
+#define CLK_PLL_PERI1_150M_AUTO	304
+#define CLK_PLL_PERI1_400M_ALL_AUTO	305
+#define CLK_PLL_PERI1_400M_AUTO	306
+#define CLK_PLL_PERI1_200M_AUTO	307
+#define CLK_PLL_VIDEO2_3X_AUTO	308
+#define CLK_PLL_VIDEO1_3X_AUTO	309
+#define CLK_PLL_VIDEO0_3X_AUTO	310
+#define CLK_PLL_VIDEO2_4X_AUTO	311
+#define CLK_PLL_VIDEO1_4X_AUTO	312
+#define CLK_PLL_VIDEO0_4X_AUTO	313
+#define CLK_PLL_GPU0_AUTO	314
+#define CLK_PLL_VE1_AUTO	315
+#define CLK_PLL_VE0_AUTO	316
+#define CLK_PLL_AUDIO1_DIV5_AUTO	317
+#define CLK_PLL_AUDIO1_DIV2_AUTO	318
+#define CLK_PLL_AUDIO0_4X_AUTO	319
+#define CLK_PLL_NPU_AUTO	320
+#define CLK_PLL_DE_3X_AUTO	321
+#define CLK_PLL_DE_4X_AUTO	322
+
+#define CLK_MAX_NO	(CLK_PLL_DE_4X_AUTO + 1)
+
+#endif /* _DT_BINDINGS_CLK_SUN60IW2_H_ */

include/dt-bindings/clock/sun60iw2-cpupll-ccu.h

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
+
+#ifndef _DT_BINDINGS_CLK_SUN60IW2_CPUPLL_H_
+#define _DT_BINDINGS_CLK_SUN60IW2_CPUPLL_H_
+
+
+#define CLK_PLL_CPU_BACK	0
+#define CLK_PLL_CPU_L		1
+#define CLK_PLL_CPU_B		2
+#define CLK_PLL_CPU_DSU		3
+#define CLK_CPU_L		4
+#define CLK_CPU_B		5
+#define CLK_CPU_DSU		6
+
+#define CLK_CPUPLL_MAX_NO	(CLK_CPU_DSU + 1)
+
+#endif /* _DT_BINDINGS_CLK_SUN60IW2_CPUPLL_H_ */

include/dt-bindings/clock/sun60iw2-r-ccu.h

@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
+/*
+ * Copyright (c) 2023 rengaomin@allwinnertech.com
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN60IW1_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN60IW1_R_CCU_H_
+
+#define CLK_R_AHB		0
+#define CLK_R_APBS0		1
+#define CLK_R_APBS1		2
+#define CLK_R_TIMER0		3
+#define CLK_R_TIMER1		4
+#define CLK_R_TIMER2		5
+#define CLK_R_TIMER3		6
+#define CLK_R_TIMER		7
+#define CLK_R_TWD		8
+#define CLK_R_BUS_PWM		9
+#define CLK_R_PWM		10
+#define CLK_R_SPI		11
+#define CLK_R_BUS_SPI		12
+#define CLK_R_MBOX		13
+#define CLK_R_UART1		14
+#define CLK_R_UART0		15
+#define CLK_R_TWI2		16
+#define CLK_R_TWI1		17
+#define CLK_R_TWI0		18
+#define CLK_R_PPU		19
+#define CLK_R_TZMA		20
+#define CLK_R_CPUS_BIST		21
+#define CLK_R_IRRX		22
+#define CLK_R_BUS_IRRX		23
+#define CLK_RTC			24
+#define CLK_RISCV_24M	25
+#define CLK_RISCV_CFG	26
+#define	CLK_RISCV		27
+#define CLK_R_CPUCFG		28
+#define CLK_VDD_USB2CPUS	29
+#define CLK_VDD_SYS2USB		30
+#define CLK_VDD_SYS2CPUS	31
+#define CLK_VDD_DDR		32
+#define CLK_TT_AUTO		33
+#define CLK_CPU_ICACHE_AUTO	34
+#define CLK_AHBS_AUTO_CLK	35
+
+#define CLK_R_NUMBER		(CLK_AHBS_AUTO_CLK + 1)
+
+#endif /* _DT_BINDINGS_CLK_SUN60IW2_R_CCU_H_ */

include/dt-bindings/clock/sun60iw2-rtc.h

@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
+/*
+ * Copyright (C) 2023 rengaomin@allwinnertech.com
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN60IW2_RTC_H_
+#define _DT_BINDINGS_CLK_SUN60IW2_RTC_H_
+
+#define CLK_IOSC		0
+#define CLK_EXT32K_GATE		1
+#define CLK_IOSC_DIV32K		2
+#define CLK_OSC32K		3
+#define CLK_DCXO24M_DIV32K	4
+#define CLK_RTC32K		5
+#define CLK_RTC_1K		6
+#define CLK_RTC_32K_FANOUT	7
+#define CLK_RTC_DCXO_WAKEUP	8
+#define CLK_RTC_DCXO_SERDES1	9
+#define CLK_RTC_DCXO_SERDES0	10
+#define CLK_RTC_SPI		11
+#define CLK_DCXO		12
+
+#define CLK_RTC_MAX_NO                      (CLK_DCXO + 1)
+
+#endif /* _DT_BINDINGS_CLK_SUN60IW2_RTC_H_ */

include/dt-bindings/clock/sunxi-clk.h

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
+/*
+ * Copyright (C) 2022 liujuan1@allwinnertech.com
+ */
+
+#ifndef __DT_SUNXI_CLK_H
+#define __DT_SUNXI_CLK_H
+
+#define TR_1	0
+#define TR_N	1
+
+#define FREQ_31_5	0
+#define FREQ_32		1
+#define FREQ_32_5	2
+#define FREQ_33		3
+
+#endif

include/dt-bindings/power/sun60iw2-power.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_SUN60IW2_H__
+#define __DT_BINDINGS_POWER_SUN60IW2_H__
+
+#define SUN60IW2_PCK_VI			0
+#define SUN60IW2_PCK_DE_SYS		1
+#define SUN60IW2_PCK_VE_DEC		2
+#define SUN60IW2_PCK_VE_ENC		3
+#define SUN60IW2_PCK_NPU		4
+#define SUN60IW2_PCK_GPU_TOP		5
+#define SUN60IW2_PCK_GPU_CORE		6
+#define SUN60IW2_PCK_PCIE		7
+#define SUN60IW2_PCK_USB2		8
+#define SUN60IW2_PCK_VO			9
+#define SUN60IW2_PCK_VO1		10
+
+#endif

include/dt-bindings/reset/sun60iw2-ccu.h

@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
+/*
+ * Copyright (C) 2023 rengaomin@allwinnertech.com
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN60IW2_H_
+#define _DT_BINDINGS_RESET_SUN60IW2_H_
+
+#define RST_BUS_ITS_PCIE0	0
+#define RST_BUS_NSI		1
+#define RST_BUS_NSI_CFG		2
+#define RST_BUS_IOMMU0_SY	3
+#define RST_BUS_MSI_LITE0_MBU	4
+#define RST_BUS_MSI_LITE0_AHB	5
+#define RST_BUS_MSI_LITE1_MBU	6
+#define RST_BUS_MSI_LITE1_AHB	7
+#define RST_BUS_MSI_LITE2_MBU	8
+#define RST_BUS_MSI_LITE2_AHB	9
+#define RST_BUS_IOMMU1_SY	10
+#define RST_BUS_DMA0		11
+#define RST_BUS_DMA1		12
+#define RST_BUS_SPINLOCK	13
+#define RST_BUS_MSGBOX0		14
+#define RST_BUS_PWM0		15
+#define RST_BUS_PWM1		16
+#define RST_BUS_DBGSY		17
+#define RST_BUS_SYSDAP		18
+#define RST_BUS_TIMER0		19
+#define RST_BUS_DE0		20
+#define RST_BUS_DI		21
+#define RST_BUS_G2D		22
+#define RST_BUS_EINK		23
+#define RST_BUS_DE_SY		24
+#define RST_BUS_VE_DEC		25
+#define RST_BUS_VE_ENC0		26
+#define RST_BUS_CE_SY		27
+#define RST_BUS_CE		28
+#define RST_BUS_NPU_AHB		29
+#define RST_BUS_NPU_AXI		30
+#define RST_BUS_NPU_CORE	31
+#define RST_BUS_GPU0		32
+#define RST_BUS_DRAM0		33
+#define RST_BUS_NAND0		34
+#define RST_BUS_SMHC0		35
+#define RST_BUS_SMHC1		36
+#define RST_BUS_SMHC2		37
+#define RST_BUS_SMHC3		38
+#define RST_BUS_UFS_AXI		39
+#define RST_BUS_UFS_AHB		40
+#define RST_BUS_UART0		41
+#define RST_BUS_UART1		42
+#define RST_BUS_UART2		43
+#define RST_BUS_UART3		44
+#define RST_BUS_UART4		45
+#define RST_BUS_UART5		46
+#define RST_BUS_UART6		47
+#define RST_BUS_TWI0		48
+#define RST_BUS_TWI1		49
+#define RST_BUS_TWI2		50
+#define RST_BUS_TWI3		51
+#define RST_BUS_TWI4		52
+#define RST_BUS_TWI5		53
+#define RST_BUS_TWI6		54
+#define RST_BUS_TWI7		55
+#define RST_BUS_TWI8		56
+#define RST_BUS_TWI9		57
+#define RST_BUS_TWI10		58
+#define RST_BUS_TWI11		59
+#define RST_BUS_TWI12		60
+#define RST_BUS_SPI0		61
+#define RST_BUS_SPI1		62
+#define RST_BUS_SPI2		63
+#define RST_BUS_SPIF		64
+#define RST_BUS_SPI3		65
+#define RST_BUS_SPI4		66
+#define RST_BUS_GPADC0		67
+#define RST_BUS_THS0		68
+#define RST_BUS_IRRX		69
+#define RST_BUS_IRTX		70
+#define RST_BUS_LRADC		71
+#define RST_BUS_SGPIO		72
+#define RST_BUS_LPC		73
+#define RST_BUS_I2SPCM0		74
+#define RST_BUS_I2SPCM1		75
+#define RST_BUS_I2SPCM2		76
+#define RST_BUS_I2SPCM3		77
+#define RST_BUS_I2SPCM4		78
+#define RST_BUS_OWA		79
+#define RST_BUS_DMIC		80
+#define RST_USB_0_PHY_RSTN	81
+#define RST_USB_0_DEVICE	82
+#define RST_USB_0_EHCI		83
+#define RST_USB_0_OHCI		84
+#define RST_USB_1_PHY_RSTN	85
+#define RST_USB_1_EHCI		86
+#define RST_USB_1_OHCI		87
+#define RST_USB_2		88
+#define RST_BUS_PCIE0		89
+#define RST_BUS_PCIE0_PWRUP	90
+#define RST_BUS_SERDES		91
+#define RST_BUS_GMAC0_AXI	92
+#define RST_BUS_GMAC0		93
+#define RST_BUS_GMAC1_AXI	94
+#define RST_BUS_GMAC1		95
+#define RST_BUS_VO0_TCONLCD0	96
+#define RST_BUS_VO0_TCONLCD1	97
+#define RST_BUS_VO0_TCONLCD2	98
+#define RST_BUS_LVDS0		99
+#define RST_BUS_LVDS1		100
+#define RST_BUS_DSI0		101
+#define RST_BUS_DSI1		102
+#define RST_BUS_TCONTV0		103
+#define RST_BUS_TCONTV1		104
+#define RST_BUS_EDP		105
+#define RST_BUS_HDMI_HDCP	106
+#define RST_BUS_HDMI_SUB	107
+#define RST_BUS_HDMI_MAIN	108
+#define RST_BUS_DPSS_TOP0	109
+#define RST_BUS_DPSS_TOP1	110
+#define RST_BUS_VIDEO_OUT0	111
+#define RST_BUS_VIDEO_OUT1	112
+#define RST_BUS_LEDC		113
+#define RST_BUS_DSC		114
+#define RST_BUS_CSI		115
+#define RST_BUS_VIDEO_IN	116
+#define RST_BUS_APB2JTAG	117
+#define RST_BUS_UFS_PHY 	119
+#define RST_BUS_UFS_CORE	120
+
+#endif /* _DT_BINDINGS_RESET_SUN60IW2_H_ */

include/dt-bindings/reset/sun60iw2-r-ccu.h

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
+/*
+ * Copyright (C) 2023 rengaomin@allwinnertech.com
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN60IW2_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN60IW2_R_CCU_H_
+
+#define RST_BUS_R_TIME		0
+#define RST_BUS_R_PWM		1
+#define RST_BUS_R_SPI		2
+#define RST_BUS_R_MBOX		3
+#define RST_BUS_R_UART1		4
+#define RST_BUS_R_UART0		5
+#define RST_BUS_R_TWI2		6
+#define RST_BUS_R_TWI1		7
+#define RST_BUS_R_TWI0		8
+#define RST_BUS_R_IRRX		9
+#define RST_BUS_RTC		10
+#define RST_BUS_RISCV_CFG	11
+#define RST_BUS_R_CPUCFG	12
+#define RST_BUS_MODULE		13
+
+#endif /* _DT_BINDINGS_RST_SUN60IW2_R_CCU_H_ */