/* SPDX-License-Identifier: GPL-2.0+ */

#define PLL_CPU0_CTRL_REG 0x00000000 //PLL_CPU0 Control Register
  #define PLL_CPU0_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_CPU0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_CPU0_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_CPU0_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_CPU0_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_CPU0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_CPU0_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_CPU0_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_CPU0_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_CPU0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_CPU0_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_CPU0_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_CPU0_CTRL_REG_LOCK_OFFSET 28
  #define PLL_CPU0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_CPU0_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_CPU0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_CPU0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_CPU0_CTRL_REG_PLL_LOCK_TIME_OFFSET 24
  #define PLL_CPU0_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK 0x07000000
  #define PLL_CPU0_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_CPU0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_CPU0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_CPU0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_CPU0_CTRL_REG_PLL_M_OFFSET 0
  #define PLL_CPU0_CTRL_REG_PLL_M_CLEAR_MASK 0x00000003

#define PLL_CPU1_CTRL_REG 0x00000008 //PLL_CPU1 Control Register
  #define PLL_CPU1_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_CPU1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_CPU1_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_CPU1_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_CPU1_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_CPU1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_CPU1_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_CPU1_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_CPU1_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_CPU1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_CPU1_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_CPU1_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_CPU1_CTRL_REG_LOCK_OFFSET 28
  #define PLL_CPU1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_CPU1_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_CPU1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_CPU1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_CPU1_CTRL_REG_PLL_LOCK_TIME_OFFSET 24
  #define PLL_CPU1_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK 0x07000000
  #define PLL_CPU1_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_CPU1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_CPU1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_CPU1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_CPU1_CTRL_REG_PLL_M_OFFSET 0
  #define PLL_CPU1_CTRL_REG_PLL_M_CLEAR_MASK 0x00000003

#define PLL_CPU2_CTRL_REG 0x0000000c //PLL_CPU2 Control Register
  #define PLL_CPU2_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_CPU2_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_CPU2_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_CPU2_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_CPU2_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_CPU2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_CPU2_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_CPU2_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_CPU2_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_CPU2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_CPU2_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_CPU2_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_CPU2_CTRL_REG_LOCK_OFFSET 28
  #define PLL_CPU2_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_CPU2_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_CPU2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_CPU2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_CPU2_CTRL_REG_PLL_LOCK_TIME_OFFSET 24
  #define PLL_CPU2_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK 0x07000000
  #define PLL_CPU2_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_CPU2_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_CPU2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_CPU2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_CPU2_CTRL_REG_PLL_M_OFFSET 0
  #define PLL_CPU2_CTRL_REG_PLL_M_CLEAR_MASK 0x00000003

#define PLL_DDR_CTRL_REG 0x00000010 //PLL_DDR Control Register
  #define PLL_DDR_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_DDR_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_DDR_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_DDR_CTRL_REG_LOCK_OFFSET 28
  #define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_DDR_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET 24
  #define PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
    #define PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
    #define PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
  #define PLL_DDR_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
  #define PLL_DDR_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
  #define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
  #define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_PERI0_CTRL_REG 0x00000020 //PLL_PERI0 Control Register
  #define PLL_PERI0_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_PERI0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_PERI0_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_PERI0_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_PERI0_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_PERI0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_PERI0_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_PERI0_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_PERI0_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_PERI0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_PERI0_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_PERI0_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_PERI0_CTRL_REG_LOCK_OFFSET 28
  #define PLL_PERI0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_PERI0_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_PERI0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_PERI0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_PERI0_CTRL_REG_PLL_SDM_EN_OFFSET 24
  #define PLL_PERI0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
    #define PLL_PERI0_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
    #define PLL_PERI0_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
  #define PLL_PERI0_CTRL_REG_PLL_P1_OFFSET 20
  #define PLL_PERI0_CTRL_REG_PLL_P1_CLEAR_MASK 0x00700000
  #define PLL_PERI0_CTRL_REG_PLL_P0_OFFSET 16
  #define PLL_PERI0_CTRL_REG_PLL_P0_CLEAR_MASK 0x00070000
  #define PLL_PERI0_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_PERI0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_PERI0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_PERI0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_PERI0_CTRL_REG_PLL_P2_OFFSET 2
  #define PLL_PERI0_CTRL_REG_PLL_P2_CLEAR_MASK 0x0000001c
  #define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
  #define PLL_PERI0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define PLL_PERI1_CTRL_REG 0x00000028 //PLL_PERI1 Control Register
  #define PLL_PERI1_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_PERI1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_PERI1_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_PERI1_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_PERI1_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_PERI1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_PERI1_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_PERI1_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_PERI1_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_PERI1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_PERI1_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_PERI1_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_PERI1_CTRL_REG_LOCK_OFFSET 28
  #define PLL_PERI1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_PERI1_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_PERI1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_PERI1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_PERI1_CTRL_REG_PLL_SDM_EN_OFFSET 24
  #define PLL_PERI1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
    #define PLL_PERI1_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
    #define PLL_PERI1_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
  #define PLL_PERI1_CTRL_REG_PLL_P1_OFFSET 20
  #define PLL_PERI1_CTRL_REG_PLL_P1_CLEAR_MASK 0x00700000
  #define PLL_PERI1_CTRL_REG_PLL_P0_OFFSET 16
  #define PLL_PERI1_CTRL_REG_PLL_P0_CLEAR_MASK 0x00070000
  #define PLL_PERI1_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_PERI1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_PERI1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_PERI1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_PERI1_CTRL_REG_PLL_P2_OFFSET 2
  #define PLL_PERI1_CTRL_REG_PLL_P2_CLEAR_MASK 0x0000001c
  #define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
  #define PLL_PERI1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002

#define PLL_GPU_CTRL_REG 0x00000030 //PLL_GPU Control Register
  #define PLL_GPU_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_GPU_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_GPU_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_GPU_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_GPU_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_GPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_GPU_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_GPU_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_GPU_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_GPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_GPU_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_GPU_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_GPU_CTRL_REG_LOCK_OFFSET 28
  #define PLL_GPU_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_GPU_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_GPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_GPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_GPU_CTRL_REG_PLL_SDM_EN_OFFSET 24
  #define PLL_GPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
    #define PLL_GPU_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
    #define PLL_GPU_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
  #define PLL_GPU_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_GPU_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_GPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_GPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
  #define PLL_GPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
  #define PLL_GPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
  #define PLL_GPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_VIDEO0_CTRL_REG 0x00000040 //PLL_VIDEO0 Control Register
  #define PLL_VIDEO0_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_VIDEO0_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_VIDEO0_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_VIDEO0_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_VIDEO0_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_VIDEO0_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_VIDEO0_CTRL_REG_LOCK_OFFSET 28
  #define PLL_VIDEO0_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_VIDEO0_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_VIDEO0_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_OFFSET 24
  #define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
    #define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
    #define PLL_VIDEO0_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
  #define PLL_VIDEO0_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_VIDEO0_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_VIDEO0_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_VIDEO0_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
  #define PLL_VIDEO0_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
  #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
  #define PLL_VIDEO0_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_VIDEO1_CTRL_REG 0x00000048 //PLL_VIDEO1 Control Register
  #define PLL_VIDEO1_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_VIDEO1_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_VIDEO1_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_VIDEO1_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_VIDEO1_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_VIDEO1_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_VIDEO1_CTRL_REG_LOCK_OFFSET 28
  #define PLL_VIDEO1_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_VIDEO1_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_VIDEO1_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_OFFSET 24
  #define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
    #define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
    #define PLL_VIDEO1_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
  #define PLL_VIDEO1_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_VIDEO1_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_VIDEO1_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_VIDEO1_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
  #define PLL_VIDEO1_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
  #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
  #define PLL_VIDEO1_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_VIDEO2_CTRL_REG 0x00000050 //PLL_VIDEO2 Control Register
  #define PLL_VIDEO2_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_VIDEO2_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_VIDEO2_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_VIDEO2_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_VIDEO2_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_VIDEO2_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_VIDEO2_CTRL_REG_LOCK_OFFSET 28
  #define PLL_VIDEO2_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_VIDEO2_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_VIDEO2_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_OFFSET 24
  #define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
    #define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
    #define PLL_VIDEO2_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
  #define PLL_VIDEO2_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_VIDEO2_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_VIDEO2_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_VIDEO2_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
  #define PLL_VIDEO2_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
  #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
  #define PLL_VIDEO2_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_VE_CTRL_REG 0x00000058 //PLL_VE Control Register
  #define PLL_VE_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_VE_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_VE_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_VE_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_VE_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_VE_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_VE_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_VE_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_VE_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_VE_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_VE_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_VE_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_VE_CTRL_REG_LOCK_OFFSET 28
  #define PLL_VE_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_VE_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_VE_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_VE_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_VE_CTRL_REG_PLL_SDM_EN_OFFSET 24
  #define PLL_VE_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
    #define PLL_VE_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
    #define PLL_VE_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
  #define PLL_VE_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_VE_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_VE_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_VE_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
  #define PLL_VE_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
  #define PLL_VE_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
  #define PLL_VE_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_VIDEO3_CTRL_REG 0x00000068 //PLL_VIDEO3 Control Register
  #define PLL_VIDEO3_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_VIDEO3_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_VIDEO3_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_VIDEO3_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_VIDEO3_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_VIDEO3_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_VIDEO3_CTRL_REG_LOCK_OFFSET 28
  #define PLL_VIDEO3_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_VIDEO3_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_VIDEO3_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_OFFSET 24
  #define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
    #define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
    #define PLL_VIDEO3_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
  #define PLL_VIDEO3_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_VIDEO3_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_VIDEO3_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_VIDEO3_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_VIDEO3_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
  #define PLL_VIDEO3_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
  #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
  #define PLL_VIDEO3_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_AUDIO_CTRL_REG 0x00000078 //PLL_AUDIO Control Register
  #define PLL_AUDIO_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_AUDIO_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_AUDIO_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_AUDIO_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_AUDIO_CTRL_REG_LOCK_OFFSET 28
  #define PLL_AUDIO_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_AUDIO_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_AUDIO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_OFFSET 24
  #define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
    #define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
    #define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
  #define PLL_AUDIO_CTRL_REG_PLL_P_OFFSET 16
  #define PLL_AUDIO_CTRL_REG_PLL_P_CLEAR_MASK 0x003f0000
  #define PLL_AUDIO_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_AUDIO_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
  #define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
  #define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
  #define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_NPU_CTRL_REG 0x00000080 //PLL_NPU Control Register
  #define PLL_NPU_CTRL_REG_PLL_EN_OFFSET 31
  #define PLL_NPU_CTRL_REG_PLL_EN_CLEAR_MASK 0x80000000
    #define PLL_NPU_CTRL_REG_PLL_EN_DISABLE 0x0
    #define PLL_NPU_CTRL_REG_PLL_EN_ENABLE 0x1
  #define PLL_NPU_CTRL_REG_PLL_LDO_EN_OFFSET 30
  #define PLL_NPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK 0x40000000
    #define PLL_NPU_CTRL_REG_PLL_LDO_EN_DISABLE 0x0
    #define PLL_NPU_CTRL_REG_PLL_LDO_EN_ENABLE 0x1
  #define PLL_NPU_CTRL_REG_LOCK_ENABLE_OFFSET 29
  #define PLL_NPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK 0x20000000
    #define PLL_NPU_CTRL_REG_LOCK_ENABLE_DISABLE 0x0
    #define PLL_NPU_CTRL_REG_LOCK_ENABLE_ENABLE 0x1
  #define PLL_NPU_CTRL_REG_LOCK_OFFSET 28
  #define PLL_NPU_CTRL_REG_LOCK_CLEAR_MASK 0x10000000
    #define PLL_NPU_CTRL_REG_LOCK_UNLOCKED 0x0
    #define PLL_NPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0x1
  #define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
  #define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK 0x08000000
    #define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0x0
    #define PLL_NPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0x1
  #define PLL_NPU_CTRL_REG_PLL_SDM_EN_OFFSET 24
  #define PLL_NPU_CTRL_REG_PLL_SDM_EN_CLEAR_MASK 0x01000000
    #define PLL_NPU_CTRL_REG_PLL_SDM_EN_DISABLE 0x0
    #define PLL_NPU_CTRL_REG_PLL_SDM_EN_ENABLE 0x1
  #define PLL_NPU_CTRL_REG_PLL_N_OFFSET 8
  #define PLL_NPU_CTRL_REG_PLL_N_CLEAR_MASK 0x0000ff00
  #define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
  #define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK 0x000000c0
    #define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0x00
    #define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0x01
    #define PLL_NPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0x10
  #define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
  #define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK 0x00000020
    #define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0x0
    #define PLL_NPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0x1
  #define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_OFFSET 1
  #define PLL_NPU_CTRL_REG_PLL_INPUT_DIV2_CLEAR_MASK 0x00000002
  #define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
  #define PLL_NPU_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK 0x00000001

#define PLL_DDR_PAT0_CTRL_REG 0x00000110 //PLL_DDR Pattern0 Control Register
  #define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_DDR_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
  #define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
    #define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
    #define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
    #define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
    #define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
  #define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
  #define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
  #define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
    #define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
    #define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
  #define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
    #define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
    #define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ 0x01
    #define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
    #define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ 0x11
  #define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_DDR_PAT1_CTRL_REG 0x00000114 //PLL_DDR Pattern1 Control Register
  #define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
  #define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
  #define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_PERI0_PAT0_CTRL_REG 0x00000120 //PLL_PERI0 Pattern0 Control Register
  #define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_PERI0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
  #define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
    #define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
    #define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
    #define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
    #define PLL_PERI0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
  #define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_PERI0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
  #define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
  #define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
    #define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
    #define PLL_PERI0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
  #define PLL_PERI0_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_PERI0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
    #define PLL_PERI0_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
    #define PLL_PERI0_PAT0_CTRL_REG_FREQ_32KHZ 0x01
    #define PLL_PERI0_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
    #define PLL_PERI0_PAT0_CTRL_REG_FREQ_33KHZ 0x11
  #define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_PERI0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_PERI0_PAT1_CTRL_REG 0x00000124 //PLL_PERI0 Pattern1 Control Register
  #define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_PERI0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
  #define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_PERI0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
  #define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_PERI0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_PERI1_PAT0_CTRL_REG 0x00000128 //PLL_PERI1 Pattern0 Control Register
  #define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_PERI1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
  #define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
    #define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
    #define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
    #define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
    #define PLL_PERI1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
  #define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_PERI1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
  #define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
  #define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
    #define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
    #define PLL_PERI1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
  #define PLL_PERI1_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_PERI1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
    #define PLL_PERI1_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
    #define PLL_PERI1_PAT0_CTRL_REG_FREQ_32KHZ 0x01
    #define PLL_PERI1_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
    #define PLL_PERI1_PAT0_CTRL_REG_FREQ_33KHZ 0x11
  #define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_PERI1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_PERI1_PAT1_CTRL_REG 0x0000012c //PLL_PERI1 Pattern1 Control Register
  #define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_PERI1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
  #define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_PERI1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
  #define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_PERI1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_GPU_PAT0_CTRL_REG 0x00000130 //PLL_GPU Pattern0 Control Register
  #define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_GPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
  #define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
    #define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
    #define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
    #define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
    #define PLL_GPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
  #define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_GPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
  #define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
  #define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
    #define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
    #define PLL_GPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
  #define PLL_GPU_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_GPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
    #define PLL_GPU_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
    #define PLL_GPU_PAT0_CTRL_REG_FREQ_32KHZ 0x01
    #define PLL_GPU_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
    #define PLL_GPU_PAT0_CTRL_REG_FREQ_33KHZ 0x11
  #define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_GPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_GPU_PAT1_CTRL_REG 0x00000134 //PLL_GPU Pattern1 Control Register
  #define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_GPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
  #define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_GPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
  #define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_GPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO0_PAT0_CTRL_REG 0x00000140 //PLL_VIDEO0 Pattern0 Control Register
  #define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_VIDEO0_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
  #define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
    #define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
    #define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
    #define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
    #define PLL_VIDEO0_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
  #define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
  #define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
  #define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
    #define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
    #define PLL_VIDEO0_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
  #define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
    #define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
    #define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32KHZ 0x01
    #define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
    #define PLL_VIDEO0_PAT0_CTRL_REG_FREQ_33KHZ 0x11
  #define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_VIDEO0_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO0_PAT1_CTRL_REG 0x00000144 //PLL_VIDEO0 Pattern1 Control Register
  #define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_VIDEO0_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
  #define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
  #define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_VIDEO0_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO1_PAT0_CTRL_REG 0x00000148 //PLL_VIDEO1 Pattern0 Control Register
  #define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_VIDEO1_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
  #define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
    #define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
    #define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
    #define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
    #define PLL_VIDEO1_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
  #define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
  #define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
  #define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
    #define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
    #define PLL_VIDEO1_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
  #define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
    #define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
    #define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32KHZ 0x01
    #define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
    #define PLL_VIDEO1_PAT0_CTRL_REG_FREQ_33KHZ 0x11
  #define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_VIDEO1_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO1_PAT1_CTRL_REG 0x0000014c //PLL_VIDEO1 Pattern1 Control Register
  #define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_VIDEO1_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
  #define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
  #define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_VIDEO1_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO2_PAT0_CTRL_REG 0x00000150 //PLL_VIDEO2 Pattern0 Control Register
  #define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_VIDEO2_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
  #define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
    #define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
    #define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
    #define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
    #define PLL_VIDEO2_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
  #define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
  #define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
  #define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
    #define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
    #define PLL_VIDEO2_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
  #define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
    #define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
    #define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32KHZ 0x01
    #define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
    #define PLL_VIDEO2_PAT0_CTRL_REG_FREQ_33KHZ 0x11
  #define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_VIDEO2_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO2_PAT1_CTRL_REG 0x00000154 //PLL_VIDEO2 Pattern1 Control Register
  #define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_VIDEO2_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
  #define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
  #define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_VIDEO2_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_VE_PAT0_CTRL_REG 0x00000158 //PLL_VE Pattern0 Control Register
  #define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_VE_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
  #define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
    #define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
    #define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
    #define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
    #define PLL_VE_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
  #define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_VE_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
  #define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
  #define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
    #define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
    #define PLL_VE_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
  #define PLL_VE_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_VE_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
    #define PLL_VE_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
    #define PLL_VE_PAT0_CTRL_REG_FREQ_32KHZ 0x01
    #define PLL_VE_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
    #define PLL_VE_PAT0_CTRL_REG_FREQ_33KHZ 0x11
  #define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_VE_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_VE_PAT1_CTRL_REG 0x0000015c //PLL_VE Pattern1 Control Register
  #define PLL_VE_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_VE_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
  #define PLL_VE_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_VE_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
  #define PLL_VE_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_VE_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO3_PAT0_CTRL_REG 0x00000168 //PLL_VIDEO3 Pattern0 Control Register
  #define PLL_VIDEO3_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_VIDEO3_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
  #define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
    #define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
    #define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
    #define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
    #define PLL_VIDEO3_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
  #define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
  #define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
  #define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
    #define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
    #define PLL_VIDEO3_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
  #define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
    #define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
    #define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_32KHZ 0x01
    #define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
    #define PLL_VIDEO3_PAT0_CTRL_REG_FREQ_33KHZ 0x11
  #define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_VIDEO3_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_VIDEO3_PAT1_CTRL_REG 0x0000016c //PLL_VIDEO3 Pattern1 Control Register
  #define PLL_VIDEO3_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_VIDEO3_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
  #define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
  #define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_VIDEO3_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_AUDIO_PAT0_CTRL_REG 0x00000178 //PLL_AUDIO Pattern0 Control Register
  #define PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_AUDIO_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
  #define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
    #define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
    #define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
    #define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
    #define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
  #define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
  #define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
  #define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
    #define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
    #define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
  #define PLL_AUDIO_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_AUDIO_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
    #define PLL_AUDIO_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
    #define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32KHZ 0x01
    #define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
    #define PLL_AUDIO_PAT0_CTRL_REG_FREQ_33KHZ 0x11
  #define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_AUDIO_PAT1_CTRL_REG 0x0000017c //PLL_AUDIO Pattern1 Control Register
  #define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
  #define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
  #define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_NPU_PAT0_CTRL_REG 0x00000180 //PLL_NPU Pattern0 Control Register
  #define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
  #define PLL_NPU_PAT0_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK 0x80000000
  #define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 29
  #define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK 0x60000000
    #define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0x00
    #define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0x01
    #define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0x10
    #define PLL_NPU_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0x11
  #define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_OFFSET 20
  #define PLL_NPU_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK 0x1ff00000
  #define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
  #define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK 0x00080000
    #define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_24MHZ 0x0
    #define PLL_NPU_PAT0_CTRL_REG_SDM_CLK_SEL_12MHZ 0x1
  #define PLL_NPU_PAT0_CTRL_REG_FREQ_OFFSET 17
  #define PLL_NPU_PAT0_CTRL_REG_FREQ_CLEAR_MASK 0x00060000
    #define PLL_NPU_PAT0_CTRL_REG_FREQ_31_5KHZ 0x00
    #define PLL_NPU_PAT0_CTRL_REG_FREQ_32KHZ 0x01
    #define PLL_NPU_PAT0_CTRL_REG_FREQ_32_5KHZ 0x10
    #define PLL_NPU_PAT0_CTRL_REG_FREQ_33KHZ 0x11
  #define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
  #define PLL_NPU_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK 0x0001ffff

#define PLL_NPU_PAT1_CTRL_REG 0x00000184 //PLL_NPU Pattern1 Control Register
  #define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
  #define PLL_NPU_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK 0x01000000
  #define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
  #define PLL_NPU_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK 0x00100000
  #define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
  #define PLL_NPU_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK 0x0001ffff

#define PLL_CPU0_BIAS_REG 0x00000300 //PLL_CPU0 Bias Register
  #define PLL_CPU0_BIAS_REG_PLL_VCO_RST_IN_OFFSET 31
  #define PLL_CPU0_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK 0x80000000
  #define PLL_CPU0_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_CPU0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_CPU1_BIAS_REG 0x00000308 //PLL_CPU1 Bias Register
  #define PLL_CPU1_BIAS_REG_PLL_VCO_RST_IN_OFFSET 31
  #define PLL_CPU1_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK 0x80000000
  #define PLL_CPU1_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_CPU1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_CPU2_BIAS_REG 0x0000030c //PLL_CPU2 Bias Register
  #define PLL_CPU2_BIAS_REG_PLL_VCO_RST_IN_OFFSET 31
  #define PLL_CPU2_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK 0x80000000
  #define PLL_CPU2_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_CPU2_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_DDR_BIAS_REG 0x00000310 //PLL_DDR Bias Register
  #define PLL_DDR_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_PERI0_BIAS_REG 0x00000320 //PLL_PERI0 Bias Register
  #define PLL_PERI0_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_PERI0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_PERI1_BIAS_REG 0x00000328 //PLL_PERI1 Bias Register
  #define PLL_PERI1_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_PERI1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_GPU_BIAS_REG 0x00000330 //PLL_GPU Bias Register
  #define PLL_GPU_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_GPU_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_VIDEO0_BIAS_REG 0x00000340 //PLL_VIDEO0 Bias Register
  #define PLL_VIDEO0_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_VIDEO0_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_VIDEO1_BIAS_REG 0x00000348 //PLL_VIDEO1 Bias Register
  #define PLL_VIDEO1_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_VIDEO1_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_VIDEO2_BIAS_REG 0x00000350 //PLL_VIDEO2 Bias Register
  #define PLL_VIDEO2_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_VIDEO2_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_VE_BIAS_REG 0x00000358 //PLL_VE Bias Register
  #define PLL_VE_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_VE_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_VIDEO3_BIAS_REG 0x00000368 //PLL_VIDEO3 Bias Register
  #define PLL_VIDEO3_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_VIDEO3_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_AUDIO_BIAS_REG 0x00000378 //PLL_AUDIO Bias Register
  #define PLL_AUDIO_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_AUDIO_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_NPU_BIAS_REG 0x00000380 //PLL_NPU Bias Register
  #define PLL_NPU_BIAS_REG_PLL_CP_OFFSET 16
  #define PLL_NPU_BIAS_REG_PLL_CP_CLEAR_MASK 0x001f0000

#define PLL_CPU0_TUN_REG 0x00000400 //PLL_CPU0 Tuning Register
  #define PLL_CPU0_TUN_REG_PLL_VCO_OFFSET 28
  #define PLL_CPU0_TUN_REG_PLL_VCO_CLEAR_MASK 0x70000000
  #define PLL_CPU0_TUN_REG_PLL_VCO_GAIN_OFFSET 24
  #define PLL_CPU0_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK 0x07000000
  #define PLL_CPU0_TUN_REG_PLL_CNT_INT_OFFSET 16
  #define PLL_CPU0_TUN_REG_PLL_CNT_INT_CLEAR_MASK 0x007f0000
  #define PLL_CPU0_TUN_REG_PLL_REG_OD_OFFSET 15
  #define PLL_CPU0_TUN_REG_PLL_REG_OD_CLEAR_MASK 0x00008000
  #define PLL_CPU0_TUN_REG_PLL_B_IN_OFFSET 8
  #define PLL_CPU0_TUN_REG_PLL_B_IN_CLEAR_MASK 0x00007f00
  #define PLL_CPU0_TUN_REG_PLL_REG_OD1_OFFSET 7
  #define PLL_CPU0_TUN_REG_PLL_REG_OD1_CLEAR_MASK 0x00000080
  #define PLL_CPU0_TUN_REG_PLL_B_OUT_OFFSET 0
  #define PLL_CPU0_TUN_REG_PLL_B_OUT_CLEAR_MASK 0x0000007f

#define PLL_CPU1_TUN_REG 0x00000408 //PLL_CPU1 Tuning Register
  #define PLL_CPU1_TUN_REG_PLL_VCO_OFFSET 28
  #define PLL_CPU1_TUN_REG_PLL_VCO_CLEAR_MASK 0x70000000
  #define PLL_CPU1_TUN_REG_PLL_VCO_GAIN_OFFSET 24
  #define PLL_CPU1_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK 0x07000000
  #define PLL_CPU1_TUN_REG_PLL_CNT_INT_OFFSET 16
  #define PLL_CPU1_TUN_REG_PLL_CNT_INT_CLEAR_MASK 0x007f0000
  #define PLL_CPU1_TUN_REG_PLL_REG_OD_OFFSET 15
  #define PLL_CPU1_TUN_REG_PLL_REG_OD_CLEAR_MASK 0x00008000
  #define PLL_CPU1_TUN_REG_PLL_B_IN_OFFSET 8
  #define PLL_CPU1_TUN_REG_PLL_B_IN_CLEAR_MASK 0x00007f00
  #define PLL_CPU1_TUN_REG_PLL_REG_OD1_OFFSET 7
  #define PLL_CPU1_TUN_REG_PLL_REG_OD1_CLEAR_MASK 0x00000080
  #define PLL_CPU1_TUN_REG_PLL_B_OUT_OFFSET 0
  #define PLL_CPU1_TUN_REG_PLL_B_OUT_CLEAR_MASK 0x0000007f

#define PLL_CPU2_TUN_REG 0x0000040c //PLL_CPU2 Tuning Register
  #define PLL_CPU2_TUN_REG_PLL_VCO_OFFSET 28
  #define PLL_CPU2_TUN_REG_PLL_VCO_CLEAR_MASK 0x70000000
  #define PLL_CPU2_TUN_REG_PLL_VCO_GAIN_OFFSET 24
  #define PLL_CPU2_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK 0x07000000
  #define PLL_CPU2_TUN_REG_PLL_CNT_INT_OFFSET 16
  #define PLL_CPU2_TUN_REG_PLL_CNT_INT_CLEAR_MASK 0x007f0000
  #define PLL_CPU2_TUN_REG_PLL_REG_OD_OFFSET 15
  #define PLL_CPU2_TUN_REG_PLL_REG_OD_CLEAR_MASK 0x00008000
  #define PLL_CPU2_TUN_REG_PLL_B_IN_OFFSET 8
  #define PLL_CPU2_TUN_REG_PLL_B_IN_CLEAR_MASK 0x00007f00
  #define PLL_CPU2_TUN_REG_PLL_REG_OD1_OFFSET 7
  #define PLL_CPU2_TUN_REG_PLL_REG_OD1_CLEAR_MASK 0x00000080
  #define PLL_CPU2_TUN_REG_PLL_B_OUT_OFFSET 0
  #define PLL_CPU2_TUN_REG_PLL_B_OUT_CLEAR_MASK 0x0000007f

#define CPU_CLK_REG 0x00000500 //CPU Clock Register
  #define CPU_CLK_REG_CPU_CLK_SEL_OFFSET 24
  #define CPU_CLK_REG_CPU_CLK_SEL_CLEAR_MASK 0x07000000
    #define CPU_CLK_REG_CPU_CLK_SEL_HOSC 0x000
    #define CPU_CLK_REG_CPU_CLK_SEL_CLK32K 0x001
    #define CPU_CLK_REG_CPU_CLK_SEL_CLK16M_RC 0x010
    #define CPU_CLK_REG_CPU_CLK_SEL_CPU0PLL_P 0x011
    #define CPU_CLK_REG_CPU_CLK_SEL_PERI0_600M 0x100
    #define CPU_CLK_REG_CPU_CLK_SEL_CPU2PLL 0x101
  #define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_OFFSET 16
  #define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_CLEAR_MASK 0x00030000
    #define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_1 0x00
    #define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_2 0x01
    #define CPU_CLK_REG_PLL_CPU0_OUT_EXT_DIVP_4 0x10
  #define CPU_CLK_REG_CPU_APB_DIV_CFG_OFFSET 8
  #define CPU_CLK_REG_CPU_APB_DIV_CFG_CLEAR_MASK 0x00000300
  #define CPU_CLK_REG_CPU_PERI_DIV_CFG_OFFSET 2
  #define CPU_CLK_REG_CPU_PERI_DIV_CFG_CLEAR_MASK 0x0000000c
    #define CPU_CLK_REG_CPU_PERI_DIV_CFG__M__FACTOR_M1__1 0x1
  #define CPU_CLK_REG_CPU_AXI_DIV_CFG_OFFSET 0
  #define CPU_CLK_REG_CPU_AXI_DIV_CFG_CLEAR_MASK 0x00000003

#define CPU_GATING_REG 0x00000504 //CPU Gating Configuration Register
  #define CPU_GATING_REG_CPU_GATING_FIELD_OFFSET 16
  #define CPU_GATING_REG_CPU_GATING_FIELD_CLEAR_MASK 0xffff0000
    #define CPU_GATING_REG_CPU_GATING_FIELD_0_SIGNAL 0x15
  #define CPU_GATING_REG_DSU_CLK_GATING_OFFSET 1
  #define CPU_GATING_REG_DSU_CLK_GATING_CLEAR_MASK 0x00000002
    #define CPU_GATING_REG_DSU_CLK_GATING_CLOCK_IS_OFF 0x0
    #define CPU_GATING_REG_DSU_CLK_GATING_CLOCK_IS_ON 0x1
  #define CPU_GATING_REG_CPU0_CLK_GATING_OFFSET 0
  #define CPU_GATING_REG_CPU0_CLK_GATING_CLEAR_MASK 0x00000001
    #define CPU_GATING_REG_CPU0_CLK_GATING_CLOCK_IS_OFF 0x0
    #define CPU_GATING_REG_CPU0_CLK_GATING_CLOCK_IS_ON 0x1

#define TRACE_CLK_REG 0x00000508 //TRACE Clock Register
  #define TRACE_CLK_REG_TRACE_CLK_GATING_OFFSET 31
  #define TRACE_CLK_REG_TRACE_CLK_GATING_CLEAR_MASK 0x80000000
    #define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_OFF 0x0
    #define TRACE_CLK_REG_TRACE_CLK_GATING_CLOCK_IS_ON 0x1
  #define TRACE_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TRACE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define TRACE_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define TRACE_CLK_REG_CLK_SRC_SEL_CLK32K 0x001
    #define TRACE_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x010
    #define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x011
    #define TRACE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x100
  #define TRACE_CLK_REG_FACTOR_M_OFFSET 0
  #define TRACE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DSU_CLK_REG 0x0000050c //DSU Clock Register
  #define DSU_CLK_REG_DSU_CLK_SEL_OFFSET 24
  #define DSU_CLK_REG_DSU_CLK_SEL_CLEAR_MASK 0x07000000
    #define DSU_CLK_REG_DSU_CLK_SEL_HOSC 0x000
    #define DSU_CLK_REG_DSU_CLK_SEL_CLK32K 0x001
    #define DSU_CLK_REG_DSU_CLK_SEL_CLK16M_RC 0x010
    #define DSU_CLK_REG_DSU_CLK_SEL_CPU1PLL_P 0x011
    #define DSU_CLK_REG_DSU_CLK_SEL_PERI0PLL2X 0x100
    #define DSU_CLK_REG_DSU_CLK_SEL_PERI0_600M 0x101
  #define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_OFFSET 16
  #define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_CLEAR_MASK 0x00030000
    #define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_1 0x00
    #define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_2 0x01
    #define DSU_CLK_REG_PLL_CPU1_OUT_EXT_DIVP_4 0x10

#define AHB_CLK_REG 0x00000510 //AHB Clock Register
  #define AHB_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define AHB_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
    #define AHB_CLK_REG_CLK_SRC_SEL_HOSC 0x00
    #define AHB_CLK_REG_CLK_SRC_SEL_CLK32K 0x01
    #define AHB_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x10
    #define AHB_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0x11
  #define AHB_CLK_REG_FACTOR_M_OFFSET 0
  #define AHB_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define APB0_CLK_REG 0x00000520 //APB0 Clock Register
  #define APB0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define APB0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
    #define APB0_CLK_REG_CLK_SRC_SEL_HOSC 0x00
    #define APB0_CLK_REG_CLK_SRC_SEL_CLK32K 0x01
    #define APB0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x10
    #define APB0_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0x11
  #define APB0_CLK_REG_FACTOR_M_OFFSET 0
  #define APB0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define APB1_CLK_REG 0x00000524 //APB1 Clock Register
  #define APB1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define APB1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
    #define APB1_CLK_REG_CLK_SRC_SEL_HOSC 0x00
    #define APB1_CLK_REG_CLK_SRC_SEL_CLK32K 0x01
    #define APB1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x10
    #define APB1_CLK_REG_CLK_SRC_SEL_PERI0_600M_BUS 0x11
  #define APB1_CLK_REG_FACTOR_M_OFFSET 0
  #define APB1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define MBUS_CLK_REG 0x00000540 //MBUS Clock Register
  #define MBUS_CLK_REG_SCLK_GATING_OFFSET 31
  #define MBUS_CLK_REG_SCLK_GATING_CLEAR_MASK 0x80000000
    #define MBUS_CLK_REG_SCLK_GATING_CLOCK_IS_OFF 0x0
    #define MBUS_CLK_REG_SCLK_GATING_CLOCK_IS_ON 0x1
  #define MBUS_CLK_REG_MBUS_RST_OFFSET 30
  #define MBUS_CLK_REG_MBUS_RST_CLEAR_MASK 0x40000000
    #define MBUS_CLK_REG_MBUS_RST_ASSERT 0x0
    #define MBUS_CLK_REG_MBUS_RST_DE_ASSERT 0x1
  #define MBUS_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define MBUS_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define MBUS_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define MBUS_CLK_REG_CLK_SRC_SEL_DDRPLL 0x001
    #define MBUS_CLK_REG_CLK_SRC_SEL_PERI0_600M 0x010
    #define MBUS_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x011
    #define MBUS_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x100
  #define MBUS_CLK_REG_FACTOR_M_OFFSET 0
  #define MBUS_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define NSI_BGR_REG 0x0000054c //NSI Bus Gating Reset Register
  #define NSI_BGR_REG_NSI_RST_OFFSET 16
  #define NSI_BGR_REG_NSI_RST_CLEAR_MASK 0x00010000
    #define NSI_BGR_REG_NSI_RST_ASSERT 0x0
    #define NSI_BGR_REG_NSI_RST_DE_ASSERT 0x1
  #define NSI_BGR_REG_NSI_GATING_OFFSET 0
  #define NSI_BGR_REG_NSI_GATING_CLEAR_MASK 0x00000001
    #define NSI_BGR_REG_NSI_GATING_MASK 0x0
    #define NSI_BGR_REG_NSI_GATING_PASS 0x1

#define GIC_CLK_REG 0x00000550 //GIC Clock Register
  #define GIC_CLK_REG_GIC_CLK_GATING_OFFSET 31
  #define GIC_CLK_REG_GIC_CLK_GATING_CLEAR_MASK 0x80000000
    #define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_OFF 0x0
    #define GIC_CLK_REG_GIC_CLK_GATING_CLOCK_IS_ON 0x1
  #define GIC_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define GIC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x03000000
    #define GIC_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define GIC_CLK_REG_CLK_SRC_SEL_CLK32K 0x001
    #define GIC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0x010
    #define GIC_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x011
  #define GIC_CLK_REG_FACTOR_M_OFFSET 0
  #define GIC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DE0_CLK_REG 0x00000600 //DE0 Clock Register
  #define DE0_CLK_REG_DE_CLK_GATING_OFFSET 31
  #define DE0_CLK_REG_DE_CLK_GATING_CLEAR_MASK 0x80000000
    #define DE0_CLK_REG_DE_CLK_GATING_CLOCK_IS_OFF 0x0
    #define DE0_CLK_REG_DE_CLK_GATING_CLOCK_IS_ON 0x1
  #define DE0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define DE0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define DE0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x000
    #define DE0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
    #define DE0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
    #define DE0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x011
    #define DE0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x100
    #define DE0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x101
  #define DE0_CLK_REG_FACTOR_M_OFFSET 0
  #define DE0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DE_BGR_REG 0x0000060c //DE Bus Gating Reset Register
  #define DE_BGR_REG_DE0_RST_OFFSET 16
  #define DE_BGR_REG_DE0_RST_CLEAR_MASK 0x00010000
    #define DE_BGR_REG_DE0_RST_ASSERT 0x0
    #define DE_BGR_REG_DE0_RST_DE_ASSERT 0x1
  #define DE_BGR_REG_DE0_GATING_OFFSET 0
  #define DE_BGR_REG_DE0_GATING_CLEAR_MASK 0x00000001
    #define DE_BGR_REG_DE0_GATING_MASK 0x0
    #define DE_BGR_REG_DE0_GATING_PASS 0x1

#define DI_CLK_REG 0x00000620 //DI Clock Register
  #define DI_CLK_REG_DI_CLK_GATING_OFFSET 31
  #define DI_CLK_REG_DI_CLK_GATING_CLEAR_MASK 0x80000000
    #define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_OFF 0x0
    #define DI_CLK_REG_DI_CLK_GATING_CLOCK_IS_ON 0x1
  #define DI_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define DI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define DI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x000
    #define DI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
  #define DI_CLK_REG_FACTOR_M_OFFSET 0
  #define DI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DI_BGR_REG 0x0000062c //DI Bus Gating Reset Register
  #define DI_BGR_REG_DI_RST_OFFSET 16
  #define DI_BGR_REG_DI_RST_CLEAR_MASK 0x00010000
    #define DI_BGR_REG_DI_RST_ASSERT 0x0
    #define DI_BGR_REG_DI_RST_DE_ASSERT 0x1
  #define DI_BGR_REG_DI_GATING_OFFSET 0
  #define DI_BGR_REG_DI_GATING_CLEAR_MASK 0x00000001
    #define DI_BGR_REG_DI_GATING_MASK 0x0
    #define DI_BGR_REG_DI_GATING_PASS 0x1

#define G2D_CLK_REG 0x00000630 //G2D Clock Register
  #define G2D_CLK_REG_G2D_CLK_GATING_OFFSET 31
  #define G2D_CLK_REG_G2D_CLK_GATING_CLEAR_MASK 0x80000000
    #define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_OFF 0x0
    #define G2D_CLK_REG_G2D_CLK_GATING_CLOCK_IS_ON 0x1
  #define G2D_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define G2D_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define G2D_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x000
    #define G2D_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x001
    #define G2D_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
  #define G2D_CLK_REG_FACTOR_M_OFFSET 0
  #define G2D_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define G2D_BGR_REG 0x0000063c //G2D Bus Gating Reset Register
  #define G2D_BGR_REG_G2D_RST_OFFSET 16
  #define G2D_BGR_REG_G2D_RST_CLEAR_MASK 0x00010000
    #define G2D_BGR_REG_G2D_RST_ASSERT 0x0
    #define G2D_BGR_REG_G2D_RST_DE_ASSERT 0x1
  #define G2D_BGR_REG_G2D_GATING_OFFSET 0
  #define G2D_BGR_REG_G2D_GATING_CLEAR_MASK 0x00000001
    #define G2D_BGR_REG_G2D_GATING_MASK 0x0
    #define G2D_BGR_REG_G2D_GATING_PASS 0x1

#define GPU_CORE_CLK_REG 0x00000670 //GPU_CORE Clock Register
  #define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_OFFSET 31
  #define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLEAR_MASK 0x80000000
    #define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLOCK_IS_OFF 0x0
    #define GPU_CORE_CLK_REG_GPU_CORE_CLK_GATING_CLOCK_IS_ON 0x1
  #define GPU_CORE_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define GPU_CORE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define GPU_CORE_CLK_REG_CLK_SRC_SEL_GPUPLL 0x000
    #define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_800M 0x001
    #define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_600M 0x010
    #define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x011
    #define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x100
    #define GPU_CORE_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x101
  #define GPU_CORE_CLK_REG_FACTOR_M_OFFSET 0
  #define GPU_CORE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000000f
    #define GPU_CORE_CLK_REG_FACTOR_M_NOT_MASK 0x000
    #define GPU_CORE_CLK_REG_FACTOR_M_MASK_1_CYCLE_AT_16_CYCLES 0x001
    #define GPU_CORE_CLK_REG_FACTOR_M_MASK_2_CYCLES_AT_16_CYCLES 0x010

#define GPU_GATING_REG 0x0000067c //GPU Gating Reset Configuration Register
  #define GPU_GATING_REG_GPU_RST_OFFSET 16
  #define GPU_GATING_REG_GPU_RST_CLEAR_MASK 0x00010000
    #define GPU_GATING_REG_GPU_RST_ASSERT 0x0
    #define GPU_GATING_REG_GPU_RST_DE_ASSERT 0x1
  #define GPU_GATING_REG_GPU_GATING_OFFSET 0
  #define GPU_GATING_REG_GPU_GATING_CLEAR_MASK 0x00000001
    #define GPU_GATING_REG_GPU_GATING_MASK 0x0
    #define GPU_GATING_REG_GPU_GATING_PASS 0x1

#define CE_CLK_REG 0x00000680 //CE Clock Register
  #define CE_CLK_REG_CE_CLK_GATING_OFFSET 31
  #define CE_CLK_REG_CE_CLK_GATING_CLEAR_MASK 0x80000000
    #define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_OFF 0x0
    #define CE_CLK_REG_CE_CLK_GATING_CLOCK_IS_ON 0x1
  #define CE_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define CE_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define CE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x001
    #define CE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x010
    #define CE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x011
  #define CE_CLK_REG_FACTOR_M_OFFSET 0
  #define CE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define CE_BGR_REG 0x0000068c //CE Bus Gating Reset Register
  #define CE_BGR_REG_CE_SYS_RST_OFFSET 17
  #define CE_BGR_REG_CE_SYS_RST_CLEAR_MASK 0x00020000
    #define CE_BGR_REG_CE_SYS_RST_ASSERT 0x0
    #define CE_BGR_REG_CE_SYS_RST_DE_ASSERT 0x1
  #define CE_BGR_REG_CE_RST_OFFSET 16
  #define CE_BGR_REG_CE_RST_CLEAR_MASK 0x00010000
    #define CE_BGR_REG_CE_RST_ASSERT 0x0
    #define CE_BGR_REG_CE_RST_DE_ASSERT 0x1
  #define CE_BGR_REG_CE_SYS_GATING_OFFSET 1
  #define CE_BGR_REG_CE_SYS_GATING_CLEAR_MASK 0x00000002
    #define CE_BGR_REG_CE_SYS_GATING_MASK 0x0
    #define CE_BGR_REG_CE_SYS_GATING_PASS 0x1
  #define CE_BGR_REG_CE_GATING_OFFSET 0
  #define CE_BGR_REG_CE_GATING_CLEAR_MASK 0x00000001
    #define CE_BGR_REG_CE_GATING_MASK 0x0
    #define CE_BGR_REG_CE_GATING_PASS 0x1

#define VE_CLK_REG 0x00000690 //VE Clock Register
  #define VE_CLK_REG_VE_CLK_GATING_OFFSET 31
  #define VE_CLK_REG_VE_CLK_GATING_CLEAR_MASK 0x80000000
    #define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_OFF 0x0
    #define VE_CLK_REG_VE_CLK_GATING_CLOCK_IS_ON 0x1
  #define VE_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define VE_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define VE_CLK_REG_CLK_SRC_SEL_VEPLL 0x000
    #define VE_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x001
    #define VE_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x010
    #define VE_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x011
  #define VE_CLK_REG_FACTOR_M_OFFSET 0
  #define VE_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define VE_BGR_REG 0x0000069c //VE Bus Gating Reset Register
  #define VE_BGR_REG_VE_RST_OFFSET 16
  #define VE_BGR_REG_VE_RST_CLEAR_MASK 0x00010000
    #define VE_BGR_REG_VE_RST_ASSERT 0x0
    #define VE_BGR_REG_VE_RST_DE_ASSERT 0x1
  #define VE_BGR_REG_VE_GATING_OFFSET 0
  #define VE_BGR_REG_VE_GATING_CLEAR_MASK 0x00000001
    #define VE_BGR_REG_VE_GATING_MASK 0x0
    #define VE_BGR_REG_VE_GATING_PASS 0x1

#define NPU_CLK_REG 0x000006e0 //NPU Clock Register
  #define NPU_CLK_REG_NPU_CLK_GATING_OFFSET 31
  #define NPU_CLK_REG_NPU_CLK_GATING_CLEAR_MASK 0x80000000
    #define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_OFF 0x0
    #define NPU_CLK_REG_NPU_CLK_GATING_CLOCK_IS_ON 0x1
  #define NPU_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define NPU_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define NPU_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x000
    #define NPU_CLK_REG_CLK_SRC_SEL_PERI0_600M 0x001
    #define NPU_CLK_REG_CLK_SRC_SEL_PERI0_800M 0x010
    #define NPU_CLK_REG_CLK_SRC_SEL_NPUPLL4X 0x011
  #define NPU_CLK_REG_FACTOR_M_OFFSET 0
  #define NPU_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DMA_BGR_REG 0x0000070c //DMA Bus Gating Reset Register
  #define DMA_BGR_REG_DMA_RST_OFFSET 16
  #define DMA_BGR_REG_DMA_RST_CLEAR_MASK 0x00010000
    #define DMA_BGR_REG_DMA_RST_ASSERT 0x0
    #define DMA_BGR_REG_DMA_RST_DE_ASSERT 0x1
  #define DMA_BGR_REG_DMA_GATING_OFFSET 0
  #define DMA_BGR_REG_DMA_GATING_CLEAR_MASK 0x00000001
    #define DMA_BGR_REG_DMA_GATING_MASK 0x0
    #define DMA_BGR_REG_DMA_GATING_PASS 0x1

#define MSGBOX_BGR_REG 0x0000071c //MSGBOX Bus Gating Reset Register
  #define MSGBOX_BGR_REG_MSGBOX1_RST_OFFSET 17
  #define MSGBOX_BGR_REG_MSGBOX1_RST_CLEAR_MASK 0x00020000
    #define MSGBOX_BGR_REG_MSGBOX1_RST_ASSERT 0x0
    #define MSGBOX_BGR_REG_MSGBOX1_RST_DE_ASSERT 0x1
  #define MSGBOX_BGR_REG_MSGBOX0_RST_OFFSET 16
  #define MSGBOX_BGR_REG_MSGBOX0_RST_CLEAR_MASK 0x00010000
    #define MSGBOX_BGR_REG_MSGBOX0_RST_ASSERT 0x0
    #define MSGBOX_BGR_REG_MSGBOX0_RST_DE_ASSERT 0x1
  #define MSGBOX_BGR_REG_MSGBOX1_GATING_OFFSET 1
  #define MSGBOX_BGR_REG_MSGBOX1_GATING_CLEAR_MASK 0x00000002
    #define MSGBOX_BGR_REG_MSGBOX1_GATING_MASK 0x0
    #define MSGBOX_BGR_REG_MSGBOX1_GATING_PASS 0x1
  #define MSGBOX_BGR_REG_MSGBOX0_GATING_OFFSET 0
  #define MSGBOX_BGR_REG_MSGBOX0_GATING_CLEAR_MASK 0x00000001
    #define MSGBOX_BGR_REG_MSGBOX0_GATING_MASK 0x0
    #define MSGBOX_BGR_REG_MSGBOX0_GATING_PASS 0x1

#define SPINLOCK_BGR_REG 0x0000072c //SPINLOCK Bus Gating Reset Register
  #define SPINLOCK_BGR_REG_SPINLOCK_RST_OFFSET 16
  #define SPINLOCK_BGR_REG_SPINLOCK_RST_CLEAR_MASK 0x00010000
    #define SPINLOCK_BGR_REG_SPINLOCK_RST_ASSERT 0x0
    #define SPINLOCK_BGR_REG_SPINLOCK_RST_DE_ASSERT 0x1
  #define SPINLOCK_BGR_REG_SPINLOCK_GATING_OFFSET 0
  #define SPINLOCK_BGR_REG_SPINLOCK_GATING_CLEAR_MASK 0x00000001
    #define SPINLOCK_BGR_REG_SPINLOCK_GATING_MASK 0x0
    #define SPINLOCK_BGR_REG_SPINLOCK_GATING_PASS 0x1

#define TIMER0_CLK_REG 0x00000730 //TIMER0 Clock Register
  #define TIMER0_CLK_REG_TIMER0_CLK_GATING_OFFSET 31
  #define TIMER0_CLK_REG_TIMER0_CLK_GATING_CLEAR_MASK 0x80000000
    #define TIMER0_CLK_REG_TIMER0_CLK_GATING_DISABLE 0x0
    #define TIMER0_CLK_REG_TIMER0_CLK_GATING_ENABLE 0x1
  #define TIMER0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define TIMER0_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define TIMER0_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x001
    #define TIMER0_CLK_REG_CLK_SRC_SEL_CLK32K 0x010
    #define TIMER0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x011
  #define TIMER0_CLK_REG_FACTOR_M_OFFSET 0
  #define TIMER0_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
    #define TIMER0_CLK_REG_FACTOR_M__1 0x000
    #define TIMER0_CLK_REG_FACTOR_M__2 0x001
    #define TIMER0_CLK_REG_FACTOR_M__4 0x010
    #define TIMER0_CLK_REG_FACTOR_M__8 0x011
    #define TIMER0_CLK_REG_FACTOR_M__16 0x100
    #define TIMER0_CLK_REG_FACTOR_M__32 0x101
    #define TIMER0_CLK_REG_FACTOR_M__64 0x110
    #define TIMER0_CLK_REG_FACTOR_M__128 0x111

#define TIMER1_CLK_REG 0x00000734 //TIMER1 Clock Register
  #define TIMER1_CLK_REG_TIMER1_CLK_GATING_OFFSET 31
  #define TIMER1_CLK_REG_TIMER1_CLK_GATING_CLEAR_MASK 0x80000000
    #define TIMER1_CLK_REG_TIMER1_CLK_GATING_DISABLE 0x0
    #define TIMER1_CLK_REG_TIMER1_CLK_GATING_ENABLE 0x1
  #define TIMER1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define TIMER1_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define TIMER1_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x001
    #define TIMER1_CLK_REG_CLK_SRC_SEL_CLK32K 0x010
    #define TIMER1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x011
  #define TIMER1_CLK_REG_FACTOR_M_OFFSET 0
  #define TIMER1_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
    #define TIMER1_CLK_REG_FACTOR_M__1 0x000
    #define TIMER1_CLK_REG_FACTOR_M__2 0x001
    #define TIMER1_CLK_REG_FACTOR_M__4 0x010
    #define TIMER1_CLK_REG_FACTOR_M__8 0x011
    #define TIMER1_CLK_REG_FACTOR_M__16 0x100
    #define TIMER1_CLK_REG_FACTOR_M__32 0x101
    #define TIMER1_CLK_REG_FACTOR_M__64 0x110
    #define TIMER1_CLK_REG_FACTOR_M__128 0x111

#define TIMER2_CLK_REG 0x00000738 //TIMER2 Clock Register
  #define TIMER2_CLK_REG_TIMER2_CLK_GATING_OFFSET 31
  #define TIMER2_CLK_REG_TIMER2_CLK_GATING_CLEAR_MASK 0x80000000
    #define TIMER2_CLK_REG_TIMER2_CLK_GATING_DISABLE 0x0
    #define TIMER2_CLK_REG_TIMER2_CLK_GATING_ENABLE 0x1
  #define TIMER2_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define TIMER2_CLK_REG_CLK_SRC_SEL_HOSC 0x00
    #define TIMER2_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x001
    #define TIMER2_CLK_REG_CLK_SRC_SEL_CLK32K 0x010
    #define TIMER2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x011
  #define TIMER2_CLK_REG_FACTOR_M_OFFSET 0
  #define TIMER2_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
    #define TIMER2_CLK_REG_FACTOR_M__1 0x000
    #define TIMER2_CLK_REG_FACTOR_M__2 0x001
    #define TIMER2_CLK_REG_FACTOR_M__4 0x010
    #define TIMER2_CLK_REG_FACTOR_M__8 0x011
    #define TIMER2_CLK_REG_FACTOR_M__16 0x100
    #define TIMER2_CLK_REG_FACTOR_M__32 0x101
    #define TIMER2_CLK_REG_FACTOR_M__64 0x110
    #define TIMER2_CLK_REG_FACTOR_M__128 0x111

#define TIMER3_CLK_REG 0x0000073c //TIMER3 Clock Register
  #define TIMER3_CLK_REG_TIMER3_CLK_GATING_OFFSET 31
  #define TIMER3_CLK_REG_TIMER3_CLK_GATING_CLEAR_MASK 0x80000000
    #define TIMER3_CLK_REG_TIMER3_CLK_GATING_DISABLE 0x0
    #define TIMER3_CLK_REG_TIMER3_CLK_GATING_ENABLE 0x1
  #define TIMER3_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define TIMER3_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define TIMER3_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x001
    #define TIMER3_CLK_REG_CLK_SRC_SEL_CLK32K 0x010
    #define TIMER3_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x011
  #define TIMER3_CLK_REG_FACTOR_M_OFFSET 0
  #define TIMER3_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
    #define TIMER3_CLK_REG_FACTOR_M__1 0x000
    #define TIMER3_CLK_REG_FACTOR_M__2 0x001
    #define TIMER3_CLK_REG_FACTOR_M__4 0x010
    #define TIMER3_CLK_REG_FACTOR_M__8 0x011
    #define TIMER3_CLK_REG_FACTOR_M__16 0x100
    #define TIMER3_CLK_REG_FACTOR_M__32 0x101
    #define TIMER3_CLK_REG_FACTOR_M__64 0x110
    #define TIMER3_CLK_REG_FACTOR_M__128 0x111

#define TIMER4_CLK_REG 0x00000740 //TIMER4 Clock Register
  #define TIMER4_CLK_REG_TIMER4_CLK_GATING_OFFSET 31
  #define TIMER4_CLK_REG_TIMER4_CLK_GATING_CLEAR_MASK 0x80000000
    #define TIMER4_CLK_REG_TIMER4_CLK_GATING_DISABLE 0x0
    #define TIMER4_CLK_REG_TIMER4_CLK_GATING_ENABLE 0x1
  #define TIMER4_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER4_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define TIMER4_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define TIMER4_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x001
    #define TIMER4_CLK_REG_CLK_SRC_SEL_CLK32K 0x010
    #define TIMER4_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x011
  #define TIMER4_CLK_REG_FACTOR_M_OFFSET 0
  #define TIMER4_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
    #define TIMER4_CLK_REG_FACTOR_M__1 0x000
    #define TIMER4_CLK_REG_FACTOR_M__2 0x001
    #define TIMER4_CLK_REG_FACTOR_M__4 0x010
    #define TIMER4_CLK_REG_FACTOR_M__8 0x011
    #define TIMER4_CLK_REG_FACTOR_M__16 0x100
    #define TIMER4_CLK_REG_FACTOR_M__32 0x101
    #define TIMER4_CLK_REG_FACTOR_M__64 0x110
    #define TIMER4_CLK_REG_FACTOR_M__128 0x111

#define TIMER5_CLK_REG 0x00000744 //TIMER5 Clock Register
  #define TIMER5_CLK_REG_TIMER5_CLK_GATING_OFFSET 31
  #define TIMER5_CLK_REG_TIMER5_CLK_GATING_CLEAR_MASK 0x80000000
    #define TIMER5_CLK_REG_TIMER5_CLK_GATING_DISABLE 0x0
    #define TIMER5_CLK_REG_TIMER5_CLK_GATING_ENABLE 0x1
  #define TIMER5_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TIMER5_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define TIMER5_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define TIMER5_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x001
    #define TIMER5_CLK_REG_CLK_SRC_SEL_CLK32K 0x010
    #define TIMER5_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x011
  #define TIMER5_CLK_REG_FACTOR_M_OFFSET 0
  #define TIMER5_CLK_REG_FACTOR_M_CLEAR_MASK 0x00000007
    #define TIMER5_CLK_REG_FACTOR_M__1 0x000
    #define TIMER5_CLK_REG_FACTOR_M__2 0x001
    #define TIMER5_CLK_REG_FACTOR_M__4 0x010
    #define TIMER5_CLK_REG_FACTOR_M__8 0x011
    #define TIMER5_CLK_REG_FACTOR_M__16 0x100
    #define TIMER5_CLK_REG_FACTOR_M__32 0x101
    #define TIMER5_CLK_REG_FACTOR_M__64 0x110
    #define TIMER5_CLK_REG_FACTOR_M__128 0x111

#define TIMER_BGR_REG 0x0000074c //TIMER Bus Gating Reset Register
  #define TIMER_BGR_REG_TIMER_RST_OFFSET 16
  #define TIMER_BGR_REG_TIMER_RST_CLEAR_MASK 0x00010000
    #define TIMER_BGR_REG_TIMER_RST_ASSERT 0x0
    #define TIMER_BGR_REG_TIMER_RST_DE_ASSERT 0x1
  #define TIMER_BGR_REG_TIMER_GATING_OFFSET 0
  #define TIMER_BGR_REG_TIMER_GATING_CLEAR_MASK 0x00000001
    #define TIMER_BGR_REG_TIMER_GATING_MASK 0x0
    #define TIMER_BGR_REG_TIMER_GATING_PASS 0x1

#define AVS_CLK_REG 0x00000750 //AVS Clock Register
  #define AVS_CLK_REG_AVS_CLK_GATING_OFFSET 31
  #define AVS_CLK_REG_AVS_CLK_GATING_CLEAR_MASK 0x80000000
    #define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_OFF 0x0
    #define AVS_CLK_REG_AVS_CLK_GATING_CLOCK_IS_ON 0x1

#define DBGSYS_BGR_REG 0x0000078c //DBGSYS Bus Gating Reset Register
  #define DBGSYS_BGR_REG_DBGSYS_RST_OFFSET 16
  #define DBGSYS_BGR_REG_DBGSYS_RST_CLEAR_MASK 0x00010000
    #define DBGSYS_BGR_REG_DBGSYS_RST_ASSERT 0x0
    #define DBGSYS_BGR_REG_DBGSYS_RST_DE_ASSERT 0x1
  #define DBGSYS_BGR_REG_DBGSYS_GATING_OFFSET 0
  #define DBGSYS_BGR_REG_DBGSYS_GATING_CLEAR_MASK 0x00000001
    #define DBGSYS_BGR_REG_DBGSYS_GATING_MASK 0x0
    #define DBGSYS_BGR_REG_DBGSYS_GATING_PASS 0x1

#define PWM_BGR_REG 0x000007ac //PWM Bus Gating Reset Register
  #define PWM_BGR_REG_PWM_RST_OFFSET 16
  #define PWM_BGR_REG_PWM_RST_CLEAR_MASK 0x00010000
    #define PWM_BGR_REG_PWM_RST_ASSERT 0x0
    #define PWM_BGR_REG_PWM_RST_DE_ASSERT 0x1
  #define PWM_BGR_REG_PWM_GATING_OFFSET 0
  #define PWM_BGR_REG_PWM_GATING_CLEAR_MASK 0x00000001
    #define PWM_BGR_REG_PWM_GATING_MASK 0x0
    #define PWM_BGR_REG_PWM_GATING_PASS 0x1

#define IOMMU_BGR_REG 0x000007bc //IOMMU Bus Gating Reset Register
  #define IOMMU_BGR_REG_IOMMU_GATING_OFFSET 0
  #define IOMMU_BGR_REG_IOMMU_GATING_CLEAR_MASK 0x00000001
    #define IOMMU_BGR_REG_IOMMU_GATING_MASK 0x0
    #define IOMMU_BGR_REG_IOMMU_GATING_PASS 0x1

#define DRAM_CLK_REG 0x00000800 //DRAM Clock Register
  #define DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET 31
  #define DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK 0x80000000
    #define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF 0x0
    #define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON 0x1
  #define DRAM_CLK_REG_DRAM_UPD_OFFSET 27
  #define DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK 0x08000000
    #define DRAM_CLK_REG_DRAM_UPD_INVALID 0x0
    #define DRAM_CLK_REG_DRAM_UPD_VALID 0x1
  #define DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET 24
  #define DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK 0x07000000
    #define DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL 0x000
    #define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_600M 0x001
    #define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_480M 0x010
    #define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_400M 0x011
    #define DRAM_CLK_REG_DRAM_CLK_SEL_PERI1_150M 0x100
  #define DRAM_CLK_REG_DRAM_DIV1_OFFSET 0
  #define DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK 0x0000001f

#define MBUS_MAT_CLK_GATING_REG 0x00000804 //MBUS Master Clock Gating Register
  #define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_OFFSET 22
  #define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00400000
    #define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_DISABLE 0x0
    #define MBUS_MAT_CLK_GATING_REG_NAND_MBUS_GATE_SW_CFG_ENABLE 0x1
  #define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_OFFSET 21
  #define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00200000
    #define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_DISABLE 0x0
    #define MBUS_MAT_CLK_GATING_REG_NPU_MBUS_GATE_SW_CFG_ENABLE 0x1
  #define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_OFFSET 20
  #define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00100000
    #define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_DISABLE 0x0
    #define MBUS_MAT_CLK_GATING_REG_VID_IN_MBUS_GATE_SW_CFG_ENABLE 0x1
  #define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_OFFSET 19
  #define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00080000
    #define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_DISABLE 0x0
    #define MBUS_MAT_CLK_GATING_REG_VID_OUT_MBUS_GATE_SW_CFG_ENABLE 0x1
  #define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_OFFSET 18
  #define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00040000
    #define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_DISABLE 0x0
    #define MBUS_MAT_CLK_GATING_REG_CE_MBUS_GATE_SW_CFG_ENABLE 0x1
  #define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_OFFSET 17
  #define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00020000
    #define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_DISABLE 0x0
    #define MBUS_MAT_CLK_GATING_REG_VE_MBUS_GATE_SW_CFG_ENABLE 0x1
  #define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_OFFSET 16
  #define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_CLEAR_MASK 0x00010000
    #define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_DISABLE 0x0
    #define MBUS_MAT_CLK_GATING_REG_DMA_MBUS_GATE_SW_CFG_ENABLE 0x1
  #define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_OFFSET 9
  #define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_CLEAR_MASK 0x00000200
    #define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_MASK 0x0
    #define MBUS_MAT_CLK_GATING_REG_ISP_MCLK_EN_PASS 0x1
  #define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_OFFSET 8
  #define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_CLEAR_MASK 0x00000100
    #define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_MASK 0x0
    #define MBUS_MAT_CLK_GATING_REG_CSI_MCLK_EN_PASS 0x1
  #define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_OFFSET 6
  #define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_CLEAR_MASK 0x00000040
    #define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_MASK 0x0
    #define MBUS_MAT_CLK_GATING_REG_USB3_MCLK_EN_PASS 0x1
  #define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_OFFSET 5
  #define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_CLEAR_MASK 0x00000020
    #define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_MASK 0x0
    #define MBUS_MAT_CLK_GATING_REG_NAND_MCLK_EN_PASS 0x1
  #define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_OFFSET 2
  #define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_CLEAR_MASK 0x00000004
    #define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_MASK 0x0
    #define MBUS_MAT_CLK_GATING_REG_CE_MCLK_EN_PASS 0x1
  #define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_OFFSET 1
  #define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_CLEAR_MASK 0x00000002
    #define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_MASK 0x0
    #define MBUS_MAT_CLK_GATING_REG_VE_MCLK_EN_PASS 0x1
  #define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_OFFSET 0
  #define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_CLEAR_MASK 0x00000001
    #define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_MASK 0x0
    #define MBUS_MAT_CLK_GATING_REG_DMA_MCLK_EN_PASS 0x1

#define DRAM_BGR_REG 0x0000080c //DRAM Bus Gating Reset Register
  #define DRAM_BGR_REG_DRAM_RST_OFFSET 16
  #define DRAM_BGR_REG_DRAM_RST_CLEAR_MASK 0x00010000
    #define DRAM_BGR_REG_DRAM_RST_ASSERT 0x0
    #define DRAM_BGR_REG_DRAM_RST_DE_ASSERT 0x1
  #define DRAM_BGR_REG_DRAM_GATING_OFFSET 0
  #define DRAM_BGR_REG_DRAM_GATING_CLEAR_MASK 0x00000001
    #define DRAM_BGR_REG_DRAM_GATING_MASK 0x0
    #define DRAM_BGR_REG_DRAM_GATING_PASS 0x1

#define NAND0_CLK0_CLK_REG 0x00000810 //NAND0 CLK0 Clock Register
  #define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_OFFSET 31
  #define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLEAR_MASK 0x80000000
    #define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_OFF 0x0
    #define NAND0_CLK0_CLK_REG_NAND0_CLK0_CLK_GATING_CLOCK_IS_ON 0x1
  #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
    #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x010
    #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0x011
    #define NAND0_CLK0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x100
  #define NAND0_CLK0_CLK_REG_FACTOR_M_OFFSET 0
  #define NAND0_CLK0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define NAND0_CLK1_CLK_REG 0x00000814 //NAND0 CLK1 Clock Register
  #define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_OFFSET 31
  #define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLEAR_MASK 0x80000000
    #define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_OFF 0x0
    #define NAND0_CLK1_CLK_REG_NAND0_CLK1_CLK_GATING_CLOCK_IS_ON 0x1
  #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
    #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x010
    #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0x011
    #define NAND0_CLK1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x100
  #define NAND0_CLK1_CLK_REG_FACTOR_M_OFFSET 0
  #define NAND0_CLK1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define NAND_BGR_REG 0x0000082c //NAND Bus Gating Reset Register
  #define NAND_BGR_REG_NAND0_RST_OFFSET 16
  #define NAND_BGR_REG_NAND0_RST_CLEAR_MASK 0x00010000
    #define NAND_BGR_REG_NAND0_RST_ASSERT 0x0
    #define NAND_BGR_REG_NAND0_RST_DE_ASSERT 0x1
  #define NAND_BGR_REG_NAND0_GATING_OFFSET 0
  #define NAND_BGR_REG_NAND0_GATING_CLEAR_MASK 0x00000001
    #define NAND_BGR_REG_NAND0_GATING_MASK 0x0
    #define NAND_BGR_REG_NAND0_GATING_PASS 0x1

#define SMHC0_CLK_REG 0x00000830 //SMHC0 Clock Register
  #define SMHC0_CLK_REG_SMHC0_CLK_GATING_OFFSET 31
  #define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLEAR_MASK 0x80000000
    #define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_OFF 0x0
    #define SMHC0_CLK_REG_SMHC0_CLK_GATING_CLOCK_IS_ON 0x1
  #define SMHC0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SMHC0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define SMHC0_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
    #define SMHC0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x010
    #define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_400M 0x011
    #define SMHC0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x100
  #define SMHC0_CLK_REG_FACTOR_N_OFFSET 8
  #define SMHC0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
  #define SMHC0_CLK_REG_FACTOR_M_OFFSET 0
  #define SMHC0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SMHC1_CLK_REG 0x00000834 //SMHC1 Clock Register
  #define SMHC1_CLK_REG_SMHC1_CLK_GATING_OFFSET 31
  #define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLEAR_MASK 0x80000000
    #define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_OFF 0x0
    #define SMHC1_CLK_REG_SMHC1_CLK_GATING_CLOCK_IS_ON 0x1
  #define SMHC1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SMHC1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define SMHC1_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
    #define SMHC1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x010
    #define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_400M 0x011
    #define SMHC1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x100
  #define SMHC1_CLK_REG_FACTOR_N_OFFSET 8
  #define SMHC1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
  #define SMHC1_CLK_REG_FACTOR_M_OFFSET 0
  #define SMHC1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SMHC2_CLK_REG 0x00000838 //SMHC2 Clock Register
  #define SMHC2_CLK_REG_SMHC2_CLK_GATING_OFFSET 31
  #define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLEAR_MASK 0x80000000
    #define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_OFF 0x0
    #define SMHC2_CLK_REG_SMHC2_CLK_GATING_CLOCK_IS_ON 0x1
  #define SMHC2_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SMHC2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define SMHC2_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_800M 0x001
    #define SMHC2_CLK_REG_CLK_SRC_SEL_PERI0_600M 0x010
    #define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_800M 0x011
    #define SMHC2_CLK_REG_CLK_SRC_SEL_PERI1_600M 0x100
  #define SMHC2_CLK_REG_FACTOR_N_OFFSET 8
  #define SMHC2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
  #define SMHC2_CLK_REG_FACTOR_M_OFFSET 0
  #define SMHC2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SMHC_BGR_REG 0x0000084c //SMHC Bus Gating Reset Register
  #define SMHC_BGR_REG_SMHC2_RST_OFFSET 18
  #define SMHC_BGR_REG_SMHC2_RST_CLEAR_MASK 0x00040000
    #define SMHC_BGR_REG_SMHC2_RST_ASSERT 0x0
    #define SMHC_BGR_REG_SMHC2_RST_DE_ASSERT 0x1
  #define SMHC_BGR_REG_SMHC1_RST_OFFSET 17
  #define SMHC_BGR_REG_SMHC1_RST_CLEAR_MASK 0x00020000
    #define SMHC_BGR_REG_SMHC1_RST_ASSERT 0x0
    #define SMHC_BGR_REG_SMHC1_RST_DE_ASSERT 0x1
  #define SMHC_BGR_REG_SMHC0_RST_OFFSET 16
  #define SMHC_BGR_REG_SMHC0_RST_CLEAR_MASK 0x00010000
    #define SMHC_BGR_REG_SMHC0_RST_ASSERT 0x0
    #define SMHC_BGR_REG_SMHC0_RST_DE_ASSERT 0x1
  #define SMHC_BGR_REG_SMHC2_GATING_OFFSET 2
  #define SMHC_BGR_REG_SMHC2_GATING_CLEAR_MASK 0x00000004
    #define SMHC_BGR_REG_SMHC2_GATING_MASK 0x0
    #define SMHC_BGR_REG_SMHC2_GATING_PASS 0x1
  #define SMHC_BGR_REG_SMHC1_GATING_OFFSET 1
  #define SMHC_BGR_REG_SMHC1_GATING_CLEAR_MASK 0x00000002
    #define SMHC_BGR_REG_SMHC1_GATING_MASK 0x0
    #define SMHC_BGR_REG_SMHC1_GATING_PASS 0x1
  #define SMHC_BGR_REG_SMHC0_GATING_OFFSET 0
  #define SMHC_BGR_REG_SMHC0_GATING_CLEAR_MASK 0x00000001
    #define SMHC_BGR_REG_SMHC0_GATING_MASK 0x0
    #define SMHC_BGR_REG_SMHC0_GATING_PASS 0x1

#define SYSDAP_BGR_REG 0x0000088c //SYSDAP Bus Gating Reset Register
  #define SYSDAP_BGR_REG_SYSDAP_RST_OFFSET 16
  #define SYSDAP_BGR_REG_SYSDAP_RST_CLEAR_MASK 0x00010000
    #define SYSDAP_BGR_REG_SYSDAP_RST_ASSERT 0x0
    #define SYSDAP_BGR_REG_SYSDAP_RST_DE_ASSERT 0x1
  #define SYSDAP_BGR_REG_SYSDAP_GATING_OFFSET 0
  #define SYSDAP_BGR_REG_SYSDAP_GATING_CLEAR_MASK 0x00000001
    #define SYSDAP_BGR_REG_SYSDAP_GATING_MASK 0x0
    #define SYSDAP_BGR_REG_SYSDAP_GATING_PASS 0x1

#define UART_BGR_REG 0x0000090c //UART Bus Gating Reset Register
  #define UART_BGR_REG_UART7_RST_OFFSET 23
  #define UART_BGR_REG_UART7_RST_CLEAR_MASK 0x00800000
    #define UART_BGR_REG_UART7_RST_ASSERT 0x0
    #define UART_BGR_REG_UART7_RST_DE_ASSERT 0x1
  #define UART_BGR_REG_UART6_RST_OFFSET 22
  #define UART_BGR_REG_UART6_RST_CLEAR_MASK 0x00400000
    #define UART_BGR_REG_UART6_RST_ASSERT 0x0
    #define UART_BGR_REG_UART6_RST_DE_ASSERT 0x1
  #define UART_BGR_REG_UART5_RST_OFFSET 21
  #define UART_BGR_REG_UART5_RST_CLEAR_MASK 0x00200000
    #define UART_BGR_REG_UART5_RST_ASSERT 0x0
    #define UART_BGR_REG_UART5_RST_DE_ASSERT 0x1
  #define UART_BGR_REG_UART4_RST_OFFSET 20
  #define UART_BGR_REG_UART4_RST_CLEAR_MASK 0x00100000
    #define UART_BGR_REG_UART4_RST_ASSERT 0x0
    #define UART_BGR_REG_UART4_RST_DE_ASSERT 0x1
  #define UART_BGR_REG_UART3_RST_OFFSET 19
  #define UART_BGR_REG_UART3_RST_CLEAR_MASK 0x00080000
    #define UART_BGR_REG_UART3_RST_ASSERT 0x0
    #define UART_BGR_REG_UART3_RST_DE_ASSERT 0x1
  #define UART_BGR_REG_UART2_RST_OFFSET 18
  #define UART_BGR_REG_UART2_RST_CLEAR_MASK 0x00040000
    #define UART_BGR_REG_UART2_RST_ASSERT 0x0
    #define UART_BGR_REG_UART2_RST_DE_ASSERT 0x1
  #define UART_BGR_REG_UART1_RST_OFFSET 17
  #define UART_BGR_REG_UART1_RST_CLEAR_MASK 0x00020000
    #define UART_BGR_REG_UART1_RST_ASSERT 0x0
    #define UART_BGR_REG_UART1_RST_DE_ASSERT 0x1
  #define UART_BGR_REG_UART0_RST_OFFSET 16
  #define UART_BGR_REG_UART0_RST_CLEAR_MASK 0x00010000
    #define UART_BGR_REG_UART0_RST_ASSERT 0x0
    #define UART_BGR_REG_UART0_RST_DE_ASSERT 0x1
  #define UART_BGR_REG_UART7_GATING_OFFSET 7
  #define UART_BGR_REG_UART7_GATING_CLEAR_MASK 0x00000080
    #define UART_BGR_REG_UART7_GATING_MASK 0x0
    #define UART_BGR_REG_UART7_GATING_PASS 0x1
  #define UART_BGR_REG_UART6_GATING_OFFSET 6
  #define UART_BGR_REG_UART6_GATING_CLEAR_MASK 0x00000040
    #define UART_BGR_REG_UART6_GATING_MASK 0x0
    #define UART_BGR_REG_UART6_GATING_PASS 0x1
  #define UART_BGR_REG_UART5_GATING_OFFSET 5
  #define UART_BGR_REG_UART5_GATING_CLEAR_MASK 0x00000020
    #define UART_BGR_REG_UART5_GATING_MASK 0x0
    #define UART_BGR_REG_UART5_GATING_PASS 0x1
  #define UART_BGR_REG_UART4_GATING_OFFSET 4
  #define UART_BGR_REG_UART4_GATING_CLEAR_MASK 0x00000010
    #define UART_BGR_REG_UART4_GATING_MASK 0x0
    #define UART_BGR_REG_UART4_GATING_PASS 0x1
  #define UART_BGR_REG_UART3_GATING_OFFSET 3
  #define UART_BGR_REG_UART3_GATING_CLEAR_MASK 0x00000008
    #define UART_BGR_REG_UART3_GATING_MASK 0x0
    #define UART_BGR_REG_UART3_GATING_PASS 0x1
  #define UART_BGR_REG_UART2_GATING_OFFSET 2
  #define UART_BGR_REG_UART2_GATING_CLEAR_MASK 0x00000004
    #define UART_BGR_REG_UART2_GATING_MASK 0x0
    #define UART_BGR_REG_UART2_GATING_PASS 0x1
  #define UART_BGR_REG_UART1_GATING_OFFSET 1
  #define UART_BGR_REG_UART1_GATING_CLEAR_MASK 0x00000002
    #define UART_BGR_REG_UART1_GATING_MASK 0x0
    #define UART_BGR_REG_UART1_GATING_PASS 0x1
  #define UART_BGR_REG_UART0_GATING_OFFSET 0
  #define UART_BGR_REG_UART0_GATING_CLEAR_MASK 0x00000001
    #define UART_BGR_REG_UART0_GATING_MASK 0x0
    #define UART_BGR_REG_UART0_GATING_PASS 0x1

#define TWI_BGR_REG 0x0000091c //TWI Bus Gating Reset Register
  #define TWI_BGR_REG_TWI5_RST_OFFSET 21
  #define TWI_BGR_REG_TWI5_RST_CLEAR_MASK 0x00200000
    #define TWI_BGR_REG_TWI5_RST_ASSERT 0x0
    #define TWI_BGR_REG_TWI5_RST_DE_ASSERT 0x1
  #define TWI_BGR_REG_TWI4_RST_OFFSET 20
  #define TWI_BGR_REG_TWI4_RST_CLEAR_MASK 0x00100000
    #define TWI_BGR_REG_TWI4_RST_ASSERT 0x0
    #define TWI_BGR_REG_TWI4_RST_DE_ASSERT 0x1
  #define TWI_BGR_REG_TWI3_RST_OFFSET 19
  #define TWI_BGR_REG_TWI3_RST_CLEAR_MASK 0x00080000
    #define TWI_BGR_REG_TWI3_RST_ASSERT 0x0
    #define TWI_BGR_REG_TWI3_RST_DE_ASSERT 0x1
  #define TWI_BGR_REG_TWI2_RST_OFFSET 18
  #define TWI_BGR_REG_TWI2_RST_CLEAR_MASK 0x00040000
    #define TWI_BGR_REG_TWI2_RST_ASSERT 0x0
    #define TWI_BGR_REG_TWI2_RST_DE_ASSERT 0x1
  #define TWI_BGR_REG_TWI1_RST_OFFSET 17
  #define TWI_BGR_REG_TWI1_RST_CLEAR_MASK 0x00020000
    #define TWI_BGR_REG_TWI1_RST_ASSERT 0x0
    #define TWI_BGR_REG_TWI1_RST_DE_ASSERT 0x1
  #define TWI_BGR_REG_TWI0_RST_OFFSET 16
  #define TWI_BGR_REG_TWI0_RST_CLEAR_MASK 0x00010000
    #define TWI_BGR_REG_TWI0_RST_ASSERT 0x0
    #define TWI_BGR_REG_TWI0_RST_DE_ASSERT 0x1
  #define TWI_BGR_REG_TWI5_GATING_OFFSET 5
  #define TWI_BGR_REG_TWI5_GATING_CLEAR_MASK 0x00000020
    #define TWI_BGR_REG_TWI5_GATING_MASK 0x0
    #define TWI_BGR_REG_TWI5_GATING_PASS 0x1
  #define TWI_BGR_REG_TWI4_GATING_OFFSET 4
  #define TWI_BGR_REG_TWI4_GATING_CLEAR_MASK 0x00000010
    #define TWI_BGR_REG_TWI4_GATING_MASK 0x0
    #define TWI_BGR_REG_TWI4_GATING_PASS 0x1
  #define TWI_BGR_REG_TWI3_GATING_OFFSET 3
  #define TWI_BGR_REG_TWI3_GATING_CLEAR_MASK 0x00000008
    #define TWI_BGR_REG_TWI3_GATING_MASK 0x0
    #define TWI_BGR_REG_TWI3_GATING_PASS 0x1
  #define TWI_BGR_REG_TWI2_GATING_OFFSET 2
  #define TWI_BGR_REG_TWI2_GATING_CLEAR_MASK 0x00000004
    #define TWI_BGR_REG_TWI2_GATING_MASK 0x0
    #define TWI_BGR_REG_TWI2_GATING_PASS 0x1
  #define TWI_BGR_REG_TWI1_GATING_OFFSET 1
  #define TWI_BGR_REG_TWI1_GATING_CLEAR_MASK 0x00000002
    #define TWI_BGR_REG_TWI1_GATING_MASK 0x0
    #define TWI_BGR_REG_TWI1_GATING_PASS 0x1
  #define TWI_BGR_REG_TWI0_GATING_OFFSET 0
  #define TWI_BGR_REG_TWI0_GATING_CLEAR_MASK 0x00000001
    #define TWI_BGR_REG_TWI0_GATING_MASK 0x0
    #define TWI_BGR_REG_TWI0_GATING_PASS 0x1

#define CAN_BGR_REG 0x0000092c //CAN Bus Gating Reset Register
  #define CAN_BGR_REG_CAN0_RST_OFFSET 16
  #define CAN_BGR_REG_CAN0_RST_CLEAR_MASK 0x00010000
    #define CAN_BGR_REG_CAN0_RST_ASSERT 0x0
    #define CAN_BGR_REG_CAN0_RST_DE_ASSERT 0x1
  #define CAN_BGR_REG_CAN0_GATING_OFFSET 0
  #define CAN_BGR_REG_CAN0_GATING_CLEAR_MASK 0x00000001
    #define CAN_BGR_REG_CAN0_GATING_MASK 0x0
    #define CAN_BGR_REG_CAN0_GATING_PASS 0x1

/*#define SPI0_CLK_REG 0x00000940*/ //SPI0 Clock Register
  #define SPI0_CLK_REG_SPI0_CLK_GATING_OFFSET 31
  #define SPI0_CLK_REG_SPI0_CLK_GATING_CLEAR_MASK 0x80000000
    #define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_OFF 0x0
    #define SPI0_CLK_REG_SPI0_CLK_GATING_CLOCK_IS_ON 0x1
  #define SPI0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SPI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define SPI0_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x001
    #define SPI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x010
    #define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x011
    #define SPI0_CLK_REG_CLK_SRC_SEL_PERI1_200M 0x100
  #define SPI0_CLK_REG_FACTOR_M_OFFSET 0
  #define SPI0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SPI1_CLK_REG 0x00000944 //SPI1 Clock Register
  #define SPI1_CLK_REG_SPI1_CLK_GATING_OFFSET 31
  #define SPI1_CLK_REG_SPI1_CLK_GATING_CLEAR_MASK 0x80000000
    #define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_OFF 0x0
    #define SPI1_CLK_REG_SPI1_CLK_GATING_CLOCK_IS_ON 0x1
  #define SPI1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SPI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define SPI1_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x001
    #define SPI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x010
    #define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x011
    #define SPI1_CLK_REG_CLK_SRC_SEL_PERI1_200M 0x100
  #define SPI1_CLK_REG_FACTOR_M_OFFSET 0
  #define SPI1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SPI2_CLK_REG 0x00000948 //SPI2 Clock Register
  #define SPI2_CLK_REG_SPI2_CLK_GATING_OFFSET 31
  #define SPI2_CLK_REG_SPI2_CLK_GATING_CLEAR_MASK 0x80000000
    #define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_OFF 0x0
    #define SPI2_CLK_REG_SPI2_CLK_GATING_CLOCK_IS_ON 0x1
  #define SPI2_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SPI2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define SPI2_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x001
    #define SPI2_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x010
    #define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x011
    #define SPI2_CLK_REG_CLK_SRC_SEL_PERI1_200M 0x100
  #define SPI2_CLK_REG_FACTOR_M_OFFSET 0
  #define SPI2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SPIF_CLK_REG 0x00000950 //SPIF Clock Register
  #define SPIF_CLK_REG_SPIF_CLK_GATING_OFFSET 31
  #define SPIF_CLK_REG_SPIF_CLK_GATING_CLEAR_MASK 0x80000000
    #define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_OFF 0x0
    #define SPIF_CLK_REG_SPIF_CLK_GATING_CLOCK_IS_ON 0x1
  #define SPIF_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define SPIF_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define SPIF_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x001
    #define SPIF_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x010
    #define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_200M 0x011
    #define SPIF_CLK_REG_CLK_SRC_SEL_PERI1_300M 0x100
  #define SPIF_CLK_REG_FACTOR_N_OFFSET 8
  #define SPIF_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
  #define SPIF_CLK_REG_FACTOR_M_OFFSET 0
  #define SPIF_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define SPI_BGR_REG 0x0000096c //SPI Bus Gating Reset Register
  #define SPI_BGR_REG_SPIF_RST_OFFSET 19
  #define SPI_BGR_REG_SPIF_RST_CLEAR_MASK 0x00080000
    #define SPI_BGR_REG_SPIF_RST_ASSERT 0x0
    #define SPI_BGR_REG_SPIF_RST_DE_ASSERT 0x1
  #define SPI_BGR_REG_SPI2_RST_OFFSET 18
  #define SPI_BGR_REG_SPI2_RST_CLEAR_MASK 0x00040000
    #define SPI_BGR_REG_SPI2_RST_ASSERT 0x0
    #define SPI_BGR_REG_SPI2_RST_DE_ASSERT 0x1
  #define SPI_BGR_REG_SPI1_RST_OFFSET 17
  #define SPI_BGR_REG_SPI1_RST_CLEAR_MASK 0x00020000
    #define SPI_BGR_REG_SPI1_RST_ASSERT 0x0
    #define SPI_BGR_REG_SPI1_RST_DE_ASSERT 0x1
  #define SPI_BGR_REG_SPI0_RST_OFFSET 16
  #define SPI_BGR_REG_SPI0_RST_CLEAR_MASK 0x00010000
    #define SPI_BGR_REG_SPI0_RST_ASSERT 0x0
    #define SPI_BGR_REG_SPI0_RST_DE_ASSERT 0x1
  #define SPI_BGR_REG_SPIF_GATING_OFFSET 3
  #define SPI_BGR_REG_SPIF_GATING_CLEAR_MASK 0x00000008
    #define SPI_BGR_REG_SPIF_GATING_MASK 0x0
    #define SPI_BGR_REG_SPIF_GATING_PASS 0x1
  #define SPI_BGR_REG_SPI2_GATING_OFFSET 2
  #define SPI_BGR_REG_SPI2_GATING_CLEAR_MASK 0x00000004
    #define SPI_BGR_REG_SPI2_GATING_MASK 0x0
    #define SPI_BGR_REG_SPI2_GATING_PASS 0x1
  #define SPI_BGR_REG_SPI1_GATING_OFFSET 1
  #define SPI_BGR_REG_SPI1_GATING_CLEAR_MASK 0x00000002
    #define SPI_BGR_REG_SPI1_GATING_MASK 0x0
    #define SPI_BGR_REG_SPI1_GATING_PASS 0x1
  #define SPI_BGR_REG_SPI0_GATING_OFFSET 0
  #define SPI_BGR_REG_SPI0_GATING_CLEAR_MASK 0x00000001
    #define SPI_BGR_REG_SPI0_GATING_MASK 0x0
    #define SPI_BGR_REG_SPI0_GATING_PASS 0x1

#define GMAC0_25M_CLK_REG 0x00000970 //GMAC0_25M Clock Register
  #define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_OFFSET 31
  #define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLEAR_MASK 0x80000000
    #define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLOCK_IS_OFF 0x0
    #define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_GATING_CLOCK_IS_ON 0x1
  #define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_OFFSET 30
  #define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLEAR_MASK 0x40000000
    #define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLOCK_IS_OFF 0x0
    #define GMAC0_25M_CLK_REG_GMAC0_25M_CLK_SRC_GATING_CLOCK_IS_ON 0x1

#define GMAC1_25M_CLK_REG 0x00000974 //GMAC1_25M Clock Register
  #define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_OFFSET 31
  #define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLEAR_MASK 0x80000000
    #define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLOCK_IS_OFF 0x0
    #define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_GATING_CLOCK_IS_ON 0x1
  #define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_OFFSET 30
  #define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLEAR_MASK 0x40000000
    #define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLOCK_IS_OFF 0x0
    #define GMAC1_25M_CLK_REG_GMAC1_25M_CLK_SRC_GATING_CLOCK_IS_ON 0x1

#define GMAC_BGR_REG 0x0000097c //GMAC Bus Gating Reset Register
  #define GMAC_BGR_REG_GMAC1_RST_OFFSET 17
  #define GMAC_BGR_REG_GMAC1_RST_CLEAR_MASK 0x00020000
    #define GMAC_BGR_REG_GMAC1_RST_ASSERT 0x0
    #define GMAC_BGR_REG_GMAC1_RST_DE_ASSERT 0x1
  #define GMAC_BGR_REG_GMAC0_RST_OFFSET 16
  #define GMAC_BGR_REG_GMAC0_RST_CLEAR_MASK 0x00010000
    #define GMAC_BGR_REG_GMAC0_RST_ASSERT 0x0
    #define GMAC_BGR_REG_GMAC0_RST_DE_ASSERT 0x1
  #define GMAC_BGR_REG_GMAC1_GATING_OFFSET 1
  #define GMAC_BGR_REG_GMAC1_GATING_CLEAR_MASK 0x00000002
    #define GMAC_BGR_REG_GMAC1_GATING_MASKS 0x0
    #define GMAC_BGR_REG_GMAC1_GATING_PASS 0x1
  #define GMAC_BGR_REG_GMAC0_GATING_OFFSET 0
  #define GMAC_BGR_REG_GMAC0_GATING_CLEAR_MASK 0x00000001
    #define GMAC_BGR_REG_GMAC0_GATING_MASK 0x0
    #define GMAC_BGR_REG_GMAC0_GATING_PASS 0x1

#define IRRX_CLK_REG 0x00000990 //IRRX Clock Register
  #define IRRX_CLK_REG_IRRX_CLK_GATING_OFFSET 31
  #define IRRX_CLK_REG_IRRX_CLK_GATING_CLEAR_MASK 0x80000000
    #define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_OFF 0x0
    #define IRRX_CLK_REG_IRRX_CLK_GATING_CLOCK_IS_ON 0x1
  #define IRRX_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define IRRX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
    #define IRRX_CLK_REG_CLK_SRC_SEL_CLK32K 0x0
    #define IRRX_CLK_REG_CLK_SRC_SEL_HOSC 0x1
  #define IRRX_CLK_REG_FACTOR_M_OFFSET 0
  #define IRRX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define IRRX_BGR_REG 0x0000099c //IRRX Bus Gating Reset Register
  #define IRRX_BGR_REG_IRRX_RST_OFFSET 16
  #define IRRX_BGR_REG_IRRX_RST_CLEAR_MASK 0x00010000
    #define IRRX_BGR_REG_IRRX_RST_ASSERT 0x0
    #define IRRX_BGR_REG_IRRX_RST_DE_ASSERT 0x1
  #define IRRX_BGR_REG_IRRX_GATING_OFFSET 0
  #define IRRX_BGR_REG_IRRX_GATING_CLEAR_MASK 0x00000001
    #define IRRX_BGR_REG_IRRX_GATING_MASK 0x0
    #define IRRX_BGR_REG_IRRX_GATING_PASS 0x1

#define IRTX_CLK_REG 0x000009c0 //IRTX Clock Register
  #define IRTX_CLK_REG_IRTX_CLK_GATING_OFFSET 31
  #define IRTX_CLK_REG_IRTX_CLK_GATING_CLEAR_MASK 0x80000000
    #define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_OFF 0x0
    #define IRTX_CLK_REG_IRTX_CLK_GATING_CLOCK_IS_ON 0x1
  #define IRTX_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define IRTX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define IRTX_CLK_REG_CLK_SRC_SEL_HOSC 0x0
    #define IRTX_CLK_REG_CLK_SRC_SEL_PERI1_600M 0x1
  #define IRTX_CLK_REG_FACTOR_M_OFFSET 0
  #define IRTX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define IRTX_BGR_REG 0x000009cc //IRTX Bus Gating Reset Register
  #define IRTX_BGR_REG_IRTX_RST_OFFSET 16
  #define IRTX_BGR_REG_IRTX_RST_CLEAR_MASK 0x00010000
    #define IRTX_BGR_REG_IRTX_RST_ASSERT 0x0
    #define IRTX_BGR_REG_IRTX_RST_DE_ASSERT 0x1
  #define IRTX_BGR_REG_IRTX_GATING_OFFSET 0
  #define IRTX_BGR_REG_IRTX_GATING_CLEAR_MASK 0x00000001
    #define IRTX_BGR_REG_IRTX_GATING_MASK 0x0
    #define IRTX_BGR_REG_IRTX_GATING_PASS 0x1

#define GPADC_24M_CLK_REG 0x000009e0 //GPADC_24M Clock Register
  #define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_OFFSET 31
  #define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLEAR_MASK 0x80000000
    #define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLOCK_IS_OFF 0x0
    #define GPADC_24M_CLK_REG_GPADC_24M_CLK_GATING_CLOCK_IS_ON 0x1
  #define GPADC_24M_CLK_REG_FACTOR_M_OFFSET 0
  #define GPADC_24M_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define GPADC_BGR_REG 0x000009ec //GPADC Bus Gating Reset Register
  #define GPADC_BGR_REG_GPADC_RST_OFFSET 16
  #define GPADC_BGR_REG_GPADC_RST_CLEAR_MASK 0x00010000
    #define GPADC_BGR_REG_GPADC_RST_ASSERT 0x0
    #define GPADC_BGR_REG_GPADC_RST_DE_ASSERT 0x1
  #define GPADC_BGR_REG_GPADC_GATING_OFFSET 0
  #define GPADC_BGR_REG_GPADC_GATING_CLEAR_MASK 0x00000001
    #define GPADC_BGR_REG_GPADC_GATING_MASK 0x0
    #define GPADC_BGR_REG_GPADC_GATING_PASS 0x1

#define THS_BGR_REG 0x000009fc //THS Bus Gating Reset Register
  #define THS_BGR_REG_THS_RST_OFFSET 16
  #define THS_BGR_REG_THS_RST_CLEAR_MASK 0x00010000
    #define THS_BGR_REG_THS_RST_ASSERT 0x0
    #define THS_BGR_REG_THS_RST_DE_ASSERT 0x1
  #define THS_BGR_REG_THS_GATING_OFFSET 0
  #define THS_BGR_REG_THS_GATING_CLEAR_MASK 0x00000001
    #define THS_BGR_REG_THS_GATING_MASK 0x0
    #define THS_BGR_REG_THS_GATING_PASS 0x1

#define USB0_CLK_REG 0x00000a70 //USB0 Clock Register
  #define USB0_CLK_REG_USB0_CLKEN_OFFSET 31
  #define USB0_CLK_REG_USB0_CLKEN_CLEAR_MASK 0x80000000
    #define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_OFF 0x0
    #define USB0_CLK_REG_USB0_CLKEN_CLOCK_IS_ON 0x1
  #define USB0_CLK_REG_USBPHY0_RSTN_OFFSET 30
  #define USB0_CLK_REG_USBPHY0_RSTN_CLEAR_MASK 0x40000000
    #define USB0_CLK_REG_USBPHY0_RSTN_ASSERT 0x0
    #define USB0_CLK_REG_USBPHY0_RSTN_DE_ASSERT 0x1
  #define USB0_CLK_REG_USB0_CLK12M_SEL_OFFSET 24
  #define USB0_CLK_REG_USB0_CLK12M_SEL_CLEAR_MASK 0x03000000
    #define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0x00
    #define USB0_CLK_REG_USB0_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ 0x01
    #define USB0_CLK_REG_USB0_CLK12M_SEL_RTC_32K 0x10

#define USB1_CLK_REG 0x00000a74 //USB1 Clock Register
  #define USB1_CLK_REG_USB1_CLKEN_OFFSET 31
  #define USB1_CLK_REG_USB1_CLKEN_CLEAR_MASK 0x80000000
    #define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_OFF 0x0
    #define USB1_CLK_REG_USB1_CLKEN_CLOCK_IS_ON 0x1
  #define USB1_CLK_REG_USBPHY1_RSTN_OFFSET 30
  #define USB1_CLK_REG_USBPHY1_RSTN_CLEAR_MASK 0x40000000
    #define USB1_CLK_REG_USBPHY1_RSTN_ASSERT 0x0
    #define USB1_CLK_REG_USBPHY1_RSTN_DE_ASSERT 0x1
  #define USB1_CLK_REG_USB1_CLK12M_SEL_OFFSET 24
  #define USB1_CLK_REG_USB1_CLK12M_SEL_CLEAR_MASK 0x03000000
    #define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_48MHZ 0x00
    #define USB1_CLK_REG_USB1_CLK12M_SEL_12M_DIVIDED_FROM_24MHZ 0x01
    #define USB1_CLK_REG_USB1_CLK12M_SEL_RTC_32K 0x10

#define USB2_REF_CLK_REG 0x00000a78 //USB2_REF Clock Register
  #define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_OFFSET 31
  #define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLEAR_MASK 0x80000000
    #define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_OFF 0x0
    #define USB2_REF_CLK_REG_USB2_REF_CLK_GATING_CLOCK_IS_ON 0x1

#define USB2_SUSPEND_CLK_REG 0x00000a7c //USB2_SUSPEND Clock Register
  #define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_OFFSET 31
  #define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLEAR_MASK 0x80000000
    #define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_OFF 0x0
    #define USB2_SUSPEND_CLK_REG_USB2_SUSPEND_CLK_GATING_CLOCK_IS_ON 0x1

#define USB_BGR_REG 0x00000a8c //USB Bus Gating Reset Register
  #define USB_BGR_REG_USB2_PHY_RST_OFFSET 26
  #define USB_BGR_REG_USB2_PHY_RST_CLEAR_MASK 0x04000000
    #define USB_BGR_REG_USB2_PHY_RST_ASSERT 0x0
    #define USB_BGR_REG_USB2_PHY_RST_DE_ASSERT 0x1
  #define USB_BGR_REG_USB2_RST_OFFSET 25
  #define USB_BGR_REG_USB2_RST_CLEAR_MASK 0x02000000
    #define USB_BGR_REG_USB2_RST_ASSERT 0x0
    #define USB_BGR_REG_USB2_RST_DE_ASSERT 0x1
  #define USB_BGR_REG_USBOTG0_RST_OFFSET 24
  #define USB_BGR_REG_USBOTG0_RST_CLEAR_MASK 0x01000000
    #define USB_BGR_REG_USBOTG0_RST_ASSERT 0x0
    #define USB_BGR_REG_USBOTG0_RST_DE_ASSERT 0x1
  #define USB_BGR_REG_USBEHCI1_RST_OFFSET 21
  #define USB_BGR_REG_USBEHCI1_RST_CLEAR_MASK 0x00200000
    #define USB_BGR_REG_USBEHCI1_RST_ASSERT 0x0
    #define USB_BGR_REG_USBEHCI1_RST_DE_ASSERT 0x1
  #define USB_BGR_REG_USBEHCI0_RST_OFFSET 20
  #define USB_BGR_REG_USBEHCI0_RST_CLEAR_MASK 0x00100000
    #define USB_BGR_REG_USBEHCI0_RST_ASSERT 0x0
    #define USB_BGR_REG_USBEHCI0_RST_DE_ASSERT 0x1
  #define USB_BGR_REG_USBOHCI1_RST_OFFSET 17
  #define USB_BGR_REG_USBOHCI1_RST_CLEAR_MASK 0x00020000
    #define USB_BGR_REG_USBOHCI1_RST_ASSERT 0x0
    #define USB_BGR_REG_USBOHCI1_RST_DE_ASSERT 0x1
  #define USB_BGR_REG_USBOHCI0_RST_OFFSET 16
  #define USB_BGR_REG_USBOHCI0_RST_CLEAR_MASK 0x00010000
    #define USB_BGR_REG_USBOHCI0_RST_ASSERT 0x0
    #define USB_BGR_REG_USBOHCI0_RST_DE_ASSERT 0x1
  #define USB_BGR_REG_USB2_GATING_OFFSET 9
  #define USB_BGR_REG_USB2_GATING_CLEAR_MASK 0x00000200
    #define USB_BGR_REG_USB2_GATING_MASK 0x0
    #define USB_BGR_REG_USB2_GATING_PASS 0x1
  #define USB_BGR_REG_USBOTG0_GATING_OFFSET 8
  #define USB_BGR_REG_USBOTG0_GATING_CLEAR_MASK 0x00000100
    #define USB_BGR_REG_USBOTG0_GATING_MASK 0x0
    #define USB_BGR_REG_USBOTG0_GATING_PASS 0x1
  #define USB_BGR_REG_USBEHCI1_GATING_OFFSET 5
  #define USB_BGR_REG_USBEHCI1_GATING_CLEAR_MASK 0x00000020
    #define USB_BGR_REG_USBEHCI1_GATING_MASK 0x0
    #define USB_BGR_REG_USBEHCI1_GATING_PASS 0x1
  #define USB_BGR_REG_USBEHCI0_GATING_OFFSET 4
  #define USB_BGR_REG_USBEHCI0_GATING_CLEAR_MASK 0x00000010
    #define USB_BGR_REG_USBEHCI0_GATING_MASK 0x0
    #define USB_BGR_REG_USBEHCI0_GATING_PASS 0x1
  #define USB_BGR_REG_USBOHCI1_GATING_OFFSET 1
  #define USB_BGR_REG_USBOHCI1_GATING_CLEAR_MASK 0x00000002
    #define USB_BGR_REG_USBOHCI1_GATING_MASK 0x0
    #define USB_BGR_REG_USBOHCI1_GATING_PASS 0x1
  #define USB_BGR_REG_USBOHCI0_GATING_OFFSET 0
  #define USB_BGR_REG_USBOHCI0_GATING_CLEAR_MASK 0x00000001
    #define USB_BGR_REG_USBOHCI0_GATING_MASK 0x0
    #define USB_BGR_REG_USBOHCI0_GATING_PASS 0x1

#define LRADC_BGR_REG 0x00000a9c //LRADC Bus Gating Reset Register
  #define LRADC_BGR_REG_LRADC_RST_OFFSET 16
  #define LRADC_BGR_REG_LRADC_RST_CLEAR_MASK 0x00010000
    #define LRADC_BGR_REG_LRADC_RST_ASSERT 0x0
    #define LRADC_BGR_REG_LRADC_RST_DE_ASSERT 0x1
  #define LRADC_BGR_REG_LRADC_GATING_OFFSET 0
  #define LRADC_BGR_REG_LRADC_GATING_CLEAR_MASK 0x00000001
    #define LRADC_BGR_REG_LRADC_GATING_MASK 0x0
    #define LRADC_BGR_REG_LRADC_GATING_PASS 0x1

#define PCIE_AUX_CLK_REG 0x00000aa0 //PCIE_AUX Clock Register
  #define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_OFFSET 31
  #define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLEAR_MASK 0x80000000
    #define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_OFF 0x0
    #define PCIE_AUX_CLK_REG_PCIE_AUX_CLK_GATING_CLOCK_IS_ON 0x1
  #define PCIE_AUX_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
    #define PCIE_AUX_CLK_REG_CLK_SRC_SEL_HOSC 0x0
    #define PCIE_AUX_CLK_REG_CLK_SRC_SEL_CLK32K 0x1
  #define PCIE_AUX_CLK_REG_FACTOR_M_OFFSET 0
  #define PCIE_AUX_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define PCIE_REF_CLK_REG 0x00000aa4 //PCIE_REF Clock Register
  #define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_OFFSET 31
  #define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLEAR_MASK 0x80000000
    #define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLOCK_IS_OFF 0x0
    #define PCIE_REF_CLK_REG_PCIE_REF_CLK_GATING_CLOCK_IS_ON 0x1

#define PCIE_BGR_REG 0x00000aac //PCIE Bus Gating Reset Register
  #define PCIE_BGR_REG_PCIE_PE_RST_OFFSET 18
  #define PCIE_BGR_REG_PCIE_PE_RST_CLEAR_MASK 0x00040000
    #define PCIE_BGR_REG_PCIE_PE_RST_ASSERT 0x0
    #define PCIE_BGR_REG_PCIE_PE_RST_DE_ASSERT 0x1
  #define PCIE_BGR_REG_PCIE_POWER_UP_RST_OFFSET 17
  #define PCIE_BGR_REG_PCIE_POWER_UP_RST_CLEAR_MASK 0x00020000
    #define PCIE_BGR_REG_PCIE_POWER_UP_RST_ASSERT 0x0
    #define PCIE_BGR_REG_PCIE_POWER_UP_RST_DE_ASSERT 0x1
  #define PCIE_BGR_REG_PCIE_RST_OFFSET 16
  #define PCIE_BGR_REG_PCIE_RST_CLEAR_MASK 0x00010000
    #define PCIE_BGR_REG_PCIE_RST_ASSERT 0x0
    #define PCIE_BGR_REG_PCIE_RST_DE_ASSERT 0x1
  #define PCIE_BGR_REG_PCIE_GATING_OFFSET 0
  #define PCIE_BGR_REG_PCIE_GATING_CLEAR_MASK 0x00000001
    #define PCIE_BGR_REG_PCIE_GATING_MASK 0x0
    #define PCIE_BGR_REG_PCIE_GATING_PASS 0x1

#define DPSS_TOP0_BGR_REG 0x00000abc //DPSS_TOP0 Bus Gating Reset Register
  #define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_OFFSET 16
  #define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_CLEAR_MASK 0x00010000
    #define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_ASSERT 0x0
    #define DPSS_TOP0_BGR_REG_DPSS_TOP0_RST_DE_ASSERT 0x1
  #define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_OFFSET 0
  #define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_CLEAR_MASK 0x00000001
    #define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_MASK 0x0
    #define DPSS_TOP0_BGR_REG_DPSS_TOP0_GATING_PASS 0x1

#define DPSS_TOP1_BGR_REG 0x00000acc //DPSS_TOP1 Bus Gating Reset Register
  #define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_OFFSET 16
  #define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_CLEAR_MASK 0x00010000
    #define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_ASSERT 0x0
    #define DPSS_TOP1_BGR_REG_DPSS_TOP1_RST_DE_ASSERT 0x1
  #define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_OFFSET 0
  #define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_CLEAR_MASK 0x00000001
    #define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_MASK 0x0
    #define DPSS_TOP1_BGR_REG_DPSS_TOP1_GATING_PASS 0x1

#define HDMI_24M_CLK_REG 0x00000b04 //HDMI_24M Clock Register
  #define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_OFFSET 31
  #define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLEAR_MASK 0x80000000
    #define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLOCK_IS_OFF 0x0
    #define HDMI_24M_CLK_REG_HDMI_24M_CLK_GATING_CLOCK_IS_ON 0x1

#define HDMI_CEC_CLK_REG 0x00000b10 //HDMI CEC Clock Register
  #define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_OFFSET 31
  #define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLEAR_MASK 0x80000000
    #define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_OFF 0x0
    #define HDMI_CEC_CLK_REG_HDMI_CEC_CLK_GATING_CLOCK_IS_ON 0x1
  #define HDMI_CEC_CLK_REG_PERI_GATING_OFFSET 30
  #define HDMI_CEC_CLK_REG_PERI_GATING_CLEAR_MASK 0x40000000
    #define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_OFF 0x0
    #define HDMI_CEC_CLK_REG_PERI_GATING_CLOCK_IS_ON 0x1
  #define HDMI_CEC_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
    #define HDMI_CEC_CLK_REG_CLK_SRC_SEL_CLK32K 0x0
    #define HDMI_CEC_CLK_REG_CLK_SRC_SEL_HDMI_CEC_CLK32K__PLL_PERI_2X__36621___32_768KHZ 0x1

#define HDMI_BGR_REG 0x00000b1c //HDMI Bus Gating Reset Register
  #define HDMI_BGR_REG_HDMI_SUB_RST_OFFSET 17
  #define HDMI_BGR_REG_HDMI_SUB_RST_CLEAR_MASK 0x00020000
    #define HDMI_BGR_REG_HDMI_SUB_RST_ASSERT 0x0
    #define HDMI_BGR_REG_HDMI_SUB_RST_DE_ASSERT 0x1
  #define HDMI_BGR_REG_HDMI_MAIN_RST_OFFSET 16
  #define HDMI_BGR_REG_HDMI_MAIN_RST_CLEAR_MASK 0x00010000
    #define HDMI_BGR_REG_HDMI_MAIN_RST_ASSERT 0x0
    #define HDMI_BGR_REG_HDMI_MAIN_RST_DE_ASSERT 0x1
  #define HDMI_BGR_REG_HDMI_GATING_OFFSET 0
  #define HDMI_BGR_REG_HDMI_GATING_CLEAR_MASK 0x00000001
    #define HDMI_BGR_REG_HDMI_GATING_MASK 0x0
    #define HDMI_BGR_REG_HDMI_GATING_PASS 0x1

#define DSI0_CLK_REG 0x00000b24 //DSI0 Clock Register
  #define DSI0_CLK_REG_DSI0_CLK_GATING_OFFSET 31
  #define DSI0_CLK_REG_DSI0_CLK_GATING_CLEAR_MASK 0x80000000
    #define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_OFF 0x0
    #define DSI0_CLK_REG_DSI0_CLK_GATING_CLOCK_IS_ON 0x1
  #define DSI0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define DSI0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define DSI0_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x001
    #define DSI0_CLK_REG_CLK_SRC_SEL_PERI0_150M 0x010
  #define DSI0_CLK_REG_FACTOR_M_OFFSET 0
  #define DSI0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DSI1_CLK_REG 0x00000b28 //DSI1 Clock Register
  #define DSI1_CLK_REG_DSI1_CLK_GATING_OFFSET 31
  #define DSI1_CLK_REG_DSI1_CLK_GATING_CLEAR_MASK 0x80000000
    #define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_OFF 0x0
    #define DSI1_CLK_REG_DSI1_CLK_GATING_CLOCK_IS_ON 0x1
  #define DSI1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define DSI1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define DSI1_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_200M 0x001
    #define DSI1_CLK_REG_CLK_SRC_SEL_PERI0_150M 0x010
  #define DSI1_CLK_REG_FACTOR_M_OFFSET 0
  #define DSI1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define DSI_BGR_REG 0x00000b4c //DSI Bus Gating Reset Register
  #define DSI_BGR_REG_DSI1_RST_OFFSET 17
  #define DSI_BGR_REG_DSI1_RST_CLEAR_MASK 0x00020000
    #define DSI_BGR_REG_DSI1_RST_ASSERT 0x0
    #define DSI_BGR_REG_DSI1_RST_DE_ASSERT 0x1
  #define DSI_BGR_REG_DSI0_RST_OFFSET 16
  #define DSI_BGR_REG_DSI0_RST_CLEAR_MASK 0x00010000
    #define DSI_BGR_REG_DSI0_RST_ASSERT 0x0
    #define DSI_BGR_REG_DSI0_RST_DE_ASSERT 0x1
  #define DSI_BGR_REG_DSI1_GATING_OFFSET 1
  #define DSI_BGR_REG_DSI1_GATING_CLEAR_MASK 0x00000002
    #define DSI_BGR_REG_DSI1_GATING_MASK 0x0
    #define DSI_BGR_REG_DSI1_GATING_PASS 0x1
  #define DSI_BGR_REG_DSI0_GATING_OFFSET 0
  #define DSI_BGR_REG_DSI0_GATING_CLEAR_MASK 0x00000001
    #define DSI_BGR_REG_DSI0_GATING_MASK 0x0
    #define DSI_BGR_REG_DSI0_GATING_PASS 0x1

#define VO0_TCONLCD0_CLK_REG 0x00000b60 //VO0_TCONLCD0 Clock Register
  #define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_OFFSET 31
  #define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLEAR_MASK 0x80000000
    #define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_OFF 0x0
    #define VO0_TCONLCD0_CLK_REG_VO0_TCONLCD0_CLK_GATING_CLOCK_IS_ON 0x1
  #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x000
    #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x001
    #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x010
    #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
    #define VO0_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x100
  #define VO0_TCONLCD0_CLK_REG_FACTOR_M_OFFSET 0
  #define VO0_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define VO0_TCONLCD1_CLK_REG 0x00000b64 //VO0_TCONLCD1 Clock Register
  #define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_OFFSET 31
  #define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLEAR_MASK 0x80000000
    #define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_OFF 0x0
    #define VO0_TCONLCD1_CLK_REG_VO0_TCONLCD1_CLK_GATING_CLOCK_IS_ON 0x1
  #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x000
    #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x001
    #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x010
    #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
    #define VO0_TCONLCD1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x100
  #define VO0_TCONLCD1_CLK_REG_FACTOR_M_OFFSET 0
  #define VO0_TCONLCD1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define VO1_TCONLCD0_CLK_REG 0x00000b68 //VO1_TCONLCD0 Clock Register
  #define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_OFFSET 31
  #define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLEAR_MASK 0x80000000
    #define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLOCK_IS_OFF 0x0
    #define VO1_TCONLCD0_CLK_REG_VO1_TCONLCD0_CLK_GATING_CLOCK_IS_ON 0x1
  #define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x000
    #define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x001
    #define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x010
    #define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
    #define VO1_TCONLCD0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x100
  #define VO1_TCONLCD0_CLK_REG_FACTOR_M_OFFSET 0
  #define VO1_TCONLCD0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define COMBPHY0_CLK_REG 0x00000b6c //COMBPHY0 Clock Register
  #define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_OFFSET 31
  #define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLEAR_MASK 0x80000000
    #define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_OFF 0x0
    #define COMBPHY0_CLK_REG_COMBPHY0_CLK_GATING_CLOCK_IS_ON 0x1
  #define COMBPHY0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define COMBPHY0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x000
    #define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x001
    #define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x010
    #define COMBPHY0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
    #define COMBPHY0_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x100
  #define COMBPHY0_CLK_REG_FACTOR_M_OFFSET 0
  #define COMBPHY0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define COMBPHY1_CLK_REG 0x00000b70 //COMBPHY1 Clock Register
  #define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_OFFSET 31
  #define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLEAR_MASK 0x80000000
    #define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_OFF 0x0
    #define COMBPHY1_CLK_REG_COMBPHY1_CLK_GATING_CLOCK_IS_ON 0x1
  #define COMBPHY1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define COMBPHY1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x000
    #define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x001
    #define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x010
    #define COMBPHY1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
    #define COMBPHY1_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x100
  #define COMBPHY1_CLK_REG_FACTOR_M_OFFSET 0
  #define COMBPHY1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define TCONLCD_BGR_REG 0x00000b7c //TCONLCD Bus Gating Reset Register
  #define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_OFFSET 18
  #define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_CLEAR_MASK 0x00040000
    #define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_ASSERT 0x0
    #define TCONLCD_BGR_REG_VO1_TCONLCD0_RST_DE_ASSERT 0x1
  #define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_OFFSET 17
  #define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_CLEAR_MASK 0x00020000
    #define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_ASSERT 0x0
    #define TCONLCD_BGR_REG_VO0_TCONLCD1_RST_DE_ASSERT 0x1
  #define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_OFFSET 16
  #define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_CLEAR_MASK 0x00010000
    #define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_ASSERT 0x0
    #define TCONLCD_BGR_REG_VO0_TCONLCD0_RST_DE_ASSERT 0x1
  #define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_OFFSET 2
  #define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_CLEAR_MASK 0x00000004
    #define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_MASK 0x0
    #define TCONLCD_BGR_REG_VO1_TCONLCD0_GATING_PASS 0x1
  #define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_OFFSET 1
  #define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_CLEAR_MASK 0x00000002
    #define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_MASK 0x0
    #define TCONLCD_BGR_REG_VO0_TCONLCD1_GATING_PASS 0x1
  #define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_OFFSET 0
  #define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_CLEAR_MASK 0x00000001
    #define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_MASK 0x0
    #define TCONLCD_BGR_REG_VO0_TCONLCD0_GATING_PASS 0x1

#define TCONTV_CLK_REG 0x00000b80 //TCONTV Clock Register
  #define TCONTV_CLK_REG_TCONTV_CLK_GATING_OFFSET 31
  #define TCONTV_CLK_REG_TCONTV_CLK_GATING_CLEAR_MASK 0x80000000
    #define TCONTV_CLK_REG_TCONTV_CLK_GATING_CLOCK_IS_OFF 0x0
    #define TCONTV_CLK_REG_TCONTV_CLK_GATING_CLOCK_IS_ON 0x1
  #define TCONTV_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define TCONTV_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x000
    #define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x001
    #define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x010
    #define TCONTV_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
    #define TCONTV_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x100
  #define TCONTV_CLK_REG_FACTOR_M_OFFSET 0
  #define TCONTV_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define TCONTV_BGR_REG 0x00000b9c //TCONTV Bus Gating Reset Register
  #define TCONTV_BGR_REG_TCONTV_RST_OFFSET 16
  #define TCONTV_BGR_REG_TCONTV_RST_CLEAR_MASK 0x00010000
    #define TCONTV_BGR_REG_TCONTV_RST_ASSERT 0x0
    #define TCONTV_BGR_REG_TCONTV_RST_DE_ASSERT 0x1
  #define TCONTV_BGR_REG_TCONTV_GATING_OFFSET 0
  #define TCONTV_BGR_REG_TCONTV_GATING_CLEAR_MASK 0x00000001
    #define TCONTV_BGR_REG_TCONTV_GATING_MASK 0x0
    #define TCONTV_BGR_REG_TCONTV_GATING_PASS 0x1

#define LVDS_BGR_REG 0x00000bac //LVDS Bus Gating Reset Register
  #define LVDS_BGR_REG_LVDS1_RST_OFFSET 17
  #define LVDS_BGR_REG_LVDS1_RST_CLEAR_MASK 0x00020000
    #define LVDS_BGR_REG_LVDS1_RST_ASSERT 0x0
    #define LVDS_BGR_REG_LVDS1_RST_DE_ASSERT 0x1
  #define LVDS_BGR_REG_LVDS0_RST_OFFSET 16
  #define LVDS_BGR_REG_LVDS0_RST_CLEAR_MASK 0x00010000
    #define LVDS_BGR_REG_LVDS0_RST_ASSERT 0x0
    #define LVDS_BGR_REG_LVDS0_RST_DE_ASSERT 0x1

#define LEDC_CLK_REG 0x00000bf0 //LEDC Clock Register
  #define LEDC_CLK_REG_LEDC_CLK_GATING_OFFSET 31
  #define LEDC_CLK_REG_LEDC_CLK_GATING_CLEAR_MASK 0x80000000
    #define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_OFF 0x0
    #define LEDC_CLK_REG_LEDC_CLK_GATING_CLOCK_IS_ON 0x1
  #define LEDC_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define LEDC_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x01000000
    #define LEDC_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define LEDC_CLK_REG_CLK_SRC_SEL_PERI0_600M 0x001
  #define LEDC_CLK_REG_FACTOR_M_OFFSET 0
  #define LEDC_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define LEDC_BGR_REG 0x00000bfc //LEDC Bus Gating Reset Register
  #define LEDC_BGR_REG_LEDC_RST_OFFSET 16
  #define LEDC_BGR_REG_LEDC_RST_CLEAR_MASK 0x00010000
    #define LEDC_BGR_REG_LEDC_RST_ASSERT 0x0
    #define LEDC_BGR_REG_LEDC_RST_DE_ASSERT 0x1
  #define LEDC_BGR_REG_LEDC_GATING_OFFSET 0
  #define LEDC_BGR_REG_LEDC_GATING_CLEAR_MASK 0x00000001
    #define LEDC_BGR_REG_LEDC_GATING_MASK 0x0
    #define LEDC_BGR_REG_LEDC_GATING_PASS 0x1

#define CSI_CLK_REG 0x00000c04 //CSI Clock Register
  #define CSI_CLK_REG_CSI_CLK_GATING_OFFSET 31
  #define CSI_CLK_REG_CSI_CLK_GATING_CLEAR_MASK 0x80000000
    #define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_OFF 0x0
    #define CSI_CLK_REG_CSI_CLK_GATING_CLOCK_IS_ON 0x1
  #define CSI_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CSI_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define CSI_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x000
    #define CSI_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
    #define CSI_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x010
    #define CSI_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x011
    #define CSI_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x100
  #define CSI_CLK_REG_FACTOR_M_OFFSET 0
  #define CSI_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define CSI_MASTER0_CLK_REG 0x00000c08 //CSI Master0 Clock Register
  #define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_OFFSET 31
  #define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLEAR_MASK 0x80000000
    #define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_OFF 0x0
    #define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_GATING_CLOCK_IS_ON 0x1
  #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x001
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x011
    #define CSI_MASTER0_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x100
  #define CSI_MASTER0_CLK_REG_FACTOR_N_OFFSET 8
  #define CSI_MASTER0_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
  #define CSI_MASTER0_CLK_REG_FACTOR_M_OFFSET 0
  #define CSI_MASTER0_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define CSI_MASTER1_CLK_REG 0x00000c0c //CSI Master1 Clock Register
  #define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_OFFSET 31
  #define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLEAR_MASK 0x80000000
    #define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_OFF 0x0
    #define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_GATING_CLOCK_IS_ON 0x1
  #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x001
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x011
    #define CSI_MASTER1_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x100
  #define CSI_MASTER1_CLK_REG_FACTOR_N_OFFSET 8
  #define CSI_MASTER1_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
  #define CSI_MASTER1_CLK_REG_FACTOR_M_OFFSET 0
  #define CSI_MASTER1_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define CSI_MASTER2_CLK_REG 0x00000c10 //CSI Master2 Clock Register
  #define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_OFFSET 31
  #define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLEAR_MASK 0x80000000
    #define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_OFF 0x0
    #define CSI_MASTER2_CLK_REG_CSI_MASTER2_CLK_GATING_CLOCK_IS_ON 0x1
  #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x001
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x011
    #define CSI_MASTER2_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x100
  #define CSI_MASTER2_CLK_REG_FACTOR_N_OFFSET 8
  #define CSI_MASTER2_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
  #define CSI_MASTER2_CLK_REG_FACTOR_M_OFFSET 0
  #define CSI_MASTER2_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define CSI_MASTER3_CLK_REG 0x00000c14 //CSI Master3 Clock Register
  #define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_OFFSET 31
  #define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLEAR_MASK 0x80000000
    #define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_OFF 0x0
    #define CSI_MASTER3_CLK_REG_CSI_MASTER3_CLK_GATING_CLOCK_IS_ON 0x1
  #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x001
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO1PLL4X 0x011
    #define CSI_MASTER3_CLK_REG_CLK_SRC_SEL_VIDEO2PLL4X 0x100
  #define CSI_MASTER3_CLK_REG_FACTOR_N_OFFSET 8
  #define CSI_MASTER3_CLK_REG_FACTOR_N_CLEAR_MASK 0x00001f00
  #define CSI_MASTER3_CLK_REG_FACTOR_M_OFFSET 0
  #define CSI_MASTER3_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define CSI_BGR_REG 0x00000c1c //CSI Bus Gating Reset Register
  #define CSI_BGR_REG_CSI_RST_OFFSET 16
  #define CSI_BGR_REG_CSI_RST_CLEAR_MASK 0x00010000
    #define CSI_BGR_REG_CSI_RST_ASSERT 0x0
    #define CSI_BGR_REG_CSI_RST_DE_ASSERT 0x1
  #define CSI_BGR_REG_CSI_GATING_OFFSET 0
  #define CSI_BGR_REG_CSI_GATING_CLEAR_MASK 0x00000001
    #define CSI_BGR_REG_CSI_GATING_MASK 0x0
    #define CSI_BGR_REG_CSI_GATING_PASS 0x1

#define ISP_CLK_REG 0x00000c20 //ISP Clock Register
  #define ISP_CLK_REG_ISP_CLK_GATING_OFFSET 31
  #define ISP_CLK_REG_ISP_CLK_GATING_CLEAR_MASK 0x80000000
    #define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_OFF 0x0
    #define ISP_CLK_REG_ISP_CLK_GATING_CLOCK_IS_ON 0x1
  #define ISP_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define ISP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define ISP_CLK_REG_CLK_SRC_SEL_PERI0_300M 0x000
    #define ISP_CLK_REG_CLK_SRC_SEL_PERI0_400M 0x001
    #define ISP_CLK_REG_CLK_SRC_SEL_VIDEO0PLL4X 0x010
    #define ISP_CLK_REG_CLK_SRC_SEL_VIDEO3PLL4X 0x011
  #define ISP_CLK_REG_FACTOR_M_OFFSET 0
  #define ISP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define ISP_BGR_REG 0x00000c2c //ISP Bus Gating Reset Register
  #define ISP_BGR_REG_ISP_RST_OFFSET 16
  #define ISP_BGR_REG_ISP_RST_CLEAR_MASK 0x00010000
    #define ISP_BGR_REG_ISP_RST_ASSERT 0x0
    #define ISP_BGR_REG_ISP_RST_DE_ASSERT 0x1

#define DSP_CLK_REG 0x00000c70 //DSP Clock Register
  #define DSP_CLK_REG_DSP_CLK_GATING_OFFSET 31
  #define DSP_CLK_REG_DSP_CLK_GATING_CLEAR_MASK 0x80000000
    #define DSP_CLK_REG_DSP_CLK_GATING_CLOCK_IS_OFF 0x0
    #define DSP_CLK_REG_DSP_CLK_GATING_CLOCK_IS_ON 0x1
  #define DSP_CLK_REG_CLK_SRC_SEL_OFFSET 24
  #define DSP_CLK_REG_CLK_SRC_SEL_CLEAR_MASK 0x07000000
    #define DSP_CLK_REG_CLK_SRC_SEL_HOSC 0x000
    #define DSP_CLK_REG_CLK_SRC_SEL_CLK32K 0x001
    #define DSP_CLK_REG_CLK_SRC_SEL_CLK16M_RC 0x010
    #define DSP_CLK_REG_CLK_SRC_SEL_PERI0PLL2X 0x011
    #define DSP_CLK_REG_CLK_SRC_SEL_PERI0_480M 0x100
  #define DSP_CLK_REG_FACTOR_M_OFFSET 0
  #define DSP_CLK_REG_FACTOR_M_CLEAR_MASK 0x0000001f

#define AHB_GATE_EN_REG 0x00000e04 //AHB Gate Enable Register
  #define AHB_GATE_EN_REG_AHB_MONITOR_EN_OFFSET 31
  #define AHB_GATE_EN_REG_AHB_MONITOR_EN_CLEAR_MASK 0x80000000
    #define AHB_GATE_EN_REG_AHB_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0x0
    #define AHB_GATE_EN_REG_AHB_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0x1
  #define AHB_GATE_EN_REG_SD_MONITOR_EN_OFFSET 29
  #define AHB_GATE_EN_REG_SD_MONITOR_EN_CLEAR_MASK 0x20000000
    #define AHB_GATE_EN_REG_SD_MONITOR_EN_DISABLE_AUTO_CLOCK_GATE 0x0
    #define AHB_GATE_EN_REG_SD_MONITOR_EN_ENABLE_AUTO_CLOCK_GATE 0x1
  #define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_OFFSET 28
  #define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_CLEAR_MASK 0x10000000
    #define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_CPUS_HCLK_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_OFFSET 22
  #define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00400000
    #define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_SPIF_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_OFFSET 21
  #define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00200000
    #define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_GMAC1_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_OFFSET 20
  #define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00100000
    #define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_GMAC0_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_OFFSET 19
  #define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00080000
    #define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_SMHC2_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_OFFSET 18
  #define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00040000
    #define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_SMHC1_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_OFFSET 17
  #define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00020000
    #define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_SMHC0_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_OFFSET 16
  #define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_CLEAR_MASK 0x00010000
    #define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_USB_MBUS_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_OFFSET 9
  #define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000200
    #define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_GMAC1_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_OFFSET 8
  #define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000100
    #define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_GMAC0_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_OFFSET 7
  #define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000080
    #define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_SMHC2_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_OFFSET 6
  #define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000040
    #define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_SMHC1_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_OFFSET 5
  #define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000020
    #define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_SMHC0_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_OFFSET 4
  #define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000010
    #define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_USB_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_OFFSET 3
  #define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000008
    #define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_VID_OUT_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_OFFSET 2
  #define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000004
    #define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_VID_IN_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_OFFSET 1
  #define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000002
    #define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_VE_AHB_GATE_SW_CFG_ENABLE 0x1
  #define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_OFFSET 0
  #define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_CLEAR_MASK 0x00000001
    #define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_DISABLE 0x0
    #define AHB_GATE_EN_REG_NPU_AHB_GATE_SW_CFG_ENABLE 0x1

#define PERI0PLL_GATE_EN_REG 0x00000e08 //PERI0PLL Gate Enable Register
  #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_OFFSET 27
  #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_CLEAR_MASK 0x08000000
    #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_DISABLE 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_GATE_SW_CFG_ENABLE 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_OFFSET 26
  #define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_CLEAR_MASK 0x04000000
    #define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_DISABLE 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_800M_GATE_SW_CFG_ENABLE 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_OFFSET 25
  #define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_CLEAR_MASK 0x02000000
    #define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_DISABLE 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_600M_GATE_SW_CFG_ENABLE 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_OFFSET 24
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_CLEAR_MASK 0x01000000
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_DISABLE 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_ALL_CFG_ENABLE 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_OFFSET 23
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_CLEAR_MASK 0x00800000
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_DISABLE 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_GATE_SW_CFG_ENABLE 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_OFFSET 22
  #define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_CLEAR_MASK 0x00400000
    #define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_DISABLE 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_160M_GATE_SW_CFG_ENABLE 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_OFFSET 21
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_CLEAR_MASK 0x00200000
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_DISABLE 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_ALL_CFG_ENABLE 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_OFFSET 20
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_CLEAR_MASK 0x00100000
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_DISABLE 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_GATE_SW_CFG_ENABLE 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_OFFSET 19
  #define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_CLEAR_MASK 0x00080000
    #define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_DISABLE 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_150M_GATE_SW_CFG_ENABLE 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_OFFSET 18
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_CLEAR_MASK 0x00040000
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_DISABLE 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_ALL_CFG_ENABLE 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_OFFSET 17
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_CLEAR_MASK 0x00020000
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_DISABLE 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_GATE_SW_CFG_ENABLE 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_OFFSET 16
  #define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_CLEAR_MASK 0x00010000
    #define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_DISABLE 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_200M_GATE_SW_CFG_ENABLE 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_OFFSET 11
  #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_CLEAR_MASK 0x00000800
    #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_AUTO 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0PLL2X_AUTO_GATE_EN_NO_AUTO 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_OFFSET 10
  #define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_CLEAR_MASK 0x00000400
    #define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_AUTO 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_800M_AUTO_GATE_EN_NO_AUTO 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_OFFSET 9
  #define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_CLEAR_MASK 0x00000200
    #define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_AUTO 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_600M_AUTO_GATE_EN_NO_AUTO 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_OFFSET 8
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000100
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_AUTO 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_ALL_NO_AUTO 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_OFFSET 7
  #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_CLEAR_MASK 0x00000080
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_AUTO 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_480M_AUTO_GATE_EN_NO_AUTO 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_OFFSET 6
  #define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_CLEAR_MASK 0x00000040
    #define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_AUTO 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_160M_AUTO_GATE_EN_NO_AUTO 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_OFFSET 5
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000020
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_AUTO 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_ALL_NO_AUTO 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_OFFSET 4
  #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_CLEAR_MASK 0x00000010
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_AUTO 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_300M_AUTO_GATE_EN_NO_AUTO 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_OFFSET 3
  #define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_CLEAR_MASK 0x00000008
    #define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_AUTO 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_150M_AUTO_GATE_EN_NO_AUTO 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_OFFSET 2
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_CLEAR_MASK 0x00000004
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_AUTO 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_ALL_NO_AUTO 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_OFFSET 1
  #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_CLEAR_MASK 0x00000002
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_AUTO 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_400M_AUTO_GATE_EN_NO_AUTO 0x1
  #define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_OFFSET 0
  #define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_CLEAR_MASK 0x00000001
    #define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_AUTO 0x0
    #define PERI0PLL_GATE_EN_REG_PERI0_200M_AUTO_GATE_EN_NO_AUTO 0x1

#define CLK24M_GATE_EN_REG 0x00000e0c //CLK24M Gate Enable Register
  #define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_OFFSET 3
  #define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_CLEAR_MASK 0x00000008
    #define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_DISABLE 0x0
    #define CLK24M_GATE_EN_REG_RES_DCAP_24M_GATE_EN_ENABLE 0x1
  #define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_OFFSET 1
  #define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_CLEAR_MASK 0x00000002
    #define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_DISABLE 0x0
    #define CLK24M_GATE_EN_REG_WIEGAND_24M_GATE_EN_ENABLE 0x1
  #define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_OFFSET 0
  #define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_CLEAR_MASK 0x00000001
    #define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_DISABLE 0x0
    #define CLK24M_GATE_EN_REG_USB_24M_GATE_EN_ENABLE 0x1

#define CCMU_SEC_SWITCH_REG 0x00000f00 //CCMU Security Switch Register
  #define CCMU_SEC_SWITCH_REG_MBUS_SEC_OFFSET 2
  #define CCMU_SEC_SWITCH_REG_MBUS_SEC_CLEAR_MASK 0x00000004
    #define CCMU_SEC_SWITCH_REG_MBUS_SEC_SECURE 0x0
    #define CCMU_SEC_SWITCH_REG_MBUS_SEC_NON_SECURE 0x1
  #define CCMU_SEC_SWITCH_REG_BUS_SEC_OFFSET 1
  #define CCMU_SEC_SWITCH_REG_BUS_SEC_CLEAR_MASK 0x00000002
    #define CCMU_SEC_SWITCH_REG_BUS_SEC_SECURE 0x0
    #define CCMU_SEC_SWITCH_REG_BUS_SEC_NON_SECURE 0x1
  #define CCMU_SEC_SWITCH_REG_PLL_SEC_OFFSET 0
  #define CCMU_SEC_SWITCH_REG_PLL_SEC_CLEAR_MASK 0x00000001
    #define CCMU_SEC_SWITCH_REG_PLL_SEC_SECURE 0x0
    #define CCMU_SEC_SWITCH_REG_PLL_SEC_NON_SECURE 0x1

#define PLL_LOCK_DBG_CTRL_REG 0x00000f04 //PLL Lock Debug Control Register
  #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_OFFSET 31
  #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_CLEAR_MASK 0x80000000
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_DISABLE 0x0
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_EN_ENABLE 0x1
  #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_OFFSET 20
  #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CLEAR_MASK 0x00700000
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CPUPLL 0x000
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_DDRPLL 0x001
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_PERIPLL2X 0x010
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_VIDEO0PLL4X 0x011
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_CSIPLL4X 0x100
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_AUDIOPLL4X 0x110
    #define PLL_LOCK_DBG_CTRL_REG_PLL_LOCK_FLAG_SEL_NPUPLL 0x111

#define SYSDAP_REQ_CTRL_REG 0x00000f08 //SYSDAP REQ Control Register
  #define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_OFFSET 0
  #define SYSDAP_REQ_CTRL_REG_SYSDAP_REQ_ENABLE_CLEAR_MASK 0x00000001

#define CCMU_FAN_GATE_REG 0x00000f30 //CCMU FANOUT CLOCK GATE Register
  #define CCMU_FAN_GATE_REG_CLK25M_EN_OFFSET 3
  #define CCMU_FAN_GATE_REG_CLK25M_EN_CLEAR_MASK 0x00000008
    #define CCMU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_OFF 0x0
    #define CCMU_FAN_GATE_REG_CLK25M_EN_CLOCK_IS_ON 0x1
  #define CCMU_FAN_GATE_REG_CLK16M_EN_OFFSET 2
  #define CCMU_FAN_GATE_REG_CLK16M_EN_CLEAR_MASK 0x00000004
    #define CCMU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_OFF 0x0
    #define CCMU_FAN_GATE_REG_CLK16M_EN_CLOCK_IS_ON 0x1
  #define CCMU_FAN_GATE_REG_CLK12M_EN_OFFSET 1
  #define CCMU_FAN_GATE_REG_CLK12M_EN_CLEAR_MASK 0x00000002
    #define CCMU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_OFF 0x0
    #define CCMU_FAN_GATE_REG_CLK12M_EN_CLOCK_IS_ON 0x1
  #define CCMU_FAN_GATE_REG_CLK24M_EN_OFFSET 0
  #define CCMU_FAN_GATE_REG_CLK24M_EN_CLEAR_MASK 0x00000001
    #define CCMU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_OFF 0x0
    #define CCMU_FAN_GATE_REG_CLK24M_EN_CLOCK_IS_ON 0x1

#define CLK27M_FAN_REG 0x00000f34 //CLK27M FANOUT Register
  #define CLK27M_FAN_REG_CLK27M_EN_OFFSET 31
  #define CLK27M_FAN_REG_CLK27M_EN_CLEAR_MASK 0x80000000
    #define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_OFF 0x0
    #define CLK27M_FAN_REG_CLK27M_EN_CLOCK_IS_ON 0x1
  #define CLK27M_FAN_REG_CLK27M_SCR_SEL_OFFSET 24
  #define CLK27M_FAN_REG_CLK27M_SCR_SEL_CLEAR_MASK 0x03000000
    #define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO0PLL1X 0x000
    #define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO1PLL1X 0x001
    #define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO2PLL1X 0x010
    #define CLK27M_FAN_REG_CLK27M_SCR_SEL_VIDEO3PLL1X 0x011
  #define CLK27M_FAN_REG_CLK27M_DIV1_OFFSET 8
  #define CLK27M_FAN_REG_CLK27M_DIV1_CLEAR_MASK 0x00001f00
  #define CLK27M_FAN_REG_CLK27M_DIV0_OFFSET 0
  #define CLK27M_FAN_REG_CLK27M_DIV0_CLEAR_MASK 0x0000001f

#define CLK_FAN_REG 0x00000f38 //CLK FANOUT Register
  #define CLK_FAN_REG_PCLK_DIV_EN_OFFSET 31
  #define CLK_FAN_REG_PCLK_DIV_EN_CLEAR_MASK 0x80000000
    #define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_OFF 0x0
    #define CLK_FAN_REG_PCLK_DIV_EN_CLOCK_IS_ON 0x1
  #define CLK_FAN_REG_PCLK_DIV1_OFFSET 5
  #define CLK_FAN_REG_PCLK_DIV1_CLEAR_MASK 0x000003e0
  #define CLK_FAN_REG_PCLK_DIV_OFFSET 0
  #define CLK_FAN_REG_PCLK_DIV_CLEAR_MASK 0x0000001f

#define CCMU_FAN_REG 0x00000f3c //CCMU FANOUT Register
  #define CCMU_FAN_REG_CLK_FANOUT2_EN_OFFSET 23
  #define CCMU_FAN_REG_CLK_FANOUT2_EN_CLEAR_MASK 0x00800000
    #define CCMU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_OFF 0x0
    #define CCMU_FAN_REG_CLK_FANOUT2_EN_CLOCK_IS_ON 0x1
  #define CCMU_FAN_REG_CLK_FANOUT1_EN_OFFSET 22
  #define CCMU_FAN_REG_CLK_FANOUT1_EN_CLEAR_MASK 0x00400000
    #define CCMU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_OFF 0x0
    #define CCMU_FAN_REG_CLK_FANOUT1_EN_CLOCK_IS_ON 0x1
  #define CCMU_FAN_REG_CLK_FANOUT0_EN_OFFSET 21
  #define CCMU_FAN_REG_CLK_FANOUT0_EN_CLEAR_MASK 0x00200000
    #define CCMU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_OFF 0x0
    #define CCMU_FAN_REG_CLK_FANOUT0_EN_CLOCK_IS_ON 0x1
  #define CCMU_FAN_REG_CLK_FANOUT2_SEL_OFFSET 6
  #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLEAR_MASK 0x000001c0
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLK32K_FANOUT_FROM_SYSRTC 0x000
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLK12M_FROM_DCXO_2 0x001
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLK16M_FROM_PERI_160M_10 0x010
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLK24M_FROM_DCXO 0x011
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLK25M_FROM_PERI_150M_6 0x100
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_CLK27M 0x101
    #define CCMU_FAN_REG_CLK_FANOUT2_SEL_PCLK 0x110
  #define CCMU_FAN_REG_CLK_FANOUT1_SEL_OFFSET 3
  #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLEAR_MASK 0x00000038
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLK32K_FANOUT_FROM_SYSRTC 0x000
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLK12M_FROM_DCXO_2 0x001
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLK16M_FROM_PERI_160M_10 0x010
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLK24M_FROM_DCXO 0x011
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLK25M_FROM_PERI_150M_6 0x100
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_CLK27M 0x101
    #define CCMU_FAN_REG_CLK_FANOUT1_SEL_PCLK 0x110
  #define CCMU_FAN_REG_CLK_FANOUT0_SEL_OFFSET 0
  #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLEAR_MASK 0x00000007
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLK32K_FANOUT_FROM_SYSRTC 0x000
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLK12M_FROM_DCXO_2 0x001
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLK16M_FROM_PERI_160M_10 0x010
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLK24M_FROM_DCXO 0x011
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLK25M_FROM_PERI_150M_6 0x100
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_CLK27M 0x101
    #define CCMU_FAN_REG_CLK_FANOUT0_SEL_PCLK 0x110

#define PLL_CFG0_REG 0x00000f40 //PLL Configuration0 Register
  #define PLL_CFG0_REG_PLL_CONFIG0_OFFSET 0
  #define PLL_CFG0_REG_PLL_CONFIG0_CLEAR_MASK 0xffffffff

#define PLL_CFG1_REG 0x00000f44 //PLL Configuration1 Register
  #define PLL_CFG1_REG_PLL_CONFIG1_OFFSET 0
  #define PLL_CFG1_REG_PLL_CONFIG1_CLEAR_MASK 0xffffffff

#define PLL_CFG2_REG 0x00000f48 //PLL Configuration2 Register
  #define PLL_CFG2_REG_PLL_CONFIG2_OFFSET 0
  #define PLL_CFG2_REG_PLL_CONFIG2_CLEAR_MASK 0xffffffff

#define CCMU_VERSION_REG 0x00000ff0 //CCMU Version Register
  #define CCMU_VERSION_REG_CCMU_MAIN_VERSION_OFFSET 16
  #define CCMU_VERSION_REG_CCMU_MAIN_VERSION_CLEAR_MASK 0xffff0000
  #define CCMU_VERSION_REG_CCMU_SUB_VERSION_OFFSET 0
  #define CCMU_VERSION_REG_CCMU_SUB_VERSION_CLEAR_MASK 0x0000ffff

struct CCMU_st {
	uint32_t pll_cpu0_ctrl_reg;//pll_cpu0 control register
	uint32_t pad_until_0x0008[1];
	uint32_t pll_cpu1_ctrl_reg;//pll_cpu1 control register
	uint32_t pll_cpu2_ctrl_reg;//pll_cpu2 control register
	uint32_t pll_ddr_ctrl_reg;//pll_ddr control register
	uint32_t pad_until_0x0020[3];
	uint32_t pll_peri0_ctrl_reg;//pll_peri0 control register
	uint32_t pad_until_0x0028[1];
	uint32_t pll_peri1_ctrl_reg;//pll_peri1 control register
	uint32_t pad_until_0x0030[1];
	uint32_t pll_gpu_ctrl_reg;//pll_gpu control register
	uint32_t pad_until_0x0040[3];
	uint32_t pll_video0_ctrl_reg;//pll_video0 control register
	uint32_t pad_until_0x0048[1];
	uint32_t pll_video1_ctrl_reg;//pll_video1 control register
	uint32_t pad_until_0x0050[1];
	uint32_t pll_video2_ctrl_reg;//pll_video2 control register
	uint32_t pad_until_0x0058[1];
	uint32_t pll_ve_ctrl_reg;//pll_ve control register
	uint32_t pad_until_0x0068[3];
	uint32_t pll_video3_ctrl_reg;//pll_video3 control register
	uint32_t pad_until_0x0078[3];
	uint32_t pll_audio_ctrl_reg;//pll_audio control register
	uint32_t pad_until_0x0080[1];
	uint32_t pll_npu_ctrl_reg;//pll_npu control register
	uint32_t pad_until_0x0110[35];
	uint32_t pll_ddr_pat0_ctrl_reg;//pll_ddr pattern0 control register
	uint32_t pll_ddr_pat1_ctrl_reg;//pll_ddr pattern1 control register
	uint32_t pad_until_0x0120[2];
	uint32_t pll_peri0_pat0_ctrl_reg;//pll_peri0 pattern0 control register
	uint32_t pll_peri0_pat1_ctrl_reg;//pll_peri0 pattern1 control register
	uint32_t pll_peri1_pat0_ctrl_reg;//pll_peri1 pattern0 control register
	uint32_t pll_peri1_pat1_ctrl_reg;//pll_peri1 pattern1 control register
	uint32_t pll_gpu_pat0_ctrl_reg;//pll_gpu pattern0 control register
	uint32_t pll_gpu_pat1_ctrl_reg;//pll_gpu pattern1 control register
	uint32_t pad_until_0x0140[2];
	uint32_t pll_video0_pat0_ctrl_reg;//pll_video0 pattern0 control register
	uint32_t pll_video0_pat1_ctrl_reg;//pll_video0 pattern1 control register
	uint32_t pll_video1_pat0_ctrl_reg;//pll_video1 pattern0 control register
	uint32_t pll_video1_pat1_ctrl_reg;//pll_video1 pattern1 control register
	uint32_t pll_video2_pat0_ctrl_reg;//pll_video2 pattern0 control register
	uint32_t pll_video2_pat1_ctrl_reg;//pll_video2 pattern1 control register
	uint32_t pll_ve_pat0_ctrl_reg;//pll_ve pattern0 control register
	uint32_t pll_ve_pat1_ctrl_reg;//pll_ve pattern1 control register
	uint32_t pad_until_0x0168[2];
	uint32_t pll_video3_pat0_ctrl_reg;//pll_video3 pattern0 control register
	uint32_t pll_video3_pat1_ctrl_reg;//pll_video3 pattern1 control register
	uint32_t pad_until_0x0178[2];
	uint32_t pll_audio_pat0_ctrl_reg;//pll_audio pattern0 control register
	uint32_t pll_audio_pat1_ctrl_reg;//pll_audio pattern1 control register
	uint32_t pll_npu_pat0_ctrl_reg;//pll_npu pattern0 control register
	uint32_t pll_npu_pat1_ctrl_reg;//pll_npu pattern1 control register
	uint32_t pad_until_0x0300[94];
	uint32_t pll_cpu0_bias_reg;//pll_cpu0 bias register
	uint32_t pad_until_0x0308[1];
	uint32_t pll_cpu1_bias_reg;//pll_cpu1 bias register
	uint32_t pll_cpu2_bias_reg;//pll_cpu2 bias register
	uint32_t pll_ddr_bias_reg;//pll_ddr bias register
	uint32_t pad_until_0x0320[3];
	uint32_t pll_peri0_bias_reg;//pll_peri0 bias register
	uint32_t pad_until_0x0328[1];
	uint32_t pll_peri1_bias_reg;//pll_peri1 bias register
	uint32_t pad_until_0x0330[1];
	uint32_t pll_gpu_bias_reg;//pll_gpu bias register
	uint32_t pad_until_0x0340[3];
	uint32_t pll_video0_bias_reg;//pll_video0 bias register
	uint32_t pad_until_0x0348[1];
	uint32_t pll_video1_bias_reg;//pll_video1 bias register
	uint32_t pad_until_0x0350[1];
	uint32_t pll_video2_bias_reg;//pll_video2 bias register
	uint32_t pad_until_0x0358[1];
	uint32_t pll_ve_bias_reg;//pll_ve bias register
	uint32_t pad_until_0x0368[3];
	uint32_t pll_video3_bias_reg;//pll_video3 bias register
	uint32_t pad_until_0x0378[3];
	uint32_t pll_audio_bias_reg;//pll_audio bias register
	uint32_t pad_until_0x0380[1];
	uint32_t pll_npu_bias_reg;//pll_npu bias register
	uint32_t pad_until_0x0400[31];
	uint32_t pll_cpu0_tun_reg;//pll_cpu0 tuning register
	uint32_t pad_until_0x0408[1];
	uint32_t pll_cpu1_tun_reg;//pll_cpu1 tuning register
	uint32_t pll_cpu2_tun_reg;//pll_cpu2 tuning register
	uint32_t pad_until_0x0500[60];
	uint32_t cpu_clk_reg;//cpu clock register
	uint32_t cpu_gating_reg;//cpu gating configuration register
	uint32_t trace_clk_reg;//trace clock register
	uint32_t dsu_clk_reg;//dsu clock register
	uint32_t ahb_clk_reg;//ahb clock register
	uint32_t pad_until_0x0520[3];
	uint32_t apb0_clk_reg;//apb0 clock register
	uint32_t apb1_clk_reg;//apb1 clock register
	uint32_t pad_until_0x0540[6];
	uint32_t mbus_clk_reg;//mbus clock register
	uint32_t pad_until_0x054c[2];
	uint32_t nsi_bgr_reg;//nsi bus gating reset register
	uint32_t gic_clk_reg;//gic clock register
	uint32_t pad_until_0x0600[43];
	uint32_t de0_clk_reg;//de0 clock register
	uint32_t pad_until_0x060c[2];
	uint32_t de_bgr_reg;//de bus gating reset register
	uint32_t pad_until_0x0620[4];
	uint32_t di_clk_reg;//di clock register
	uint32_t pad_until_0x062c[2];
	uint32_t di_bgr_reg;//di bus gating reset register
	uint32_t g2d_clk_reg;//g2d clock register
	uint32_t pad_until_0x063c[2];
	uint32_t g2d_bgr_reg;//g2d bus gating reset register
	uint32_t pad_until_0x0670[12];
	uint32_t gpu_core_clk_reg;//gpu_core clock register
	uint32_t pad_until_0x067c[2];
	uint32_t gpu_gating_reg;//gpu gating reset configuration register
	uint32_t ce_clk_reg;//ce clock register
	uint32_t pad_until_0x068c[2];
	uint32_t ce_bgr_reg;//ce bus gating reset register
	uint32_t ve_clk_reg;//ve clock register
	uint32_t pad_until_0x069c[2];
	uint32_t ve_bgr_reg;//ve bus gating reset register
	uint32_t pad_until_0x06e0[16];
	uint32_t npu_clk_reg;//npu clock register
	uint32_t pad_until_0x070c[10];
	uint32_t dma_bgr_reg;//dma bus gating reset register
	uint32_t pad_until_0x071c[3];
	uint32_t msgbox_bgr_reg;//msgbox bus gating reset register
	uint32_t pad_until_0x072c[3];
	uint32_t spinlock_bgr_reg;//spinlock bus gating reset register
	uint32_t timer0_clk_reg;//timer0 clock register
	uint32_t timer1_clk_reg;//timer1 clock register
	uint32_t timer2_clk_reg;//timer2 clock register
	uint32_t timer3_clk_reg;//timer3 clock register
	uint32_t timer4_clk_reg;//timer4 clock register
	uint32_t timer5_clk_reg;//timer5 clock register
	uint32_t pad_until_0x074c[1];
	uint32_t timer_bgr_reg;//timer bus gating reset register
	uint32_t avs_clk_reg;//avs clock register
	uint32_t pad_until_0x078c[14];
	uint32_t dbgsys_bgr_reg;//dbgsys bus gating reset register
	uint32_t pad_until_0x07ac[7];
	uint32_t pwm_bgr_reg;//pwm bus gating reset register
	uint32_t pad_until_0x07bc[3];
	uint32_t iommu_bgr_reg;//iommu bus gating reset register
	uint32_t pad_until_0x0800[16];
	uint32_t dram_clk_reg;//dram clock register
	uint32_t mbus_mat_clk_gating_reg;//mbus master clock gating register
	uint32_t pad_until_0x080c[1];
	uint32_t dram_bgr_reg;//dram bus gating reset register
	uint32_t nand0_clk0_clk_reg;//nand0 clk0 clock register
	uint32_t nand0_clk1_clk_reg;//nand0 clk1 clock register
	uint32_t pad_until_0x082c[5];
	uint32_t nand_bgr_reg;//nand bus gating reset register
	uint32_t smhc0_clk_reg;//smhc0 clock register
	uint32_t smhc1_clk_reg;//smhc1 clock register
	uint32_t smhc2_clk_reg;//smhc2 clock register
	uint32_t pad_until_0x084c[4];
	uint32_t smhc_bgr_reg;//smhc bus gating reset register
	uint32_t pad_until_0x088c[15];
	uint32_t sysdap_bgr_reg;//sysdap bus gating reset register
	uint32_t pad_until_0x090c[31];
	uint32_t uart_bgr_reg;//uart bus gating reset register
	uint32_t pad_until_0x091c[3];
	uint32_t twi_bgr_reg;//twi bus gating reset register
	uint32_t pad_until_0x092c[3];
	uint32_t can_bgr_reg;//can bus gating reset register
	uint32_t pad_until_0x0940[4];
	uint32_t spi0_clk_reg;//spi0 clock register
	uint32_t spi1_clk_reg;//spi1 clock register
	uint32_t spi2_clk_reg;//spi2 clock register
	uint32_t pad_until_0x0950[1];
	uint32_t spif_clk_reg;//spif clock register
	uint32_t pad_until_0x096c[6];
	uint32_t spi_bgr_reg;//spi bus gating reset register
	uint32_t gmac0_25m_clk_reg;//gmac0_25m clock register
	uint32_t gmac1_25m_clk_reg;//gmac1_25m clock register
	uint32_t pad_until_0x097c[1];
	uint32_t gmac_bgr_reg;//gmac bus gating reset register
	uint32_t pad_until_0x0990[4];
	uint32_t irrx_clk_reg;//irrx clock register
	uint32_t pad_until_0x099c[2];
	uint32_t irrx_bgr_reg;//irrx bus gating reset register
	uint32_t pad_until_0x09c0[8];
	uint32_t irtx_clk_reg;//irtx clock register
	uint32_t pad_until_0x09cc[2];
	uint32_t irtx_bgr_reg;//irtx bus gating reset register
	uint32_t pad_until_0x09e0[4];
	uint32_t gpadc_24m_clk_reg;//gpadc_24m clock register
	uint32_t pad_until_0x09ec[2];
	uint32_t gpadc_bgr_reg;//gpadc bus gating reset register
	uint32_t pad_until_0x09fc[3];
	uint32_t ths_bgr_reg;//ths bus gating reset register
	uint32_t pad_until_0x0a70[28];
	uint32_t usb0_clk_reg;//usb0 clock register
	uint32_t usb1_clk_reg;//usb1 clock register
	uint32_t usb2_ref_clk_reg;//usb2_ref clock register
	uint32_t usb2_suspend_clk_reg;//usb2_suspend clock register
	uint32_t pad_until_0x0a8c[3];
	uint32_t usb_bgr_reg;//usb bus gating reset register
	uint32_t pad_until_0x0a9c[3];
	uint32_t lradc_bgr_reg;//lradc bus gating reset register
	uint32_t pcie_aux_clk_reg;//pcie_aux clock register
	uint32_t pcie_ref_clk_reg;//pcie_ref clock register
	uint32_t pad_until_0x0aac[1];
	uint32_t pcie_bgr_reg;//pcie bus gating reset register
	uint32_t pad_until_0x0abc[3];
	uint32_t dpss_top0_bgr_reg;//dpss_top0 bus gating reset register
	uint32_t pad_until_0x0acc[3];
	uint32_t dpss_top1_bgr_reg;//dpss_top1 bus gating reset register
	uint32_t pad_until_0x0b04[13];
	uint32_t hdmi_24m_clk_reg;//hdmi_24m clock register
	uint32_t pad_until_0x0b10[2];
	uint32_t hdmi_cec_clk_reg;//hdmi cec clock register
	uint32_t pad_until_0x0b1c[2];
	uint32_t hdmi_bgr_reg;//hdmi bus gating reset register
	uint32_t pad_until_0x0b24[1];
	uint32_t dsi0_clk_reg;//dsi0 clock register
	uint32_t dsi1_clk_reg;//dsi1 clock register
	uint32_t pad_until_0x0b4c[8];
	uint32_t dsi_bgr_reg;//dsi bus gating reset register
	uint32_t pad_until_0x0b60[4];
	uint32_t vo0_tconlcd0_clk_reg;//vo0_tconlcd0 clock register
	uint32_t vo0_tconlcd1_clk_reg;//vo0_tconlcd1 clock register
	uint32_t vo1_tconlcd0_clk_reg;//vo1_tconlcd0 clock register
	uint32_t combphy0_clk_reg;//combphy0 clock register
	uint32_t combphy1_clk_reg;//combphy1 clock register
	uint32_t pad_until_0x0b7c[2];
	uint32_t tconlcd_bgr_reg;//tconlcd bus gating reset register
	uint32_t tcontv_clk_reg;//tcontv clock register
	uint32_t pad_until_0x0b9c[6];
	uint32_t tcontv_bgr_reg;//tcontv bus gating reset register
	uint32_t pad_until_0x0bac[3];
	uint32_t lvds_bgr_reg;//lvds bus gating reset register
	uint32_t pad_until_0x0bf0[16];
	uint32_t ledc_clk_reg;//ledc clock register
	uint32_t pad_until_0x0bfc[2];
	uint32_t ledc_bgr_reg;//ledc bus gating reset register
	uint32_t pad_until_0x0c04[1];
	uint32_t csi_clk_reg;//csi clock register
	uint32_t csi_master0_clk_reg;//csi master0 clock register
	uint32_t csi_master1_clk_reg;//csi master1 clock register
	uint32_t csi_master2_clk_reg;//csi master2 clock register
	uint32_t csi_master3_clk_reg;//csi master3 clock register
	uint32_t pad_until_0x0c1c[1];
	uint32_t csi_bgr_reg;//csi bus gating reset register
	uint32_t isp_clk_reg;//isp clock register
	uint32_t pad_until_0x0c2c[2];
	uint32_t isp_bgr_reg;//isp bus gating reset register
	uint32_t pad_until_0x0c70[16];
	uint32_t dsp_clk_reg;//dsp clock register
	uint32_t pad_until_0x0e04[100];
	uint32_t ahb_gate_en_reg;//ahb gate enable register
	uint32_t peri0pll_gate_en_reg;//peri0pll gate enable register
	uint32_t clk24m_gate_en_reg;//clk24m gate enable register
	uint32_t pad_until_0x0f00[60];
	uint32_t ccmu_sec_switch_reg;//ccmu security switch register
	uint32_t pll_lock_dbg_ctrl_reg;//pll lock debug control register
	uint32_t sysdap_req_ctrl_reg;//sysdap req control register
	uint32_t pad_until_0x0f30[9];
	uint32_t ccmu_fan_gate_reg;//ccmu fanout clock gate register
	uint32_t clk27m_fan_reg;//clk27m fanout register
	uint32_t clk_fan_reg;//clk fanout register
	uint32_t ccmu_fan_reg;//ccmu fanout register
	uint32_t pll_cfg0_reg;//pll configuration0 register
	uint32_t pll_cfg1_reg;//pll configuration1 register
	uint32_t pll_cfg2_reg;//pll configuration2 register
	uint32_t pad_until_0x0ff0[41];
	uint32_t ccmu_version_reg;//ccmu version register
};

