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fel: ignore more bits in SCTLR

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Some bits are not meaningful both in ARMv5 and ARMv7/8, however they're
read as 0 in ARMv5 but 1 in ARMv7/8.

Ignore them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Andre Przywara <osp@andrep.de>
This commit is contained in:
Icenowy Zheng 2018-01-13 19:59:47 +08:00 committed by Andre Przywara
parent 4fb307f1e4
commit 0512f4d916
1 changed files with 7 additions and 2 deletions
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9
fel.c
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@ -623,9 +623,14 @@ uint32_t *aw_backup_and_disable_mmu(feldev_handle *dev,
* checks needs to be relaxed).
*/
/* Basically, ignore M/Z/I/V/UNK bits and expect no TEX remap */
/*
* Basically, ignore M/Z/I/V/UNK bits and expect no TEX remap.
* Bits [23:22] are Read-As-One on ARMv7, but Should-Be-Zero
* on ARMv5, so ignore them.
* We need the RES1 bits[18,16,4,3] and CP15BEN[5].
*/
sctlr = aw_get_sctlr(dev, soc_info);
if ((sctlr & ~((0x7 << 11) | (1 << 6) | 1)) != 0x00C50038)
if ((sctlr & ~((0x3 << 22) | (0x7 << 11) | (1 << 6) | 1)) != 0x00050038)
pr_fatal("Unexpected SCTLR (%08X)\n", sctlr);
if (!(sctlr & 1)) {