diff --git a/soc_info.c b/soc_info.c
index 20c982b..5ae2b23 100644
--- a/soc_info.c
+++ b/soc_info.c
@@ -145,6 +145,23 @@ sram_swap_buffers r329_sram_swap_buffers[] = {
 	{ .size = 0 }  /* End of the table */
 };
 
+/*
+ * The FEL code from BROM in F1C100s also uses SRAM A in a similar way
+ * with A10/A13/A20.
+ * Unfortunately the SRAM layout of F1C100s is not documented at all, so
+ * we can only try by r/w under FEL mode.
+ * The result is that there's a contingous SRAM zone from 0x8800 to 0xb5ff.
+ */
+sram_swap_buffers f1c100s_sram_swap_buffers[] = {
+	/* 0x1C00-0x1FFF (IRQ stack) */
+	{ .buf1 = 0x1C00, .buf2 = 0x9000, .size = 0x0400 },
+	/* 0x5C00-0x6FFF (Stack) */
+	{ .buf1 = 0x5C00, .buf2 = 0x9400, .size = 0x1400 },
+	/* 0x7C00-0x7FFF (Something important) */
+	{ .buf1 = 0x7C00, .buf2 = 0xa800, .size = 0x0400 },
+	{ .size = 0 }  /* End of the table */
+};
+
 const watchdog_info wd_a10_compat = {
 	.reg_mode = 0x01C20C94,
 	.reg_mode_value = 3,
@@ -246,6 +263,15 @@ soc_info_t soc_info_table[] = {
 		.sid_base     = 0X01C0E000,
 		.sid_offset   = 0x200,
 		.watchdog     = &wd_a80,
+	},{
+		.soc_id       = 0x1663, /* Allwinner F1C100s (all new sun3i?) */
+		.name         = "F1C100s",
+		.scratch_addr = 0x1000,
+		.thunk_addr   = 0xb400, .thunk_size = 0x200,
+		.swap_buffers = f1c100s_sram_swap_buffers,
+		.sram_size    = 32 * 1024,
+		/* No SID */
+		.watchdog     = &wd_h3_compat,
 	},{
 		.soc_id       = 0x1673, /* Allwinner A83T */
 		.name         = "A83T",