diff --git a/soc_info.c b/soc_info.c index 56a158c..866e012 100644 --- a/soc_info.c +++ b/soc_info.c @@ -125,6 +125,12 @@ sram_swap_buffers v831_sram_swap_buffers[] = { { .size = 0 } /* End of the table */ }; +/* H616 situation is the same as V831 one, except it has 32 KiB of SRAM A1. */ +sram_swap_buffers h616_sram_swap_buffers[] = { + { .buf1 = 0x21000, .buf2 = 0x28000, .size = 0x1000 }, + { .size = 0 } /* End of the table */ +}; + const watchdog_info wd_a10_compat = { .reg_mode = 0x01C20C94, .reg_mode_value = 3, @@ -274,6 +280,16 @@ soc_info_t soc_info_table[] = { .swap_buffers = v831_sram_swap_buffers, .sid_base = 0x03006000, .sid_offset = 0x200, + },{ + .soc_id = 0x1823, /* Allwinner H616 */ + .name = "H616", + .spl_addr = 0x20000, + .scratch_addr = 0x21000, + .thunk_addr = 0x2A200, .thunk_size = 0x200, + .swap_buffers = h616_sram_swap_buffers, + .sid_base = 0x03006000, + .sid_offset = 0x200, + .rvbar_reg = 0x09010040, },{ .swap_buffers = NULL /* End of the table */ } diff --git a/uart0-helloworld-sdboot.c b/uart0-helloworld-sdboot.c index a33584f..52d7e43 100644 --- a/uart0-helloworld-sdboot.c +++ b/uart0-helloworld-sdboot.c @@ -147,6 +147,7 @@ enum sunxi_gpio_number { #define SUN8I_V831_GPH_UART0 (5) #define SUN50I_H5_GPA_UART0 (2) #define SUN50I_H6_GPH_UART0 (2) +#define SUN50I_H616_GPH_UART0 (2) #define SUN50I_A64_GPB_UART0 (4) #define SUNXI_GPF_UART0 (4) @@ -306,6 +307,7 @@ void soc_detection_init(void) #define soc_is_a64() (soc_id == 0x1689) #define soc_is_h5() (soc_id == 0x1718) #define soc_is_h6() (soc_id == 0x1728) +#define soc_is_h616() (soc_id == 0x1823) #define soc_is_r40() (soc_id == 0x1701) #define soc_is_v3s() (soc_id == 0x1681) #define soc_is_v831() (soc_id == 0x1817) @@ -384,7 +386,7 @@ void clock_init_uart_h6(void) void clock_init_uart(void) { - if (soc_is_h6() || soc_is_v831()) + if (soc_is_h6() || soc_is_v831() || soc_is_h616()) clock_init_uart_h6(); else clock_init_uart_legacy(); @@ -434,6 +436,10 @@ void gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); + } else if (soc_is_h616()) { + sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); } else if (soc_is_v3s()) { sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); @@ -518,7 +524,7 @@ int get_boot_device(void) u32 *spl_signature = (void *)0x4; if (soc_is_a64() || soc_is_a80() || soc_is_h5()) spl_signature = (void *)0x10004; - if (soc_is_h6() || soc_is_v831()) + if (soc_is_h6() || soc_is_v831() || soc_is_h616()) spl_signature = (void *)0x20004; /* Check the eGON.BT0 magic in the SPL header */ @@ -536,7 +542,7 @@ int get_boot_device(void) void bases_init(void) { - if (soc_is_h6() || soc_is_v831()) { + if (soc_is_h6() || soc_is_v831() || soc_is_h616()) { pio_base = H6_PIO_BASE; uart0_base = H6_UART0_BASE; } else { @@ -573,6 +579,8 @@ int main(void) uart0_puts("Allwinner H5!\n"); else if (soc_is_h6()) uart0_puts("Allwinner H6!\n"); + else if (soc_is_h616()) + uart0_puts("Allwinner H616!\n"); else if (soc_is_r40()) uart0_puts("Allwinner R40!\n"); else if (soc_is_v3s())