add V536 SoC support

HW very similar to V831, for the purpose of fel practically identical
This commit is contained in:
Daniel Kucera 2021-11-28 21:13:28 +01:00
parent 74273b671a
commit 458a2c6d25
2 changed files with 15 additions and 0 deletions

View File

@ -122,6 +122,7 @@ static uint32_t gpio_base(feldev_handle *dev)
{
soc_info_t *soc_info = dev->soc_info;
switch (soc_info->soc_id) {
case 0x1816: /* V536 */
case 0x1817: /* V831 */
case 0x1728: /* H6 */
case 0x1823: /* H616 */
@ -140,6 +141,7 @@ static uint32_t spi_base(feldev_handle *dev)
case 0x1651: /* A20 */
case 0x1701: /* R40 */
return 0x01C05000;
case 0x1816: /* V536 */
case 0x1817: /* V831 */
case 0x1728: /* H6 */
case 0x1823: /* H616 */
@ -181,6 +183,7 @@ static bool soc_is_h6_style(feldev_handle *dev)
{
soc_info_t *soc_info = dev->soc_info;
switch (soc_info->soc_id) {
case 0x1816: /* V536 */
case 0x1817: /* V831 */
case 0x1728: /* H6 */
case 0x1823: /* H616 */
@ -228,6 +231,7 @@ static bool spi0_init(feldev_handle *dev)
gpio_set_cfgpin(dev, PC, 2, SUN50I_GPC_SPI0);
gpio_set_cfgpin(dev, PC, 3, SUN50I_GPC_SPI0);
break;
case 0x1816: /* Allwinner V536 */
case 0x1817: /* Allwinner V831 */
gpio_set_cfgpin(dev, PC, 1, SUN50I_GPC_SPI0); /* SPI0-CS */
/* fall-through */

View File

@ -307,6 +307,17 @@ soc_info_t soc_info_table[] = {
/* Check L.NOP in the OpenRISC reset vector */
.needs_smc_workaround_if_zero_word_at_addr = 0x100004,
.watchdog = &wd_h6_compat,
},{
.soc_id = 0x1816, /* Allwinner V536 */
.name = "V536",
.spl_addr = 0x20000,
.scratch_addr = 0x21000,
.thunk_addr = 0x2A200, .thunk_size = 0x200,
.swap_buffers = v831_sram_swap_buffers,
.sram_size = 228 * 1024,
.sid_base = 0x03006000,
.sid_offset = 0x200,
.watchdog = &wd_h6_compat,
},{
.soc_id = 0x1817, /* Allwinner V831 */
.name = "V831",