12 Commits

Author SHA1 Message Date
Karl Palsson
39bd0d1dd8 Provide a wrapper for reset via watchdog
The watchdog register isn't in the same place, nor uses the same values
to trigger a reset.

Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2020-06-14 14:50:34 +03:00
Icenowy Zheng
ed54b135c1 fel: add SoC info for H6 SoC
Allwinner H6 is a new SoC with its memory map changed.

Add its SoC info, including SRAM addresses and SID address.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Andre Przywara <osp@andrep.de>
2018-07-09 09:16:24 +01:00
Siarhei Siamashka
275827ad73 fel: Enable the SMC workaround for H3/H5/A64/H64
Use a hardwired L.NOP instruction from the OpenRISC reset
vector as a way to check if the workaround is necessary.
Because these L.NOP instructions are guaranteed to be there
and are read-only, this is the most reliable non-invasive test.

Reading SID would be less reliable because it is one-time
programmable and theoretically may be set to zero on some boards.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
2017-02-28 21:10:44 +02:00
Icenowy Zheng
463cd64cbd fel: workaround H3 SID issue
H3 SID controller has some bug, that makes the initial value at
0x01c14200 wrong.

This commit workarounds this bug by reading them with register access
first.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Bernhard Nortmann <bernhard.nortmann@web.de>
2016-12-28 13:30:09 +01:00
Bernhard Nortmann
5c501c5bb8 soc_info: Split sid_addr into sid_base + sid_offset
This is a preparatory step. Instead of using memory-based access,
we might want to retrieve SID keys (e-fuses) via SID registers.
For this, it's convenient if the plain base address is available.

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
2016-12-28 13:29:47 +01:00
Icenowy Zheng
8361dac255 fel: Add SOC ID, SRAM info and SID address for V3s
The V3s SoC looks like A10/13/20 in SRAM mapping and SID address.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
2016-12-28 17:45:03 +08:00
Bernhard Nortmann
445b1747e5 soc_info: Iterate over soc_info_table with pointer, not by index
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
2016-12-01 16:24:07 +01:00
Bernhard Nortmann
dfc93db131 fel_lib: Add a human-readable SoC name field to the device handle
open_fel_device() will automatically provide this member field,
based on the SoC ID from FEL/BROM version data. The field will
either receive a human-readable identifier, or the ID in 4-digit
hexadecimal representation (for unknown SoCs).

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
2016-11-29 14:45:36 +01:00
Chen-Yu Tsai
4c4111034f fel: Add SID register address for A80
The SID block in the A80 is at 0x01c0e000, with the e-fuses we care
about at offset 0x200 within the block.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2016-11-29 13:47:39 +01:00
Chen-Yu Tsai
bbfcf117bb fel: Add SOC ID, SRAM info and SID address for R40
The R40 is marketed as the successor to the A20. The SRAM layout is the
same as the A20, but there doesn't seem to be a secure SRAM block.

The SID block is at a completely different address. The layout is the
same as the newer SoCs, with the e-fuses at an offset of 0x200.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2016-11-29 15:21:17 +08:00
Bernhard Nortmann
93a26d58ad uart0-helloworld: Refactor SoC detection
Besides having fewer lines of code, the #define macros should
also prevent users from accidentally using these names without
braces (i.e. as function pointers). Instead, this will cause
compiler errors now.

soc_info.c: add "A10s" label in comment for SoC ID 0x1625.

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
2016-11-16 17:37:50 +01:00
Bernhard Nortmann
8640291376 fel: Factor out SoC information (and SRAM buffers) retrieval
While at it, modify the former "sram_info" identifiers
to carry a broader "soc_info" meaning.

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
2016-11-13 21:33:58 +01:00