edcbe4f4b8
This adds SoC-specific pin muxing descriptions to select JTAG on the SD pins, with a helper function. The JTAG pins are always the same (PF0/1/3/5) so they are hardcoded, while the mux is either 3 or 4 depending on the platform. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
225 lines
6.7 KiB
C
225 lines
6.7 KiB
C
/*
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* Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Partially based on the uart code from ar100-info
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*
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* (C) Copyright 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Partially based on the sunxi gpio code from U-Boot
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*
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* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
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*
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* Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c:
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _BARE_METAL_H_
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#define _BARE_METAL_H_
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typedef unsigned int u32;
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typedef unsigned short int u16;
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typedef unsigned char u8;
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#ifndef NULL
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#define NULL ((void*)0)
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#endif
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
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#define set_wbit(addr, v) (*((volatile unsigned long *)(addr)) |= (unsigned long)(v))
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#define readl(addr) (*((volatile unsigned long *)(addr)))
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#define writel(v, addr) (*((volatile unsigned long *)(addr)) = (unsigned long)(v))
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#define SUNXI_UART0_BASE 0x01C28000
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#define SUNXI_PIO_BASE 0x01C20800
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#define AW_CCM_BASE 0x01c20000
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#define AW_SRAMCTRL_BASE 0x01c00000
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#define A80_SRAMCTRL_BASE 0x00800000
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#define A80_CCM_BASE 0x06000000
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#define A80_PIO_BASE 0x06000800
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#define A80_UART0_BASE 0x07000000
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#define H6_UART0_BASE 0x05000000
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#define H6_PIO_BASE 0x0300B000
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#define H6_CCM_BASE 0x03001000
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#define H6_SRAMCTRL_BASE 0x03000000
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#define R329_UART0_BASE 0x02500000
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#define R329_PIO_BASE 0x02000400
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#define R329_CCM_BASE 0x02001000
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#define V853_PIO_BASE 0x02000000
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#define SUNIV_UART0_BASE 0x01c25000
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#define SRAM_A1_ADDR_0 0x00000000
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#define SRAM_A1_ADDR_10000 0x00010000
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#define SRAM_A1_ADDR_20000 0x00020000
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#define SRAM_A1_ADDR_100000 0x00100000
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/*****************************************************************************
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* GPIO code, borrowed from U-Boot *
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*****************************************************************************/
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#define SUNXI_GPIO_A 0
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#define SUNXI_GPIO_B 1
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#define SUNXI_GPIO_C 2
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#define SUNXI_GPIO_D 3
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#define SUNXI_GPIO_E 4
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#define SUNXI_GPIO_F 5
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#define SUNXI_GPIO_G 6
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#define SUNXI_GPIO_H 7
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#define SUNXI_GPIO_I 8
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#define GPIO_BANK(pin) ((pin) >> 5)
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#define GPIO_NUM(pin) ((pin) & 0x1F)
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#define GPIO_CFG_BASE(bank) ((u32 *)(pio_base + (bank) * pio_bank_size))
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#define GPIO_CFG_INDEX(pin) (((pin) & 0x1F) >> 3)
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#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1F) & 0x7) << 2)
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#define GPIO_PULL_BASE(bank) ((u32 *)(pio_base + (bank) * pio_bank_size + pio_pull_off))
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#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4)
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#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
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#define GPIO_DAT_BASE(bank) ((u32 *)(pio_base + (bank) * pio_bank_size + pio_dat_off))
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/* GPIO bank sizes */
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#define SUNXI_GPIO_A_NR (32)
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#define SUNXI_GPIO_B_NR (32)
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#define SUNXI_GPIO_C_NR (32)
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#define SUNXI_GPIO_D_NR (32)
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#define SUNXI_GPIO_E_NR (32)
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#define SUNXI_GPIO_F_NR (32)
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#define SUNXI_GPIO_G_NR (32)
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#define SUNXI_GPIO_H_NR (32)
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#define SUNXI_GPIO_I_NR (32)
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#define SUNXI_GPIO_NEXT(__gpio) ((__gpio##_START) + (__gpio##_NR) + 0)
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enum sunxi_gpio_number {
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SUNXI_GPIO_A_START = 0,
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SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A),
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SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B),
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SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C),
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SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D),
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SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E),
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SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
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SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
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SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
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};
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/* SUNXI GPIO number definitions */
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#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr))
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#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr))
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#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr))
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#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr))
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#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr))
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#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr))
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#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
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#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
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#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
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/* GPIO pin function config */
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#define MUX_GPIO_INPUT 0
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#define MUX_GPIO_OUTPUT 1
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#define MUX_2 2
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#define MUX_3 3
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#define MUX_4 4
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#define MUX_5 5
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#define MUX_6 6
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/* GPIO pin pull-up/down config */
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#define SUNXI_GPIO_PULL_DISABLE (0)
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#define SUNXI_GPIO_PULL_UP (1)
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#define SUNXI_GPIO_PULL_DOWN (2)
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#define BIT(x) (1U << (x))
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#define FLAG_VAR0 0
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#define FLAG_VAR1 BIT(0)
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#define FLAG_UART_ON_PORTF BIT(1)
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#define FLAG_NEW_GPIO BIT(2)
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#define FLAG_NEW_CLOCK BIT(3)
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#define FLAG_UART_ON_APB1 BIT(4)
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#define FLAG_A80_CLOCK BIT(5)
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#define FLAG_NCAT2 FLAG_NEW_GPIO | FLAG_NEW_CLOCK
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enum { BOOT_DEVICE_UNK, BOOT_DEVICE_FEL, BOOT_DEVICE_MMC0, BOOT_DEVICE_SPI };
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struct soc_info {
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u16 id;
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char name[10];
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u8 flags;
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const struct {
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u32 base;
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} pio;
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const struct {
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u32 base;
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} ccu;
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const struct {
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u32 a1_base;
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} sram;
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const struct {
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u32 base;
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u16 pin_tx;
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u8 pinmux;
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} uart0;
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const struct {
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u8 pinmux;
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} jtag;
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};
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const struct soc_info *sunxi_detect_soc(void);
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void gpio_init(const struct soc_info *soc);
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void jtag_init(const struct soc_info *soc);
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void uart0_init(const struct soc_info *soc);
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void uart0_putc(char c);
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void uart0_puts(const char *s);
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int get_boot_device(const struct soc_info *soc);
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#endif
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