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gpio L

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This commit is contained in:
MikuQ.com 2016-06-02 20:58:01 +08:00
parent a75d3c30e1
commit 1801a9b2b8
5 changed files with 34 additions and 127 deletions
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4
README.md
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@ -5,6 +5,7 @@ gcc -Wall -o hello3.exe hello3.c -lMikuDuino
./hello3.exe
</code></pre>
<pre><code>
+-----+-----+---------+------+---+- MikuPi -+---+------+---------+-----+-----+
| CPU | wPi | Name | Mode | V | Physical | V | Mode | Name | wPi | CPU |
+-----+-----+---------+------+---+----++----+---+------+---------+-----+-----+
@ -30,4 +31,5 @@ gcc -Wall -o hello3.exe hello3.c -lMikuDuino
| | | GND | | | 39 || 40 | 0 | IN | GPIO.29 | 29 | 147 |
+-----+-----+---------+------+---+----++----+---+------+---------+-----+-----+
| CPU | wPi | Name | Mode | V | Physical | V | Mode | Name | wPi | CPU |
+-----+-----+---------+------+---+- BPI-M3 -+---+------+---------+-----+-----+
+-----+-----+---------+------+---+- BPI-M3 -+---+------+---------+-----+-----+
</code></pre>

27
test/gpio_lib.c
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@ -40,6 +40,7 @@
unsigned int SUNXI_PIO_BASE = 0;
unsigned int SUNXI_PIO_LM_BASE = 0;
static volatile long int *gpio_map = NULL;
int sunxi_gpio_init(void) {
@ -58,15 +59,22 @@ int sunxi_gpio_init(void) {
addr_start = SW_PORTC_IO_BASE & PageMask;
addr_offset = SW_PORTC_IO_BASE & ~PageMask;
gpio_map = (void *)mmap(0, PageSize*2, PROT_READ|PROT_WRITE, MAP_SHARED, fd, addr_start);
if(gpio_map == MAP_FAILED) {
return SETUP_MMAP_FAIL;
}
SUNXI_PIO_BASE = (unsigned int)gpio_map;
SUNXI_PIO_BASE += addr_offset;
addr_start = SW_PORTL_IO_BASE & PageMask;
addr_offset = SW_PORTL_IO_BASE & ~PageMask;
gpio_map = (void *)mmap(0, PageSize*2, PROT_READ|PROT_WRITE, MAP_SHARED, fd, addr_start);
if(gpio_map == MAP_FAILED) {
return SETUP_MMAP_FAIL;
}
SUNXI_PIO_LM_BASE = (unsigned int)gpio_map;
SUNXI_PIO_LM_BASE += addr_offset;
close(fd);
return SETUP_OK;
}
@ -82,9 +90,11 @@ int sunxi_gpio_set_cfgpin(unsigned int pin, unsigned int val) {
return -1;
}
struct sunxi_gpio *pio =
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
struct sunxi_gpio *pio;
if(bank>10)
pio = &((struct sunxi_gpio_reg *)SUNXI_PIO_LM_BASE)->gpio_bank[bank-11];
else
pio = &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
cfg = *(&pio->cfg[0] + index);
cfg &= ~(0xf << offset);
@ -119,7 +129,12 @@ int sunxi_gpio_output(unsigned int pin, unsigned int val) {
{
return -1;
}
struct sunxi_gpio *pio =&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
struct sunxi_gpio *pio;
if(bank>10)
pio = &((struct sunxi_gpio_reg *)SUNXI_PIO_LM_BASE)->gpio_bank[bank-11];
else
pio = &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
if(val)
*(&pio->dat) |= 1 << num;

119
test/gpio_lib.h
View File

@ -1,22 +1,8 @@
#ifndef _GPIO_LIB_H_
#define _GPIO_LIB_H_
#define SW_PORTC_IO_BASE 0x01c20800
#define SUNXI_GPIO_A 0
#define SUNXI_GPIO_B 1
#define SUNXI_GPIO_C 2
#define SUNXI_GPIO_D 3
#define SUNXI_GPIO_E 4
#define SUNXI_GPIO_F 5
#define SUNXI_GPIO_G 6
#define SUNXI_GPIO_H 7
#define SUNXI_GPIO_I 8
#define SUNXI_GPIO_J 9
#define SUNXI_GPIO_K 10
#define SUNXI_GPIO_L 11
#define SW_PORTC_IO_BASE 0x01c20800
#define SW_PORTL_IO_BASE 0x01f02c00
#define SETUP_OK 0
#define SETUP_DEVMEM_FAIL 1
@ -47,7 +33,7 @@ struct sunxi_gpio_int {
};
struct sunxi_gpio_reg {
struct sunxi_gpio gpio_bank[12];
struct sunxi_gpio gpio_bank[9];
unsigned char res[0xbc];
struct sunxi_gpio_int gpio_int;
};
@ -58,104 +44,6 @@ struct sunxi_gpio_reg {
#define GPIO_CFG_INDEX(pin) (((pin) & 0x1F) >> 3)
#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1F) & 0x7) << 2)
/* GPIO bank sizes */
#define SUNXI_GPIO_A_NR (32)
#define SUNXI_GPIO_B_NR (32)
#define SUNXI_GPIO_C_NR (32)
#define SUNXI_GPIO_D_NR (32)
#define SUNXI_GPIO_E_NR (32)
#define SUNXI_GPIO_F_NR (32)
#define SUNXI_GPIO_G_NR (32)
#define SUNXI_GPIO_H_NR (32)
#define SUNXI_GPIO_I_NR (32)
#define SUNXI_GPIO_J_NR (32)
#define SUNXI_GPIO_K_NR (32)
#define SUNXI_GPIO_L_NR (32)
#define SUNXI_GPIO_NEXT(__gpio) ((__gpio##_START)+(__gpio##_NR)+0)
enum sunxi_gpio_number {
SUNXI_GPIO_A_START = 0,
SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), //32
SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), //64
SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), //96
SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), //128
SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), //160
SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), //192
SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), //224
SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), //256
SUNXI_GPIO_J_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_I), //192
SUNXI_GPIO_K_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_J), //224
SUNXI_GPIO_L_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_K) //256
};
/* SUNXI GPIO number definitions */
#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr))
#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr))
#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr))
#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr))
#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr))
#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr))
#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
#define SUNXI_GPJ(_nr) (SUNXI_GPIO_J_START + (_nr))
#define SUNXI_GPK(_nr) (SUNXI_GPIO_K_START + (_nr))
#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
/* GPIO pin function config */
#define SUNXI_GPIO_INPUT (0)
#define SUNXI_GPIO_OUTPUT (1)
#define SUNXI_GPIO_PER (2)
#define SUNXI_GPA0_ERXD3 (2)
#define SUNXI_GPA0_SPI1_CS0 (3)
#define SUNXI_GPA0_UART2_RTS (4)
#define SUNXI_GPA1_ERXD2 (2)
#define SUNXI_GPA1_SPI1_CLK (3)
#define SUNXI_GPA1_UART2_CTS (4)
#define SUNXI_GPA2_ERXD1 (2)
#define SUNXI_GPA2_SPI1_MOSI (3)
#define SUNXI_GPA2_UART2_TX (4)
#define SUNXI_GPA10_UART1_TX (4)
#define SUNXI_GPA11_UART1_RX (4)
#define SUN4I_GPB22_UART0_TX (2)
#define SUN4I_GPB23_UART0_RX (2)
#define SUN5I_GPG3_UART0_TX (4)
#define SUN5I_GPG4_UART0_RX (4)
#define SUNXI_GPC2_NCLE (2)
#define SUNXI_GPC2_SPI0_CLK (3)
#define SUNXI_GPC6_NRB0 (2)
#define SUNXI_GPC6_SDC2_CMD (3)
#define SUNXI_GPC7_NRB1 (2)
#define SUNXI_GPC7_SDC2_CLK (3)
#define SUNXI_GPC8_NDQ0 (2)
#define SUNXI_GPC8_SDC2_D0 (3)
#define SUNXI_GPC9_NDQ1 (2)
#define SUNXI_GPC9_SDC2_D1 (3)
#define SUNXI_GPC10_NDQ2 (2)
#define SUNXI_GPC10_SDC2_D2 (3)
#define SUNXI_GPC11_NDQ3 (2)
#define SUNXI_GPC11_SDC2_D3 (3)
#define SUNXI_GPF2_SDC0_CLK (2)
#define SUNXI_GPF2_UART0_TX (4)
#define SUNXI_GPF4_SDC0_D3 (2)
#define SUNXI_GPF4_UART0_RX (4)
extern int sunxi_gpio_input(unsigned int pin);
extern int sunxi_gpio_init(void);
extern int sunxi_gpio_set_cfgpin(unsigned int pin, unsigned int val);
@ -164,4 +52,5 @@ extern int sunxi_gpio_output(unsigned int pin, unsigned int val);
extern void sunxi_gpio_cleanup(void);
extern unsigned int SUNXI_PIO_BASE;
extern unsigned int SUNXI_PIO_LM_BASE;
#endif

11
test/hello4.c
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@ -1,14 +1,14 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "gpio_lib.h"
// pinToGpio:
// Take a Wiring pin (0 through X) and re-map it to the BCM_GPIO pin
// Cope for 3 different board revisions here.
static int *wPinToGpio ;
//static int *wPinToGpio ;
static int wPinToGpioM2p [32] =
{
@ -18,6 +18,7 @@ static int wPinToGpioM2p [32] =
10,17,354,356, 21,20,19,18
} ;
/*
static int wPinToGpioM3 [32] =
{
68,35,71,81, 34,360,361,362,
@ -25,8 +26,9 @@ static int wPinToGpioM3 [32] =
33,-1,-1,-1, -1,82,202,203,
204,132,205,133, 146,147,227,226
} ;
*/
//static int *bPinTowPin;
//static int *bPinTowPin; git add . git commit -a -m "gpio test" git push origin master
static int bPinTowPin[41] =
{
@ -55,7 +57,7 @@ static int bPinTowPin[41] =
} ;
//#define PA6 SUNXI_GPA(6) *32+6
#define PA6 wPinToGpioM2p[bPinTowPin[36]]
#define PA6 wPinToGpioM2p[bPinTowPin[32]]
int main()
{
@ -76,7 +78,6 @@ int main()
return -1;
}
int i,j;
while(1) {
if(sunxi_gpio_output(PA6,HIGH)){
printf("Failed to set GPIO pin value\n");

BIN
test/hello4.exe
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