From 9a0908f9babdb7bb3aa71feeecd56f6e4cbdd901 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Tue, 11 Jul 2023 19:15:39 +0300 Subject: [PATCH] update rk3588-edge to v6.5-rc1 --- .../kernel/linux-rockchip-rk3588-edge.config | 91 +- config/sources/families/rockchip-rk3588.conf | 4 +- .../0010-Introduce-RK806-Support.patch | 4362 ----------------- ...-rockchip-rk3588-add-GIC-ITS-support.patch | 48 - ... => 0014-RK3588-Add-Cpufreq-Support.patch} | 114 +- ...er-domain-add-rk3588-mem-module-supp.patch | 266 - ...-arm64-dts-rockchip-Add-rk3588-timer.patch | 34 - ...tch => 0020-Add-RK3588-USB2-Support.patch} | 172 +- .../0020-RK3588-ADC-support.patch | 684 --- .../0021-Add-RK3588-SATA-support.patch | 341 +- .../0022-RK3588-PCIe2-support.patch | 119 +- .../0023-Add-RK3588-OTP-memory-support.patch | 847 ---- ...tch => 0023-Add-RK3588-USB3-Support.patch} | 42 +- .../0024-enable-ethernet-for-rock-5b.patch | 33 - ...64-dts-rockchip-rk3588-add-sfc-node.patch} | 0 ...-Support-for-RK3588s-Indiedroid-Nova.patch | 968 ---- 16 files changed, 207 insertions(+), 7918 deletions(-) delete mode 100644 patch/kernel/rockchip-rk3588-edge/0010-Introduce-RK806-Support.patch delete mode 100644 patch/kernel/rockchip-rk3588-edge/0011-arm64-dts-rockchip-rk3588-add-GIC-ITS-support.patch rename patch/kernel/rockchip-rk3588-edge/{0029-RK3588-Add-Cpufreq-Support.patch => 0014-RK3588-Add-Cpufreq-Support.patch} (92%) delete mode 100644 patch/kernel/rockchip-rk3588-edge/0014-soc-rockchip-power-domain-add-rk3588-mem-module-supp.patch delete mode 100644 patch/kernel/rockchip-rk3588-edge/0015-arm64-dts-rockchip-Add-rk3588-timer.patch rename patch/kernel/rockchip-rk3588-edge/{0025-Add-RK3588-USB2-Support.patch => 0020-Add-RK3588-USB2-Support.patch} (85%) delete mode 100644 patch/kernel/rockchip-rk3588-edge/0020-RK3588-ADC-support.patch delete mode 100644 patch/kernel/rockchip-rk3588-edge/0023-Add-RK3588-OTP-memory-support.patch rename patch/kernel/rockchip-rk3588-edge/{0026-Add-RK3588-USB3-Support.patch => 0023-Add-RK3588-USB3-Support.patch} (98%) delete mode 100644 patch/kernel/rockchip-rk3588-edge/0024-enable-ethernet-for-rock-5b.patch rename patch/kernel/rockchip-rk3588-edge/{0028-arm64-dts-rockchip-rk3588-add-sfc-node.patch => 0025-arm64-dts-rockchip-rk3588-add-sfc-node.patch} (100%) delete mode 100644 patch/kernel/rockchip-rk3588-edge/0027-Add-Support-for-RK3588s-Indiedroid-Nova.patch diff --git a/config/kernel/linux-rockchip-rk3588-edge.config b/config/kernel/linux-rockchip-rk3588-edge.config index 61ed71dce..d6de40015 100644 --- a/config/kernel/linux-rockchip-rk3588-edge.config +++ b/config/kernel/linux-rockchip-rk3588-edge.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.4.1 Kernel Configuration +# Linux/arm64 6.5.0-rc1 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 11.3.0-1ubuntu1~22.04) 11.3.0" CONFIG_CC_IS_GCC=y @@ -254,6 +254,7 @@ CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y +CONFIG_CACHESTAT_SYSCALL=y # CONFIG_DEBUG_RSEQ is not set CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y @@ -320,6 +321,7 @@ CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_NXP is not set +# CONFIG_ARCH_MA35 is not set # CONFIG_ARCH_NPCM is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set @@ -327,6 +329,7 @@ CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y CONFIG_ARCH_ROCKCHIP=y # CONFIG_ARCH_SEATTLE is not set # CONFIG_ARCH_INTEL_SOCFPGA is not set +# CONFIG_ARCH_STM32 is not set # CONFIG_ARCH_SYNQUACER is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_SPRD is not set @@ -346,6 +349,7 @@ CONFIG_ARCH_ROCKCHIP=y # # ARM errata workarounds via the alternatives framework # +CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y CONFIG_ARM64_ERRATUM_826319=y CONFIG_ARM64_ERRATUM_827319=y @@ -502,7 +506,6 @@ CONFIG_ARM64_EPAN=y CONFIG_ARM64_SVE=y CONFIG_ARM64_SME=y -CONFIG_ARM64_MODULE_PLTS=y CONFIG_ARM64_PSEUDO_NMI=y # CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set CONFIG_RELOCATABLE=y @@ -599,6 +602,7 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y +# CONFIG_ACPI_CPPC_CPUFREQ is not set CONFIG_ARM_ROCKCHIP_CPUFREQ=y # CONFIG_ARM_SCMI_CPUFREQ is not set # end of CPU Frequency scaling @@ -623,7 +627,6 @@ CONFIG_ACPI_FAN=m CONFIG_ACPI_DOCK=y CONFIG_ACPI_PROCESSOR_IDLE=y CONFIG_ACPI_MCFG=y -CONFIG_ACPI_CPPC_LIB=y CONFIG_ACPI_PROCESSOR=y CONFIG_ACPI_IPMI=m CONFIG_ACPI_HOTPLUG_CPU=y @@ -690,6 +693,8 @@ CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_HAVE_IMA_KEXEC=y CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set @@ -719,6 +724,8 @@ CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_EVENTS_NMI=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y @@ -927,6 +934,7 @@ CONFIG_ZPOOL=y CONFIG_SWAP=y CONFIG_ZSWAP=y CONFIG_ZSWAP_DEFAULT_ON=y +# CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set @@ -947,7 +955,7 @@ CONFIG_ZSMALLOC_CHAIN_SIZE=8 # # SLAB allocator options # -# CONFIG_SLAB is not set +# CONFIG_SLAB_DEPRECATED is not set CONFIG_SLUB=y # CONFIG_SLUB_TINY is not set CONFIG_SLAB_MERGE_DEFAULT=y @@ -2122,6 +2130,7 @@ CONFIG_CXL_PORT=m CONFIG_CXL_SUSPEND=y CONFIG_CXL_REGION=y # CONFIG_CXL_REGION_INVALIDATION_TEST is not set +CONFIG_CXL_PMU=m # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set @@ -3413,6 +3422,7 @@ CONFIG_CAN_8DEV_USB=m CONFIG_CAN_EMS_USB=m CONFIG_CAN_ESD_USB=m CONFIG_CAN_ETAS_ES58X=m +# CONFIG_CAN_F81604 is not set CONFIG_CAN_GS_USB=m CONFIG_CAN_KVASER_USB=m CONFIG_CAN_MCBA_USB=m @@ -3438,6 +3448,7 @@ CONFIG_MDIO_MSCC_MIIM=m # CONFIG_MDIO_OCTEON is not set # CONFIG_MDIO_IPQ4019 is not set CONFIG_MDIO_IPQ8064=m +CONFIG_MDIO_REGMAP=m CONFIG_MDIO_THUNDER=y # @@ -3452,8 +3463,8 @@ CONFIG_MDIO_BUS_MUX_MMIOREG=y # PCS device drivers # CONFIG_PCS_XPCS=y +CONFIG_PCS_LYNX=m CONFIG_PCS_MTK_LYNXI=m -CONFIG_PCS_ALTERA_TSE=m # end of PCS device drivers CONFIG_PPP=m @@ -3464,6 +3475,11 @@ CONFIG_PPP_MPPE=m CONFIG_PPP_MULTILINK=y CONFIG_PPPOATM=m CONFIG_PPPOE=m +# CONFIG_PPPOE_HASH_BITS_1 is not set +# CONFIG_PPPOE_HASH_BITS_2 is not set +CONFIG_PPPOE_HASH_BITS_4=y +# CONFIG_PPPOE_HASH_BITS_8 is not set +CONFIG_PPPOE_HASH_BITS=4 CONFIG_PPTP=m CONFIG_PPPOL2TP=m CONFIG_PPP_ASYNC=m @@ -3811,6 +3827,7 @@ CONFIG_RTW89_CORE=m CONFIG_RTW89_PCI=m CONFIG_RTW89_8852A=m CONFIG_RTW89_8852C=m +# CONFIG_RTW89_8851BE is not set CONFIG_RTW89_8852AE=m # CONFIG_RTW89_8852BE is not set CONFIG_RTW89_8852CE=m @@ -3839,8 +3856,6 @@ CONFIG_WLCORE_SPI=m CONFIG_WLCORE_SDIO=m CONFIG_RTL8723DU=m CONFIG_RTL8723DS=m -CONFIG_RTL8822BU=m -CONFIG_RTL8821CU=m CONFIG_88XXAU=m CONFIG_RTL8192EU=m CONFIG_RTL8189FS=m @@ -3921,6 +3936,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_JOYDEV=m CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_KUNIT_TEST is not set # # Input Device Drivers @@ -4076,7 +4092,6 @@ CONFIG_TOUCHSCREEN_MTOUCH=m CONFIG_TOUCHSCREEN_IMAGIS=m CONFIG_TOUCHSCREEN_IMX6UL_TSC=m CONFIG_TOUCHSCREEN_INEXIO=m -CONFIG_TOUCHSCREEN_MK712=m CONFIG_TOUCHSCREEN_PENMOUNT=m CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_TOUCHSCREEN_TOUCHRIGHT=m @@ -4847,6 +4862,7 @@ CONFIG_SENSORS_MAX197=m CONFIG_SENSORS_MAX31722=m CONFIG_SENSORS_MAX31730=m CONFIG_SENSORS_MAX31760=m +# CONFIG_MAX31827 is not set CONFIG_SENSORS_MAX6620=m CONFIG_SENSORS_MAX6621=m CONFIG_SENSORS_MAX6639=m @@ -5013,6 +5029,7 @@ CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set # CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set CONFIG_THERMAL_GOV_FAIR_SHARE=y CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_THERMAL_GOV_BANG_BANG=y @@ -5046,6 +5063,7 @@ CONFIG_SOFT_WATCHDOG=m CONFIG_GPIO_WATCHDOG=m CONFIG_WDAT_WDT=m # CONFIG_XILINX_WATCHDOG is not set +# CONFIG_XILINX_WINDOW_WATCHDOG is not set # CONFIG_ZIIRAVE_WATCHDOG is not set CONFIG_ARM_SP805_WATCHDOG=y CONFIG_ARM_SBSA_WATCHDOG=y @@ -5110,7 +5128,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_AXP20X_I2C is not set CONFIG_MFD_CROS_EC_DEV=y # CONFIG_MFD_MADERA is not set -# CONFIG_MFD_MAX597X is not set +# CONFIG_MFD_MAX5970 is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_SPI is not set # CONFIG_MFD_DA9052_I2C is not set @@ -5134,6 +5152,7 @@ CONFIG_MFD_CROS_EC_DEV=y # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set # CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77541 is not set # CONFIG_MFD_MAX77620 is not set # CONFIG_MFD_MAX77650 is not set # CONFIG_MFD_MAX77686 is not set @@ -5191,6 +5210,8 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_TPS65910 is not set # CONFIG_MFD_TPS65912_I2C is not set # CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS6594_I2C is not set +# CONFIG_MFD_TPS6594_SPI is not set # CONFIG_TWL4030_CORE is not set # CONFIG_TWL6040_CORE is not set CONFIG_MFD_WL1273_CORE=m @@ -5272,6 +5293,7 @@ CONFIG_REGULATOR_PFUZE100=m CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_SPMI=y # CONFIG_REGULATOR_QCOM_USB_VBUS is not set +# CONFIG_REGULATOR_RAA215300 is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RT4801 is not set @@ -5292,6 +5314,7 @@ CONFIG_REGULATOR_SY8824X=m # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set # CONFIG_REGULATOR_TPS6286X is not set +# CONFIG_REGULATOR_TPS6287X is not set # CONFIG_REGULATOR_TPS65023 is not set # CONFIG_REGULATOR_TPS6507X is not set # CONFIG_REGULATOR_TPS65132 is not set @@ -5497,7 +5520,6 @@ CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y CONFIG_VIDEO_PVRUSB2_DVB=y # CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_STK1160_COMMON=m CONFIG_VIDEO_STK1160=m # @@ -5861,6 +5883,7 @@ CONFIG_VIDEO_MT9V011=m CONFIG_VIDEO_MT9V032=m CONFIG_VIDEO_MT9V111=m # CONFIG_VIDEO_OG01A1B is not set +# CONFIG_VIDEO_OV01A10 is not set CONFIG_VIDEO_OV02A10=m # CONFIG_VIDEO_OV08D10 is not set # CONFIG_VIDEO_OV08X40 is not set @@ -6384,6 +6407,7 @@ CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m CONFIG_DRM_PANEL_SAMSUNG_DB7430=m CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m +# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set @@ -6518,6 +6542,8 @@ CONFIG_FB_SYS_IMAGEBLIT=y # CONFIG_FB_FOREIGN_ENDIAN is not set CONFIG_FB_SYS_FOPS=y CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_SYS_HELPERS=y +CONFIG_FB_SYS_HELPERS_DEFERRED=y CONFIG_FB_BACKLIGHT=m CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y @@ -6656,6 +6682,7 @@ CONFIG_SND_SEQ_MIDI_EVENT=m CONFIG_SND_SEQ_MIDI=m CONFIG_SND_SEQ_MIDI_EMUL=m CONFIG_SND_SEQ_VIRMIDI=m +# CONFIG_SND_SEQ_UMP is not set CONFIG_SND_MPU401_UART=m CONFIG_SND_OPL3_LIB=m CONFIG_SND_OPL3_LIB_SEQ=m @@ -6664,6 +6691,7 @@ CONFIG_SND_AC97_CODEC=m CONFIG_SND_DRIVERS=y CONFIG_SND_DUMMY=m CONFIG_SND_ALOOP=m +# CONFIG_SND_PCMTEST is not set CONFIG_SND_VIRMIDI=m CONFIG_SND_MTPAV=m CONFIG_SND_SERIAL_U16550=m @@ -6787,6 +6815,7 @@ CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m CONFIG_SND_SPI=y CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y CONFIG_SND_USB_UA101=m CONFIG_SND_USB_CAIAQ=m @@ -6841,6 +6870,7 @@ CONFIG_SND_SOC_FSL_RPMSG=m CONFIG_SND_SOC_IMX_AUDMUX=m # end of SoC Audio for Freescale CPUs +# CONFIG_SND_SOC_CHV3_I2S is not set CONFIG_SND_I2S_HI6210_I2S=m CONFIG_SND_SOC_IMG=y CONFIG_SND_SOC_IMG_I2S_IN=m @@ -6909,6 +6939,7 @@ CONFIG_SND_SOC_AW8738=m # CONFIG_SND_SOC_AW88395 is not set CONFIG_SND_SOC_BD28623=m CONFIG_SND_SOC_BT_SCO=m +# CONFIG_SND_SOC_CHV3_CODEC is not set CONFIG_SND_SOC_CROS_EC_CODEC=m CONFIG_SND_SOC_CS35L32=m CONFIG_SND_SOC_CS35L33=m @@ -6974,6 +7005,7 @@ CONFIG_SND_SOC_MAX98520=m CONFIG_SND_SOC_MAX98373=m CONFIG_SND_SOC_MAX98373_I2C=m CONFIG_SND_SOC_MAX98373_SDW=m +# CONFIG_SND_SOC_MAX98388 is not set CONFIG_SND_SOC_MAX98390=m CONFIG_SND_SOC_MAX98396=m CONFIG_SND_SOC_MAX9860=m @@ -7022,6 +7054,7 @@ CONFIG_SND_SOC_RT711_SDW=m CONFIG_SND_SOC_RT711_SDCA_SDW=m # CONFIG_SND_SOC_RT712_SDCA_SDW is not set # CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW is not set +# CONFIG_SND_SOC_RT722_SDCA_SDW is not set CONFIG_SND_SOC_RT715=m CONFIG_SND_SOC_RT715_SDW=m CONFIG_SND_SOC_RT715_SDCA_SDW=m @@ -7042,6 +7075,7 @@ CONFIG_SND_SOC_SSM2518=m CONFIG_SND_SOC_SSM2602=m CONFIG_SND_SOC_SSM2602_SPI=m CONFIG_SND_SOC_SSM2602_I2C=m +# CONFIG_SND_SOC_SSM3515 is not set CONFIG_SND_SOC_SSM4567=m CONFIG_SND_SOC_STA32X=m CONFIG_SND_SOC_STA350=m @@ -7051,6 +7085,7 @@ CONFIG_SND_SOC_TAS2562=m CONFIG_SND_SOC_TAS2764=m CONFIG_SND_SOC_TAS2770=m CONFIG_SND_SOC_TAS2780=m +# CONFIG_SND_SOC_TAS2781_I2C is not set CONFIG_SND_SOC_TAS5086=m CONFIG_SND_SOC_TAS571X=m CONFIG_SND_SOC_TAS5720=m @@ -7109,6 +7144,7 @@ CONFIG_SND_SOC_WM8978=m CONFIG_SND_SOC_WM8985=m CONFIG_SND_SOC_WSA881X=m CONFIG_SND_SOC_WSA883X=m +# CONFIG_SND_SOC_WSA884X is not set CONFIG_SND_SOC_ZL38060=m CONFIG_SND_SOC_MAX9759=m CONFIG_SND_SOC_MT6351=m @@ -7223,6 +7259,7 @@ CONFIG_HID_NINTENDO=m # CONFIG_NINTENDO_FF is not set CONFIG_HID_NTI=m CONFIG_HID_NTRIG=m +# CONFIG_HID_NVIDIA_SHIELD is not set CONFIG_HID_ORTEK=m CONFIG_HID_PANTHERLORD=m CONFIG_PANTHERLORD_FF=y @@ -7274,6 +7311,7 @@ CONFIG_HID_SENSOR_HUB=m CONFIG_HID_SENSOR_CUSTOM_SENSOR=m CONFIG_HID_ALPS=m CONFIG_HID_MCP2221=m +# CONFIG_HID_KUNIT_TEST is not set # end of Special HID drivers # @@ -7591,6 +7629,7 @@ CONFIG_USB_GOKU=m CONFIG_USB_EG20T=m CONFIG_USB_GADGET_XILINX=m CONFIG_USB_MAX3420_UDC=m +# CONFIG_USB_CDNS2_UDC is not set CONFIG_USB_DUMMY_HCD=m # end of USB Peripheral Controller @@ -7698,6 +7737,7 @@ CONFIG_TYPEC_WUSB3801=m CONFIG_TYPEC_MUX_FSA4480=m # CONFIG_TYPEC_MUX_GPIO_SBU is not set CONFIG_TYPEC_MUX_PI3USB30532=m +# CONFIG_TYPEC_MUX_NB7VPQ904M is not set # end of USB Type-C Multiplexer/DeMultiplexer Switch support # @@ -7781,6 +7821,7 @@ CONFIG_LEDS_CLASS_FLASH=m # LED drivers # CONFIG_LEDS_AN30259A=m +# CONFIG_LEDS_AW200XX is not set # CONFIG_LEDS_AW2013 is not set # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set @@ -8066,13 +8107,25 @@ CONFIG_VFIO_CONTAINER=y CONFIG_VFIO_IOMMU_TYPE1=y # CONFIG_VFIO_NOIOMMU is not set CONFIG_VFIO_VIRQFD=y + +# +# VFIO support for PCI devices +# CONFIG_VFIO_PCI_CORE=y CONFIG_VFIO_PCI_MMAP=y CONFIG_VFIO_PCI_INTX=y CONFIG_VFIO_PCI=y CONFIG_MLX5_VFIO_PCI=m # CONFIG_HISI_ACC_VFIO_PCI is not set +# end of VFIO support for PCI devices + +# +# VFIO support for platform devices +# # CONFIG_VFIO_PLATFORM is not set +# CONFIG_VFIO_AMBA is not set +# end of VFIO support for platform devices + CONFIG_VIRT_DRIVERS=y CONFIG_VMGENID=y CONFIG_NITRO_ENCLAVES=m @@ -8946,6 +8999,7 @@ CONFIG_ISL29125=m CONFIG_HID_SENSOR_ALS=m CONFIG_HID_SENSOR_PROX=m CONFIG_JSA1212=m +# CONFIG_ROHM_BU27008 is not set # CONFIG_ROHM_BU27034 is not set CONFIG_RPR0521=m CONFIG_LTR501=m @@ -8955,6 +9009,7 @@ CONFIG_MAX44000=m CONFIG_MAX44009=m CONFIG_NOA1305=m CONFIG_OPT3001=m +# CONFIG_OPT4001 is not set CONFIG_PA12203001=m CONFIG_SI1133=m CONFIG_SI1145=m @@ -9047,6 +9102,7 @@ CONFIG_MCP4018=m # CONFIG_MCP4531 is not set CONFIG_MCP41010=m # CONFIG_TPL0102 is not set +# CONFIG_X9250 is not set # end of Digital potentiometers # @@ -9071,6 +9127,7 @@ CONFIG_ICP10100=m # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set CONFIG_MPL3115=m +# CONFIG_MPRLS0025PA is not set # CONFIG_MS5611 is not set # CONFIG_MS5637 is not set # CONFIG_IIO_ST_PRESS is not set @@ -9747,7 +9804,6 @@ CONFIG_SECURITY_NETWORK=y CONFIG_SECURITY_NETWORK_XFRM=y CONFIG_SECURITY_PATH=y CONFIG_LSM_MMAP_MIN_ADDR=0 -CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y CONFIG_HARDENED_USERCOPY=y CONFIG_FORTIFY_SOURCE=y # CONFIG_STATIC_USERMODEHELPER is not set @@ -9862,6 +9918,7 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SIG2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y @@ -9954,6 +10011,7 @@ CONFIG_CRYPTO_AEGIS128_SIMD=y CONFIG_CRYPTO_CHACHA20POLY1305=m CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GENIV=y CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=m CONFIG_CRYPTO_ESSIV=m @@ -9974,7 +10032,7 @@ CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SHA3=y CONFIG_CRYPTO_SM3=m CONFIG_CRYPTO_SM3_GENERIC=m CONFIG_CRYPTO_STREEBOG=m @@ -10014,6 +10072,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set CONFIG_CRYPTO_KDF800108_CTR=y # end of Random number generation @@ -10228,6 +10287,7 @@ CONFIG_HAS_IOPORT=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y CONFIG_DMA_OPS=y +CONFIG_NEED_SG_DMA_FLAGS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y @@ -10238,6 +10298,7 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_SWIOTLB=y +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y CONFIG_DMA_RESTRICTED_POOL=y CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_COHERENT_POOL=y @@ -10427,8 +10488,11 @@ CONFIG_HAVE_ARCH_KFENCE=y CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 # CONFIG_SOFTLOCKUP_DETECTOR is not set +CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y +# CONFIG_HARDLOCKUP_DETECTOR is not set # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_WQ_WATCHDOG is not set +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set CONFIG_TEST_LOCKUP=m # end of Debug Oops, Lockups and Hangs @@ -10502,6 +10566,7 @@ CONFIG_RCU_TRACE=y CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y @@ -10612,6 +10677,7 @@ CONFIG_TEST_BLACKHOLE_DEV=m # CONFIG_TEST_FIRMWARE is not set # CONFIG_TEST_SYSCTL is not set # CONFIG_BITFIELD_KUNIT is not set +# CONFIG_CHECKSUM_KUNIT is not set # CONFIG_HASH_KUNIT_TEST is not set CONFIG_RESOURCE_KUNIT_TEST=m # CONFIG_SYSCTL_KUNIT_TEST is not set @@ -10628,6 +10694,7 @@ CONFIG_MEMCPY_SLOW_KUNIT_TEST=y # CONFIG_OVERFLOW_KUNIT_TEST is not set # CONFIG_STACKINIT_KUNIT_TEST is not set # CONFIG_FORTIFY_KUNIT_TEST is not set +# CONFIG_STRCAT_KUNIT_TEST is not set # CONFIG_STRSCPY_KUNIT_TEST is not set # CONFIG_SIPHASH_KUNIT_TEST is not set # CONFIG_TEST_UDELAY is not set diff --git a/config/sources/families/rockchip-rk3588.conf b/config/sources/families/rockchip-rk3588.conf index a80e95b35..e75f67d38 100644 --- a/config/sources/families/rockchip-rk3588.conf +++ b/config/sources/families/rockchip-rk3588.conf @@ -33,8 +33,8 @@ case $BRANCH in SKIP_BOOTSPLASH="yes" LINUXFAMILY=rockchip-rk3588 LINUXCONFIG='linux-rockchip-rk3588-'$BRANCH - KERNEL_MAJOR_MINOR="6.4" # Major and minor versions of this kernel. - KERNELBRANCH='branch:linux-6.4.y' + KERNEL_MAJOR_MINOR="6.5" # Major and minor versions of this kernel. + KERNELBRANCH='tag:v6.5-rc1' KERNELPATCHDIR='rockchip-rk3588-edge' ;; diff --git a/patch/kernel/rockchip-rk3588-edge/0010-Introduce-RK806-Support.patch b/patch/kernel/rockchip-rk3588-edge/0010-Introduce-RK806-Support.patch deleted file mode 100644 index 5887515eb..000000000 --- a/patch/kernel/rockchip-rk3588-edge/0010-Introduce-RK806-Support.patch +++ /dev/null @@ -1,4362 +0,0 @@ -From 4c89cdd103083e4af11f3cf144aa6ab5a1f2bc1b Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 12 Jul 2022 14:19:57 +0200 -Subject: [PATCH 01/17] clk: RK808: reduce 'struct rk808' usage - -Reduce usage of 'struct rk808' (driver data of the parent MFD), so -that only the chip variant field is still being accessed directly. -This allows restructuring the MFD driver to support SPI based -PMICs. - -Acked-by: Stephen Boyd -Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B -Tested-by: Vincent Legoll # Pine64 QuartzPro64 -Signed-off-by: Sebastian Reichel ---- - drivers/clk/clk-rk808.c | 34 ++++++++++++++++------------------ - 1 file changed, 16 insertions(+), 18 deletions(-) - -diff --git a/drivers/clk/clk-rk808.c b/drivers/clk/clk-rk808.c -index 32f833d732ed..f7412b137e5e 100644 ---- a/drivers/clk/clk-rk808.c -+++ b/drivers/clk/clk-rk808.c -@@ -12,10 +12,9 @@ - #include - #include - #include --#include - - struct rk808_clkout { -- struct rk808 *rk808; -+ struct regmap *regmap; - struct clk_hw clkout1_hw; - struct clk_hw clkout2_hw; - }; -@@ -31,9 +30,8 @@ static int rk808_clkout2_enable(struct clk_hw *hw, bool enable) - struct rk808_clkout *rk808_clkout = container_of(hw, - struct rk808_clkout, - clkout2_hw); -- struct rk808 *rk808 = rk808_clkout->rk808; - -- return regmap_update_bits(rk808->regmap, RK808_CLK32OUT_REG, -+ return regmap_update_bits(rk808_clkout->regmap, RK808_CLK32OUT_REG, - CLK32KOUT2_EN, enable ? CLK32KOUT2_EN : 0); - } - -@@ -52,10 +50,9 @@ static int rk808_clkout2_is_prepared(struct clk_hw *hw) - struct rk808_clkout *rk808_clkout = container_of(hw, - struct rk808_clkout, - clkout2_hw); -- struct rk808 *rk808 = rk808_clkout->rk808; - uint32_t val; - -- int ret = regmap_read(rk808->regmap, RK808_CLK32OUT_REG, &val); -+ int ret = regmap_read(rk808_clkout->regmap, RK808_CLK32OUT_REG, &val); - - if (ret < 0) - return ret; -@@ -93,9 +90,8 @@ static int rk817_clkout2_enable(struct clk_hw *hw, bool enable) - struct rk808_clkout *rk808_clkout = container_of(hw, - struct rk808_clkout, - clkout2_hw); -- struct rk808 *rk808 = rk808_clkout->rk808; - -- return regmap_update_bits(rk808->regmap, RK817_SYS_CFG(1), -+ return regmap_update_bits(rk808_clkout->regmap, RK817_SYS_CFG(1), - RK817_CLK32KOUT2_EN, - enable ? RK817_CLK32KOUT2_EN : 0); - } -@@ -115,10 +111,9 @@ static int rk817_clkout2_is_prepared(struct clk_hw *hw) - struct rk808_clkout *rk808_clkout = container_of(hw, - struct rk808_clkout, - clkout2_hw); -- struct rk808 *rk808 = rk808_clkout->rk808; - unsigned int val; - -- int ret = regmap_read(rk808->regmap, RK817_SYS_CFG(1), &val); -+ int ret = regmap_read(rk808_clkout->regmap, RK817_SYS_CFG(1), &val); - - if (ret < 0) - return 0; -@@ -153,18 +148,21 @@ static const struct clk_ops *rkpmic_get_ops(long variant) - static int rk808_clkout_probe(struct platform_device *pdev) - { - struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent); -- struct i2c_client *client = rk808->i2c; -- struct device_node *node = client->dev.of_node; -+ struct device *dev = &pdev->dev; - struct clk_init_data init = {}; - struct rk808_clkout *rk808_clkout; - int ret; - -- rk808_clkout = devm_kzalloc(&client->dev, -+ dev->of_node = pdev->dev.parent->of_node; -+ -+ rk808_clkout = devm_kzalloc(dev, - sizeof(*rk808_clkout), GFP_KERNEL); - if (!rk808_clkout) - return -ENOMEM; - -- rk808_clkout->rk808 = rk808; -+ rk808_clkout->regmap = dev_get_regmap(pdev->dev.parent, NULL); -+ if (!rk808_clkout->regmap) -+ return -ENODEV; - - init.parent_names = NULL; - init.num_parents = 0; -@@ -173,10 +171,10 @@ static int rk808_clkout_probe(struct platform_device *pdev) - rk808_clkout->clkout1_hw.init = &init; - - /* optional override of the clockname */ -- of_property_read_string_index(node, "clock-output-names", -+ of_property_read_string_index(dev->of_node, "clock-output-names", - 0, &init.name); - -- ret = devm_clk_hw_register(&client->dev, &rk808_clkout->clkout1_hw); -+ ret = devm_clk_hw_register(dev, &rk808_clkout->clkout1_hw); - if (ret) - return ret; - -@@ -185,10 +183,10 @@ static int rk808_clkout_probe(struct platform_device *pdev) - rk808_clkout->clkout2_hw.init = &init; - - /* optional override of the clockname */ -- of_property_read_string_index(node, "clock-output-names", -+ of_property_read_string_index(dev->of_node, "clock-output-names", - 1, &init.name); - -- ret = devm_clk_hw_register(&client->dev, &rk808_clkout->clkout2_hw); -+ ret = devm_clk_hw_register(dev, &rk808_clkout->clkout2_hw); - if (ret) - return ret; - --- -2.41.0 - - -From 0bd4e344dfa8325b345c0c2ccb3f2e2f4ad21baa Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 28 Jun 2022 18:05:55 +0200 -Subject: [PATCH 02/17] mfd: rk808: convert to device managed resources - -Fully convert the driver to device managed resources. - -Acked-for-MFD-by: Lee Jones -Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B -Tested-by: Vincent Legoll # Pine64 QuartzPro64 -Signed-off-by: Sebastian Reichel ---- - drivers/mfd/rk808.c | 64 ++++++++++++++++----------------------------- - 1 file changed, 22 insertions(+), 42 deletions(-) - -diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c -index 0f22ef61e817..a996a43f9204 100644 ---- a/drivers/mfd/rk808.c -+++ b/drivers/mfd/rk808.c -@@ -548,13 +548,11 @@ static const struct regmap_irq_chip rk818_irq_chip = { - .init_ack_masked = true, - }; - --static struct i2c_client *rk808_i2c_client; -- --static void rk808_pm_power_off(void) -+static int rk808_power_off(struct sys_off_data *data) - { -+ struct rk808 *rk808 = data->cb_data; - int ret; - unsigned int reg, bit; -- struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); - - switch (rk808->variant) { - case RK805_ID: -@@ -575,16 +573,18 @@ static void rk808_pm_power_off(void) - bit = DEV_OFF; - break; - default: -- return; -+ return NOTIFY_DONE; - } - ret = regmap_update_bits(rk808->regmap, reg, bit, bit); - if (ret) -- dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n"); -+ dev_err(&rk808->i2c->dev, "Failed to shutdown device!\n"); -+ -+ return NOTIFY_DONE; - } - --static int rk808_restart_notify(struct notifier_block *this, unsigned long mode, void *cmd) -+static int rk808_restart(struct sys_off_data *data) - { -- struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); -+ struct rk808 *rk808 = data->cb_data; - unsigned int reg, bit; - int ret; - -@@ -600,16 +600,11 @@ static int rk808_restart_notify(struct notifier_block *this, unsigned long mode, - } - ret = regmap_update_bits(rk808->regmap, reg, bit, bit); - if (ret) -- dev_err(&rk808_i2c_client->dev, "Failed to restart device!\n"); -+ dev_err(&rk808->i2c->dev, "Failed to restart device!\n"); - - return NOTIFY_DONE; - } - --static struct notifier_block rk808_restart_handler = { -- .notifier_call = rk808_restart_notify, -- .priority = 192, --}; -- - static void rk8xx_shutdown(struct i2c_client *client) - { - struct rk808 *rk808 = i2c_get_clientdata(client); -@@ -745,9 +740,9 @@ static int rk808_probe(struct i2c_client *client) - return -EINVAL; - } - -- ret = regmap_add_irq_chip(rk808->regmap, client->irq, -- IRQF_ONESHOT, -1, -- rk808->regmap_irq_chip, &rk808->irq_data); -+ ret = devm_regmap_add_irq_chip(&client->dev, rk808->regmap, client->irq, -+ IRQF_ONESHOT, -1, -+ rk808->regmap_irq_chip, &rk808->irq_data); - if (ret) { - dev_err(&client->dev, "Failed to add irq_chip %d\n", ret); - return ret; -@@ -771,17 +766,23 @@ static int rk808_probe(struct i2c_client *client) - regmap_irq_get_domain(rk808->irq_data)); - if (ret) { - dev_err(&client->dev, "failed to add MFD devices %d\n", ret); -- goto err_irq; -+ return ret; - } - - if (of_property_read_bool(np, "rockchip,system-power-controller")) { -- rk808_i2c_client = client; -- pm_power_off = rk808_pm_power_off; -+ ret = devm_register_sys_off_handler(&client->dev, -+ SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH, -+ &rk808_power_off, rk808); -+ if (ret) -+ return dev_err_probe(&client->dev, ret, -+ "failed to register poweroff handler\n"); - - switch (rk808->variant) { - case RK809_ID: - case RK817_ID: -- ret = register_restart_handler(&rk808_restart_handler); -+ ret = devm_register_sys_off_handler(&client->dev, -+ SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH, -+ &rk808_restart, rk808); - if (ret) - dev_warn(&client->dev, "failed to register rst handler, %d\n", ret); - break; -@@ -792,26 +793,6 @@ static int rk808_probe(struct i2c_client *client) - } - - return 0; -- --err_irq: -- regmap_del_irq_chip(client->irq, rk808->irq_data); -- return ret; --} -- --static void rk808_remove(struct i2c_client *client) --{ -- struct rk808 *rk808 = i2c_get_clientdata(client); -- -- regmap_del_irq_chip(client->irq, rk808->irq_data); -- -- /** -- * pm_power_off may points to a function from another module. -- * Check if the pointer is set by us and only then overwrite it. -- */ -- if (pm_power_off == rk808_pm_power_off) -- pm_power_off = NULL; -- -- unregister_restart_handler(&rk808_restart_handler); - } - - static int __maybe_unused rk8xx_suspend(struct device *dev) -@@ -868,7 +849,6 @@ static struct i2c_driver rk808_i2c_driver = { - .pm = &rk8xx_pm_ops, - }, - .probe_new = rk808_probe, -- .remove = rk808_remove, - .shutdown = rk8xx_shutdown, - }; - --- -2.41.0 - - -From f80cd95d149c38e6112ffe0f8723d0f5eabc05ec Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 28 Jun 2022 18:12:06 +0200 -Subject: [PATCH 03/17] mfd: rk808: use dev_err_probe - -Use dev_err_probe instead of dev_err in probe function, -which simplifies code a little bit and prints the error -code. - -Also drop possibly incorrect printing of chip id registers -while touching the error message. - -Acked-for-MFD-by: Lee Jones -Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B -Tested-by: Vincent Legoll # Pine64 QuartzPro64 -Signed-off-by: Sebastian Reichel ---- - drivers/mfd/rk808.c | 48 +++++++++++++++------------------------------ - 1 file changed, 16 insertions(+), 32 deletions(-) - -diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c -index a996a43f9204..f42e09e3a3f5 100644 ---- a/drivers/mfd/rk808.c -+++ b/drivers/mfd/rk808.c -@@ -670,18 +670,12 @@ static int rk808_probe(struct i2c_client *client) - - /* Read chip variant */ - msb = i2c_smbus_read_byte_data(client, pmic_id_msb); -- if (msb < 0) { -- dev_err(&client->dev, "failed to read the chip id at 0x%x\n", -- RK808_ID_MSB); -- return msb; -- } -+ if (msb < 0) -+ return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n"); - - lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb); -- if (lsb < 0) { -- dev_err(&client->dev, "failed to read the chip id at 0x%x\n", -- RK808_ID_LSB); -- return lsb; -- } -+ if (lsb < 0) -+ return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n"); - - rk808->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK; - dev_info(&client->dev, "chip id: 0x%x\n", (unsigned int)rk808->variant); -@@ -730,44 +724,34 @@ static int rk808_probe(struct i2c_client *client) - i2c_set_clientdata(client, rk808); - - rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg); -- if (IS_ERR(rk808->regmap)) { -- dev_err(&client->dev, "regmap initialization failed\n"); -- return PTR_ERR(rk808->regmap); -- } -+ if (IS_ERR(rk808->regmap)) -+ return dev_err_probe(&client->dev, PTR_ERR(rk808->regmap), -+ "regmap initialization failed\n"); - -- if (!client->irq) { -- dev_err(&client->dev, "No interrupt support, no core IRQ\n"); -- return -EINVAL; -- } -+ if (!client->irq) -+ return dev_err_probe(&client->dev, -EINVAL, "No interrupt support, no core IRQ\n"); - - ret = devm_regmap_add_irq_chip(&client->dev, rk808->regmap, client->irq, - IRQF_ONESHOT, -1, - rk808->regmap_irq_chip, &rk808->irq_data); -- if (ret) { -- dev_err(&client->dev, "Failed to add irq_chip %d\n", ret); -- return ret; -- } -+ if (ret) -+ return dev_err_probe(&client->dev, ret, "Failed to add irq_chip\n"); - - for (i = 0; i < nr_pre_init_regs; i++) { - ret = regmap_update_bits(rk808->regmap, - pre_init_reg[i].addr, - pre_init_reg[i].mask, - pre_init_reg[i].value); -- if (ret) { -- dev_err(&client->dev, -- "0x%x write err\n", -- pre_init_reg[i].addr); -- return ret; -- } -+ if (ret) -+ return dev_err_probe(&client->dev, ret, "0x%x write err\n", -+ pre_init_reg[i].addr); - } - - ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE, - cells, nr_cells, NULL, 0, - regmap_irq_get_domain(rk808->irq_data)); -- if (ret) { -- dev_err(&client->dev, "failed to add MFD devices %d\n", ret); -- return ret; -- } -+ if (ret) -+ return dev_err_probe(&client->dev, ret, "failed to add MFD devices\n"); - - if (of_property_read_bool(np, "rockchip,system-power-controller")) { - ret = devm_register_sys_off_handler(&client->dev, --- -2.41.0 - - -From 434f1e394f58e310e9675d0781b7c1fd81be81ec Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 12 Jul 2022 14:17:54 +0200 -Subject: [PATCH 04/17] mfd: rk808: replace 'struct i2c_client' with 'struct - device' - -Put 'struct device' pointer into the MFD platform_data instead -of the 'struct i2c_client' pointer. This simplifies the code -and prepares the MFD for SPI support. - -Acked-for-MFD-by: Lee Jones -Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B -Tested-by: Vincent Legoll # Pine64 QuartzPro64 -Signed-off-by: Sebastian Reichel ---- - drivers/mfd/rk808.c | 6 +++--- - include/linux/mfd/rk808.h | 2 +- - 2 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c -index f42e09e3a3f5..ce52307cbaea 100644 ---- a/drivers/mfd/rk808.c -+++ b/drivers/mfd/rk808.c -@@ -577,7 +577,7 @@ static int rk808_power_off(struct sys_off_data *data) - } - ret = regmap_update_bits(rk808->regmap, reg, bit, bit); - if (ret) -- dev_err(&rk808->i2c->dev, "Failed to shutdown device!\n"); -+ dev_err(rk808->dev, "Failed to shutdown device!\n"); - - return NOTIFY_DONE; - } -@@ -600,7 +600,7 @@ static int rk808_restart(struct sys_off_data *data) - } - ret = regmap_update_bits(rk808->regmap, reg, bit, bit); - if (ret) -- dev_err(&rk808->i2c->dev, "Failed to restart device!\n"); -+ dev_err(rk808->dev, "Failed to restart device!\n"); - - return NOTIFY_DONE; - } -@@ -720,7 +720,7 @@ static int rk808_probe(struct i2c_client *client) - return -EINVAL; - } - -- rk808->i2c = client; -+ rk808->dev = &client->dev; - i2c_set_clientdata(client, rk808); - - rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg); -diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h -index 9af1f3105f80..a89ddd9ba68e 100644 ---- a/include/linux/mfd/rk808.h -+++ b/include/linux/mfd/rk808.h -@@ -787,7 +787,7 @@ enum { - }; - - struct rk808 { -- struct i2c_client *i2c; -+ struct device *dev; - struct regmap_irq_chip_data *irq_data; - struct regmap *regmap; - long variant; --- -2.41.0 - - -From 6bc5b1ab7856d87ec8dcdbf69499e589e62c8ed6 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Wed, 29 Jun 2022 16:56:32 +0200 -Subject: [PATCH 05/17] mfd: rk808: split into core and i2c - -Split rk808 into a core and an i2c part in preparation for -SPI support. - -Acked-for-MFD-by: Lee Jones -Acked-by: Alexandre Belloni # for RTC -Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B -Tested-by: Vincent Legoll # Pine64 QuartzPro64 -Signed-off-by: Sebastian Reichel ---- - drivers/clk/Kconfig | 2 +- - drivers/input/misc/Kconfig | 2 +- - drivers/mfd/Kconfig | 7 +- - drivers/mfd/Makefile | 3 +- - drivers/mfd/{rk808.c => rk8xx-core.c} | 209 +++++--------------------- - drivers/mfd/rk8xx-i2c.c | 200 ++++++++++++++++++++++++ - drivers/pinctrl/Kconfig | 2 +- - drivers/power/supply/Kconfig | 2 +- - drivers/regulator/Kconfig | 2 +- - drivers/rtc/Kconfig | 2 +- - include/linux/mfd/rk808.h | 6 + - sound/soc/codecs/Kconfig | 2 +- - 12 files changed, 256 insertions(+), 183 deletions(-) - rename drivers/mfd/{rk808.c => rk8xx-core.c} (76%) - create mode 100644 drivers/mfd/rk8xx-i2c.c - -diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig -index 016814e15536..c0c8e526a1e9 100644 ---- a/drivers/clk/Kconfig -+++ b/drivers/clk/Kconfig -@@ -82,7 +82,7 @@ config COMMON_CLK_MAX9485 - - config COMMON_CLK_RK808 - tristate "Clock driver for RK805/RK808/RK809/RK817/RK818" -- depends on MFD_RK808 -+ depends on MFD_RK8XX - help - This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock. - These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each. -diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig -index 81a54a59e13c..8a320e6218e3 100644 ---- a/drivers/input/misc/Kconfig -+++ b/drivers/input/misc/Kconfig -@@ -609,7 +609,7 @@ config INPUT_PWM_VIBRA - - config INPUT_RK805_PWRKEY - tristate "Rockchip RK805 PMIC power key support" -- depends on MFD_RK808 -+ depends on MFD_RK8XX - help - Select this option to enable power key driver for RK805. - -diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig -index e90463c4441c..de53e6c701fd 100644 ---- a/drivers/mfd/Kconfig -+++ b/drivers/mfd/Kconfig -@@ -1183,12 +1183,17 @@ config MFD_RC5T583 - Additional drivers must be enabled in order to use the - different functionality of the device. - --config MFD_RK808 -+config MFD_RK8XX -+ bool -+ select MFD_CORE -+ -+config MFD_RK8XX_I2C - tristate "Rockchip RK805/RK808/RK809/RK817/RK818 Power Management Chip" - depends on I2C && OF - select MFD_CORE - select REGMAP_I2C - select REGMAP_IRQ -+ select MFD_RK8XX - help - If you say yes here you get support for the RK805, RK808, RK809, - RK817 and RK818 Power Management chips. -diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile -index 1d2392f06f78..ba373193e999 100644 ---- a/drivers/mfd/Makefile -+++ b/drivers/mfd/Makefile -@@ -214,7 +214,8 @@ obj-$(CONFIG_MFD_PALMAS) += palmas.o - obj-$(CONFIG_MFD_VIPERBOARD) += viperboard.o - obj-$(CONFIG_MFD_NTXEC) += ntxec.o - obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o --obj-$(CONFIG_MFD_RK808) += rk808.o -+obj-$(CONFIG_MFD_RK8XX) += rk8xx-core.o -+obj-$(CONFIG_MFD_RK8XX_I2C) += rk8xx-i2c.o - obj-$(CONFIG_MFD_RN5T618) += rn5t618.o - obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o - obj-$(CONFIG_MFD_SYSCON) += syscon.o -diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk8xx-core.c -similarity index 76% -rename from drivers/mfd/rk808.c -rename to drivers/mfd/rk8xx-core.c -index ce52307cbaea..5c0a5acef34c 100644 ---- a/drivers/mfd/rk808.c -+++ b/drivers/mfd/rk8xx-core.c -@@ -1,18 +1,15 @@ - // SPDX-License-Identifier: GPL-2.0-only - /* -- * MFD core driver for Rockchip RK808/RK818 -+ * MFD core driver for Rockchip RK8XX - * - * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH - * - * Author: Chris Zhong - * Author: Zhang Qing -- * -- * Copyright (C) 2016 PHYTEC Messtechnik GmbH -- * - * Author: Wadim Egorov - */ - --#include - #include - #include - #include -@@ -27,92 +24,6 @@ struct rk808_reg_data { - int value; - }; - --static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg) --{ -- /* -- * Notes: -- * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but -- * we don't use that feature. It's better to cache. -- * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since -- * bits are cleared in case when we shutoff anyway, but better safe. -- */ -- -- switch (reg) { -- case RK808_SECONDS_REG ... RK808_WEEKS_REG: -- case RK808_RTC_STATUS_REG: -- case RK808_VB_MON_REG: -- case RK808_THERMAL_REG: -- case RK808_DCDC_UV_STS_REG: -- case RK808_LDO_UV_STS_REG: -- case RK808_DCDC_PG_REG: -- case RK808_LDO_PG_REG: -- case RK808_DEVCTRL_REG: -- case RK808_INT_STS_REG1: -- case RK808_INT_STS_REG2: -- return true; -- } -- -- return false; --} -- --static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg) --{ -- /* -- * Notes: -- * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but -- * we don't use that feature. It's better to cache. -- */ -- -- switch (reg) { -- case RK817_SECONDS_REG ... RK817_WEEKS_REG: -- case RK817_RTC_STATUS_REG: -- case RK817_CODEC_DTOP_LPT_SRST: -- case RK817_GAS_GAUGE_ADC_CONFIG0 ... RK817_GAS_GAUGE_CUR_ADC_K0: -- case RK817_PMIC_CHRG_STS: -- case RK817_PMIC_CHRG_OUT: -- case RK817_PMIC_CHRG_IN: -- case RK817_INT_STS_REG0: -- case RK817_INT_STS_REG1: -- case RK817_INT_STS_REG2: -- case RK817_SYS_STS: -- return true; -- } -- -- return false; --} -- --static const struct regmap_config rk818_regmap_config = { -- .reg_bits = 8, -- .val_bits = 8, -- .max_register = RK818_USB_CTRL_REG, -- .cache_type = REGCACHE_RBTREE, -- .volatile_reg = rk808_is_volatile_reg, --}; -- --static const struct regmap_config rk805_regmap_config = { -- .reg_bits = 8, -- .val_bits = 8, -- .max_register = RK805_OFF_SOURCE_REG, -- .cache_type = REGCACHE_RBTREE, -- .volatile_reg = rk808_is_volatile_reg, --}; -- --static const struct regmap_config rk808_regmap_config = { -- .reg_bits = 8, -- .val_bits = 8, -- .max_register = RK808_IO_POL_REG, -- .cache_type = REGCACHE_RBTREE, -- .volatile_reg = rk808_is_volatile_reg, --}; -- --static const struct regmap_config rk817_regmap_config = { -- .reg_bits = 8, -- .val_bits = 8, -- .max_register = RK817_GPIO_INT_CFG, -- .cache_type = REGCACHE_NONE, -- .volatile_reg = rk817_is_volatile_reg, --}; -- - static const struct resource rtc_resources[] = { - DEFINE_RES_IRQ(RK808_IRQ_RTC_ALARM), - }; -@@ -605,9 +516,9 @@ static int rk808_restart(struct sys_off_data *data) - return NOTIFY_DONE; - } - --static void rk8xx_shutdown(struct i2c_client *client) -+void rk8xx_shutdown(struct device *dev) - { -- struct rk808 *rk808 = i2c_get_clientdata(client); -+ struct rk808 *rk808 = dev_get_drvdata(dev); - int ret; - - switch (rk808->variant) { -@@ -628,61 +539,31 @@ static void rk8xx_shutdown(struct i2c_client *client) - return; - } - if (ret) -- dev_warn(&client->dev, -+ dev_warn(dev, - "Cannot switch to power down function\n"); - } -+EXPORT_SYMBOL_GPL(rk8xx_shutdown); - --static const struct of_device_id rk808_of_match[] = { -- { .compatible = "rockchip,rk805" }, -- { .compatible = "rockchip,rk808" }, -- { .compatible = "rockchip,rk809" }, -- { .compatible = "rockchip,rk817" }, -- { .compatible = "rockchip,rk818" }, -- { }, --}; --MODULE_DEVICE_TABLE(of, rk808_of_match); -- --static int rk808_probe(struct i2c_client *client) -+int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap) - { -- struct device_node *np = client->dev.of_node; - struct rk808 *rk808; - const struct rk808_reg_data *pre_init_reg; - const struct mfd_cell *cells; - int nr_pre_init_regs; - int nr_cells; -- int msb, lsb; -- unsigned char pmic_id_msb, pmic_id_lsb; - int ret; - int i; - -- rk808 = devm_kzalloc(&client->dev, sizeof(*rk808), GFP_KERNEL); -+ rk808 = devm_kzalloc(dev, sizeof(*rk808), GFP_KERNEL); - if (!rk808) - return -ENOMEM; -- -- if (of_device_is_compatible(np, "rockchip,rk817") || -- of_device_is_compatible(np, "rockchip,rk809")) { -- pmic_id_msb = RK817_ID_MSB; -- pmic_id_lsb = RK817_ID_LSB; -- } else { -- pmic_id_msb = RK808_ID_MSB; -- pmic_id_lsb = RK808_ID_LSB; -- } -- -- /* Read chip variant */ -- msb = i2c_smbus_read_byte_data(client, pmic_id_msb); -- if (msb < 0) -- return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n"); -- -- lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb); -- if (lsb < 0) -- return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n"); -- -- rk808->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK; -- dev_info(&client->dev, "chip id: 0x%x\n", (unsigned int)rk808->variant); -+ rk808->dev = dev; -+ rk808->variant = variant; -+ rk808->regmap = regmap; -+ dev_set_drvdata(dev, rk808); - - switch (rk808->variant) { - case RK805_ID: -- rk808->regmap_cfg = &rk805_regmap_config; - rk808->regmap_irq_chip = &rk805_irq_chip; - pre_init_reg = rk805_pre_init_reg; - nr_pre_init_regs = ARRAY_SIZE(rk805_pre_init_reg); -@@ -690,7 +571,6 @@ static int rk808_probe(struct i2c_client *client) - nr_cells = ARRAY_SIZE(rk805s); - break; - case RK808_ID: -- rk808->regmap_cfg = &rk808_regmap_config; - rk808->regmap_irq_chip = &rk808_irq_chip; - pre_init_reg = rk808_pre_init_reg; - nr_pre_init_regs = ARRAY_SIZE(rk808_pre_init_reg); -@@ -698,7 +578,6 @@ static int rk808_probe(struct i2c_client *client) - nr_cells = ARRAY_SIZE(rk808s); - break; - case RK818_ID: -- rk808->regmap_cfg = &rk818_regmap_config; - rk808->regmap_irq_chip = &rk818_irq_chip; - pre_init_reg = rk818_pre_init_reg; - nr_pre_init_regs = ARRAY_SIZE(rk818_pre_init_reg); -@@ -707,7 +586,6 @@ static int rk808_probe(struct i2c_client *client) - break; - case RK809_ID: - case RK817_ID: -- rk808->regmap_cfg = &rk817_regmap_config; - rk808->regmap_irq_chip = &rk817_irq_chip; - pre_init_reg = rk817_pre_init_reg; - nr_pre_init_regs = ARRAY_SIZE(rk817_pre_init_reg); -@@ -715,27 +593,20 @@ static int rk808_probe(struct i2c_client *client) - nr_cells = ARRAY_SIZE(rk817s); - break; - default: -- dev_err(&client->dev, "Unsupported RK8XX ID %lu\n", -- rk808->variant); -+ dev_err(dev, "Unsupported RK8XX ID %lu\n", rk808->variant); - return -EINVAL; - } - -- rk808->dev = &client->dev; -- i2c_set_clientdata(client, rk808); -- -- rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg); -- if (IS_ERR(rk808->regmap)) -- return dev_err_probe(&client->dev, PTR_ERR(rk808->regmap), -- "regmap initialization failed\n"); -+ dev_info(dev, "chip id: 0x%x\n", (unsigned int)rk808->variant); - -- if (!client->irq) -- return dev_err_probe(&client->dev, -EINVAL, "No interrupt support, no core IRQ\n"); -+ if (!irq) -+ return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n"); - -- ret = devm_regmap_add_irq_chip(&client->dev, rk808->regmap, client->irq, -+ ret = devm_regmap_add_irq_chip(dev, rk808->regmap, irq, - IRQF_ONESHOT, -1, - rk808->regmap_irq_chip, &rk808->irq_data); - if (ret) -- return dev_err_probe(&client->dev, ret, "Failed to add irq_chip\n"); -+ return dev_err_probe(dev, ret, "Failed to add irq_chip\n"); - - for (i = 0; i < nr_pre_init_regs; i++) { - ret = regmap_update_bits(rk808->regmap, -@@ -743,45 +614,46 @@ static int rk808_probe(struct i2c_client *client) - pre_init_reg[i].mask, - pre_init_reg[i].value); - if (ret) -- return dev_err_probe(&client->dev, ret, "0x%x write err\n", -+ return dev_err_probe(dev, ret, "0x%x write err\n", - pre_init_reg[i].addr); - } - -- ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE, -+ ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, - cells, nr_cells, NULL, 0, - regmap_irq_get_domain(rk808->irq_data)); - if (ret) -- return dev_err_probe(&client->dev, ret, "failed to add MFD devices\n"); -+ return dev_err_probe(dev, ret, "failed to add MFD devices\n"); - -- if (of_property_read_bool(np, "rockchip,system-power-controller")) { -- ret = devm_register_sys_off_handler(&client->dev, -+ if (device_property_read_bool(dev, "rockchip,system-power-controller")) { -+ ret = devm_register_sys_off_handler(dev, - SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH, - &rk808_power_off, rk808); - if (ret) -- return dev_err_probe(&client->dev, ret, -+ return dev_err_probe(dev, ret, - "failed to register poweroff handler\n"); - - switch (rk808->variant) { - case RK809_ID: - case RK817_ID: -- ret = devm_register_sys_off_handler(&client->dev, -+ ret = devm_register_sys_off_handler(dev, - SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH, - &rk808_restart, rk808); - if (ret) -- dev_warn(&client->dev, "failed to register rst handler, %d\n", ret); -+ dev_warn(dev, "failed to register rst handler, %d\n", ret); - break; - default: -- dev_dbg(&client->dev, "pmic controlled board reset not supported\n"); -+ dev_dbg(dev, "pmic controlled board reset not supported\n"); - break; - } - } - - return 0; - } -+EXPORT_SYMBOL_GPL(rk8xx_probe); - --static int __maybe_unused rk8xx_suspend(struct device *dev) -+int rk8xx_suspend(struct device *dev) - { -- struct rk808 *rk808 = i2c_get_clientdata(to_i2c_client(dev)); -+ struct rk808 *rk808 = dev_get_drvdata(dev); - int ret = 0; - - switch (rk808->variant) { -@@ -804,10 +676,11 @@ static int __maybe_unused rk8xx_suspend(struct device *dev) - - return ret; - } -+EXPORT_SYMBOL_GPL(rk8xx_suspend); - --static int __maybe_unused rk8xx_resume(struct device *dev) -+int rk8xx_resume(struct device *dev) - { -- struct rk808 *rk808 = i2c_get_clientdata(to_i2c_client(dev)); -+ struct rk808 *rk808 = dev_get_drvdata(dev); - int ret = 0; - - switch (rk808->variant) { -@@ -824,22 +697,10 @@ static int __maybe_unused rk8xx_resume(struct device *dev) - - return ret; - } --static SIMPLE_DEV_PM_OPS(rk8xx_pm_ops, rk8xx_suspend, rk8xx_resume); -- --static struct i2c_driver rk808_i2c_driver = { -- .driver = { -- .name = "rk808", -- .of_match_table = rk808_of_match, -- .pm = &rk8xx_pm_ops, -- }, -- .probe_new = rk808_probe, -- .shutdown = rk8xx_shutdown, --}; -- --module_i2c_driver(rk808_i2c_driver); -+EXPORT_SYMBOL_GPL(rk8xx_resume); - - MODULE_LICENSE("GPL"); - MODULE_AUTHOR("Chris Zhong "); - MODULE_AUTHOR("Zhang Qing "); - MODULE_AUTHOR("Wadim Egorov "); --MODULE_DESCRIPTION("RK808/RK818 PMIC driver"); -+MODULE_DESCRIPTION("RK8xx PMIC core"); -diff --git a/drivers/mfd/rk8xx-i2c.c b/drivers/mfd/rk8xx-i2c.c -new file mode 100644 -index 000000000000..6d121b589fec ---- /dev/null -+++ b/drivers/mfd/rk8xx-i2c.c -@@ -0,0 +1,200 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Rockchip RK808/RK818 Core (I2C) driver -+ * -+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH -+ * -+ * Author: Chris Zhong -+ * Author: Zhang Qing -+ * Author: Wadim Egorov -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg) -+{ -+ /* -+ * Notes: -+ * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but -+ * we don't use that feature. It's better to cache. -+ * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since -+ * bits are cleared in case when we shutoff anyway, but better safe. -+ */ -+ -+ switch (reg) { -+ case RK808_SECONDS_REG ... RK808_WEEKS_REG: -+ case RK808_RTC_STATUS_REG: -+ case RK808_VB_MON_REG: -+ case RK808_THERMAL_REG: -+ case RK808_DCDC_UV_STS_REG: -+ case RK808_LDO_UV_STS_REG: -+ case RK808_DCDC_PG_REG: -+ case RK808_LDO_PG_REG: -+ case RK808_DEVCTRL_REG: -+ case RK808_INT_STS_REG1: -+ case RK808_INT_STS_REG2: -+ return true; -+ } -+ -+ return false; -+} -+ -+static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg) -+{ -+ /* -+ * Notes: -+ * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but -+ * we don't use that feature. It's better to cache. -+ */ -+ -+ switch (reg) { -+ case RK817_SECONDS_REG ... RK817_WEEKS_REG: -+ case RK817_RTC_STATUS_REG: -+ case RK817_CODEC_DTOP_LPT_SRST: -+ case RK817_GAS_GAUGE_ADC_CONFIG0 ... RK817_GAS_GAUGE_CUR_ADC_K0: -+ case RK817_PMIC_CHRG_STS: -+ case RK817_PMIC_CHRG_OUT: -+ case RK817_PMIC_CHRG_IN: -+ case RK817_INT_STS_REG0: -+ case RK817_INT_STS_REG1: -+ case RK817_INT_STS_REG2: -+ case RK817_SYS_STS: -+ return true; -+ } -+ -+ return false; -+} -+ -+ -+static const struct regmap_config rk818_regmap_config = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ .max_register = RK818_USB_CTRL_REG, -+ .cache_type = REGCACHE_RBTREE, -+ .volatile_reg = rk808_is_volatile_reg, -+}; -+ -+static const struct regmap_config rk805_regmap_config = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ .max_register = RK805_OFF_SOURCE_REG, -+ .cache_type = REGCACHE_RBTREE, -+ .volatile_reg = rk808_is_volatile_reg, -+}; -+ -+static const struct regmap_config rk808_regmap_config = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ .max_register = RK808_IO_POL_REG, -+ .cache_type = REGCACHE_RBTREE, -+ .volatile_reg = rk808_is_volatile_reg, -+}; -+ -+static const struct regmap_config rk817_regmap_config = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ .max_register = RK817_GPIO_INT_CFG, -+ .cache_type = REGCACHE_NONE, -+ .volatile_reg = rk817_is_volatile_reg, -+}; -+ -+static int rk8xx_i2c_get_variant(struct i2c_client *client) -+{ -+ u8 pmic_id_msb, pmic_id_lsb; -+ int msb, lsb; -+ -+ if (of_device_is_compatible(client->dev.of_node, "rockchip,rk817") || -+ of_device_is_compatible(client->dev.of_node, "rockchip,rk809")) { -+ pmic_id_msb = RK817_ID_MSB; -+ pmic_id_lsb = RK817_ID_LSB; -+ } else { -+ pmic_id_msb = RK808_ID_MSB; -+ pmic_id_lsb = RK808_ID_LSB; -+ } -+ -+ /* Read chip variant */ -+ msb = i2c_smbus_read_byte_data(client, pmic_id_msb); -+ if (msb < 0) -+ return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n"); -+ -+ lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb); -+ if (lsb < 0) -+ return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n"); -+ -+ return ((msb << 8) | lsb) & RK8XX_ID_MSK; -+} -+ -+static int rk8xx_i2c_probe(struct i2c_client *client) -+{ -+ const struct regmap_config *regmap_cfg; -+ struct regmap *regmap; -+ int variant; -+ -+ variant = rk8xx_i2c_get_variant(client); -+ if (variant < 0) -+ return variant; -+ -+ switch (variant) { -+ case RK805_ID: -+ regmap_cfg = &rk805_regmap_config; -+ break; -+ case RK808_ID: -+ regmap_cfg = &rk808_regmap_config; -+ break; -+ case RK818_ID: -+ regmap_cfg = &rk818_regmap_config; -+ break; -+ case RK809_ID: -+ case RK817_ID: -+ regmap_cfg = &rk817_regmap_config; -+ break; -+ default: -+ return dev_err_probe(&client->dev, -EINVAL, "Unsupported RK8XX ID %x\n", variant); -+ } -+ -+ regmap = devm_regmap_init_i2c(client, regmap_cfg); -+ if (IS_ERR(regmap)) -+ return dev_err_probe(&client->dev, PTR_ERR(regmap), -+ "regmap initialization failed\n"); -+ -+ return rk8xx_probe(&client->dev, variant, client->irq, regmap); -+} -+ -+static void rk8xx_i2c_shutdown(struct i2c_client *client) -+{ -+ rk8xx_shutdown(&client->dev); -+} -+ -+static SIMPLE_DEV_PM_OPS(rk8xx_i2c_pm_ops, rk8xx_suspend, rk8xx_resume); -+ -+static const struct of_device_id rk8xx_i2c_of_match[] = { -+ { .compatible = "rockchip,rk805" }, -+ { .compatible = "rockchip,rk808" }, -+ { .compatible = "rockchip,rk809" }, -+ { .compatible = "rockchip,rk817" }, -+ { .compatible = "rockchip,rk818" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, rk8xx_i2c_of_match); -+ -+static struct i2c_driver rk8xx_i2c_driver = { -+ .driver = { -+ .name = "rk8xx-i2c", -+ .of_match_table = rk8xx_i2c_of_match, -+ .pm = &rk8xx_i2c_pm_ops, -+ }, -+ .probe_new = rk8xx_i2c_probe, -+ .shutdown = rk8xx_i2c_shutdown, -+}; -+module_i2c_driver(rk8xx_i2c_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Chris Zhong "); -+MODULE_AUTHOR("Zhang Qing "); -+MODULE_AUTHOR("Wadim Egorov "); -+MODULE_DESCRIPTION("RK8xx I2C PMIC driver"); -diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig -index 5787c579dcf6..77ff9a641aeb 100644 ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -407,7 +407,7 @@ config PINCTRL_PISTACHIO - - config PINCTRL_RK805 - tristate "Pinctrl and GPIO driver for RK805 PMIC" -- depends on MFD_RK808 -+ depends on MFD_RK8XX - select GPIOLIB - select PINMUX - select GENERIC_PINCONF -diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig -index c78be9f322e6..4a5e8e1d1237 100644 ---- a/drivers/power/supply/Kconfig -+++ b/drivers/power/supply/Kconfig -@@ -706,7 +706,7 @@ config CHARGER_BQ256XX - - config CHARGER_RK817 - tristate "Rockchip RK817 PMIC Battery Charger" -- depends on MFD_RK808 -+ depends on MFD_RK8XX - help - Say Y to include support for Rockchip RK817 Battery Charger. - -diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig -index e5f3613c15fa..f2881fe3e0a7 100644 ---- a/drivers/regulator/Kconfig -+++ b/drivers/regulator/Kconfig -@@ -1056,7 +1056,7 @@ config REGULATOR_RC5T583 - - config REGULATOR_RK808 - tristate "Rockchip RK805/RK808/RK809/RK817/RK818 Power regulators" -- depends on MFD_RK808 -+ depends on MFD_RK8XX - help - Select this option to enable the power regulator of ROCKCHIP - PMIC RK805,RK809&RK817,RK808 and RK818. -diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig -index 753872408615..ffca9a8bb878 100644 ---- a/drivers/rtc/Kconfig -+++ b/drivers/rtc/Kconfig -@@ -395,7 +395,7 @@ config RTC_DRV_NCT3018Y - - config RTC_DRV_RK808 - tristate "Rockchip RK805/RK808/RK809/RK817/RK818 RTC" -- depends on MFD_RK808 -+ depends on MFD_RK8XX - help - If you say yes here you will get support for the - RTC of RK805, RK809 and RK817, RK808 and RK818 PMIC. -diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h -index a89ddd9ba68e..4183427a80fe 100644 ---- a/include/linux/mfd/rk808.h -+++ b/include/linux/mfd/rk808.h -@@ -794,4 +794,10 @@ struct rk808 { - const struct regmap_config *regmap_cfg; - const struct regmap_irq_chip *regmap_irq_chip; - }; -+ -+void rk8xx_shutdown(struct device *dev); -+int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap); -+int rk8xx_suspend(struct device *dev); -+int rk8xx_resume(struct device *dev); -+ - #endif /* __LINUX_REGULATOR_RK808_H */ -diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig -index 8020097d4e4c..0c4c5cbaa809 100644 ---- a/sound/soc/codecs/Kconfig -+++ b/sound/soc/codecs/Kconfig -@@ -1313,7 +1313,7 @@ config SND_SOC_RK3328 - - config SND_SOC_RK817 - tristate "Rockchip RK817 audio CODEC" -- depends on MFD_RK808 || COMPILE_TEST -+ depends on MFD_RK8XX || COMPILE_TEST - - config SND_SOC_RL6231 - tristate --- -2.41.0 - - -From e2c1d7f2ee6ecbeb73c90bdf3f9db7180638b2dc Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 24 Jan 2023 14:25:32 +0100 -Subject: [PATCH 06/17] mfd: rk8xx-i2c: use device_get_match_data - -Simplify the device identification logic by supplying the relevant -information via of_match_data. This also removes the dev_info() -printing the chip version, since that's supplied by the match data -now. - -Due to lack of hardware this change is compile-tested only. - -Acked-for-MFD-by: Lee Jones -Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B -Tested-by: Vincent Legoll # Pine64 QuartzPro64 -Signed-off-by: Sebastian Reichel ---- - drivers/mfd/rk8xx-core.c | 2 - - drivers/mfd/rk8xx-i2c.c | 89 +++++++++++++++++----------------------- - 2 files changed, 37 insertions(+), 54 deletions(-) - -diff --git a/drivers/mfd/rk8xx-core.c b/drivers/mfd/rk8xx-core.c -index 5c0a5acef34c..ddf2052c5190 100644 ---- a/drivers/mfd/rk8xx-core.c -+++ b/drivers/mfd/rk8xx-core.c -@@ -597,8 +597,6 @@ int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap - return -EINVAL; - } - -- dev_info(dev, "chip id: 0x%x\n", (unsigned int)rk808->variant); -- - if (!irq) - return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n"); - -diff --git a/drivers/mfd/rk8xx-i2c.c b/drivers/mfd/rk8xx-i2c.c -index 6d121b589fec..2822bfa8a04a 100644 ---- a/drivers/mfd/rk8xx-i2c.c -+++ b/drivers/mfd/rk8xx-i2c.c -@@ -16,6 +16,11 @@ - #include - #include - -+struct rk8xx_i2c_platform_data { -+ const struct regmap_config *regmap_cfg; -+ int variant; -+}; -+ - static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg) - { - /* -@@ -103,66 +108,46 @@ static const struct regmap_config rk817_regmap_config = { - .volatile_reg = rk817_is_volatile_reg, - }; - --static int rk8xx_i2c_get_variant(struct i2c_client *client) --{ -- u8 pmic_id_msb, pmic_id_lsb; -- int msb, lsb; -- -- if (of_device_is_compatible(client->dev.of_node, "rockchip,rk817") || -- of_device_is_compatible(client->dev.of_node, "rockchip,rk809")) { -- pmic_id_msb = RK817_ID_MSB; -- pmic_id_lsb = RK817_ID_LSB; -- } else { -- pmic_id_msb = RK808_ID_MSB; -- pmic_id_lsb = RK808_ID_LSB; -- } -+static const struct rk8xx_i2c_platform_data rk805_data = { -+ .regmap_cfg = &rk805_regmap_config, -+ .variant = RK805_ID, -+}; -+ -+static const struct rk8xx_i2c_platform_data rk808_data = { -+ .regmap_cfg = &rk808_regmap_config, -+ .variant = RK808_ID, -+}; - -- /* Read chip variant */ -- msb = i2c_smbus_read_byte_data(client, pmic_id_msb); -- if (msb < 0) -- return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n"); -+static const struct rk8xx_i2c_platform_data rk809_data = { -+ .regmap_cfg = &rk817_regmap_config, -+ .variant = RK809_ID, -+}; - -- lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb); -- if (lsb < 0) -- return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n"); -+static const struct rk8xx_i2c_platform_data rk817_data = { -+ .regmap_cfg = &rk817_regmap_config, -+ .variant = RK817_ID, -+}; - -- return ((msb << 8) | lsb) & RK8XX_ID_MSK; --} -+static const struct rk8xx_i2c_platform_data rk818_data = { -+ .regmap_cfg = &rk818_regmap_config, -+ .variant = RK818_ID, -+}; - - static int rk8xx_i2c_probe(struct i2c_client *client) - { -- const struct regmap_config *regmap_cfg; -+ const struct rk8xx_i2c_platform_data *data; - struct regmap *regmap; -- int variant; - -- variant = rk8xx_i2c_get_variant(client); -- if (variant < 0) -- return variant; -- -- switch (variant) { -- case RK805_ID: -- regmap_cfg = &rk805_regmap_config; -- break; -- case RK808_ID: -- regmap_cfg = &rk808_regmap_config; -- break; -- case RK818_ID: -- regmap_cfg = &rk818_regmap_config; -- break; -- case RK809_ID: -- case RK817_ID: -- regmap_cfg = &rk817_regmap_config; -- break; -- default: -- return dev_err_probe(&client->dev, -EINVAL, "Unsupported RK8XX ID %x\n", variant); -- } -+ data = device_get_match_data(&client->dev); -+ if (!data) -+ return -ENODEV; - -- regmap = devm_regmap_init_i2c(client, regmap_cfg); -+ regmap = devm_regmap_init_i2c(client, data->regmap_cfg); - if (IS_ERR(regmap)) - return dev_err_probe(&client->dev, PTR_ERR(regmap), - "regmap initialization failed\n"); - -- return rk8xx_probe(&client->dev, variant, client->irq, regmap); -+ return rk8xx_probe(&client->dev, data->variant, client->irq, regmap); - } - - static void rk8xx_i2c_shutdown(struct i2c_client *client) -@@ -173,11 +158,11 @@ static void rk8xx_i2c_shutdown(struct i2c_client *client) - static SIMPLE_DEV_PM_OPS(rk8xx_i2c_pm_ops, rk8xx_suspend, rk8xx_resume); - - static const struct of_device_id rk8xx_i2c_of_match[] = { -- { .compatible = "rockchip,rk805" }, -- { .compatible = "rockchip,rk808" }, -- { .compatible = "rockchip,rk809" }, -- { .compatible = "rockchip,rk817" }, -- { .compatible = "rockchip,rk818" }, -+ { .compatible = "rockchip,rk805", .data = &rk805_data }, -+ { .compatible = "rockchip,rk808", .data = &rk808_data }, -+ { .compatible = "rockchip,rk809", .data = &rk809_data }, -+ { .compatible = "rockchip,rk817", .data = &rk817_data }, -+ { .compatible = "rockchip,rk818", .data = &rk818_data }, - { }, - }; - MODULE_DEVICE_TABLE(of, rk8xx_i2c_of_match); --- -2.41.0 - - -From e11f727558b8979ff2ec7a5619e4e005bdee13f6 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Fri, 19 Aug 2022 18:19:43 +0200 -Subject: [PATCH 07/17] dt-bindings: mfd: add rk806 binding - -Add DT binding document for Rockchip's RK806 PMIC. - -Reviewed-by: Rob Herring -Signed-off-by: Sebastian Reichel ---- - .../bindings/mfd/rockchip,rk806.yaml | 406 ++++++++++++++++++ - 1 file changed, 406 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml - -diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml -new file mode 100644 -index 000000000000..cf2500f2e9a0 ---- /dev/null -+++ b/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml -@@ -0,0 +1,406 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mfd/rockchip,rk806.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: RK806 Power Management Integrated Circuit -+ -+maintainers: -+ - Sebastian Reichel -+ -+description: -+ Rockchip RK806 series PMIC. This device consists of an spi or -+ i2c controlled MFD that includes multiple switchable regulators. -+ -+properties: -+ compatible: -+ enum: -+ - rockchip,rk806 -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ gpio-controller: true -+ -+ '#gpio-cells': -+ const: 2 -+ -+ vcc1-supply: -+ description: -+ The input supply for dcdc-reg1. -+ -+ vcc2-supply: -+ description: -+ The input supply for dcdc-reg2. -+ -+ vcc3-supply: -+ description: -+ The input supply for dcdc-reg3. -+ -+ vcc4-supply: -+ description: -+ The input supply for dcdc-reg4. -+ -+ vcc5-supply: -+ description: -+ The input supply for dcdc-reg5. -+ -+ vcc6-supply: -+ description: -+ The input supply for dcdc-reg6. -+ -+ vcc7-supply: -+ description: -+ The input supply for dcdc-reg7. -+ -+ vcc8-supply: -+ description: -+ The input supply for dcdc-reg8. -+ -+ vcc9-supply: -+ description: -+ The input supply for dcdc-reg9. -+ -+ vcc10-supply: -+ description: -+ The input supply for dcdc-reg10. -+ -+ vcc11-supply: -+ description: -+ The input supply for pldo-reg1, pldo-reg2 and pldo-reg3. -+ -+ vcc12-supply: -+ description: -+ The input supply for pldo-reg4 and pldo-reg5. -+ -+ vcc13-supply: -+ description: -+ The input supply for nldo-reg1, nldo-reg2 and nldo-reg3. -+ -+ vcc14-supply: -+ description: -+ The input supply for nldo-reg4 and nldo-reg5. -+ -+ vcca-supply: -+ description: -+ The input supply for pldo-reg6. -+ -+ regulators: -+ type: object -+ additionalProperties: false -+ patternProperties: -+ "^(dcdc-reg([1-9]|10)|pldo-reg[1-6]|nldo-reg[1-5])$": -+ type: object -+ $ref: /schemas/regulator/regulator.yaml# -+ unevaluatedProperties: false -+ -+patternProperties: -+ '-pins$': -+ type: object -+ additionalProperties: false -+ $ref: /schemas/pinctrl/pinmux-node.yaml -+ -+ properties: -+ function: -+ enum: [pin_fun0, pin_fun1, pin_fun2, pin_fun3, pin_fun4, pin_fun5] -+ -+ pins: -+ $ref: /schemas/types.yaml#/definitions/string -+ enum: [gpio_pwrctrl1, gpio_pwrctrl2, gpio_pwrctrl3] -+ -+allOf: -+ - $ref: /schemas/spi/spi-peripheral-props.yaml -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ spi { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ reg = <0x0>; -+ -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc5v0_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc5v0_sys>; -+ vcc13-supply = <&vcc5v0_sys>; -+ vcc14-supply = <&vcc_1v1_nldo_s3>; -+ vcca-supply = <&vcc5v0_sys>; -+ -+ regulators { -+ vdd_gpu_s0: dcdc-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_gpu_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_npu_s0: dcdc-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_npu_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_log_s0: dcdc-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_log_s0"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: dcdc-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_vdenc_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu_mem_s0: dcdc-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_gpu_mem_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_npu_mem_s0: dcdc-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_npu_mem_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2000000>; -+ regulator-max-microvolt = <2000000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_2v0_pldo_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vdd_vdenc_mem_s0: dcdc-reg8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_vdenc_mem_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd2_ddr_s3: dcdc-reg9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vdd2_ddr_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v1_nldo_s3: dcdc-reg10 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_1v1_nldo_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1100000>; -+ }; -+ }; -+ -+ avcc_1v8_s0: pldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "avcc_1v8_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd1_1v8_ddr_s3: pldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd1_1v8_ddr_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_1v8_s3: pldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_1v8_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_3v3_s0: pldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_3v3_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vccio_sd_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ master_pldo6_s3: pldo-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "master_pldo6_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_0v75_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd2l_0v9_ddr_s3: nldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-name = "vdd2l_0v9_ddr_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ master_nldo3: nldo-reg3 { -+ regulator-name = "master_nldo3"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ avdd_0v75_s0: nldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "avdd_0v75_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v85_s0: nldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_0v85_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ }; --- -2.41.0 - - -From ece3cf25607136eeba646a67b98407f62e3ca2b6 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Wed, 29 Jun 2022 18:35:59 +0200 -Subject: [PATCH 08/17] mfd: rk8xx: add rk806 support - -Add support for SPI connected rk806, which is used by the RK3588 -evaluation boards. The PMIC is advertised to support I2C and SPI, -but the evaluation boards all use SPI. Thus only SPI support is -added here. - -Acked-for-MFD-by: Lee Jones -Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B -Tested-by: Vincent Legoll # Pine64 QuartzPro64 -Signed-off-by: Sebastian Reichel ---- - drivers/mfd/Kconfig | 14 ++ - drivers/mfd/Makefile | 1 + - drivers/mfd/rk8xx-core.c | 69 ++++++- - drivers/mfd/rk8xx-spi.c | 124 ++++++++++++ - include/linux/mfd/rk808.h | 409 ++++++++++++++++++++++++++++++++++++++ - 5 files changed, 614 insertions(+), 3 deletions(-) - create mode 100644 drivers/mfd/rk8xx-spi.c - -diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig -index de53e6c701fd..d4879cb4e1f6 100644 ---- a/drivers/mfd/Kconfig -+++ b/drivers/mfd/Kconfig -@@ -1201,6 +1201,20 @@ config MFD_RK8XX_I2C - through I2C interface. The device supports multiple sub-devices - including interrupts, RTC, LDO & DCDC regulators, and onkey. - -+config MFD_RK8XX_SPI -+ tristate "Rockchip RK806 Power Management Chip" -+ depends on SPI && OF -+ select MFD_CORE -+ select REGMAP_SPI -+ select REGMAP_IRQ -+ select MFD_RK8XX -+ help -+ If you say yes here you get support for the RK806 Power Management -+ chip. -+ This driver provides common support for accessing the device -+ through an SPI interface. The device supports multiple sub-devices -+ including interrupts, LDO & DCDC regulators, and power on-key. -+ - config MFD_RN5T618 - tristate "Ricoh RN5T567/618 PMIC" - depends on I2C -diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile -index ba373193e999..4e666ef5b7fc 100644 ---- a/drivers/mfd/Makefile -+++ b/drivers/mfd/Makefile -@@ -216,6 +216,7 @@ obj-$(CONFIG_MFD_NTXEC) += ntxec.o - obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o - obj-$(CONFIG_MFD_RK8XX) += rk8xx-core.o - obj-$(CONFIG_MFD_RK8XX_I2C) += rk8xx-i2c.o -+obj-$(CONFIG_MFD_RK8XX_SPI) += rk8xx-spi.o - obj-$(CONFIG_MFD_RN5T618) += rn5t618.o - obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o - obj-$(CONFIG_MFD_SYSCON) += syscon.o -diff --git a/drivers/mfd/rk8xx-core.c b/drivers/mfd/rk8xx-core.c -index ddf2052c5190..e8fc9e2ab1d0 100644 ---- a/drivers/mfd/rk8xx-core.c -+++ b/drivers/mfd/rk8xx-core.c -@@ -37,6 +37,11 @@ static const struct resource rk805_key_resources[] = { - DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL), - }; - -+static struct resource rk806_pwrkey_resources[] = { -+ DEFINE_RES_IRQ(RK806_IRQ_PWRON_FALL), -+ DEFINE_RES_IRQ(RK806_IRQ_PWRON_RISE), -+}; -+ - static const struct resource rk817_pwrkey_resources[] = { - DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE), - DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL), -@@ -64,6 +69,17 @@ static const struct mfd_cell rk805s[] = { - }, - }; - -+static const struct mfd_cell rk806s[] = { -+ { .name = "rk805-pinctrl", .id = PLATFORM_DEVID_AUTO, }, -+ { .name = "rk808-regulator", .id = PLATFORM_DEVID_AUTO, }, -+ { -+ .name = "rk805-pwrkey", -+ .resources = rk806_pwrkey_resources, -+ .num_resources = ARRAY_SIZE(rk806_pwrkey_resources), -+ .id = PLATFORM_DEVID_AUTO, -+ }, -+}; -+ - static const struct mfd_cell rk808s[] = { - { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, }, - { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, }, -@@ -123,6 +139,12 @@ static const struct rk808_reg_data rk805_pre_init_reg[] = { - {RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C}, - }; - -+static const struct rk808_reg_data rk806_pre_init_reg[] = { -+ { RK806_GPIO_INT_CONFIG, RK806_INT_POL_MSK, RK806_INT_POL_L }, -+ { RK806_SYS_CFG3, RK806_SLAVE_RESTART_FUN_MSK, RK806_SLAVE_RESTART_FUN_EN }, -+ { RK806_SYS_OPTION, RK806_SYS_ENB2_2M_MSK, RK806_SYS_ENB2_2M_EN }, -+}; -+ - static const struct rk808_reg_data rk808_pre_init_reg[] = { - { RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_150MA }, - { RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_200MA }, -@@ -273,6 +295,27 @@ static const struct regmap_irq rk805_irqs[] = { - }, - }; - -+static const struct regmap_irq rk806_irqs[] = { -+ /* INT_STS0 IRQs */ -+ REGMAP_IRQ_REG(RK806_IRQ_PWRON_FALL, 0, RK806_INT_STS_PWRON_FALL), -+ REGMAP_IRQ_REG(RK806_IRQ_PWRON_RISE, 0, RK806_INT_STS_PWRON_RISE), -+ REGMAP_IRQ_REG(RK806_IRQ_PWRON, 0, RK806_INT_STS_PWRON), -+ REGMAP_IRQ_REG(RK806_IRQ_PWRON_LP, 0, RK806_INT_STS_PWRON_LP), -+ REGMAP_IRQ_REG(RK806_IRQ_HOTDIE, 0, RK806_INT_STS_HOTDIE), -+ REGMAP_IRQ_REG(RK806_IRQ_VDC_RISE, 0, RK806_INT_STS_VDC_RISE), -+ REGMAP_IRQ_REG(RK806_IRQ_VDC_FALL, 0, RK806_INT_STS_VDC_FALL), -+ REGMAP_IRQ_REG(RK806_IRQ_VB_LO, 0, RK806_INT_STS_VB_LO), -+ /* INT_STS1 IRQs */ -+ REGMAP_IRQ_REG(RK806_IRQ_REV0, 1, RK806_INT_STS_REV0), -+ REGMAP_IRQ_REG(RK806_IRQ_REV1, 1, RK806_INT_STS_REV1), -+ REGMAP_IRQ_REG(RK806_IRQ_REV2, 1, RK806_INT_STS_REV2), -+ REGMAP_IRQ_REG(RK806_IRQ_CRC_ERROR, 1, RK806_INT_STS_CRC_ERROR), -+ REGMAP_IRQ_REG(RK806_IRQ_SLP3_GPIO, 1, RK806_INT_STS_SLP3_GPIO), -+ REGMAP_IRQ_REG(RK806_IRQ_SLP2_GPIO, 1, RK806_INT_STS_SLP2_GPIO), -+ REGMAP_IRQ_REG(RK806_IRQ_SLP1_GPIO, 1, RK806_INT_STS_SLP1_GPIO), -+ REGMAP_IRQ_REG(RK806_IRQ_WDT, 1, RK806_INT_STS_WDT), -+}; -+ - static const struct regmap_irq rk808_irqs[] = { - /* INT_STS */ - [RK808_IRQ_VOUT_LO] = { -@@ -423,6 +466,18 @@ static struct regmap_irq_chip rk805_irq_chip = { - .init_ack_masked = true, - }; - -+static struct regmap_irq_chip rk806_irq_chip = { -+ .name = "rk806", -+ .irqs = rk806_irqs, -+ .num_irqs = ARRAY_SIZE(rk806_irqs), -+ .num_regs = 2, -+ .irq_reg_stride = 2, -+ .mask_base = RK806_INT_MSK0, -+ .status_base = RK806_INT_STS0, -+ .ack_base = RK806_INT_STS0, -+ .init_ack_masked = true, -+}; -+ - static const struct regmap_irq_chip rk808_irq_chip = { - .name = "rk808", - .irqs = rk808_irqs, -@@ -549,6 +604,7 @@ int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap - struct rk808 *rk808; - const struct rk808_reg_data *pre_init_reg; - const struct mfd_cell *cells; -+ int dual_support = 0; - int nr_pre_init_regs; - int nr_cells; - int ret; -@@ -570,6 +626,14 @@ int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap - cells = rk805s; - nr_cells = ARRAY_SIZE(rk805s); - break; -+ case RK806_ID: -+ rk808->regmap_irq_chip = &rk806_irq_chip; -+ pre_init_reg = rk806_pre_init_reg; -+ nr_pre_init_regs = ARRAY_SIZE(rk806_pre_init_reg); -+ cells = rk806s; -+ nr_cells = ARRAY_SIZE(rk806s); -+ dual_support = IRQF_SHARED; -+ break; - case RK808_ID: - rk808->regmap_irq_chip = &rk808_irq_chip; - pre_init_reg = rk808_pre_init_reg; -@@ -601,7 +665,7 @@ int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap - return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n"); - - ret = devm_regmap_add_irq_chip(dev, rk808->regmap, irq, -- IRQF_ONESHOT, -1, -+ IRQF_ONESHOT | dual_support, -1, - rk808->regmap_irq_chip, &rk808->irq_data); - if (ret) - return dev_err_probe(dev, ret, "Failed to add irq_chip\n"); -@@ -616,8 +680,7 @@ int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap - pre_init_reg[i].addr); - } - -- ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, -- cells, nr_cells, NULL, 0, -+ ret = devm_mfd_add_devices(dev, 0, cells, nr_cells, NULL, 0, - regmap_irq_get_domain(rk808->irq_data)); - if (ret) - return dev_err_probe(dev, ret, "failed to add MFD devices\n"); -diff --git a/drivers/mfd/rk8xx-spi.c b/drivers/mfd/rk8xx-spi.c -new file mode 100644 -index 000000000000..fd137f38c2c4 ---- /dev/null -+++ b/drivers/mfd/rk8xx-spi.c -@@ -0,0 +1,124 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip RK806 Core (SPI) driver -+ * -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ * Copyright (c) 2023 Collabora Ltd. -+ * -+ * Author: Xu Shengfei -+ * Author: Sebastian Reichel -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define RK806_ADDR_SIZE 2 -+#define RK806_CMD_WITH_SIZE(CMD, VALUE_BYTES) \ -+ (RK806_CMD_##CMD | RK806_CMD_CRC_DIS | (VALUE_BYTES - 1)) -+ -+static const struct regmap_range rk806_volatile_ranges[] = { -+ regmap_reg_range(RK806_POWER_EN0, RK806_POWER_EN5), -+ regmap_reg_range(RK806_DVS_START_CTRL, RK806_INT_MSK1), -+}; -+ -+static const struct regmap_access_table rk806_volatile_table = { -+ .yes_ranges = rk806_volatile_ranges, -+ .n_yes_ranges = ARRAY_SIZE(rk806_volatile_ranges), -+}; -+ -+static const struct regmap_config rk806_regmap_config_spi = { -+ .reg_bits = 16, -+ .val_bits = 8, -+ .max_register = RK806_BUCK_RSERVE_REG5, -+ .cache_type = REGCACHE_RBTREE, -+ .volatile_table = &rk806_volatile_table, -+}; -+ -+static int rk806_spi_bus_write(void *context, const void *vdata, size_t count) -+{ -+ struct device *dev = context; -+ struct spi_device *spi = to_spi_device(dev); -+ struct spi_transfer xfer[2] = { 0 }; -+ /* data and thus count includes the register address */ -+ size_t val_size = count - RK806_ADDR_SIZE; -+ char cmd; -+ -+ if (val_size < 1 || val_size > (RK806_CMD_LEN_MSK + 1)) -+ return -EINVAL; -+ -+ cmd = RK806_CMD_WITH_SIZE(WRITE, val_size); -+ -+ xfer[0].tx_buf = &cmd; -+ xfer[0].len = sizeof(cmd); -+ xfer[1].tx_buf = vdata; -+ xfer[1].len = count; -+ -+ return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); -+} -+ -+static int rk806_spi_bus_read(void *context, const void *vreg, size_t reg_size, -+ void *val, size_t val_size) -+{ -+ struct device *dev = context; -+ struct spi_device *spi = to_spi_device(dev); -+ char txbuf[3] = { 0 }; -+ -+ if (reg_size != RK806_ADDR_SIZE || -+ val_size < 1 || val_size > (RK806_CMD_LEN_MSK + 1)) -+ return -EINVAL; -+ -+ /* TX buffer contains command byte followed by two address bytes */ -+ txbuf[0] = RK806_CMD_WITH_SIZE(READ, val_size); -+ memcpy(txbuf+1, vreg, reg_size); -+ -+ return spi_write_then_read(spi, txbuf, sizeof(txbuf), val, val_size); -+} -+ -+static const struct regmap_bus rk806_regmap_bus_spi = { -+ .write = rk806_spi_bus_write, -+ .read = rk806_spi_bus_read, -+ .reg_format_endian_default = REGMAP_ENDIAN_LITTLE, -+}; -+ -+static int rk8xx_spi_probe(struct spi_device *spi) -+{ -+ struct regmap *regmap; -+ -+ regmap = devm_regmap_init(&spi->dev, &rk806_regmap_bus_spi, -+ &spi->dev, &rk806_regmap_config_spi); -+ if (IS_ERR(regmap)) -+ return dev_err_probe(&spi->dev, PTR_ERR(regmap), -+ "Failed to init regmap\n"); -+ -+ return rk8xx_probe(&spi->dev, RK806_ID, spi->irq, regmap); -+} -+ -+static const struct of_device_id rk8xx_spi_of_match[] = { -+ { .compatible = "rockchip,rk806", }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, rk8xx_spi_of_match); -+ -+static const struct spi_device_id rk8xx_spi_id_table[] = { -+ { "rk806", 0 }, -+ { } -+}; -+MODULE_DEVICE_TABLE(spi, rk8xx_spi_id_table); -+ -+static struct spi_driver rk8xx_spi_driver = { -+ .driver = { -+ .name = "rk8xx-spi", -+ .of_match_table = rk8xx_spi_of_match, -+ }, -+ .probe = rk8xx_spi_probe, -+ .id_table = rk8xx_spi_id_table, -+}; -+module_spi_driver(rk8xx_spi_driver); -+ -+MODULE_AUTHOR("Xu Shengfei "); -+MODULE_DESCRIPTION("RK8xx SPI PMIC driver"); -+MODULE_LICENSE("GPL"); -diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h -index 4183427a80fe..78e167a92483 100644 ---- a/include/linux/mfd/rk808.h -+++ b/include/linux/mfd/rk808.h -@@ -289,6 +289,414 @@ enum rk805_reg { - #define RK805_INT_ALARM_EN (1 << 3) - #define RK805_INT_TIMER_EN (1 << 2) - -+/* RK806 */ -+#define RK806_POWER_EN0 0x0 -+#define RK806_POWER_EN1 0x1 -+#define RK806_POWER_EN2 0x2 -+#define RK806_POWER_EN3 0x3 -+#define RK806_POWER_EN4 0x4 -+#define RK806_POWER_EN5 0x5 -+#define RK806_POWER_SLP_EN0 0x6 -+#define RK806_POWER_SLP_EN1 0x7 -+#define RK806_POWER_SLP_EN2 0x8 -+#define RK806_POWER_DISCHRG_EN0 0x9 -+#define RK806_POWER_DISCHRG_EN1 0xA -+#define RK806_POWER_DISCHRG_EN2 0xB -+#define RK806_BUCK_FB_CONFIG 0xC -+#define RK806_SLP_LP_CONFIG 0xD -+#define RK806_POWER_FPWM_EN0 0xE -+#define RK806_POWER_FPWM_EN1 0xF -+#define RK806_BUCK1_CONFIG 0x10 -+#define RK806_BUCK2_CONFIG 0x11 -+#define RK806_BUCK3_CONFIG 0x12 -+#define RK806_BUCK4_CONFIG 0x13 -+#define RK806_BUCK5_CONFIG 0x14 -+#define RK806_BUCK6_CONFIG 0x15 -+#define RK806_BUCK7_CONFIG 0x16 -+#define RK806_BUCK8_CONFIG 0x17 -+#define RK806_BUCK9_CONFIG 0x18 -+#define RK806_BUCK10_CONFIG 0x19 -+#define RK806_BUCK1_ON_VSEL 0x1A -+#define RK806_BUCK2_ON_VSEL 0x1B -+#define RK806_BUCK3_ON_VSEL 0x1C -+#define RK806_BUCK4_ON_VSEL 0x1D -+#define RK806_BUCK5_ON_VSEL 0x1E -+#define RK806_BUCK6_ON_VSEL 0x1F -+#define RK806_BUCK7_ON_VSEL 0x20 -+#define RK806_BUCK8_ON_VSEL 0x21 -+#define RK806_BUCK9_ON_VSEL 0x22 -+#define RK806_BUCK10_ON_VSEL 0x23 -+#define RK806_BUCK1_SLP_VSEL 0x24 -+#define RK806_BUCK2_SLP_VSEL 0x25 -+#define RK806_BUCK3_SLP_VSEL 0x26 -+#define RK806_BUCK4_SLP_VSEL 0x27 -+#define RK806_BUCK5_SLP_VSEL 0x28 -+#define RK806_BUCK6_SLP_VSEL 0x29 -+#define RK806_BUCK7_SLP_VSEL 0x2A -+#define RK806_BUCK8_SLP_VSEL 0x2B -+#define RK806_BUCK9_SLP_VSEL 0x2D -+#define RK806_BUCK10_SLP_VSEL 0x2E -+#define RK806_BUCK_DEBUG1 0x30 -+#define RK806_BUCK_DEBUG2 0x31 -+#define RK806_BUCK_DEBUG3 0x32 -+#define RK806_BUCK_DEBUG4 0x33 -+#define RK806_BUCK_DEBUG5 0x34 -+#define RK806_BUCK_DEBUG6 0x35 -+#define RK806_BUCK_DEBUG7 0x36 -+#define RK806_BUCK_DEBUG8 0x37 -+#define RK806_BUCK_DEBUG9 0x38 -+#define RK806_BUCK_DEBUG10 0x39 -+#define RK806_BUCK_DEBUG11 0x3A -+#define RK806_BUCK_DEBUG12 0x3B -+#define RK806_BUCK_DEBUG13 0x3C -+#define RK806_BUCK_DEBUG14 0x3D -+#define RK806_BUCK_DEBUG15 0x3E -+#define RK806_BUCK_DEBUG16 0x3F -+#define RK806_BUCK_DEBUG17 0x40 -+#define RK806_BUCK_DEBUG18 0x41 -+#define RK806_NLDO_IMAX 0x42 -+#define RK806_NLDO1_ON_VSEL 0x43 -+#define RK806_NLDO2_ON_VSEL 0x44 -+#define RK806_NLDO3_ON_VSEL 0x45 -+#define RK806_NLDO4_ON_VSEL 0x46 -+#define RK806_NLDO5_ON_VSEL 0x47 -+#define RK806_NLDO1_SLP_VSEL 0x48 -+#define RK806_NLDO2_SLP_VSEL 0x49 -+#define RK806_NLDO3_SLP_VSEL 0x4A -+#define RK806_NLDO4_SLP_VSEL 0x4B -+#define RK806_NLDO5_SLP_VSEL 0x4C -+#define RK806_PLDO_IMAX 0x4D -+#define RK806_PLDO1_ON_VSEL 0x4E -+#define RK806_PLDO2_ON_VSEL 0x4F -+#define RK806_PLDO3_ON_VSEL 0x50 -+#define RK806_PLDO4_ON_VSEL 0x51 -+#define RK806_PLDO5_ON_VSEL 0x52 -+#define RK806_PLDO6_ON_VSEL 0x53 -+#define RK806_PLDO1_SLP_VSEL 0x54 -+#define RK806_PLDO2_SLP_VSEL 0x55 -+#define RK806_PLDO3_SLP_VSEL 0x56 -+#define RK806_PLDO4_SLP_VSEL 0x57 -+#define RK806_PLDO5_SLP_VSEL 0x58 -+#define RK806_PLDO6_SLP_VSEL 0x59 -+#define RK806_CHIP_NAME 0x5A -+#define RK806_CHIP_VER 0x5B -+#define RK806_OTP_VER 0x5C -+#define RK806_SYS_STS 0x5D -+#define RK806_SYS_CFG0 0x5E -+#define RK806_SYS_CFG1 0x5F -+#define RK806_SYS_OPTION 0x61 -+#define RK806_SLEEP_CONFIG0 0x62 -+#define RK806_SLEEP_CONFIG1 0x63 -+#define RK806_SLEEP_CTR_SEL0 0x64 -+#define RK806_SLEEP_CTR_SEL1 0x65 -+#define RK806_SLEEP_CTR_SEL2 0x66 -+#define RK806_SLEEP_CTR_SEL3 0x67 -+#define RK806_SLEEP_CTR_SEL4 0x68 -+#define RK806_SLEEP_CTR_SEL5 0x69 -+#define RK806_DVS_CTRL_SEL0 0x6A -+#define RK806_DVS_CTRL_SEL1 0x6B -+#define RK806_DVS_CTRL_SEL2 0x6C -+#define RK806_DVS_CTRL_SEL3 0x6D -+#define RK806_DVS_CTRL_SEL4 0x6E -+#define RK806_DVS_CTRL_SEL5 0x6F -+#define RK806_DVS_START_CTRL 0x70 -+#define RK806_SLEEP_GPIO 0x71 -+#define RK806_SYS_CFG3 0x72 -+#define RK806_ON_SOURCE 0x74 -+#define RK806_OFF_SOURCE 0x75 -+#define RK806_PWRON_KEY 0x76 -+#define RK806_INT_STS0 0x77 -+#define RK806_INT_MSK0 0x78 -+#define RK806_INT_STS1 0x79 -+#define RK806_INT_MSK1 0x7A -+#define RK806_GPIO_INT_CONFIG 0x7B -+#define RK806_DATA_REG0 0x7C -+#define RK806_DATA_REG1 0x7D -+#define RK806_DATA_REG2 0x7E -+#define RK806_DATA_REG3 0x7F -+#define RK806_DATA_REG4 0x80 -+#define RK806_DATA_REG5 0x81 -+#define RK806_DATA_REG6 0x82 -+#define RK806_DATA_REG7 0x83 -+#define RK806_DATA_REG8 0x84 -+#define RK806_DATA_REG9 0x85 -+#define RK806_DATA_REG10 0x86 -+#define RK806_DATA_REG11 0x87 -+#define RK806_DATA_REG12 0x88 -+#define RK806_DATA_REG13 0x89 -+#define RK806_DATA_REG14 0x8A -+#define RK806_DATA_REG15 0x8B -+#define RK806_TM_REG 0x8C -+#define RK806_OTP_EN_REG 0x8D -+#define RK806_FUNC_OTP_EN_REG 0x8E -+#define RK806_TEST_REG1 0x8F -+#define RK806_TEST_REG2 0x90 -+#define RK806_TEST_REG3 0x91 -+#define RK806_TEST_REG4 0x92 -+#define RK806_TEST_REG5 0x93 -+#define RK806_BUCK_VSEL_OTP_REG0 0x94 -+#define RK806_BUCK_VSEL_OTP_REG1 0x95 -+#define RK806_BUCK_VSEL_OTP_REG2 0x96 -+#define RK806_BUCK_VSEL_OTP_REG3 0x97 -+#define RK806_BUCK_VSEL_OTP_REG4 0x98 -+#define RK806_BUCK_VSEL_OTP_REG5 0x99 -+#define RK806_BUCK_VSEL_OTP_REG6 0x9A -+#define RK806_BUCK_VSEL_OTP_REG7 0x9B -+#define RK806_BUCK_VSEL_OTP_REG8 0x9C -+#define RK806_BUCK_VSEL_OTP_REG9 0x9D -+#define RK806_NLDO1_VSEL_OTP_REG0 0x9E -+#define RK806_NLDO1_VSEL_OTP_REG1 0x9F -+#define RK806_NLDO1_VSEL_OTP_REG2 0xA0 -+#define RK806_NLDO1_VSEL_OTP_REG3 0xA1 -+#define RK806_NLDO1_VSEL_OTP_REG4 0xA2 -+#define RK806_PLDO_VSEL_OTP_REG0 0xA3 -+#define RK806_PLDO_VSEL_OTP_REG1 0xA4 -+#define RK806_PLDO_VSEL_OTP_REG2 0xA5 -+#define RK806_PLDO_VSEL_OTP_REG3 0xA6 -+#define RK806_PLDO_VSEL_OTP_REG4 0xA7 -+#define RK806_PLDO_VSEL_OTP_REG5 0xA8 -+#define RK806_BUCK_EN_OTP_REG1 0xA9 -+#define RK806_NLDO_EN_OTP_REG1 0xAA -+#define RK806_PLDO_EN_OTP_REG1 0xAB -+#define RK806_BUCK_FB_RES_OTP_REG1 0xAC -+#define RK806_OTP_RESEV_REG0 0xAD -+#define RK806_OTP_RESEV_REG1 0xAE -+#define RK806_OTP_RESEV_REG2 0xAF -+#define RK806_OTP_RESEV_REG3 0xB0 -+#define RK806_OTP_RESEV_REG4 0xB1 -+#define RK806_BUCK_SEQ_REG0 0xB2 -+#define RK806_BUCK_SEQ_REG1 0xB3 -+#define RK806_BUCK_SEQ_REG2 0xB4 -+#define RK806_BUCK_SEQ_REG3 0xB5 -+#define RK806_BUCK_SEQ_REG4 0xB6 -+#define RK806_BUCK_SEQ_REG5 0xB7 -+#define RK806_BUCK_SEQ_REG6 0xB8 -+#define RK806_BUCK_SEQ_REG7 0xB9 -+#define RK806_BUCK_SEQ_REG8 0xBA -+#define RK806_BUCK_SEQ_REG9 0xBB -+#define RK806_BUCK_SEQ_REG10 0xBC -+#define RK806_BUCK_SEQ_REG11 0xBD -+#define RK806_BUCK_SEQ_REG12 0xBE -+#define RK806_BUCK_SEQ_REG13 0xBF -+#define RK806_BUCK_SEQ_REG14 0xC0 -+#define RK806_BUCK_SEQ_REG15 0xC1 -+#define RK806_BUCK_SEQ_REG16 0xC2 -+#define RK806_BUCK_SEQ_REG17 0xC3 -+#define RK806_HK_TRIM_REG1 0xC4 -+#define RK806_HK_TRIM_REG2 0xC5 -+#define RK806_BUCK_REF_TRIM_REG1 0xC6 -+#define RK806_BUCK_REF_TRIM_REG2 0xC7 -+#define RK806_BUCK_REF_TRIM_REG3 0xC8 -+#define RK806_BUCK_REF_TRIM_REG4 0xC9 -+#define RK806_BUCK_REF_TRIM_REG5 0xCA -+#define RK806_BUCK_OSC_TRIM_REG1 0xCB -+#define RK806_BUCK_OSC_TRIM_REG2 0xCC -+#define RK806_BUCK_OSC_TRIM_REG3 0xCD -+#define RK806_BUCK_OSC_TRIM_REG4 0xCE -+#define RK806_BUCK_OSC_TRIM_REG5 0xCF -+#define RK806_BUCK_TRIM_ZCDIOS_REG1 0xD0 -+#define RK806_BUCK_TRIM_ZCDIOS_REG2 0xD1 -+#define RK806_NLDO_TRIM_REG1 0xD2 -+#define RK806_NLDO_TRIM_REG2 0xD3 -+#define RK806_NLDO_TRIM_REG3 0xD4 -+#define RK806_PLDO_TRIM_REG1 0xD5 -+#define RK806_PLDO_TRIM_REG2 0xD6 -+#define RK806_PLDO_TRIM_REG3 0xD7 -+#define RK806_TRIM_ICOMP_REG1 0xD8 -+#define RK806_TRIM_ICOMP_REG2 0xD9 -+#define RK806_EFUSE_CONTROL_REGH 0xDA -+#define RK806_FUSE_PROG_REG 0xDB -+#define RK806_MAIN_FSM_STS_REG 0xDD -+#define RK806_FSM_REG 0xDE -+#define RK806_TOP_RESEV_OFFR 0xEC -+#define RK806_TOP_RESEV_POR 0xED -+#define RK806_BUCK_VRSN_REG1 0xEE -+#define RK806_BUCK_VRSN_REG2 0xEF -+#define RK806_NLDO_RLOAD_SEL_REG1 0xF0 -+#define RK806_PLDO_RLOAD_SEL_REG1 0xF1 -+#define RK806_PLDO_RLOAD_SEL_REG2 0xF2 -+#define RK806_BUCK_CMIN_MX_REG1 0xF3 -+#define RK806_BUCK_CMIN_MX_REG2 0xF4 -+#define RK806_BUCK_FREQ_SET_REG1 0xF5 -+#define RK806_BUCK_FREQ_SET_REG2 0xF6 -+#define RK806_BUCK_RS_MEABS_REG1 0xF7 -+#define RK806_BUCK_RS_MEABS_REG2 0xF8 -+#define RK806_BUCK_RS_ZDLEB_REG1 0xF9 -+#define RK806_BUCK_RS_ZDLEB_REG2 0xFA -+#define RK806_BUCK_RSERVE_REG1 0xFB -+#define RK806_BUCK_RSERVE_REG2 0xFC -+#define RK806_BUCK_RSERVE_REG3 0xFD -+#define RK806_BUCK_RSERVE_REG4 0xFE -+#define RK806_BUCK_RSERVE_REG5 0xFF -+ -+/* INT_STS Register field definitions */ -+#define RK806_INT_STS_PWRON_FALL BIT(0) -+#define RK806_INT_STS_PWRON_RISE BIT(1) -+#define RK806_INT_STS_PWRON BIT(2) -+#define RK806_INT_STS_PWRON_LP BIT(3) -+#define RK806_INT_STS_HOTDIE BIT(4) -+#define RK806_INT_STS_VDC_RISE BIT(5) -+#define RK806_INT_STS_VDC_FALL BIT(6) -+#define RK806_INT_STS_VB_LO BIT(7) -+#define RK806_INT_STS_REV0 BIT(0) -+#define RK806_INT_STS_REV1 BIT(1) -+#define RK806_INT_STS_REV2 BIT(2) -+#define RK806_INT_STS_CRC_ERROR BIT(3) -+#define RK806_INT_STS_SLP3_GPIO BIT(4) -+#define RK806_INT_STS_SLP2_GPIO BIT(5) -+#define RK806_INT_STS_SLP1_GPIO BIT(6) -+#define RK806_INT_STS_WDT BIT(7) -+ -+/* SPI command */ -+#define RK806_CMD_READ 0 -+#define RK806_CMD_WRITE BIT(7) -+#define RK806_CMD_CRC_EN BIT(6) -+#define RK806_CMD_CRC_DIS 0 -+#define RK806_CMD_LEN_MSK 0x0f -+#define RK806_REG_H 0x00 -+ -+#define VERSION_AB 0x01 -+ -+enum rk806_reg_id { -+ RK806_ID_DCDC1 = 0, -+ RK806_ID_DCDC2, -+ RK806_ID_DCDC3, -+ RK806_ID_DCDC4, -+ RK806_ID_DCDC5, -+ RK806_ID_DCDC6, -+ RK806_ID_DCDC7, -+ RK806_ID_DCDC8, -+ RK806_ID_DCDC9, -+ RK806_ID_DCDC10, -+ -+ RK806_ID_NLDO1, -+ RK806_ID_NLDO2, -+ RK806_ID_NLDO3, -+ RK806_ID_NLDO4, -+ RK806_ID_NLDO5, -+ -+ RK806_ID_PLDO1, -+ RK806_ID_PLDO2, -+ RK806_ID_PLDO3, -+ RK806_ID_PLDO4, -+ RK806_ID_PLDO5, -+ RK806_ID_PLDO6, -+ RK806_ID_END, -+}; -+ -+/* Define the RK806 IRQ numbers */ -+enum rk806_irqs { -+ /* INT_STS0 registers */ -+ RK806_IRQ_PWRON_FALL, -+ RK806_IRQ_PWRON_RISE, -+ RK806_IRQ_PWRON, -+ RK806_IRQ_PWRON_LP, -+ RK806_IRQ_HOTDIE, -+ RK806_IRQ_VDC_RISE, -+ RK806_IRQ_VDC_FALL, -+ RK806_IRQ_VB_LO, -+ -+ /* INT_STS0 registers */ -+ RK806_IRQ_REV0, -+ RK806_IRQ_REV1, -+ RK806_IRQ_REV2, -+ RK806_IRQ_CRC_ERROR, -+ RK806_IRQ_SLP3_GPIO, -+ RK806_IRQ_SLP2_GPIO, -+ RK806_IRQ_SLP1_GPIO, -+ RK806_IRQ_WDT, -+}; -+ -+/* VCC1 Low Voltage Threshold */ -+enum rk806_lv_sel { -+ VB_LO_SEL_2800, -+ VB_LO_SEL_2900, -+ VB_LO_SEL_3000, -+ VB_LO_SEL_3100, -+ VB_LO_SEL_3200, -+ VB_LO_SEL_3300, -+ VB_LO_SEL_3400, -+ VB_LO_SEL_3500, -+}; -+ -+/* System Shutdown Voltage Select */ -+enum rk806_uv_sel { -+ VB_UV_SEL_2700, -+ VB_UV_SEL_2800, -+ VB_UV_SEL_2900, -+ VB_UV_SEL_3000, -+ VB_UV_SEL_3100, -+ VB_UV_SEL_3200, -+ VB_UV_SEL_3300, -+ VB_UV_SEL_3400, -+}; -+ -+/* Pin Function */ -+enum rk806_pwrctrl_fun { -+ PWRCTRL_NULL_FUN, -+ PWRCTRL_SLP_FUN, -+ PWRCTRL_POWOFF_FUN, -+ PWRCTRL_RST_FUN, -+ PWRCTRL_DVS_FUN, -+ PWRCTRL_GPIO_FUN, -+}; -+ -+/* Pin Polarity */ -+enum rk806_pin_level { -+ POL_LOW, -+ POL_HIGH, -+}; -+ -+enum rk806_vsel_ctr_sel { -+ CTR_BY_NO_EFFECT, -+ CTR_BY_PWRCTRL1, -+ CTR_BY_PWRCTRL2, -+ CTR_BY_PWRCTRL3, -+}; -+ -+enum rk806_dvs_ctr_sel { -+ CTR_SEL_NO_EFFECT, -+ CTR_SEL_DVS_START1, -+ CTR_SEL_DVS_START2, -+ CTR_SEL_DVS_START3, -+}; -+ -+enum rk806_pin_dr_sel { -+ RK806_PIN_INPUT, -+ RK806_PIN_OUTPUT, -+}; -+ -+#define RK806_INT_POL_MSK BIT(1) -+#define RK806_INT_POL_H BIT(1) -+#define RK806_INT_POL_L 0 -+ -+#define RK806_SLAVE_RESTART_FUN_MSK BIT(1) -+#define RK806_SLAVE_RESTART_FUN_EN BIT(1) -+#define RK806_SLAVE_RESTART_FUN_OFF 0 -+ -+#define RK806_SYS_ENB2_2M_MSK BIT(1) -+#define RK806_SYS_ENB2_2M_EN BIT(1) -+#define RK806_SYS_ENB2_2M_OFF 0 -+ -+enum rk806_int_fun { -+ RK806_INT_ONLY, -+ RK806_INT_ADN_WKUP, -+}; -+ -+enum rk806_dvs_mode { -+ RK806_DVS_NOT_SUPPORT, -+ RK806_DVS_START1, -+ RK806_DVS_START2, -+ RK806_DVS_START3, -+ RK806_DVS_PWRCTRL1, -+ RK806_DVS_PWRCTRL2, -+ RK806_DVS_PWRCTRL3, -+ RK806_DVS_START_PWRCTR1, -+ RK806_DVS_START_PWRCTR2, -+ RK806_DVS_START_PWRCTR3, -+ RK806_DVS_END, -+}; -+ - /* RK808 IRQ Definitions */ - #define RK808_IRQ_VOUT_LO 0 - #define RK808_IRQ_VB_LO 1 -@@ -780,6 +1188,7 @@ enum { - - enum { - RK805_ID = 0x8050, -+ RK806_ID = 0x8060, - RK808_ID = 0x0000, - RK809_ID = 0x8090, - RK817_ID = 0x8170, --- -2.41.0 - - -From 984d12c0aa8c7ccf9757b9dcc6e7cd76c5f368dd Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 4 Jul 2022 18:56:16 +0200 -Subject: [PATCH 09/17] pinctrl: rk805: add rk806 pinctrl support - -Add support for rk806 dvs pinctrl to the existing rk805 -driver. - -This has been implemented using shengfei Xu's rk806 -specific driver from the vendor tree as reference. - -Co-developed-by: shengfei Xu -Signed-off-by: shengfei Xu -Reviewed-by: Linus Walleij -Acked-by: Linus Walleij -Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B -Tested-by: Vincent Legoll # Pine64 QuartzPro64 -Signed-off-by: Sebastian Reichel ---- - drivers/pinctrl/pinctrl-rk805.c | 189 ++++++++++++++++++++++++++++---- - 1 file changed, 168 insertions(+), 21 deletions(-) - -diff --git a/drivers/pinctrl/pinctrl-rk805.c b/drivers/pinctrl/pinctrl-rk805.c -index 7c1f7408fb9a..2639a9ee82cd 100644 ---- a/drivers/pinctrl/pinctrl-rk805.c -+++ b/drivers/pinctrl/pinctrl-rk805.c -@@ -1,10 +1,12 @@ - // SPDX-License-Identifier: GPL-2.0-or-later - /* -- * Pinctrl driver for Rockchip RK805 PMIC -+ * Pinctrl driver for Rockchip RK805/RK806 PMIC - * - * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - * Author: Joseph Chen -+ * Author: Xu Shengfei - * - * Based on the pinctrl-as3722 driver - */ -@@ -44,6 +46,7 @@ struct rk805_pin_group { - - /* - * @reg: gpio setting register; -+ * @fun_reg: functions select register; - * @fun_mask: functions select mask value, when set is gpio; - * @dir_mask: input or output mask value, when set is output, otherwise input; - * @val_mask: gpio set value, when set is level high, otherwise low; -@@ -56,6 +59,7 @@ struct rk805_pin_group { - */ - struct rk805_pin_config { - u8 reg; -+ u8 fun_reg; - u8 fun_msk; - u8 dir_msk; - u8 val_msk; -@@ -80,22 +84,50 @@ enum rk805_pinmux_option { - RK805_PINMUX_GPIO, - }; - -+enum rk806_pinmux_option { -+ RK806_PINMUX_FUN0 = 0, -+ RK806_PINMUX_FUN1, -+ RK806_PINMUX_FUN2, -+ RK806_PINMUX_FUN3, -+ RK806_PINMUX_FUN4, -+ RK806_PINMUX_FUN5, -+}; -+ - enum { - RK805_GPIO0, - RK805_GPIO1, - }; - -+enum { -+ RK806_GPIO_DVS1, -+ RK806_GPIO_DVS2, -+ RK806_GPIO_DVS3 -+}; -+ - static const char *const rk805_gpio_groups[] = { - "gpio0", - "gpio1", - }; - -+static const char *const rk806_gpio_groups[] = { -+ "gpio_pwrctrl1", -+ "gpio_pwrctrl2", -+ "gpio_pwrctrl3", -+}; -+ - /* RK805: 2 output only GPIOs */ - static const struct pinctrl_pin_desc rk805_pins_desc[] = { - PINCTRL_PIN(RK805_GPIO0, "gpio0"), - PINCTRL_PIN(RK805_GPIO1, "gpio1"), - }; - -+/* RK806 */ -+static const struct pinctrl_pin_desc rk806_pins_desc[] = { -+ PINCTRL_PIN(RK806_GPIO_DVS1, "gpio_pwrctrl1"), -+ PINCTRL_PIN(RK806_GPIO_DVS2, "gpio_pwrctrl2"), -+ PINCTRL_PIN(RK806_GPIO_DVS3, "gpio_pwrctrl3"), -+}; -+ - static const struct rk805_pin_function rk805_pin_functions[] = { - { - .name = "gpio", -@@ -105,6 +137,45 @@ static const struct rk805_pin_function rk805_pin_functions[] = { - }, - }; - -+static const struct rk805_pin_function rk806_pin_functions[] = { -+ { -+ .name = "pin_fun0", -+ .groups = rk806_gpio_groups, -+ .ngroups = ARRAY_SIZE(rk806_gpio_groups), -+ .mux_option = RK806_PINMUX_FUN0, -+ }, -+ { -+ .name = "pin_fun1", -+ .groups = rk806_gpio_groups, -+ .ngroups = ARRAY_SIZE(rk806_gpio_groups), -+ .mux_option = RK806_PINMUX_FUN1, -+ }, -+ { -+ .name = "pin_fun2", -+ .groups = rk806_gpio_groups, -+ .ngroups = ARRAY_SIZE(rk806_gpio_groups), -+ .mux_option = RK806_PINMUX_FUN2, -+ }, -+ { -+ .name = "pin_fun3", -+ .groups = rk806_gpio_groups, -+ .ngroups = ARRAY_SIZE(rk806_gpio_groups), -+ .mux_option = RK806_PINMUX_FUN3, -+ }, -+ { -+ .name = "pin_fun4", -+ .groups = rk806_gpio_groups, -+ .ngroups = ARRAY_SIZE(rk806_gpio_groups), -+ .mux_option = RK806_PINMUX_FUN4, -+ }, -+ { -+ .name = "pin_fun5", -+ .groups = rk806_gpio_groups, -+ .ngroups = ARRAY_SIZE(rk806_gpio_groups), -+ .mux_option = RK806_PINMUX_FUN5, -+ }, -+}; -+ - static const struct rk805_pin_group rk805_pin_groups[] = { - { - .name = "gpio0", -@@ -118,6 +189,24 @@ static const struct rk805_pin_group rk805_pin_groups[] = { - }, - }; - -+static const struct rk805_pin_group rk806_pin_groups[] = { -+ { -+ .name = "gpio_pwrctrl1", -+ .pins = { RK806_GPIO_DVS1 }, -+ .npins = 1, -+ }, -+ { -+ .name = "gpio_pwrctrl2", -+ .pins = { RK806_GPIO_DVS2 }, -+ .npins = 1, -+ }, -+ { -+ .name = "gpio_pwrctrl3", -+ .pins = { RK806_GPIO_DVS3 }, -+ .npins = 1, -+ } -+}; -+ - #define RK805_GPIO0_VAL_MSK BIT(0) - #define RK805_GPIO1_VAL_MSK BIT(1) - -@@ -132,6 +221,40 @@ static const struct rk805_pin_config rk805_gpio_cfgs[] = { - }, - }; - -+#define RK806_PWRCTRL1_DR BIT(0) -+#define RK806_PWRCTRL2_DR BIT(1) -+#define RK806_PWRCTRL3_DR BIT(2) -+#define RK806_PWRCTRL1_DATA BIT(4) -+#define RK806_PWRCTRL2_DATA BIT(5) -+#define RK806_PWRCTRL3_DATA BIT(6) -+#define RK806_PWRCTRL1_FUN GENMASK(2, 0) -+#define RK806_PWRCTRL2_FUN GENMASK(6, 4) -+#define RK806_PWRCTRL3_FUN GENMASK(2, 0) -+ -+static struct rk805_pin_config rk806_gpio_cfgs[] = { -+ { -+ .fun_reg = RK806_SLEEP_CONFIG0, -+ .fun_msk = RK806_PWRCTRL1_FUN, -+ .reg = RK806_SLEEP_GPIO, -+ .val_msk = RK806_PWRCTRL1_DATA, -+ .dir_msk = RK806_PWRCTRL1_DR, -+ }, -+ { -+ .fun_reg = RK806_SLEEP_CONFIG0, -+ .fun_msk = RK806_PWRCTRL2_FUN, -+ .reg = RK806_SLEEP_GPIO, -+ .val_msk = RK806_PWRCTRL2_DATA, -+ .dir_msk = RK806_PWRCTRL2_DR, -+ }, -+ { -+ .fun_reg = RK806_SLEEP_CONFIG1, -+ .fun_msk = RK806_PWRCTRL3_FUN, -+ .reg = RK806_SLEEP_GPIO, -+ .val_msk = RK806_PWRCTRL3_DATA, -+ .dir_msk = RK806_PWRCTRL3_DR, -+ } -+}; -+ - /* generic gpio chip */ - static int rk805_gpio_get(struct gpio_chip *chip, unsigned int offset) - { -@@ -289,19 +412,13 @@ static int _rk805_pinctrl_set_mux(struct pinctrl_dev *pctldev, - if (!pci->pin_cfg[offset].fun_msk) - return 0; - -- if (mux == RK805_PINMUX_GPIO) { -- ret = regmap_update_bits(pci->rk808->regmap, -- pci->pin_cfg[offset].reg, -- pci->pin_cfg[offset].fun_msk, -- pci->pin_cfg[offset].fun_msk); -- if (ret) { -- dev_err(pci->dev, "set gpio%d GPIO failed\n", offset); -- return ret; -- } -- } else { -- dev_err(pci->dev, "Couldn't find function mux %d\n", mux); -- return -EINVAL; -- } -+ mux <<= ffs(pci->pin_cfg[offset].fun_msk) - 1; -+ ret = regmap_update_bits(pci->rk808->regmap, -+ pci->pin_cfg[offset].fun_reg, -+ pci->pin_cfg[offset].fun_msk, mux); -+ -+ if (ret) -+ dev_err(pci->dev, "set gpio%d func%d failed\n", offset, mux); - - return 0; - } -@@ -317,6 +434,22 @@ static int rk805_pinctrl_set_mux(struct pinctrl_dev *pctldev, - return _rk805_pinctrl_set_mux(pctldev, offset, mux); - } - -+static int rk805_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, -+ struct pinctrl_gpio_range *range, -+ unsigned int offset) -+{ -+ struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); -+ -+ switch (pci->rk808->variant) { -+ case RK805_ID: -+ return _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO); -+ case RK806_ID: -+ return _rk805_pinctrl_set_mux(pctldev, offset, RK806_PINMUX_FUN5); -+ } -+ -+ return -ENOTSUPP; -+} -+ - static int rk805_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset, bool input) -@@ -324,13 +457,6 @@ static int rk805_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, - struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); - int ret; - -- /* switch to gpio function */ -- ret = _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO); -- if (ret) { -- dev_err(pci->dev, "set gpio%d mux failed\n", offset); -- return ret; -- } -- - /* set direction */ - if (!pci->pin_cfg[offset].dir_msk) - return 0; -@@ -352,6 +478,7 @@ static const struct pinmux_ops rk805_pinmux_ops = { - .get_function_name = rk805_pinctrl_get_func_name, - .get_function_groups = rk805_pinctrl_get_func_groups, - .set_mux = rk805_pinctrl_set_mux, -+ .gpio_request_enable = rk805_pinctrl_gpio_request_enable, - .gpio_set_direction = rk805_pmx_gpio_set_direction, - }; - -@@ -364,6 +491,7 @@ static int rk805_pinconf_get(struct pinctrl_dev *pctldev, - - switch (param) { - case PIN_CONFIG_OUTPUT: -+ case PIN_CONFIG_INPUT_ENABLE: - arg = rk805_gpio_get(&pci->gpio_chip, pin); - break; - default: -@@ -393,6 +521,12 @@ static int rk805_pinconf_set(struct pinctrl_dev *pctldev, - rk805_gpio_set(&pci->gpio_chip, pin, arg); - rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false); - break; -+ case PIN_CONFIG_INPUT_ENABLE: -+ if (pci->rk808->variant != RK805_ID && arg) { -+ rk805_pmx_gpio_set_direction(pctldev, NULL, pin, true); -+ break; -+ } -+ fallthrough; - default: - dev_err(pci->dev, "Properties not supported\n"); - return -ENOTSUPP; -@@ -448,6 +582,18 @@ static int rk805_pinctrl_probe(struct platform_device *pdev) - pci->pin_cfg = rk805_gpio_cfgs; - pci->gpio_chip.ngpio = ARRAY_SIZE(rk805_gpio_cfgs); - break; -+ case RK806_ID: -+ pci->pins = rk806_pins_desc; -+ pci->num_pins = ARRAY_SIZE(rk806_pins_desc); -+ pci->functions = rk806_pin_functions; -+ pci->num_functions = ARRAY_SIZE(rk806_pin_functions); -+ pci->groups = rk806_pin_groups; -+ pci->num_pin_groups = ARRAY_SIZE(rk806_pin_groups); -+ pci->pinctrl_desc.pins = rk806_pins_desc; -+ pci->pinctrl_desc.npins = ARRAY_SIZE(rk806_pins_desc); -+ pci->pin_cfg = rk806_gpio_cfgs; -+ pci->gpio_chip.ngpio = ARRAY_SIZE(rk806_gpio_cfgs); -+ break; - default: - dev_err(&pdev->dev, "unsupported RK805 ID %lu\n", - pci->rk808->variant); -@@ -488,5 +634,6 @@ static struct platform_driver rk805_pinctrl_driver = { - module_platform_driver(rk805_pinctrl_driver); - - MODULE_DESCRIPTION("RK805 pin control and GPIO driver"); -+MODULE_AUTHOR("Xu Shengfei "); - MODULE_AUTHOR("Joseph Chen "); - MODULE_LICENSE("GPL v2"); --- -2.41.0 - - -From ab67c69e1f4bd6286e6aa1e6075c04777c8e5853 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Fri, 9 Sep 2022 18:24:43 +0200 -Subject: [PATCH 10/17] regulator: expose regulator_find_closest_bigger - -Expose and document the table lookup logic used by -regulator_set_ramp_delay_regmap, so that it can be -reused for devices that cannot be configured via -regulator_set_ramp_delay_regmap. - -Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B -Tested-by: Vincent Legoll # Pine64 QuartzPro64 -Signed-off-by: Sebastian Reichel ---- - drivers/regulator/helpers.c | 22 ++++++++++++++++++---- - include/linux/regulator/driver.h | 2 ++ - 2 files changed, 20 insertions(+), 4 deletions(-) - -diff --git a/drivers/regulator/helpers.c b/drivers/regulator/helpers.c -index ad2237a95572..586f42e378ee 100644 ---- a/drivers/regulator/helpers.c -+++ b/drivers/regulator/helpers.c -@@ -902,8 +902,21 @@ bool regulator_is_equal(struct regulator *reg1, struct regulator *reg2) - } - EXPORT_SYMBOL_GPL(regulator_is_equal); - --static int find_closest_bigger(unsigned int target, const unsigned int *table, -- unsigned int num_sel, unsigned int *sel) -+/** -+ * regulator_find_closest_bigger - helper to find offset in ramp delay table -+ * -+ * @target: targeted ramp_delay -+ * @table: table with supported ramp delays -+ * @num_sel: number of entries in the table -+ * @sel: Pointer to store table offset -+ * -+ * This is the internal helper used by regulator_set_ramp_delay_regmap to -+ * map ramp delay to register value. It should only be used directly if -+ * regulator_set_ramp_delay_regmap cannot handle a specific device setup -+ * (e.g. because the value is split over multiple registers). -+ */ -+int regulator_find_closest_bigger(unsigned int target, const unsigned int *table, -+ unsigned int num_sel, unsigned int *sel) - { - unsigned int s, tmp, max, maxsel = 0; - bool found = false; -@@ -933,6 +946,7 @@ static int find_closest_bigger(unsigned int target, const unsigned int *table, - - return 0; - } -+EXPORT_SYMBOL_GPL(regulator_find_closest_bigger); - - /** - * regulator_set_ramp_delay_regmap - set_ramp_delay() helper -@@ -951,8 +965,8 @@ int regulator_set_ramp_delay_regmap(struct regulator_dev *rdev, int ramp_delay) - if (WARN_ON(!rdev->desc->n_ramp_values || !rdev->desc->ramp_delay_table)) - return -EINVAL; - -- ret = find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table, -- rdev->desc->n_ramp_values, &sel); -+ ret = regulator_find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table, -+ rdev->desc->n_ramp_values, &sel); - - if (ret) { - dev_warn(rdev_get_dev(rdev), -diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h -index d3b4a3d4514a..c6ef7d68eb9a 100644 ---- a/include/linux/regulator/driver.h -+++ b/include/linux/regulator/driver.h -@@ -758,6 +758,8 @@ int regulator_set_current_limit_regmap(struct regulator_dev *rdev, - int min_uA, int max_uA); - int regulator_get_current_limit_regmap(struct regulator_dev *rdev); - void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data); -+int regulator_find_closest_bigger(unsigned int target, const unsigned int *table, -+ unsigned int num_sel, unsigned int *sel); - int regulator_set_ramp_delay_regmap(struct regulator_dev *rdev, int ramp_delay); - int regulator_sync_voltage_rdev(struct regulator_dev *rdev); - --- -2.41.0 - - -From 35bb06513ceaee87f043d03cfd76a85f368703e7 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Wed, 3 May 2023 18:38:26 +0200 -Subject: [PATCH 11/17] regulator: rk808: fix asynchronous probing - -If the probe routine fails with -EPROBE_DEFER after taking over the -OF node from its parent driver, reprobing triggers pinctrl_bind_pins() -and that will fail. Fix this by setting of_node_reused, so that the -device does not try to setup pin muxing. - -For me this always happens once the driver is marked to prefer async -probing and never happens without that flag. - -Fixes: 259b93b21a9f ("regulator: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in 4.14") -Signed-off-by: Sebastian Reichel ---- - drivers/regulator/rk808-regulator.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/regulator/rk808-regulator.c b/drivers/regulator/rk808-regulator.c -index 3637e81654a8..80ba782d8923 100644 ---- a/drivers/regulator/rk808-regulator.c -+++ b/drivers/regulator/rk808-regulator.c -@@ -1336,6 +1336,7 @@ static int rk808_regulator_probe(struct platform_device *pdev) - - config.dev = &pdev->dev; - config.dev->of_node = pdev->dev.parent->of_node; -+ config.dev->of_node_reused = true; - config.driver_data = pdata; - config.regmap = regmap; - --- -2.41.0 - - -From c4c269e0c5c1df5a64a738229c42a7307195be51 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Wed, 3 May 2023 19:19:42 +0200 -Subject: [PATCH 12/17] regulator: rk808: cleanup parent device usage - -By overridering the device's of_node a bit earlier we can -get the GPIOs and any other DT properties from our own -device instead of relying on the parent device. - -Signed-off-by: Sebastian Reichel ---- - drivers/regulator/rk808-regulator.c | 13 ++++++------- - 1 file changed, 6 insertions(+), 7 deletions(-) - -diff --git a/drivers/regulator/rk808-regulator.c b/drivers/regulator/rk808-regulator.c -index 80ba782d8923..71a1ca8b917e 100644 ---- a/drivers/regulator/rk808-regulator.c -+++ b/drivers/regulator/rk808-regulator.c -@@ -1245,20 +1245,19 @@ static const struct regulator_desc rk818_reg[] = { - }; - - static int rk808_regulator_dt_parse_pdata(struct device *dev, -- struct device *client_dev, - struct regmap *map, - struct rk808_regulator_data *pdata) - { - struct device_node *np; - int tmp, ret = 0, i; - -- np = of_get_child_by_name(client_dev->of_node, "regulators"); -+ np = of_get_child_by_name(dev->of_node, "regulators"); - if (!np) - return -ENXIO; - - for (i = 0; i < ARRAY_SIZE(pdata->dvs_gpio); i++) { - pdata->dvs_gpio[i] = -- devm_gpiod_get_index_optional(client_dev, "dvs", i, -+ devm_gpiod_get_index_optional(dev, "dvs", i, - GPIOD_OUT_LOW); - if (IS_ERR(pdata->dvs_gpio[i])) { - ret = PTR_ERR(pdata->dvs_gpio[i]); -@@ -1292,6 +1291,9 @@ static int rk808_regulator_probe(struct platform_device *pdev) - struct regmap *regmap; - int ret, i, nregulators; - -+ pdev->dev.of_node = pdev->dev.parent->of_node; -+ pdev->dev.of_node_reused = true; -+ - regmap = dev_get_regmap(pdev->dev.parent, NULL); - if (!regmap) - return -ENODEV; -@@ -1300,8 +1302,7 @@ static int rk808_regulator_probe(struct platform_device *pdev) - if (!pdata) - return -ENOMEM; - -- ret = rk808_regulator_dt_parse_pdata(&pdev->dev, pdev->dev.parent, -- regmap, pdata); -+ ret = rk808_regulator_dt_parse_pdata(&pdev->dev, regmap, pdata); - if (ret < 0) - return ret; - -@@ -1335,8 +1336,6 @@ static int rk808_regulator_probe(struct platform_device *pdev) - } - - config.dev = &pdev->dev; -- config.dev->of_node = pdev->dev.parent->of_node; -- config.dev->of_node_reused = true; - config.driver_data = pdata; - config.regmap = regmap; - --- -2.41.0 - - -From 78e05e407cf16cbe6030872f4e2f4dfb538552d7 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 4 May 2023 16:11:48 +0200 -Subject: [PATCH 13/17] regulator: rk808: revert to synchronous probing - -The rk808 driver registers a bunch of regulator devices in a loop. -If one of the later regulators fails to register (usually because -its input supply is not yet available) everything will be unrolled -(i.e. previously registered regulators will be unregistered). With -asynchronous registration there might already be consumers, though. -We do not have the necessary infrastructure to properly unregister -the consumer device, so this scenario should be avoided. - -First checking all input supplies or disallowing usage of the regulators -until all are registered does not work, since there can be -self-references (e.g. DCDC channels providing the supply of LDOs). - -The only sensible solution I found is registering the regulator devices -asynchronously, so that we do not have to unroll. Since this is a major -rework let's revert back to synchronous probing for now to fix the issue -at hand. - -Signed-off-by: Sebastian Reichel ---- - drivers/regulator/rk808-regulator.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/regulator/rk808-regulator.c b/drivers/regulator/rk808-regulator.c -index 71a1ca8b917e..5f14d6dd4593 100644 ---- a/drivers/regulator/rk808-regulator.c -+++ b/drivers/regulator/rk808-regulator.c -@@ -1355,7 +1355,7 @@ static struct platform_driver rk808_regulator_driver = { - .probe = rk808_regulator_probe, - .driver = { - .name = "rk808-regulator", -- .probe_type = PROBE_PREFER_ASYNCHRONOUS, -+ .probe_type = PROBE_FORCE_SYNCHRONOUS, - }, - }; - --- -2.41.0 - - -From 3cca89c12b88238f62c774a01dbe1d2d78a23193 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 20 Oct 2022 22:08:09 +0200 -Subject: [PATCH 14/17] regulator: rk808: add rk806 support - -Add rk806 support to the existing rk808 regulator -driver. - -This has been implemented using shengfei Xu's rk806 -specific driver from the vendor tree as reference. - -Co-developed-by: shengfei Xu -Signed-off-by: shengfei Xu -Reviewed-by: Matti Vaittinen -Tested-by: Diederik de Haas # Rock64, Quartz64 Model A + B -Tested-by: Vincent Legoll # Pine64 QuartzPro64 -Signed-off-by: Sebastian Reichel ---- - drivers/regulator/rk808-regulator.c | 385 ++++++++++++++++++++++++++++ - 1 file changed, 385 insertions(+) - -diff --git a/drivers/regulator/rk808-regulator.c b/drivers/regulator/rk808-regulator.c -index 5f14d6dd4593..460525ed006c 100644 ---- a/drivers/regulator/rk808-regulator.c -+++ b/drivers/regulator/rk808-regulator.c -@@ -3,9 +3,11 @@ - * Regulator driver for Rockchip RK805/RK808/RK818 - * - * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - * Author: Chris Zhong - * Author: Zhang Qing -+ * Author: Xu Shengfei - * - * Copyright (C) 2016 PHYTEC Messtechnik GmbH - * -@@ -39,6 +41,13 @@ - #define RK818_LDO3_ON_VSEL_MASK 0xf - #define RK818_BOOST_ON_VSEL_MASK 0xe0 - -+#define RK806_DCDC_SLP_REG_OFFSET 0x0A -+#define RK806_NLDO_SLP_REG_OFFSET 0x05 -+#define RK806_PLDO_SLP_REG_OFFSET 0x06 -+ -+#define RK806_BUCK_SEL_CNT 0xff -+#define RK806_LDO_SEL_CNT 0xff -+ - /* Ramp rate definitions for buck1 / buck2 only */ - #define RK808_RAMP_RATE_OFFSET 3 - #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET) -@@ -117,6 +126,34 @@ - RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \ - _vmask, _ereg, _emask, 0, 0, _etime, &rk805_reg_ops) - -+#define RK806_REGULATOR(_name, _supply_name, _id, _ops,\ -+ _n_voltages, _vr, _er, _lr, ctrl_bit,\ -+ _rr, _rm, _rt)\ -+[_id] = {\ -+ .name = _name,\ -+ .supply_name = _supply_name,\ -+ .of_match = of_match_ptr(_name),\ -+ .regulators_node = of_match_ptr("regulators"),\ -+ .id = _id,\ -+ .ops = &_ops,\ -+ .type = REGULATOR_VOLTAGE,\ -+ .n_voltages = _n_voltages,\ -+ .linear_ranges = _lr,\ -+ .n_linear_ranges = ARRAY_SIZE(_lr),\ -+ .vsel_reg = _vr,\ -+ .vsel_mask = 0xff,\ -+ .enable_reg = _er,\ -+ .enable_mask = ENABLE_MASK(ctrl_bit),\ -+ .enable_val = ENABLE_MASK(ctrl_bit),\ -+ .disable_val = DISABLE_VAL(ctrl_bit),\ -+ .of_map_mode = rk8xx_regulator_of_map_mode,\ -+ .ramp_reg = _rr,\ -+ .ramp_mask = _rm,\ -+ .ramp_delay_table = _rt, \ -+ .n_ramp_values = ARRAY_SIZE(_rt), \ -+ .owner = THIS_MODULE,\ -+ } -+ - #define RK8XX_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \ - _vmask, _ereg, _emask, _etime) \ - RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \ -@@ -153,6 +190,17 @@ - RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \ - 0, 0, &rk808_switch_ops) - -+struct rk8xx_register_bit { -+ u8 reg; -+ u8 bit; -+}; -+ -+#define RK8XX_REG_BIT(_reg, _bit) \ -+ { \ -+ .reg = _reg, \ -+ .bit = BIT(_bit), \ -+ } -+ - struct rk808_regulator_data { - struct gpio_desc *dvs_gpio[2]; - }; -@@ -216,6 +264,133 @@ static const unsigned int rk817_buck1_4_ramp_table[] = { - 3000, 6300, 12500, 25000 - }; - -+static int rk806_set_mode_dcdc(struct regulator_dev *rdev, unsigned int mode) -+{ -+ int rid = rdev_get_id(rdev); -+ int ctr_bit, reg; -+ -+ reg = RK806_POWER_FPWM_EN0 + rid / 8; -+ ctr_bit = rid % 8; -+ -+ switch (mode) { -+ case REGULATOR_MODE_FAST: -+ return regmap_update_bits(rdev->regmap, reg, -+ PWM_MODE_MSK << ctr_bit, -+ FPWM_MODE << ctr_bit); -+ case REGULATOR_MODE_NORMAL: -+ return regmap_update_bits(rdev->regmap, reg, -+ PWM_MODE_MSK << ctr_bit, -+ AUTO_PWM_MODE << ctr_bit); -+ default: -+ dev_err(rdev_get_dev(rdev), "mode unsupported: %u\n", mode); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static unsigned int rk806_get_mode_dcdc(struct regulator_dev *rdev) -+{ -+ int rid = rdev_get_id(rdev); -+ int ctr_bit, reg; -+ unsigned int val; -+ int err; -+ -+ reg = RK806_POWER_FPWM_EN0 + rid / 8; -+ ctr_bit = rid % 8; -+ -+ err = regmap_read(rdev->regmap, reg, &val); -+ if (err) -+ return err; -+ -+ if ((val >> ctr_bit) & FPWM_MODE) -+ return REGULATOR_MODE_FAST; -+ else -+ return REGULATOR_MODE_NORMAL; -+} -+ -+static const struct rk8xx_register_bit rk806_dcdc_rate2[] = { -+ RK8XX_REG_BIT(0xEB, 0), -+ RK8XX_REG_BIT(0xEB, 1), -+ RK8XX_REG_BIT(0xEB, 2), -+ RK8XX_REG_BIT(0xEB, 3), -+ RK8XX_REG_BIT(0xEB, 4), -+ RK8XX_REG_BIT(0xEB, 5), -+ RK8XX_REG_BIT(0xEB, 6), -+ RK8XX_REG_BIT(0xEB, 7), -+ RK8XX_REG_BIT(0xEA, 0), -+ RK8XX_REG_BIT(0xEA, 1), -+}; -+ -+static const unsigned int rk806_ramp_delay_table_dcdc[] = { -+ 50000, 25000, 12500, 6250, 3125, 1560, 961, 390 -+}; -+ -+static int rk806_set_ramp_delay_dcdc(struct regulator_dev *rdev, int ramp_delay) -+{ -+ int rid = rdev_get_id(rdev); -+ int regval, ramp_value, ret; -+ -+ ret = regulator_find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table, -+ rdev->desc->n_ramp_values, &ramp_value); -+ if (ret) { -+ dev_warn(rdev_get_dev(rdev), -+ "Can't set ramp-delay %u, setting %u\n", ramp_delay, -+ rdev->desc->ramp_delay_table[ramp_value]); -+ } -+ -+ regval = ramp_value << (ffs(rdev->desc->ramp_mask) - 1); -+ -+ ret = regmap_update_bits(rdev->regmap, rdev->desc->ramp_reg, -+ rdev->desc->ramp_mask, regval); -+ if (ret) -+ return ret; -+ -+ /* -+ * The above is effectively a copy of regulator_set_ramp_delay_regmap(), -+ * but that only stores the lower 2 bits for rk806 DCDC ramp. The MSB must -+ * be stored in a separate register, so this open codes the implementation -+ * to have access to the ramp_value. -+ */ -+ -+ regval = (ramp_value >> 2) & 0x1 ? rk806_dcdc_rate2[rid].bit : 0; -+ return regmap_update_bits(rdev->regmap, rk806_dcdc_rate2[rid].reg, -+ rk806_dcdc_rate2[rid].bit, -+ regval); -+} -+ -+static const unsigned int rk806_ramp_delay_table_ldo[] = { -+ 100000, 50000, 25000, 12500, 6280, 3120, 1900, 780 -+}; -+ -+static int rk806_set_suspend_voltage_range(struct regulator_dev *rdev, int reg_offset, int uv) -+{ -+ int sel = regulator_map_voltage_linear_range(rdev, uv, uv); -+ unsigned int reg; -+ -+ if (sel < 0) -+ return -EINVAL; -+ -+ reg = rdev->desc->vsel_reg + reg_offset; -+ -+ return regmap_update_bits(rdev->regmap, reg, rdev->desc->vsel_mask, sel); -+} -+ -+static int rk806_set_suspend_voltage_range_dcdc(struct regulator_dev *rdev, int uv) -+{ -+ return rk806_set_suspend_voltage_range(rdev, RK806_DCDC_SLP_REG_OFFSET, uv); -+} -+ -+static int rk806_set_suspend_voltage_range_nldo(struct regulator_dev *rdev, int uv) -+{ -+ return rk806_set_suspend_voltage_range(rdev, RK806_NLDO_SLP_REG_OFFSET, uv); -+} -+ -+static int rk806_set_suspend_voltage_range_pldo(struct regulator_dev *rdev, int uv) -+{ -+ return rk806_set_suspend_voltage_range(rdev, RK806_PLDO_SLP_REG_OFFSET, uv); -+} -+ - static int rk808_buck1_2_get_voltage_sel_regmap(struct regulator_dev *rdev) - { - struct rk808_regulator_data *pdata = rdev_get_drvdata(rdev); -@@ -393,6 +568,47 @@ static int rk805_set_suspend_disable(struct regulator_dev *rdev) - 0); - } - -+static const struct rk8xx_register_bit rk806_suspend_bits[] = { -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 0), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 1), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 2), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 3), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 4), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 5), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 6), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 7), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 6), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 7), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 0), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 1), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 2), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 3), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 4), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 1), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 2), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 3), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 4), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 5), -+ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 0), -+}; -+ -+static int rk806_set_suspend_enable(struct regulator_dev *rdev) -+{ -+ int rid = rdev_get_id(rdev); -+ -+ return regmap_update_bits(rdev->regmap, rk806_suspend_bits[rid].reg, -+ rk806_suspend_bits[rid].bit, -+ rk806_suspend_bits[rid].bit); -+} -+ -+static int rk806_set_suspend_disable(struct regulator_dev *rdev) -+{ -+ int rid = rdev_get_id(rdev); -+ -+ return regmap_update_bits(rdev->regmap, rk806_suspend_bits[rid].reg, -+ rk806_suspend_bits[rid].bit, 0); -+} -+ - static int rk808_set_suspend_enable(struct regulator_dev *rdev) - { - unsigned int reg; -@@ -561,6 +777,64 @@ static const struct regulator_ops rk805_switch_ops = { - .set_suspend_disable = rk805_set_suspend_disable, - }; - -+static const struct regulator_ops rk806_ops_dcdc = { -+ .list_voltage = regulator_list_voltage_linear_range, -+ .map_voltage = regulator_map_voltage_linear_range, -+ .get_voltage_sel = regulator_get_voltage_sel_regmap, -+ .set_voltage_sel = regulator_set_voltage_sel_regmap, -+ .set_voltage_time_sel = regulator_set_voltage_time_sel, -+ .set_mode = rk806_set_mode_dcdc, -+ .get_mode = rk806_get_mode_dcdc, -+ -+ .enable = regulator_enable_regmap, -+ .disable = regulator_disable_regmap, -+ .is_enabled = rk8xx_is_enabled_wmsk_regmap, -+ -+ .set_suspend_mode = rk806_set_mode_dcdc, -+ .set_ramp_delay = rk806_set_ramp_delay_dcdc, -+ -+ .set_suspend_voltage = rk806_set_suspend_voltage_range_dcdc, -+ .set_suspend_enable = rk806_set_suspend_enable, -+ .set_suspend_disable = rk806_set_suspend_disable, -+}; -+ -+static const struct regulator_ops rk806_ops_nldo = { -+ .list_voltage = regulator_list_voltage_linear_range, -+ .map_voltage = regulator_map_voltage_linear_range, -+ .get_voltage_sel = regulator_get_voltage_sel_regmap, -+ .set_voltage_sel = regulator_set_voltage_sel_regmap, -+ .set_voltage_time_sel = regulator_set_voltage_time_sel, -+ -+ .enable = regulator_enable_regmap, -+ .disable = regulator_disable_regmap, -+ .is_enabled = regulator_is_enabled_regmap, -+ -+ .set_ramp_delay = regulator_set_ramp_delay_regmap, -+ -+ .set_suspend_voltage = rk806_set_suspend_voltage_range_nldo, -+ .set_suspend_enable = rk806_set_suspend_enable, -+ .set_suspend_disable = rk806_set_suspend_disable, -+}; -+ -+static const struct regulator_ops rk806_ops_pldo = { -+ .list_voltage = regulator_list_voltage_linear_range, -+ .map_voltage = regulator_map_voltage_linear_range, -+ -+ .get_voltage_sel = regulator_get_voltage_sel_regmap, -+ .set_voltage_sel = regulator_set_voltage_sel_regmap, -+ .set_voltage_time_sel = regulator_set_voltage_time_sel, -+ -+ .enable = regulator_enable_regmap, -+ .disable = regulator_disable_regmap, -+ .is_enabled = regulator_is_enabled_regmap, -+ -+ .set_ramp_delay = regulator_set_ramp_delay_regmap, -+ -+ .set_suspend_voltage = rk806_set_suspend_voltage_range_pldo, -+ .set_suspend_enable = rk806_set_suspend_enable, -+ .set_suspend_disable = rk806_set_suspend_disable, -+}; -+ - static const struct regulator_ops rk808_buck1_2_ops = { - .list_voltage = regulator_list_voltage_linear, - .map_voltage = regulator_map_voltage_linear, -@@ -743,6 +1017,112 @@ static const struct regulator_desc rk805_reg[] = { - BIT(2), 400), - }; - -+static const struct linear_range rk806_buck_voltage_ranges[] = { -+ REGULATOR_LINEAR_RANGE(500000, 0, 160, 6250), /* 500mV ~ 1500mV */ -+ REGULATOR_LINEAR_RANGE(1500000, 161, 237, 25000), /* 1500mV ~ 3400mV */ -+ REGULATOR_LINEAR_RANGE(3400000, 238, 255, 0), -+}; -+ -+static const struct linear_range rk806_ldo_voltage_ranges[] = { -+ REGULATOR_LINEAR_RANGE(500000, 0, 232, 12500), /* 500mV ~ 3400mV */ -+ REGULATOR_LINEAR_RANGE(3400000, 233, 255, 0), /* 500mV ~ 3400mV */ -+}; -+ -+static const struct regulator_desc rk806_reg[] = { -+ RK806_REGULATOR("dcdc-reg1", "vcc1", RK806_ID_DCDC1, rk806_ops_dcdc, -+ RK806_BUCK_SEL_CNT, RK806_BUCK1_ON_VSEL, -+ RK806_POWER_EN0, rk806_buck_voltage_ranges, 0, -+ RK806_BUCK1_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), -+ RK806_REGULATOR("dcdc-reg2", "vcc2", RK806_ID_DCDC2, rk806_ops_dcdc, -+ RK806_BUCK_SEL_CNT, RK806_BUCK2_ON_VSEL, -+ RK806_POWER_EN0, rk806_buck_voltage_ranges, 1, -+ RK806_BUCK2_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), -+ RK806_REGULATOR("dcdc-reg3", "vcc3", RK806_ID_DCDC3, rk806_ops_dcdc, -+ RK806_BUCK_SEL_CNT, RK806_BUCK3_ON_VSEL, -+ RK806_POWER_EN0, rk806_buck_voltage_ranges, 2, -+ RK806_BUCK3_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), -+ RK806_REGULATOR("dcdc-reg4", "vcc4", RK806_ID_DCDC4, rk806_ops_dcdc, -+ RK806_BUCK_SEL_CNT, RK806_BUCK4_ON_VSEL, -+ RK806_POWER_EN0, rk806_buck_voltage_ranges, 3, -+ RK806_BUCK4_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), -+ -+ RK806_REGULATOR("dcdc-reg5", "vcc5", RK806_ID_DCDC5, rk806_ops_dcdc, -+ RK806_BUCK_SEL_CNT, RK806_BUCK5_ON_VSEL, -+ RK806_POWER_EN1, rk806_buck_voltage_ranges, 0, -+ RK806_BUCK5_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), -+ RK806_REGULATOR("dcdc-reg6", "vcc6", RK806_ID_DCDC6, rk806_ops_dcdc, -+ RK806_BUCK_SEL_CNT, RK806_BUCK6_ON_VSEL, -+ RK806_POWER_EN1, rk806_buck_voltage_ranges, 1, -+ RK806_BUCK6_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), -+ RK806_REGULATOR("dcdc-reg7", "vcc7", RK806_ID_DCDC7, rk806_ops_dcdc, -+ RK806_BUCK_SEL_CNT, RK806_BUCK7_ON_VSEL, -+ RK806_POWER_EN1, rk806_buck_voltage_ranges, 2, -+ RK806_BUCK7_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), -+ RK806_REGULATOR("dcdc-reg8", "vcc8", RK806_ID_DCDC8, rk806_ops_dcdc, -+ RK806_BUCK_SEL_CNT, RK806_BUCK8_ON_VSEL, -+ RK806_POWER_EN1, rk806_buck_voltage_ranges, 3, -+ RK806_BUCK8_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), -+ -+ RK806_REGULATOR("dcdc-reg9", "vcc9", RK806_ID_DCDC9, rk806_ops_dcdc, -+ RK806_BUCK_SEL_CNT, RK806_BUCK9_ON_VSEL, -+ RK806_POWER_EN2, rk806_buck_voltage_ranges, 0, -+ RK806_BUCK9_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), -+ RK806_REGULATOR("dcdc-reg10", "vcc10", RK806_ID_DCDC10, rk806_ops_dcdc, -+ RK806_BUCK_SEL_CNT, RK806_BUCK10_ON_VSEL, -+ RK806_POWER_EN2, rk806_buck_voltage_ranges, 1, -+ RK806_BUCK10_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc), -+ -+ RK806_REGULATOR("nldo-reg1", "vcc13", RK806_ID_NLDO1, rk806_ops_nldo, -+ RK806_LDO_SEL_CNT, RK806_NLDO1_ON_VSEL, -+ RK806_POWER_EN3, rk806_ldo_voltage_ranges, 0, -+ 0xEA, 0x38, rk806_ramp_delay_table_ldo), -+ RK806_REGULATOR("nldo-reg2", "vcc13", RK806_ID_NLDO2, rk806_ops_nldo, -+ RK806_LDO_SEL_CNT, RK806_NLDO2_ON_VSEL, -+ RK806_POWER_EN3, rk806_ldo_voltage_ranges, 1, -+ 0xEA, 0x38, rk806_ramp_delay_table_ldo), -+ RK806_REGULATOR("nldo-reg3", "vcc13", RK806_ID_NLDO3, rk806_ops_nldo, -+ RK806_LDO_SEL_CNT, RK806_NLDO3_ON_VSEL, -+ RK806_POWER_EN3, rk806_ldo_voltage_ranges, 2, -+ 0xEA, 0x38, rk806_ramp_delay_table_ldo), -+ RK806_REGULATOR("nldo-reg4", "vcc14", RK806_ID_NLDO4, rk806_ops_nldo, -+ RK806_LDO_SEL_CNT, RK806_NLDO4_ON_VSEL, -+ RK806_POWER_EN3, rk806_ldo_voltage_ranges, 3, -+ 0xEA, 0x38, rk806_ramp_delay_table_ldo), -+ -+ RK806_REGULATOR("nldo-reg5", "vcc14", RK806_ID_NLDO5, rk806_ops_nldo, -+ RK806_LDO_SEL_CNT, RK806_NLDO5_ON_VSEL, -+ RK806_POWER_EN5, rk806_ldo_voltage_ranges, 2, -+ 0xEA, 0x38, rk806_ramp_delay_table_ldo), -+ -+ RK806_REGULATOR("pldo-reg1", "vcc11", RK806_ID_PLDO1, rk806_ops_pldo, -+ RK806_LDO_SEL_CNT, RK806_PLDO1_ON_VSEL, -+ RK806_POWER_EN4, rk806_ldo_voltage_ranges, 1, -+ 0xEA, 0x38, rk806_ramp_delay_table_ldo), -+ RK806_REGULATOR("pldo-reg2", "vcc11", RK806_ID_PLDO2, rk806_ops_pldo, -+ RK806_LDO_SEL_CNT, RK806_PLDO2_ON_VSEL, -+ RK806_POWER_EN4, rk806_ldo_voltage_ranges, 2, -+ 0xEA, 0x38, rk806_ramp_delay_table_ldo), -+ RK806_REGULATOR("pldo-reg3", "vcc11", RK806_ID_PLDO3, rk806_ops_pldo, -+ RK806_LDO_SEL_CNT, RK806_PLDO3_ON_VSEL, -+ RK806_POWER_EN4, rk806_ldo_voltage_ranges, 3, -+ 0xEA, 0x38, rk806_ramp_delay_table_ldo), -+ -+ RK806_REGULATOR("pldo-reg4", "vcc12", RK806_ID_PLDO4, rk806_ops_pldo, -+ RK806_LDO_SEL_CNT, RK806_PLDO4_ON_VSEL, -+ RK806_POWER_EN5, rk806_ldo_voltage_ranges, 0, -+ 0xEA, 0x38, rk806_ramp_delay_table_ldo), -+ RK806_REGULATOR("pldo-reg5", "vcc12", RK806_ID_PLDO5, rk806_ops_pldo, -+ RK806_LDO_SEL_CNT, RK806_PLDO5_ON_VSEL, -+ RK806_POWER_EN5, rk806_ldo_voltage_ranges, 1, -+ 0xEA, 0x38, rk806_ramp_delay_table_ldo), -+ -+ RK806_REGULATOR("pldo-reg6", "vcca", RK806_ID_PLDO6, rk806_ops_pldo, -+ RK806_LDO_SEL_CNT, RK806_PLDO6_ON_VSEL, -+ RK806_POWER_EN4, rk806_ldo_voltage_ranges, 0, -+ 0xEA, 0x38, rk806_ramp_delay_table_ldo), -+}; -+ -+ - static const struct regulator_desc rk808_reg[] = { - { - .name = "DCDC_REG1", -@@ -1313,6 +1693,10 @@ static int rk808_regulator_probe(struct platform_device *pdev) - regulators = rk805_reg; - nregulators = RK805_NUM_REGULATORS; - break; -+ case RK806_ID: -+ regulators = rk806_reg; -+ nregulators = ARRAY_SIZE(rk806_reg); -+ break; - case RK808_ID: - regulators = rk808_reg; - nregulators = RK808_NUM_REGULATORS; -@@ -1366,5 +1750,6 @@ MODULE_AUTHOR("Tony xie "); - MODULE_AUTHOR("Chris Zhong "); - MODULE_AUTHOR("Zhang Qing "); - MODULE_AUTHOR("Wadim Egorov "); -+MODULE_AUTHOR("Xu Shengfei "); - MODULE_LICENSE("GPL"); - MODULE_ALIAS("platform:rk808-regulator"); --- -2.41.0 - - -From 909f24f813ef921635e5d38df6ce022bc7309ba7 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 7 Feb 2023 18:02:45 +0100 -Subject: [PATCH 15/17] arm64: defconfig: update RK8XX MFD config - -Update the defconfig for the new RK8XX MFD config name, -which got split to add SPI support. - -Reported-by: Marek Szyprowski -Fixes: c20e8c5b1203a ("mfd: rk808: Split into core and i2c") -Signed-off-by: Sebastian Reichel ---- - arch/arm64/configs/defconfig | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index a24609e14d50..cd69c9ced7da 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -688,7 +688,8 @@ CONFIG_MFD_MAX77620=y - CONFIG_MFD_MT6360=y - CONFIG_MFD_MT6397=y - CONFIG_MFD_SPMI_PMIC=y --CONFIG_MFD_RK808=y -+CONFIG_MFD_RK8XX_I2C=y -+CONFIG_MFD_RK8XX_SPI=y - CONFIG_MFD_SEC_CORE=y - CONFIG_MFD_SL28CPLD=y - CONFIG_MFD_TPS65219=y --- -2.41.0 - - -From 9ee85a98073699bf3a995905be8b78c776b70272 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 18 May 2023 05:11:10 +0200 -Subject: [PATCH 16/17] ARM: multi_v7_defconfig: update MFD_RK808 name - -MFD_RK808 got split into an I2C and SPI part named MFD_RK8XX_I2C and -MFD_RK8XX_SPI. Since there are no known ARMv7 boards using the SPI -connected RK8XX chips (which are new), it is enough to just enable -the I2C option. - -Reported-by: Marek Szyprowski -Fixes: c20e8c5b1203a ("mfd: rk808: Split into core and i2c") -Signed-off-by: Sebastian Reichel ---- - arch/arm/configs/multi_v7_defconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig -index 871fffe92187..f0800f806b5f 100644 ---- a/arch/arm/configs/multi_v7_defconfig -+++ b/arch/arm/configs/multi_v7_defconfig -@@ -596,7 +596,7 @@ CONFIG_MFD_CPCAP=y - CONFIG_MFD_PM8XXX=y - CONFIG_MFD_QCOM_RPM=y - CONFIG_MFD_SPMI_PMIC=y --CONFIG_MFD_RK808=y -+CONFIG_MFD_RK8XX_I2C=y - CONFIG_MFD_RN5T618=y - CONFIG_MFD_SEC_CORE=y - CONFIG_MFD_STMPE=y --- -2.41.0 - - -From e55f6558692a546162fe740f8590719fa26ad7c9 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 12 Jul 2022 15:17:33 +0200 -Subject: [PATCH 17/17] arm64: dts: rockchip: rk3588-evb1: add PMIC - -This adds PMIC support for the RK3588 EVB. - -Co-developed-by: shengfei Xu -Signed-off-by: shengfei Xu -Signed-off-by: Sebastian Reichel ---- - .../boot/dts/rockchip/rk3588-evb1-v10.dts | 637 ++++++++++++++++++ - 1 file changed, 637 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -index b91af0204dbe..4b2d857ee219 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts -@@ -49,6 +49,38 @@ vcc5v0_sys: vcc5v0-sys-regulator { - }; - }; - -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b2 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_b3 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ - &gmac0 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy>; -@@ -123,6 +155,611 @@ &sdhci { - status = "okay"; - }; - -+&spi2 { -+ status = "okay"; -+ assigned-clocks = <&cru CLK_SPI2>; -+ assigned-clock-rates = <200000000>; -+ num-cs = <2>; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ reg = <0x0>; -+ #gpio-cells = <2>; -+ gpio-controller; -+ interrupt-parent = <&gpio0>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -+ <&rk806_dvs2_null>, <&rk806_dvs3_null>; -+ pinctrl-names = "default"; -+ spi-max-frequency = <1000000>; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc5v0_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc5v0_sys>; -+ vcc13-supply = <&vcc5v0_sys>; -+ vcc14-supply = <&vcc_1v1_nldo_s3>; -+ vcca-supply = <&vcc5v0_sys>; -+ -+ rk806_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl1"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ -+ regulators { -+ vdd_gpu_s0: dcdc-reg1 { -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_gpu_s0"; -+ regulator-enable-ramp-delay = <400>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_npu_s0: dcdc-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_npu_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_log_s0: dcdc-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_log_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: dcdc-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_vdenc_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ -+ }; -+ -+ vdd_gpu_mem_s0: dcdc-reg5 { -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-enable-ramp-delay = <400>; -+ regulator-name = "vdd_gpu_mem_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ -+ }; -+ -+ vdd_npu_mem_s0: dcdc-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_npu_mem_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2000000>; -+ regulator-max-microvolt = <2000000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_2v0_pldo_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vdd_vdenc_mem_s0: dcdc-reg8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_vdenc_mem_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd2_ddr_s3: dcdc-reg9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vdd2_ddr_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v1_nldo_s3: dcdc-reg10 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_1v1_nldo_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1100000>; -+ }; -+ }; -+ -+ avcc_1v8_s0: pldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "avcc_1v8_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd1_1v8_ddr_s3: pldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd1_1v8_ddr_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avcc_1v8_codec_s0: pldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "avcc_1v8_codec_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3_s3: pldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_3v3_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vccio_sd_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_1v8_s3: pldo-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vccio_1v8_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_0v75_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd2l_0v9_ddr_s3: nldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-name = "vdd2l_0v9_ddr_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vdd_0v75_hdmi_edp_s0: nldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_hdmi_edp_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ avdd_0v75_s0: nldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "avdd_0v75_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v85_s0: nldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_0v85_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ -+ pmic@1 { -+ compatible = "rockchip,rk806"; -+ reg = <0x01>; -+ #gpio-cells = <2>; -+ gpio-controller; -+ interrupt-parent = <&gpio0>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, -+ <&rk806_slave_dvs3_null>; -+ pinctrl-names = "default"; -+ spi-max-frequency = <1000000>; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc5v0_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc5v0_sys>; -+ vcc13-supply = <&vcc_1v1_nldo_s3>; -+ vcc14-supply = <&vcc_2v0_pldo_s3>; -+ vcca-supply = <&vcc5v0_sys>; -+ -+ rk806_slave_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl1"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_slave_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_slave_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ regulators { -+ vdd_cpu_big1_s0: dcdc-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_big1_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big0_s0: dcdc-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_big0_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_s0: dcdc-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_lit_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3_s0: dcdc-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_3v3_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big1_mem_s0: dcdc-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_big1_mem_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ -+ vdd_cpu_big0_mem_s0: dcdc-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_big0_mem_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s0: dcdc-reg7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_1v8_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_mem_s0: dcdc-reg8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_lit_mem_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vddq_ddr_s0: dcdc-reg9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vddq_ddr_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_s0: dcdc-reg10 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <900000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_ddr_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_cam_s0: pldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_1v8_cam_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ avdd1v8_ddr_pll_s0: pldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "avdd1v8_ddr_pll_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_1v8_pll_s0: pldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_1v8_pll_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3_sd_s0: pldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_3v3_sd_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_2v8_cam_s0: pldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2800000>; -+ regulator-max-microvolt = <2800000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_2v8_cam_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ pldo6_s3: pldo-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "pldo6_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_pll_s0: nldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_0v75_pll_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_pll_s0: nldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_ddr_pll_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ avdd_0v85_s0: nldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "avdd_0v85_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ avdd_1v2_cam_s0: nldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "avdd_1v2_cam_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ avdd_1v2_s0: nldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "avdd_1v2_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ - &uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; --- -2.41.0 - diff --git a/patch/kernel/rockchip-rk3588-edge/0011-arm64-dts-rockchip-rk3588-add-GIC-ITS-support.patch b/patch/kernel/rockchip-rk3588-edge/0011-arm64-dts-rockchip-rk3588-add-GIC-ITS-support.patch deleted file mode 100644 index 64baf5ede..000000000 --- a/patch/kernel/rockchip-rk3588-edge/0011-arm64-dts-rockchip-rk3588-add-GIC-ITS-support.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 9572f9567627c5e80bf77248242ef2e5c90da600 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 18 Apr 2023 16:21:09 +0200 -Subject: [PATCH 1/1] arm64: dts: rockchip: rk3588: add GIC ITS support - -Add the two Interrupt Translation Service (ITS) IPs that are part of the -GIC-600. They are mainly required for PCIe Message Signalled Interrupts -(MSI). - -Co-developed-by: Kever Yang -Signed-off-by: Kever Yang -Signed-off-by: Sebastian Reichel ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index b46574358dd1..05af9a0fddf4 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1688,7 +1688,24 @@ gic: interrupt-controller@fe600000 { - mbi-alias = <0x0 0xfe610000>; - mbi-ranges = <424 56>; - msi-controller; -+ ranges; -+ #address-cells = <2>; - #interrupt-cells = <4>; -+ #size-cells = <2>; -+ -+ its0: msi-controller@fe640000 { -+ compatible = "arm,gic-v3-its"; -+ msi-controller; -+ #msi-cells = <1>; -+ reg = <0x0 0xfe640000 0x0 0x20000>; -+ }; -+ -+ its1: msi-controller@fe660000 { -+ compatible = "arm,gic-v3-its"; -+ msi-controller; -+ #msi-cells = <1>; -+ reg = <0x0 0xfe660000 0x0 0x20000>; -+ }; - - ppi-partitions { - ppi_partition0: interrupt-partition-0 { --- -2.41.0 - diff --git a/patch/kernel/rockchip-rk3588-edge/0029-RK3588-Add-Cpufreq-Support.patch b/patch/kernel/rockchip-rk3588-edge/0014-RK3588-Add-Cpufreq-Support.patch similarity index 92% rename from patch/kernel/rockchip-rk3588-edge/0029-RK3588-Add-Cpufreq-Support.patch rename to patch/kernel/rockchip-rk3588-edge/0014-RK3588-Add-Cpufreq-Support.patch index cebf7734d..40a0f14e3 100644 --- a/patch/kernel/rockchip-rk3588-edge/0029-RK3588-Add-Cpufreq-Support.patch +++ b/patch/kernel/rockchip-rk3588-edge/0014-RK3588-Add-Cpufreq-Support.patch @@ -1,4 +1,4 @@ -From cd27d0c81ffbcbff5a06c50ebf7cddf36bc02157 Mon Sep 17 00:00:00 2001 +From 292ab6078d7cbb8526e063f48ea6c2d7f1a72c8c Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 18 Aug 2022 14:21:30 +0200 Subject: [PATCH 1/2] cpufreq: rockchip: Introduce driver for rk3588 @@ -14,7 +14,6 @@ for the big CPU cores to avoid a system hang when firmware tries to bring them up at reboot time. Signed-off-by: Sebastian Reichel -Signed-off-by: Muhammed Efe Cetin --- drivers/cpufreq/Kconfig.arm | 10 + drivers/cpufreq/Makefile | 1 + @@ -57,10 +56,10 @@ index ef8510774913..c3f8c9cd563f 100644 obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c -index 338cf6cc6596..64cdc6496360 100644 +index e2b20080de3a..7bc19a59be26 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c -@@ -156,6 +156,8 @@ static const struct of_device_id blocklist[] __initconst = { +@@ -159,6 +159,8 @@ static const struct of_device_id blocklist[] __initconst = { { .compatible = "qcom,sm8250", }, { .compatible = "qcom,sm8350", }, @@ -719,29 +718,36 @@ index 000000000000..6a60ec05d652 2.41.0 -From 5bcd240ccd436a8538d2e4c0f57773d59f632aeb Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Wed, 5 Jul 2023 00:42:45 +0300 +From 61d65d90be91c8ffe8b50145ba48a330258a7067 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 4 Apr 2023 17:30:46 +0200 Subject: [PATCH 2/2] arm64: dts: rockchip: rk3588: add cpu frequency scaling support +Add required bits for CPU frequency scaling to the Rockchip 3588 +devicetree. This is missing the 2.4 GHz operating point for the +big cpu clusters, since that does not work well on all SoCs. +Downstream has a driver for PVTM, which reduces the requested +frequencies based on (among other things) silicon quality. + +Signed-off-by: Sebastian Reichel --- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 500 ++++++++++++++++++++++ - 1 file changed, 500 insertions(+) + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 452 ++++++++++++++++++++++ + 1 file changed, 452 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index d6dda0e6a5d0..3a9ac4b5cd04 100644 +index 1576f9bfd6de..1eb5a4add04b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -10,6 +10,7 @@ +@@ -8,6 +8,7 @@ + #include + #include #include - #include - #include +#include / { - compatible = "rockchip,rk3588s", "rockchip,rk3588"; -@@ -18,6 +19,263 @@ / { + compatible = "rockchip,rk3588"; +@@ -16,6 +17,215 @@ / { #address-cells = <2>; #size-cells = <2>; @@ -875,30 +881,6 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644 + <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; -+ opp-2256000000 { -+ opp-hz = /bits/ 64 <2256000000>; -+ opp-microvolt = <1000000 1000000 1000000>, -+ <1000000 1000000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2304000000 { -+ opp-hz = /bits/ 64 <2304000000>; -+ opp-microvolt = <1000000 1000000 1000000>, -+ <1000000 1000000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2352000000 { -+ opp-hz = /bits/ 64 <2352000000>; -+ opp-microvolt = <1000000 1000000 1000000>, -+ <1000000 1000000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2400000000 { -+ opp-hz = /bits/ 64 <2400000000>; -+ opp-microvolt = <1000000 1000000 1000000>, -+ <1000000 1000000 1000000>; -+ clock-latency-ns = <40000>; -+ }; + }; + + cluster2_opp_table: opp-table-cluster2 { @@ -976,36 +958,12 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644 + <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; -+ opp-2256000000 { -+ opp-hz = /bits/ 64 <2256000000>; -+ opp-microvolt = <1000000 1000000 1000000>, -+ <1000000 1000000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2304000000 { -+ opp-hz = /bits/ 64 <2304000000>; -+ opp-microvolt = <1000000 1000000 1000000>, -+ <1000000 1000000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2352000000 { -+ opp-hz = /bits/ 64 <2352000000>; -+ opp-microvolt = <1000000 1000000 1000000>, -+ <1000000 1000000 1000000>; -+ clock-latency-ns = <40000>; -+ }; -+ opp-2400000000 { -+ opp-hz = /bits/ 64 <2400000000>; -+ opp-microvolt = <1000000 1000000 1000000>, -+ <1000000 1000000 1000000>; -+ clock-latency-ns = <40000>; -+ }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -@@ -64,6 +322,7 @@ cpu_l0: cpu@0 { +@@ -62,6 +272,7 @@ cpu_l0: cpu@0 { clocks = <&scmi_clk SCMI_CLK_CPUL>; assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; assigned-clock-rates = <816000000>; @@ -1013,7 +971,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644 cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; -@@ -83,6 +342,7 @@ cpu_l1: cpu@100 { +@@ -81,6 +292,7 @@ cpu_l1: cpu@100 { enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; @@ -1021,7 +979,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644 cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; -@@ -102,6 +362,7 @@ cpu_l2: cpu@200 { +@@ -100,6 +312,7 @@ cpu_l2: cpu@200 { enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; @@ -1029,7 +987,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644 cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; -@@ -121,6 +382,7 @@ cpu_l3: cpu@300 { +@@ -119,6 +332,7 @@ cpu_l3: cpu@300 { enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; @@ -1037,7 +995,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644 cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; -@@ -142,6 +404,7 @@ cpu_b0: cpu@400 { +@@ -140,6 +354,7 @@ cpu_b0: cpu@400 { clocks = <&scmi_clk SCMI_CLK_CPUB01>; assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; assigned-clock-rates = <816000000>; @@ -1045,7 +1003,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644 cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; -@@ -161,6 +424,7 @@ cpu_b1: cpu@500 { +@@ -159,6 +374,7 @@ cpu_b1: cpu@500 { enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB01>; @@ -1053,7 +1011,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644 cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; -@@ -182,6 +446,7 @@ cpu_b2: cpu@600 { +@@ -180,6 +396,7 @@ cpu_b2: cpu@600 { clocks = <&scmi_clk SCMI_CLK_CPUB23>; assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; assigned-clock-rates = <816000000>; @@ -1061,7 +1019,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644 cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; -@@ -201,6 +466,7 @@ cpu_b3: cpu@700 { +@@ -199,6 +416,7 @@ cpu_b3: cpu@700 { enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB23>; @@ -1069,7 +1027,7 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644 cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; -@@ -362,6 +628,230 @@ spll: clock-0 { +@@ -360,6 +578,230 @@ spll: clock-0 { #clock-cells = <0>; }; @@ -1300,11 +1258,10 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644 timer { compatible = "arm,armv8-timer"; interrupts = , -@@ -506,6 +996,16 @@ sys_grf: syscon@fd58c000 { - compatible = "rockchip,rk3588-sys-grf", "syscon"; +@@ -402,6 +844,16 @@ sys_grf: syscon@fd58c000 { reg = <0x0 0xfd58c000 0x0 0x1000>; }; -+ + + bigcore0_grf: syscon@fd590000 { + compatible = "rockchip,rk3588-bigcore0-grf", "syscon"; + reg = <0x0 0xfd590000 0x0 0x100>; @@ -1314,9 +1271,10 @@ index d6dda0e6a5d0..3a9ac4b5cd04 100644 + compatible = "rockchip,rk3588-bigcore1-grf", "syscon"; + reg = <0x0 0xfd592000 0x0 0x100>; + }; - - usb2phy0_grf: syscon@fd5d0000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", ++ + php_grf: syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf", "syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; -- 2.41.0 diff --git a/patch/kernel/rockchip-rk3588-edge/0014-soc-rockchip-power-domain-add-rk3588-mem-module-supp.patch b/patch/kernel/rockchip-rk3588-edge/0014-soc-rockchip-power-domain-add-rk3588-mem-module-supp.patch deleted file mode 100644 index 9aa7a13f1..000000000 --- a/patch/kernel/rockchip-rk3588-edge/0014-soc-rockchip-power-domain-add-rk3588-mem-module-supp.patch +++ /dev/null @@ -1,266 +0,0 @@ -From 9d842dbd76192184bd91f4a7abf57edc17ed5181 Mon Sep 17 00:00:00 2001 -From: Boris Brezillon -Date: Mon, 3 Apr 2023 21:32:50 +0200 -Subject: [PATCH 1/1] soc: rockchip: power-domain: add rk3588 mem module - support - -On RK3588 it's also possible to power down the memory used by the -particular power domains via PMU_MEM_PWR_GATE_SFTCON. This adds -support for this feature. - -Tested-by: Vincent Legoll -Co-Developed-by: Finley Xiao -Signed-off-by: Finley Xiao -Signed-off-by: Boris Brezillon -Signed-off-by: Sebastian Reichel ---- - drivers/soc/rockchip/pm_domains.c | 160 +++++++++++++++++++++++------- - 1 file changed, 125 insertions(+), 35 deletions(-) - -diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c -index 84bc022f9e5b..e3de49e671dc 100644 ---- a/drivers/soc/rockchip/pm_domains.c -+++ b/drivers/soc/rockchip/pm_domains.c -@@ -43,8 +43,10 @@ struct rockchip_domain_info { - bool active_wakeup; - int pwr_w_mask; - int req_w_mask; -+ int mem_status_mask; - int repair_status_mask; - u32 pwr_offset; -+ u32 mem_offset; - u32 req_offset; - }; - -@@ -54,6 +56,9 @@ struct rockchip_pmu_info { - u32 req_offset; - u32 idle_offset; - u32 ack_offset; -+ u32 mem_pwr_offset; -+ u32 chain_status_offset; -+ u32 mem_status_offset; - u32 repair_status_offset; - - u32 core_pwrcnt_offset; -@@ -119,13 +124,15 @@ struct rockchip_pmu { - .active_wakeup = wakeup, \ - } - --#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup) \ -+#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \ - { \ - .name = _name, \ - .pwr_offset = p_offset, \ - .pwr_w_mask = (pwr) << 16, \ - .pwr_mask = (pwr), \ - .status_mask = (status), \ -+ .mem_offset = m_offset, \ -+ .mem_status_mask = (m_status), \ - .repair_status_mask = (r_status), \ - .req_offset = r_offset, \ - .req_w_mask = (req) << 16, \ -@@ -269,8 +276,8 @@ void rockchip_pmu_unblock(void) - } - EXPORT_SYMBOL_GPL(rockchip_pmu_unblock); - --#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \ -- DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup) -+#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \ -+ DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup) - - static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) - { -@@ -408,17 +415,92 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd) - return !(val & pd->info->status_mask); - } - -+static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd) -+{ -+ struct rockchip_pmu *pmu = pd->pmu; -+ unsigned int val; -+ -+ regmap_read(pmu->regmap, -+ pmu->info->mem_status_offset + pd->info->mem_offset, &val); -+ -+ /* 1'b0: power on, 1'b1: power off */ -+ return !(val & pd->info->mem_status_mask); -+} -+ -+static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd) -+{ -+ struct rockchip_pmu *pmu = pd->pmu; -+ unsigned int val; -+ -+ regmap_read(pmu->regmap, -+ pmu->info->chain_status_offset + pd->info->mem_offset, &val); -+ -+ /* 1'b1: power on, 1'b0: power off */ -+ return val & pd->info->mem_status_mask; -+} -+ -+static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd) -+{ -+ struct rockchip_pmu *pmu = pd->pmu; -+ struct generic_pm_domain *genpd = &pd->genpd; -+ bool is_on; -+ int ret = 0; -+ -+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on, -+ is_on == true, 0, 10000); -+ if (ret) { -+ dev_err(pmu->dev, -+ "failed to get chain status '%s', target_on=1, val=%d\n", -+ genpd->name, is_on); -+ goto error; -+ } -+ -+ udelay(20); -+ -+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, -+ (pd->info->pwr_mask | pd->info->pwr_w_mask)); -+ wmb(); -+ -+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on, -+ is_on == false, 0, 10000); -+ if (ret) { -+ dev_err(pmu->dev, -+ "failed to get mem status '%s', target_on=0, val=%d\n", -+ genpd->name, is_on); -+ goto error; -+ } -+ -+ regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, -+ pd->info->pwr_w_mask); -+ wmb(); -+ -+ ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on, -+ is_on == true, 0, 10000); -+ if (ret) { -+ dev_err(pmu->dev, -+ "failed to get mem status '%s', target_on=1, val=%d\n", -+ genpd->name, is_on); -+ } -+ -+error: -+ return ret; -+} -+ - static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, - bool on) - { - struct rockchip_pmu *pmu = pd->pmu; - struct generic_pm_domain *genpd = &pd->genpd; - u32 pd_pwr_offset = pd->info->pwr_offset; -- bool is_on; -+ bool is_on, is_mem_on = false; - - if (pd->info->pwr_mask == 0) - return; -- else if (pd->info->pwr_w_mask) -+ -+ if (on && pd->info->mem_status_mask) -+ is_mem_on = rockchip_pmu_domain_is_mem_on(pd); -+ -+ if (pd->info->pwr_w_mask) - regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, - on ? pd->info->pwr_w_mask : - (pd->info->pwr_mask | pd->info->pwr_w_mask)); -@@ -428,6 +510,9 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, - - wmb(); - -+ if (is_mem_on && rockchip_pmu_domain_mem_reset(pd)) -+ return; -+ - if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, - is_on == on, 0, 10000)) { - dev_err(pmu->dev, -@@ -645,7 +730,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, - pd->genpd.flags = GENPD_FLAG_PM_CLK; - if (pd_info->active_wakeup) - pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; -- pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd)); -+ pm_genpd_init(&pd->genpd, NULL, -+ !rockchip_pmu_domain_is_on(pd) || -+ (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd))); - - pmu->genpd_data.domains[id] = &pd->genpd; - return 0; -@@ -1024,35 +1111,35 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = { - }; - - static const struct rockchip_domain_info rk3588_pm_domains[] = { -- [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, BIT(1), 0x0, BIT(0), BIT(0), false), -- [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0, 0x0, 0, 0, false), -- [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0, 0x0, 0, 0, false), -- [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, BIT(2), 0x0, BIT(1), BIT(1), false), -- [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, BIT(3), 0x0, BIT(2), BIT(2), false), -- [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, BIT(4), 0x0, BIT(3), BIT(3), false), -- [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, BIT(5), 0x0, BIT(4), BIT(4), false), -- [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, BIT(6), 0x0, BIT(5), BIT(5), false), -- [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, BIT(7), 0x0, BIT(6), BIT(6), false), -- [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, BIT(8), 0x0, BIT(7), BIT(7), false), -- [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, BIT(9), 0x0, BIT(8), BIT(8), false), -- [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, BIT(10), 0x0, 0, 0, false), -- [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, BIT(11), 0x0, BIT(9), BIT(9), false), -- [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, BIT(12), 0x0, BIT(10), BIT(10), false), -- [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, BIT(13), 0x0, 0, 0, false), -- [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, BIT(14), 0x0, BIT(11), BIT(11), false), -- [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, BIT(15), 0x0, BIT(12), BIT(12), false), -- [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false), -- [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, BIT(17), 0x0, BIT(15), BIT(15), false), -- [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, BIT(18), 0x4, BIT(0), BIT(16), false), -- [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, BIT(19), 0x4, BIT(1), BIT(17), false), -- [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, BIT(20), 0x4, BIT(5), BIT(21), false), -- [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, BIT(21), 0x0, 0, 0, false), -- [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, BIT(22), 0x0, 0, 0, true), -- [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0, 0x4, BIT(2), BIT(18), false), -- [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, BIT(23), 0x0, 0, 0, false), -- [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, BIT(24), 0x4, BIT(3), BIT(19), false), -- [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, BIT(25), 0x4, BIT(4), BIT(20), true), -- [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, BIT(26), 0x0, 0, 0, false), -+ [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false), -+ [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false), -+ [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false), -+ [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false), -+ [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false), -+ [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false), -+ [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false), -+ [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false), -+ [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false), -+ [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false), -+ [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false), -+ [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false), -+ [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false), -+ [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false), -+ [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false), -+ [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false), -+ [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false), -+ [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false), -+ [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false), -+ [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false), -+ [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false), -+ [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false), -+ [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false), -+ [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true), -+ [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false), -+ [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false), -+ [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false), -+ [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true), -+ [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false), - }; - - static const struct rockchip_pmu_info px30_pmu = { -@@ -1207,6 +1294,9 @@ static const struct rockchip_pmu_info rk3588_pmu = { - .req_offset = 0x10c, - .idle_offset = 0x120, - .ack_offset = 0x118, -+ .mem_pwr_offset = 0x1a0, -+ .chain_status_offset = 0x1f0, -+ .mem_status_offset = 0x1f8, - .repair_status_offset = 0x290, - - .num_domains = ARRAY_SIZE(rk3588_pm_domains), --- -2.41.0 - diff --git a/patch/kernel/rockchip-rk3588-edge/0015-arm64-dts-rockchip-Add-rk3588-timer.patch b/patch/kernel/rockchip-rk3588-edge/0015-arm64-dts-rockchip-Add-rk3588-timer.patch deleted file mode 100644 index 32f34e463..000000000 --- a/patch/kernel/rockchip-rk3588-edge/0015-arm64-dts-rockchip-Add-rk3588-timer.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 63cae5a6a417199ccc1965ceb1e1915a0b3c3e10 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Wed, 19 Apr 2023 21:13:09 +0300 -Subject: [PATCH 1/1] arm64: dts: rockchip: Add rk3588 timer - -Add DT node for Rockchip RK3588/RK3588S SoC timer. - -Signed-off-by: Cristian Ciocaltea ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 05af9a0fddf4..96fb3a6e0c68 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1805,6 +1805,14 @@ i2c5: i2c@fead0000 { - status = "disabled"; - }; - -+ timer0: timer@feae0000 { -+ compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; -+ reg = <0x0 0xfeae0000 0x0 0x20>; -+ interrupts = ; -+ clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; -+ clock-names = "pclk", "timer"; -+ }; -+ - wdt: watchdog@feaf0000 { - compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; - reg = <0x0 0xfeaf0000 0x0 0x100>; --- -2.41.0 - diff --git a/patch/kernel/rockchip-rk3588-edge/0025-Add-RK3588-USB2-Support.patch b/patch/kernel/rockchip-rk3588-edge/0020-Add-RK3588-USB2-Support.patch similarity index 85% rename from patch/kernel/rockchip-rk3588-edge/0025-Add-RK3588-USB2-Support.patch rename to patch/kernel/rockchip-rk3588-edge/0020-Add-RK3588-USB2-Support.patch index abbf66d67..a4672c35c 100644 --- a/patch/kernel/rockchip-rk3588-edge/0025-Add-RK3588-USB2-Support.patch +++ b/patch/kernel/rockchip-rk3588-edge/0020-Add-RK3588-USB2-Support.patch @@ -1,129 +1,7 @@ -From 0900696b9f56a0ec692d22eff3ad84bce7988f1a Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 30 Mar 2023 16:31:18 +0200 -Subject: [PATCH 01/11] dt-bindings: usb: Add RK3588 OHCI - -Add compatible for RK3588 OHCI. As far as I know it's fully -compatible with generic-ohci. - -Reviewed-by: Rob Herring -Signed-off-by: Sebastian Reichel ---- - .../devicetree/bindings/usb/generic-ohci.yaml | 17 ++++++++++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml -index d06d1e7d8876..be268e23ca79 100644 ---- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml -+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml -@@ -44,6 +44,7 @@ properties: - - hpe,gxp-ohci - - ibm,476gtr-ohci - - ingenic,jz4740-ohci -+ - rockchip,rk3588-ohci - - snps,hsdk-v1.0-ohci - - const: generic-ohci - - enum: -@@ -69,7 +70,7 @@ properties: - - clocks: - minItems: 1 -- maxItems: 3 -+ maxItems: 4 - description: | - In case the Renesas R-Car Gen3 SoCs: - - if a host only channel: first clock should be host. -@@ -147,6 +148,20 @@ allOf: - then: - properties: - transceiver: false -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: rockchip,rk3588-ohci -+ then: -+ properties: -+ clocks: -+ minItems: 4 -+ else: -+ properties: -+ clocks: -+ minItems: 1 -+ maxItems: 3 - - unevaluatedProperties: false - --- -2.41.0 - - -From 924974cf321fc4efadd8da84603b97bf80cbbeb2 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Tue, 4 Apr 2023 15:32:54 +0200 -Subject: [PATCH 02/11] dt-bindings: usb: Add RK3588 EHCI - -Add compatible for RK3588 EHCI. As far as I know it's fully -compatible with generic-ehci. - -Acked-by: Krzysztof Kozlowski -Reviewed-by: Rob Herring -Signed-off-by: Sebastian Reichel ---- - Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml -index 9445764bd8de..b956bb5fada7 100644 ---- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml -+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml -@@ -61,6 +61,7 @@ properties: - - ibm,476gtr-ehci - - nxp,lpc1850-ehci - - qca,ar7100-ehci -+ - rockchip,rk3588-ehci - - snps,hsdk-v1.0-ehci - - socionext,uniphier-ehci - - const: generic-ehci --- -2.41.0 - - -From 1c5f2868b5fa9d48586f3e606baae4200516fd59 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Wed, 29 Mar 2023 18:54:49 +0200 -Subject: [PATCH 03/11] usb: host: ohci-platform: increase max clock number to - 4 - -Rockchip RK3588 OHCI requires 4 clocks to be enabled. - -Acked-by: Alan Stern -Signed-off-by: Sebastian Reichel ---- - drivers/usb/host/ohci-platform.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c -index a84305091c43..dec38a845cff 100644 ---- a/drivers/usb/host/ohci-platform.c -+++ b/drivers/usb/host/ohci-platform.c -@@ -33,7 +33,7 @@ - #include "ohci.h" - - #define DRIVER_DESC "OHCI generic platform driver" --#define OHCI_MAX_CLKS 3 -+#define OHCI_MAX_CLKS 4 - #define hcd_to_ohci_priv(h) ((struct ohci_platform_priv *)hcd_to_ohci(h)->priv) - - struct ohci_platform_priv { --- -2.41.0 - - -From bf550631e2c027488074d56b63dca6d2837418e1 Mon Sep 17 00:00:00 2001 +From a4a5f99f91beeeeb641ab3d8e49bd4d318e8d473 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 30 Mar 2023 16:25:20 +0200 -Subject: [PATCH 04/11] dt-bindings: phy: rockchip,inno-usb2phy: add rk3588 +Subject: [PATCH 1/8] dt-bindings: phy: rockchip,inno-usb2phy: add rk3588 Add compatible for the USB2 phy in the Rockchip RK3588 SoC. @@ -189,10 +67,10 @@ index 0d6b8c28be07..5254413137c6 100644 2.41.0 -From 8c33eb76698b4d6648e9ae51eb3160baa108c761 Mon Sep 17 00:00:00 2001 +From e93bbbd346ba4f70ff394c56b1d9f58fddb60b9a Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 12 Jan 2023 19:15:52 +0100 -Subject: [PATCH 05/11] phy: phy-rockchip-inno-usb2: add rk3588 support +Subject: [PATCH 2/8] phy: phy-rockchip-inno-usb2: add rk3588 support Add basic support for the USB2 PHY found in the Rockchip RK3588. @@ -544,10 +422,10 @@ index a0bc10aa7961..2c4683c67a8e 100644 2.41.0 -From 06a9d6baed9ca58eb8b79e58887bebb81deac567 Mon Sep 17 00:00:00 2001 +From 2eaf6c8660ded5426501e0da35d4746a25e142cc Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 3 Apr 2023 20:23:14 +0200 -Subject: [PATCH 06/11] phy: phy-rockchip-inno-usb2: add reset support +Subject: [PATCH 3/8] phy: phy-rockchip-inno-usb2: add reset support Add reset handling support, which is needed for proper operation with RK3588. @@ -645,10 +523,10 @@ index 2c4683c67a8e..101b46939f0b 100644 2.41.0 -From f00308d812c063b4104214ff3d4b589f89ff96b4 Mon Sep 17 00:00:00 2001 +From 8ba13deb082a06286010db007fdf308219617898 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 3 Apr 2023 20:24:06 +0200 -Subject: [PATCH 07/11] phy: phy-rockchip-inno-usb2: add rk3588 phy tuning +Subject: [PATCH 4/8] phy: phy-rockchip-inno-usb2: add rk3588 phy tuning support On RK3588 some registers need to be tweaked to support waking up from @@ -798,11 +676,10 @@ index 101b46939f0b..aa8c55609c0d 100644 2.41.0 -From 656516de7b6bdce000fad36006d392bc03c4811a Mon Sep 17 00:00:00 2001 +From 7b290174691a44964e2f735a13514c5771231d68 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 3 Apr 2023 21:49:58 +0200 -Subject: [PATCH 08/11] phy: phy-rockchip-inno-usb2: simplify phy clock - handling +Subject: [PATCH 5/8] phy: phy-rockchip-inno-usb2: simplify phy clock handling Simplify phyclk handling by using devm_clk_get_optional_enabled to acquire and enable the optional clock. This also fixes a resource @@ -864,11 +741,10 @@ index aa8c55609c0d..1cf84869e78b 100644 2.41.0 -From 4c7c30ae33f9c7b899672d43abba0cfe4e387d14 Mon Sep 17 00:00:00 2001 +From 1f09d9722948775d9ddbb55c566b1dd96cba6be1 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 3 Apr 2023 22:01:14 +0200 -Subject: [PATCH 09/11] phy: phy-rockchip-inno-usb2: simplify getting match - data +Subject: [PATCH 6/8] phy: phy-rockchip-inno-usb2: simplify getting match data Simplify the code by directly getting the match data via device_get_match_data() instead of open coding its functionality. @@ -924,10 +800,10 @@ index 1cf84869e78b..f5c30f117cba 100644 2.41.0 -From b4885b6a9f0183c270fc54326b1a3aa7b916129f Mon Sep 17 00:00:00 2001 +From 27587f10b0763bba73af92cb1d00af2de2638b40 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 15 May 2023 18:40:42 +0200 -Subject: [PATCH 10/11] phy: phy-rockchip-inno-usb2: improve error message +Subject: [PATCH 7/8] phy: phy-rockchip-inno-usb2: improve error message Printing the OF node is not useful, since we get the same information from the device context. Instead print the reg address, that could @@ -956,22 +832,24 @@ index f5c30f117cba..b982c3f0d4b5 100644 2.41.0 -From 719bf79884297d5278f735bb08ed6a9fbaf37efa Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Tue, 4 Jul 2023 13:36:35 +0300 -Subject: [PATCH 11/11] arm64: dts: rockchip: rk3588: add USB2 support +From c10b7b902f6d8d1b550c6b4ccd8615f407ca85a3 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 12 Jan 2023 19:20:37 +0100 +Subject: [PATCH 8/8] arm64: dts: rockchip: rk3588: add USB2 support This adds USB2 (EHCI & OHCI) ports including the related PHYs and GRF modules to the rk3588(s) device tree. + +Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 94 +++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 973fd6e8aa36..37e323ec9d74 100644 +index 1eb5a4add04b..2ee12ca98824 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -399,11 +399,105 @@ scmi_shmem: sram@0 { +@@ -839,11 +839,105 @@ scmi_shmem: sram@0 { }; }; @@ -1074,9 +952,9 @@ index 973fd6e8aa36..37e323ec9d74 100644 + }; + }; + - php_grf: syscon@fd5b0000 { - compatible = "rockchip,rk3588-php-grf", "syscon"; - reg = <0x0 0xfd5b0000 0x0 0x1000>; + bigcore0_grf: syscon@fd590000 { + compatible = "rockchip,rk3588-bigcore0-grf", "syscon"; + reg = <0x0 0xfd590000 0x0 0x100>; -- 2.41.0 diff --git a/patch/kernel/rockchip-rk3588-edge/0020-RK3588-ADC-support.patch b/patch/kernel/rockchip-rk3588-edge/0020-RK3588-ADC-support.patch deleted file mode 100644 index c4c6fa4ae..000000000 --- a/patch/kernel/rockchip-rk3588-edge/0020-RK3588-ADC-support.patch +++ /dev/null @@ -1,684 +0,0 @@ -From cd425173fe5788b5bc17cc4a3de7c68fd571d151 Mon Sep 17 00:00:00 2001 -From: Simon Xue -Date: Sun, 4 Jun 2023 00:23:33 +0530 -Subject: [PATCH 1/9] iio: adc: rockchip_saradc: Add callback functions - -Add start, read and power_down callback functions, -which will help in adding new rockchip device support -cleanly. - -Signed-off-by: Simon Xue -Signed-off-by: Shreeya Patel ---- - drivers/iio/adc/rockchip_saradc.c | 64 +++++++++++++++++++++++++------ - 1 file changed, 52 insertions(+), 12 deletions(-) - -diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c -index 79448c5ffc2a..21f9d92a6af4 100644 ---- a/drivers/iio/adc/rockchip_saradc.c -+++ b/drivers/iio/adc/rockchip_saradc.c -@@ -38,10 +38,15 @@ - #define SARADC_TIMEOUT msecs_to_jiffies(100) - #define SARADC_MAX_CHANNELS 8 - -+struct rockchip_saradc; -+ - struct rockchip_saradc_data { - const struct iio_chan_spec *channels; - int num_channels; - unsigned long clk_rate; -+ void (*start)(struct rockchip_saradc *info, int chn); -+ int (*read)(struct rockchip_saradc *info); -+ void (*power_down)(struct rockchip_saradc *info); - }; - - struct rockchip_saradc { -@@ -60,27 +65,50 @@ struct rockchip_saradc { - struct notifier_block nb; - }; - --static void rockchip_saradc_power_down(struct rockchip_saradc *info) -+static void rockchip_saradc_reset_controller(struct reset_control *reset); -+ -+static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn) -+{ -+ /* 8 clock periods as delay between power up and start cmd */ -+ writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); -+ /* Select the channel to be used and trigger conversion */ -+ writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) | -+ SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL); -+} -+ -+static void rockchip_saradc_start(struct rockchip_saradc *info, int chn) -+{ -+ info->data->start(info, chn); -+} -+ -+static int rockchip_saradc_read_v1(struct rockchip_saradc *info) -+{ -+ return readl_relaxed(info->regs + SARADC_DATA); -+} -+ -+static int rockchip_saradc_read(struct rockchip_saradc *info) -+{ -+ return info->data->read(info); -+} -+ -+static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info) - { -- /* Clear irq & power down adc */ - writel_relaxed(0, info->regs + SARADC_CTRL); - } - -+static void rockchip_saradc_power_down(struct rockchip_saradc *info) -+{ -+ if (info->data->power_down) -+ info->data->power_down(info); -+} -+ - static int rockchip_saradc_conversion(struct rockchip_saradc *info, - struct iio_chan_spec const *chan) - { - reinit_completion(&info->completion); - -- /* 8 clock periods as delay between power up and start cmd */ -- writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); -- - info->last_chan = chan; -- -- /* Select the channel to be used and trigger conversion */ -- writel(SARADC_CTRL_POWER_CTRL -- | (chan->channel & SARADC_CTRL_CHN_MASK) -- | SARADC_CTRL_IRQ_ENABLE, -- info->regs + SARADC_CTRL); -+ rockchip_saradc_start(info, chan->channel); - - if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT)) - return -ETIMEDOUT; -@@ -123,7 +151,7 @@ static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id) - struct rockchip_saradc *info = dev_id; - - /* Read value */ -- info->last_val = readl_relaxed(info->regs + SARADC_DATA); -+ info->last_val = rockchip_saradc_read(info); - info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0); - - rockchip_saradc_power_down(info); -@@ -163,6 +191,9 @@ static const struct rockchip_saradc_data saradc_data = { - .channels = rockchip_saradc_iio_channels, - .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels), - .clk_rate = 1000000, -+ .start = rockchip_saradc_start_v1, -+ .read = rockchip_saradc_read_v1, -+ .power_down = rockchip_saradc_power_down_v1, - }; - - static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = { -@@ -174,6 +205,9 @@ static const struct rockchip_saradc_data rk3066_tsadc_data = { - .channels = rockchip_rk3066_tsadc_iio_channels, - .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels), - .clk_rate = 50000, -+ .start = rockchip_saradc_start_v1, -+ .read = rockchip_saradc_read_v1, -+ .power_down = rockchip_saradc_power_down_v1, - }; - - static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = { -@@ -189,6 +223,9 @@ static const struct rockchip_saradc_data rk3399_saradc_data = { - .channels = rockchip_rk3399_saradc_iio_channels, - .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels), - .clk_rate = 1000000, -+ .start = rockchip_saradc_start_v1, -+ .read = rockchip_saradc_read_v1, -+ .power_down = rockchip_saradc_power_down_v1, - }; - - static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = { -@@ -206,6 +243,9 @@ static const struct rockchip_saradc_data rk3568_saradc_data = { - .channels = rockchip_rk3568_saradc_iio_channels, - .num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels), - .clk_rate = 1000000, -+ .start = rockchip_saradc_start_v1, -+ .read = rockchip_saradc_read_v1, -+ .power_down = rockchip_saradc_power_down_v1, - }; - - static const struct of_device_id rockchip_saradc_match[] = { --- -2.41.0 - - -From b5d9db8b105387c66c2c44096a622c6d9adfd5e6 Mon Sep 17 00:00:00 2001 -From: Simon Xue -Date: Sun, 4 Jun 2023 00:23:34 +0530 -Subject: [PATCH 2/9] iio: adc: rockchip_saradc: Add support for RK3588 - -Add new start and read functions to support rk3588 device. -Also, add a device compatible string for the same. - -Signed-off-by: Simon Xue -Signed-off-by: Shreeya Patel -Reviewed-by: AngeloGioacchino Del Regno ---- - drivers/iio/adc/rockchip_saradc.c | 70 +++++++++++++++++++++++++++++++ - 1 file changed, 70 insertions(+) - -diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c -index 21f9d92a6af4..312286ec91dc 100644 ---- a/drivers/iio/adc/rockchip_saradc.c -+++ b/drivers/iio/adc/rockchip_saradc.c -@@ -4,6 +4,7 @@ - * Copyright (C) 2014 ROCKCHIP, Inc. - */ - -+#include - #include - #include - #include -@@ -38,6 +39,22 @@ - #define SARADC_TIMEOUT msecs_to_jiffies(100) - #define SARADC_MAX_CHANNELS 8 - -+/* v2 registers */ -+#define SARADC2_CONV_CON 0x0 -+#define SARADC_T_PD_SOC 0x4 -+#define SARADC_T_DAS_SOC 0xc -+#define SARADC2_END_INT_EN 0x104 -+#define SARADC2_ST_CON 0x108 -+#define SARADC2_STATUS 0x10c -+#define SARADC2_END_INT_ST 0x110 -+#define SARADC2_DATA_BASE 0x120 -+ -+#define SARADC2_EN_END_INT BIT(0) -+#define SARADC2_START BIT(4) -+#define SARADC2_SINGLE_MODE BIT(5) -+ -+#define SARADC2_CONV_CHANNELS GENMASK(15, 0) -+ - struct rockchip_saradc; - - struct rockchip_saradc_data { -@@ -76,6 +93,25 @@ static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn) - SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL); - } - -+static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn) -+{ -+ int val; -+ -+ if (info->reset) -+ rockchip_saradc_reset_controller(info->reset); -+ -+ writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC); -+ writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC); -+ val = FIELD_PREP(SARADC2_EN_END_INT, 1); -+ val |= val << 16; -+ writel_relaxed(val, info->regs + SARADC2_END_INT_EN); -+ val = FIELD_PREP(SARADC2_START, 1) | -+ FIELD_PREP(SARADC2_SINGLE_MODE, 1) | -+ FIELD_PREP(SARADC2_CONV_CHANNELS, chn); -+ val |= val << 16; -+ writel(val, info->regs + SARADC2_CONV_CON); -+} -+ - static void rockchip_saradc_start(struct rockchip_saradc *info, int chn) - { - info->data->start(info, chn); -@@ -86,6 +122,18 @@ static int rockchip_saradc_read_v1(struct rockchip_saradc *info) - return readl_relaxed(info->regs + SARADC_DATA); - } - -+static int rockchip_saradc_read_v2(struct rockchip_saradc *info) -+{ -+ int offset; -+ -+ /* Clear irq */ -+ writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST); -+ -+ offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4; -+ -+ return readl_relaxed(info->regs + offset); -+} -+ - static int rockchip_saradc_read(struct rockchip_saradc *info) - { - return info->data->read(info); -@@ -248,6 +296,25 @@ static const struct rockchip_saradc_data rk3568_saradc_data = { - .power_down = rockchip_saradc_power_down_v1, - }; - -+static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = { -+ SARADC_CHANNEL(0, "adc0", 12), -+ SARADC_CHANNEL(1, "adc1", 12), -+ SARADC_CHANNEL(2, "adc2", 12), -+ SARADC_CHANNEL(3, "adc3", 12), -+ SARADC_CHANNEL(4, "adc4", 12), -+ SARADC_CHANNEL(5, "adc5", 12), -+ SARADC_CHANNEL(6, "adc6", 12), -+ SARADC_CHANNEL(7, "adc7", 12), -+}; -+ -+static const struct rockchip_saradc_data rk3588_saradc_data = { -+ .channels = rockchip_rk3588_saradc_iio_channels, -+ .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels), -+ .clk_rate = 1000000, -+ .start = rockchip_saradc_start_v2, -+ .read = rockchip_saradc_read_v2, -+}; -+ - static const struct of_device_id rockchip_saradc_match[] = { - { - .compatible = "rockchip,saradc", -@@ -261,6 +328,9 @@ static const struct of_device_id rockchip_saradc_match[] = { - }, { - .compatible = "rockchip,rk3568-saradc", - .data = &rk3568_saradc_data, -+ }, { -+ .compatible = "rockchip,rk3588-saradc", -+ .data = &rk3588_saradc_data, - }, - {}, - }; --- -2.41.0 - - -From a0ba1f7d0b8ce5cfeff1253d99556704a4b70139 Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Sun, 4 Jun 2023 00:23:35 +0530 -Subject: [PATCH 3/9] iio: adc: rockchip_saradc: Make use of - devm_clk_get_enabled - -Use devm_clk_get_enabled() to avoid manually disabling the -clock. - -Signed-off-by: Shreeya Patel ---- - drivers/iio/adc/rockchip_saradc.c | 56 +++++-------------------------- - 1 file changed, 8 insertions(+), 48 deletions(-) - -diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c -index 312286ec91dc..ac424ea50787 100644 ---- a/drivers/iio/adc/rockchip_saradc.c -+++ b/drivers/iio/adc/rockchip_saradc.c -@@ -346,20 +346,6 @@ static void rockchip_saradc_reset_controller(struct reset_control *reset) - reset_control_deassert(reset); - } - --static void rockchip_saradc_clk_disable(void *data) --{ -- struct rockchip_saradc *info = data; -- -- clk_disable_unprepare(info->clk); --} -- --static void rockchip_saradc_pclk_disable(void *data) --{ -- struct rockchip_saradc *info = data; -- -- clk_disable_unprepare(info->pclk); --} -- - static void rockchip_saradc_regulator_disable(void *data) - { - struct rockchip_saradc *info = data; -@@ -493,16 +479,6 @@ static int rockchip_saradc_probe(struct platform_device *pdev) - return ret; - } - -- info->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); -- if (IS_ERR(info->pclk)) -- return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk), -- "failed to get pclk\n"); -- -- info->clk = devm_clk_get(&pdev->dev, "saradc"); -- if (IS_ERR(info->clk)) -- return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), -- "failed to get adc clock\n"); -- - info->vref = devm_regulator_get(&pdev->dev, "vref"); - if (IS_ERR(info->vref)) - return dev_err_probe(&pdev->dev, PTR_ERR(info->vref), -@@ -540,31 +516,15 @@ static int rockchip_saradc_probe(struct platform_device *pdev) - - info->uv_vref = ret; - -- ret = clk_prepare_enable(info->pclk); -- if (ret < 0) { -- dev_err(&pdev->dev, "failed to enable pclk\n"); -- return ret; -- } -- ret = devm_add_action_or_reset(&pdev->dev, -- rockchip_saradc_pclk_disable, info); -- if (ret) { -- dev_err(&pdev->dev, "failed to register devm action, %d\n", -- ret); -- return ret; -- } -+ info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); -+ if (IS_ERR(info->pclk)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk), -+ "failed to get pclk\n"); - -- ret = clk_prepare_enable(info->clk); -- if (ret < 0) { -- dev_err(&pdev->dev, "failed to enable converter clock\n"); -- return ret; -- } -- ret = devm_add_action_or_reset(&pdev->dev, -- rockchip_saradc_clk_disable, info); -- if (ret) { -- dev_err(&pdev->dev, "failed to register devm action, %d\n", -- ret); -- return ret; -- } -+ info->clk = devm_clk_get_enabled(&pdev->dev, "saradc"); -+ if (IS_ERR(info->clk)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), -+ "failed to get adc clock\n"); - - platform_set_drvdata(pdev, indio_dev); - --- -2.41.0 - - -From 412fdfbbfc17c588c1f9ae3ee838c29860549f8e Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Sun, 4 Jun 2023 00:23:36 +0530 -Subject: [PATCH 4/9] iio: adc: rockchip_saradc: Use of_device_get_match_data - -Use of_device_get_match_data() to simplify the code. - -Signed-off-by: Shreeya Patel -Reviewed-by: AngeloGioacchino Del Regno ---- - drivers/iio/adc/rockchip_saradc.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c -index ac424ea50787..cbe347fe8df7 100644 ---- a/drivers/iio/adc/rockchip_saradc.c -+++ b/drivers/iio/adc/rockchip_saradc.c -@@ -415,10 +415,10 @@ static void rockchip_saradc_regulator_unreg_notifier(void *data) - - static int rockchip_saradc_probe(struct platform_device *pdev) - { -+ const struct rockchip_saradc_data *match_data; - struct rockchip_saradc *info = NULL; - struct device_node *np = pdev->dev.of_node; - struct iio_dev *indio_dev = NULL; -- const struct of_device_id *match; - int ret; - int irq; - -@@ -432,13 +432,13 @@ static int rockchip_saradc_probe(struct platform_device *pdev) - } - info = iio_priv(indio_dev); - -- match = of_match_device(rockchip_saradc_match, &pdev->dev); -- if (!match) { -+ match_data = of_device_get_match_data(&pdev->dev); -+ if (!match_data) { - dev_err(&pdev->dev, "failed to match device\n"); - return -ENODEV; - } - -- info->data = match->data; -+ info->data = match_data; - - /* Sanity check for possible later IP variants with more channels */ - if (info->data->num_channels > SARADC_MAX_CHANNELS) { --- -2.41.0 - - -From 7706b5ab350facf848f44aa846a2d26a8fa64a65 Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Sun, 4 Jun 2023 00:23:37 +0530 -Subject: [PATCH 5/9] iio: adc: rockchip_saradc: Match alignment with open - parenthesis - -Match alignment with open parenthesis for improving the code -readability. - -Signed-off-by: Shreeya Patel -Reviewed-by: AngeloGioacchino Del Regno ---- - drivers/iio/adc/rockchip_saradc.c | 5 ++--- - 1 file changed, 2 insertions(+), 3 deletions(-) - -diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c -index cbe347fe8df7..436e219984fd 100644 ---- a/drivers/iio/adc/rockchip_saradc.c -+++ b/drivers/iio/adc/rockchip_saradc.c -@@ -151,7 +151,7 @@ static void rockchip_saradc_power_down(struct rockchip_saradc *info) - } - - static int rockchip_saradc_conversion(struct rockchip_saradc *info, -- struct iio_chan_spec const *chan) -+ struct iio_chan_spec const *chan) - { - reinit_completion(&info->completion); - -@@ -394,8 +394,7 @@ static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p) - } - - static int rockchip_saradc_volt_notify(struct notifier_block *nb, -- unsigned long event, -- void *data) -+ unsigned long event, void *data) - { - struct rockchip_saradc *info = - container_of(nb, struct rockchip_saradc, nb); --- -2.41.0 - - -From 6511ca5e340de5a0d146d86a705f839ffdeb35ec Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Sun, 4 Jun 2023 00:23:38 +0530 -Subject: [PATCH 6/9] iio: adc: rockchip_saradc: Use dev_err_probe - -Use dev_err_probe instead of dev_err in probe function, -which simplifies code a little bit and prints the error -code. - -Signed-off-by: Shreeya Patel ---- - drivers/iio/adc/rockchip_saradc.c | 45 ++++++++++++++----------------- - 1 file changed, 20 insertions(+), 25 deletions(-) - -diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c -index 436e219984fd..921844d9232d 100644 ---- a/drivers/iio/adc/rockchip_saradc.c -+++ b/drivers/iio/adc/rockchip_saradc.c -@@ -425,25 +425,23 @@ static int rockchip_saradc_probe(struct platform_device *pdev) - return -ENODEV; - - indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); -- if (!indio_dev) { -- dev_err(&pdev->dev, "failed allocating iio device\n"); -- return -ENOMEM; -- } -+ if (!indio_dev) -+ return dev_err_probe(&pdev->dev, -ENOMEM, -+ "failed allocating iio device\n"); -+ - info = iio_priv(indio_dev); - - match_data = of_device_get_match_data(&pdev->dev); -- if (!match_data) { -- dev_err(&pdev->dev, "failed to match device\n"); -- return -ENODEV; -- } -+ if (!match_data) -+ return dev_err_probe(&pdev->dev, -ENODEV, -+ "failed to match device\n"); - - info->data = match_data; - - /* Sanity check for possible later IP variants with more channels */ -- if (info->data->num_channels > SARADC_MAX_CHANNELS) { -- dev_err(&pdev->dev, "max channels exceeded"); -- return -EINVAL; -- } -+ if (info->data->num_channels > SARADC_MAX_CHANNELS) -+ return dev_err_probe(&pdev->dev, -EINVAL, -+ "max channels exceeded"); - - info->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(info->regs)) -@@ -491,23 +489,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev) - * This may become user-configurable in the future. - */ - ret = clk_set_rate(info->clk, info->data->clk_rate); -- if (ret < 0) { -- dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret); -- return ret; -- } -+ if (ret < 0) -+ return dev_err_probe(&pdev->dev, ret, -+ "failed to set adc clk rate\n"); - - ret = regulator_enable(info->vref); -- if (ret < 0) { -- dev_err(&pdev->dev, "failed to enable vref regulator\n"); -- return ret; -- } -+ if (ret < 0) -+ return dev_err_probe(&pdev->dev, ret, -+ "failed to enable vref regulator\n"); -+ - ret = devm_add_action_or_reset(&pdev->dev, - rockchip_saradc_regulator_disable, info); -- if (ret) { -- dev_err(&pdev->dev, "failed to register devm action, %d\n", -- ret); -- return ret; -- } -+ if (ret) -+ return dev_err_probe(&pdev->dev, ret, -+ "failed to register devm action\n"); - - ret = regulator_get_voltage(info->vref); - if (ret < 0) --- -2.41.0 - - -From 97f4513badc89771a4823235dab215078534419a Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Sun, 4 Jun 2023 00:23:39 +0530 -Subject: [PATCH 7/9] arm64: dts: rockchip: Add DT node for ADC support in - RK3588 - -Add DT node for ADC support in RK3588. - -Signed-off-by: Shreeya Patel ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 977ed617f59e..e7622a44c9ea 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1906,6 +1906,18 @@ dmac2: dma-controller@fed10000 { - #dma-cells = <1>; - }; - -+ saradc: saradc@fec10000 { -+ compatible = "rockchip,rk3588-saradc"; -+ reg = <0x0 0xfec10000 0x0 0x10000>; -+ interrupts = ; -+ #io-channel-cells = <1>; -+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; -+ clock-names = "saradc", "apb_pclk"; -+ resets = <&cru SRST_P_SARADC>; -+ reset-names = "saradc-apb"; -+ status = "disabled"; -+ }; -+ - system_sram2: sram@ff001000 { - compatible = "mmio-sram"; - reg = <0x0 0xff001000 0x0 0xef000>; --- -2.41.0 - - -From a4bde5a0ce8037f213cb1ede73181c55d108df6a Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Sun, 4 Jun 2023 00:23:40 +0530 -Subject: [PATCH 8/9] dt-bindings: iio: adc: Add rockchip,rk3588-saradc string - -Add rockchip,rk3588-saradc compatible string. - -Signed-off-by: Shreeya Patel -Acked-by: Krzysztof Kozlowski ---- - Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml -index da50b529c157..11c27ea451c8 100644 ---- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml -+++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml -@@ -21,6 +21,7 @@ properties: - - rockchip,rk3308-saradc - - rockchip,rk3328-saradc - - rockchip,rk3568-saradc -+ - rockchip,rk3588-saradc - - rockchip,rv1108-saradc - - rockchip,rv1126-saradc - - const: rockchip,rk3399-saradc --- -2.41.0 - - -From 0bea534abbafa0f8d43fb27c65d9c9d84f3269f3 Mon Sep 17 00:00:00 2001 -From: Shreeya Patel -Date: Sun, 11 Jun 2023 00:56:47 +0530 -Subject: [PATCH 9/9] dt-bindings: iio: rockchip: Fix 'oneOf' condition failed - warning - -rk3588-saradc isn't compatible with the rk3399-saradc variant, -hence, fix the following dtbs_check warning for 'oneOf' condition -failure. - -DTC_CHK arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtb -/home/shreeya/linux/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtb: - saradc@fec10000: compatible: 'oneOf' conditional failed, - one must be fixed: - ['rockchip,rk3588-saradc'] is too short - 'rockchip,saradc' was expected - 'rockchip,rk3066-tsadc' was expected - 'rockchip,rk3399-saradc' was expected - -Signed-off-by: Shreeya Patel ---- - Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml -index 11c27ea451c8..aa24b841393c 100644 ---- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml -+++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml -@@ -15,13 +15,13 @@ properties: - - const: rockchip,saradc - - const: rockchip,rk3066-tsadc - - const: rockchip,rk3399-saradc -+ - const: rockchip,rk3588-saradc - - items: - - enum: - - rockchip,px30-saradc - - rockchip,rk3308-saradc - - rockchip,rk3328-saradc - - rockchip,rk3568-saradc -- - rockchip,rk3588-saradc - - rockchip,rv1108-saradc - - rockchip,rv1126-saradc - - const: rockchip,rk3399-saradc --- -2.41.0 - diff --git a/patch/kernel/rockchip-rk3588-edge/0021-Add-RK3588-SATA-support.patch b/patch/kernel/rockchip-rk3588-edge/0021-Add-RK3588-SATA-support.patch index a2a316187..4093f743d 100644 --- a/patch/kernel/rockchip-rk3588-edge/0021-Add-RK3588-SATA-support.patch +++ b/patch/kernel/rockchip-rk3588-edge/0021-Add-RK3588-SATA-support.patch @@ -1,313 +1,12 @@ -From 03b582ba80822d93be46e13ca7121f99c7132da8 Mon Sep 17 00:00:00 2001 +From a62faa8b31b2e19cffe0e299f9e1c4cbd439722f Mon Sep 17 00:00:00 2001 From: Sebastian Reichel -Date: Mon, 12 Jun 2023 19:13:33 +0200 -Subject: [PATCH 1/5] dt-bindings: ata: dwc-ahci: add PHY clocks - -Add PHY transmit and receive clocks as described by the -DW SATA AHCI HW manual. - -Suggested-by: Serge Semin -Reviewed-by: Serge Semin -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Sebastian Reichel ---- - .../devicetree/bindings/ata/snps,dwc-ahci-common.yaml | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml -index c1457910520b..34c5bf65b02d 100644 ---- a/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml -+++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml -@@ -31,11 +31,11 @@ properties: - PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx) - clock, etc. - minItems: 1 -- maxItems: 4 -+ maxItems: 6 - - clock-names: - minItems: 1 -- maxItems: 4 -+ maxItems: 6 - items: - oneOf: - - description: Application APB/AHB/AXI BIU clock -@@ -48,6 +48,10 @@ properties: - const: pmalive - - description: RxOOB detection clock - const: rxoob -+ - description: PHY Transmit Clock -+ const: asic -+ - description: PHY Receive Clock -+ const: rbc - - description: SATA Ports reference clock - const: ref - --- -2.41.0 - - -From 81b1ff2b1b72caa5ed7776df1547bbddc83395e8 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 12 Jun 2023 19:13:34 +0200 -Subject: [PATCH 2/5] dt-bindings: ata: dwc-ahci: add Rockchip RK3588 - -This adds Rockchip RK3588 AHCI binding. In order to narrow down the -allowed clocks without bloating the generic binding, the description -of Rockchip's AHCI controllers has been moved to its own file. - -Signed-off-by: Sebastian Reichel -Reviewed-by: Serge Semin -Reviewed-by: Krzysztof Kozlowski ---- - .../bindings/ata/rockchip,dwc-ahci.yaml | 124 ++++++++++++++++++ - .../bindings/ata/snps,dwc-ahci.yaml | 13 +- - 2 files changed, 133 insertions(+), 4 deletions(-) - create mode 100644 Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml - -diff --git a/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml b/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml -new file mode 100644 -index 000000000000..b5e5767d8698 ---- /dev/null -+++ b/Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml -@@ -0,0 +1,124 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Synopsys DWC AHCI SATA controller for Rockchip devices -+ -+maintainers: -+ - Serge Semin -+ -+description: -+ This document defines device tree bindings for the Synopsys DWC -+ implementation of the AHCI SATA controller found in Rockchip -+ devices. -+ -+select: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - rockchip,rk3568-dwc-ahci -+ - rockchip,rk3588-dwc-ahci -+ required: -+ - compatible -+ -+properties: -+ compatible: -+ items: -+ - enum: -+ - rockchip,rk3568-dwc-ahci -+ - rockchip,rk3588-dwc-ahci -+ - const: snps,dwc-ahci -+ -+ ports-implemented: -+ const: 1 -+ -+ sata-port@0: -+ $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port -+ -+ properties: -+ reg: -+ const: 0 -+ -+ unevaluatedProperties: false -+ -+patternProperties: -+ "^sata-port@[1-9a-e]$": false -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - clocks -+ - clock-names -+ - ports-implemented -+ -+allOf: -+ - $ref: snps,dwc-ahci-common.yaml# -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - rockchip,rk3588-dwc-ahci -+ then: -+ properties: -+ clocks: -+ maxItems: 5 -+ clock-names: -+ items: -+ - const: sata -+ - const: pmalive -+ - const: rxoob -+ - const: ref -+ - const: asic -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - rockchip,rk3568-dwc-ahci -+ then: -+ properties: -+ clocks: -+ maxItems: 3 -+ clock-names: -+ items: -+ - const: sata -+ - const: pmalive -+ - const: rxoob -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ #include -+ -+ sata@fe210000 { -+ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; -+ reg = <0xfe210000 0x1000>; -+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, -+ <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, -+ <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; -+ clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; -+ interrupts = ; -+ ports-implemented = <0x1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ sata-port@0 { -+ reg = <0>; -+ hba-port-cap = ; -+ phys = <&combphy0_ps PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ snps,rx-ts-max = <32>; -+ snps,tx-ts-max = <32>; -+ }; -+ }; -+ -+... -diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml -index 5afa4b57ce20..4c848fcb5a5d 100644 ---- a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml -+++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml -@@ -13,6 +13,15 @@ description: - This document defines device tree bindings for the generic Synopsys DWC - implementation of the AHCI SATA controller. - -+select: -+ properties: -+ compatible: -+ enum: -+ - snps,dwc-ahci -+ - snps,spear-ahci -+ required: -+ - compatible -+ - allOf: - - $ref: snps,dwc-ahci-common.yaml# - -@@ -23,10 +32,6 @@ properties: - const: snps,dwc-ahci - - description: SPEAr1340 AHCI SATA device - const: snps,spear-ahci -- - description: Rockhip RK3568 AHCI controller -- items: -- - const: rockchip,rk3568-dwc-ahci -- - const: snps,dwc-ahci - - patternProperties: - "^sata-port@[0-9a-e]$": --- -2.41.0 - - -From 15f3049fcf0e6657c7f4c594b83f4df437a6c03c Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Mon, 12 Jun 2023 19:13:35 +0200 -Subject: [PATCH 3/5] dt-bindings: phy: rockchip: rk3588 has two reset lines - -The RK3588 has two reset lines for the combphy. One for the -APB interface and one for the actual PHY. - -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Sebastian Reichel ---- - .../phy/phy-rockchip-naneng-combphy.yaml | 34 ++++++++++++++++++- - 1 file changed, 33 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml -index 9ae514fa7533..d3cd7997879f 100644 ---- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml -+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml -@@ -31,8 +31,14 @@ properties: - - const: pipe - - resets: -+ minItems: 1 -+ maxItems: 2 -+ -+ reset-names: -+ minItems: 1 - items: -- - description: exclusive PHY reset line -+ - const: phy -+ - const: apb - - rockchip,enable-ssc: - type: boolean -@@ -78,6 +84,32 @@ required: - - rockchip,pipe-phy-grf - - "#phy-cells" - -+allOf: -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: rockchip,rk3568-naneng-combphy -+ then: -+ properties: -+ resets: -+ maxItems: 1 -+ reset-names: -+ maxItems: 1 -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: rockchip,rk3588-naneng-combphy -+ then: -+ properties: -+ resets: -+ minItems: 2 -+ reset-names: -+ minItems: 2 -+ required: -+ - reset-names -+ - additionalProperties: false - - examples: --- -2.41.0 - - -From 571fb8a07c593ddafa101138ef89d346677cc518 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Tue, 4 Jul 2023 13:11:19 +0300 -Subject: [PATCH 4/5] arm64: dts: rockchip: rk3588: add combo PHYs +Date: Thu, 6 Apr 2023 16:54:11 +0200 +Subject: [PATCH 1/2] arm64: dts: rockchip: rk3588: add combo PHYs Add all 3 combo PHYs that can be found in RK3588. They are used for SATA, PCIe or USB3. + +Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 21 ++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 42 +++++++++++++++++++++++ @@ -351,10 +50,10 @@ index 8be75556af8f..9d8539b5309b 100644 + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index e7622a44c9ea..4aa15ce78365 100644 +index 2ee12ca98824..e51cd3250ad0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -407,6 +407,16 @@ php_grf: syscon@fd5b0000 { +@@ -953,6 +953,16 @@ php_grf: syscon@fd5b0000 { reg = <0x0 0xfd5b0000 0x0 0x1000>; }; @@ -371,7 +70,7 @@ index e7622a44c9ea..4aa15ce78365 100644 ioc: syscon@fd5f0000 { compatible = "rockchip,rk3588-ioc", "syscon"; reg = <0x0 0xfd5f0000 0x0 0x10000>; -@@ -1906,6 +1916,38 @@ dmac2: dma-controller@fed10000 { +@@ -2489,6 +2499,38 @@ dmac2: dma-controller@fed10000 { #dma-cells = <1>; }; @@ -407,19 +106,21 @@ index e7622a44c9ea..4aa15ce78365 100644 + status = "disabled"; + }; + - saradc: saradc@fec10000 { - compatible = "rockchip,rk3588-saradc"; - reg = <0x0 0xfec10000 0x0 0x10000>; + system_sram2: sram@ff001000 { + compatible = "mmio-sram"; + reg = <0x0 0xff001000 0x0 0xef000>; -- 2.41.0 -From 95ad8212851df865bb4146278a7bc782bca45880 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Tue, 4 Jul 2023 13:16:57 +0300 -Subject: [PATCH 5/5] arm64: dts: rockchip: rk3588: add SATA support +From b4d4e5cf5bdd5ce79f7b2cecaece5aafc0c432e2 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 6 Apr 2023 17:14:19 +0200 +Subject: [PATCH 2/2] arm64: dts: rockchip: rk3588: add SATA support Add all three SATA IP blocks to the RK3588 DT. + +Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 23 +++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 48 +++++++++++++++++++++++ @@ -460,19 +161,19 @@ index 9d8539b5309b..b9508cea34f1 100644 compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee10000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 4aa15ce78365..ee091f0a3ca3 100644 +index e51cd3250ad0..7e6c08817284 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -8,6 +8,8 @@ - #include +@@ -9,6 +9,8 @@ #include #include + #include +#include +#include / { compatible = "rockchip,rk3588"; -@@ -1180,6 +1182,52 @@ gmac1_mtl_tx_setup: tx-queues-config { +@@ -1726,6 +1728,52 @@ gmac1_mtl_tx_setup: tx-queues-config { }; }; diff --git a/patch/kernel/rockchip-rk3588-edge/0022-RK3588-PCIe2-support.patch b/patch/kernel/rockchip-rk3588-edge/0022-RK3588-PCIe2-support.patch index 9e33123ca..22b35325b 100644 --- a/patch/kernel/rockchip-rk3588-edge/0022-RK3588-PCIe2-support.patch +++ b/patch/kernel/rockchip-rk3588-edge/0022-RK3588-PCIe2-support.patch @@ -1,7 +1,7 @@ -From 55f62897ce675d323b81dc92e9ce9060543e61f3 Mon Sep 17 00:00:00 2001 +From ce732448e140a388f74734edf2e2ec02a0478c55 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel -Date: Fri, 16 Jun 2023 19:00:19 +0200 -Subject: [PATCH 1/4] dt-bindings: PCI: dwc: rockchip: Fix interrupt-names +Date: Wed, 19 Apr 2023 14:57:14 +0200 +Subject: [PATCH 1/3] dt-bindings: PCI: dwc: rockchip: Fix interrupt-names issue The RK356x (and RK3588) have 5 ganged interrupts. For example the @@ -15,19 +15,18 @@ Fix this by specifying the interrupts and add them to the example to prevent regressions. Signed-off-by: Sebastian Reichel -Reviewed-by: Rob Herring --- .../bindings/pci/rockchip-dw-pcie.yaml | 18 ++++++++++++++++++ .../devicetree/bindings/pci/snps,dw-pcie.yaml | 15 ++++++++++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -index 24c88942e59e..98e45d2d8dfe 100644 +index a4f61ced5e88..aad53c7d8485 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -@@ -56,6 +56,17 @@ properties: - - const: pclk +@@ -60,6 +60,17 @@ properties: - const: aux + - const: pipe + interrupts: + maxItems: 5 @@ -43,7 +42,7 @@ index 24c88942e59e..98e45d2d8dfe 100644 msi-map: true num-lanes: true -@@ -98,6 +109,7 @@ unevaluatedProperties: false +@@ -108,6 +119,7 @@ unevaluatedProperties: false examples: - | @@ -51,7 +50,7 @@ index 24c88942e59e..98e45d2d8dfe 100644 bus { #address-cells = <2>; -@@ -117,6 +129,12 @@ examples: +@@ -127,6 +139,12 @@ examples: "aclk_dbi", "pclk", "aux"; device_type = "pci"; @@ -96,10 +95,10 @@ index 1a83f0f65f19..9f605eb297f5 100644 2.41.0 -From ed28eed118bb1815347fbb4ea3e4ebb2a917e2b4 Mon Sep 17 00:00:00 2001 +From 24502533a9950837c50469c1cbb37324a6c83b0e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel -Date: Fri, 16 Jun 2023 19:00:20 +0200 -Subject: [PATCH 2/4] dt-bindings: PCI: dwc: rockchip: Add missing +Date: Wed, 19 Apr 2023 18:27:12 +0200 +Subject: [PATCH 2/3] dt-bindings: PCI: dwc: rockchip: Add missing legacy-interrupt-controller Rockchip RK356x and RK3588 handle legacy interrupts via a ganged @@ -109,16 +108,15 @@ implementations. This adds proper documentation for this and updates the example to avoid regressions. Signed-off-by: Sebastian Reichel -Reviewed-by: Rob Herring --- .../bindings/pci/rockchip-dw-pcie.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -index 98e45d2d8dfe..bf81d306cc80 100644 +index aad53c7d8485..7897af0ec297 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -@@ -67,6 +67,22 @@ properties: +@@ -71,6 +71,22 @@ properties: - const: legacy - const: err @@ -141,7 +139,7 @@ index 98e45d2d8dfe..bf81d306cc80 100644 msi-map: true num-lanes: true -@@ -148,6 +164,14 @@ examples: +@@ -158,6 +174,14 @@ examples: reset-names = "pipe"; #address-cells = <3>; #size-cells = <2>; @@ -160,81 +158,10 @@ index 98e45d2d8dfe..bf81d306cc80 100644 2.41.0 -From 4298296463a25b9a7830001da790e8240654337a Mon Sep 17 00:00:00 2001 +From 9afd072bbcb97efccf1be82515cbe4ba682cce38 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel -Date: Fri, 16 Jun 2023 19:00:21 +0200 -Subject: [PATCH 3/4] dt-bindings: PCI: dwc: rockchip: Update for RK3588 - -The PCIe 2.0 controllers on RK3588 need one additional clock, -one additional reset line and one for ranges entry. - -Signed-off-by: Sebastian Reichel -Reviewed-by: Rob Herring -Reviewed-by: Serge Semin ---- - .../bindings/pci/rockchip-dw-pcie.yaml | 16 +++++++++++++--- - 1 file changed, 13 insertions(+), 3 deletions(-) - -diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -index bf81d306cc80..7897af0ec297 100644 ---- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml -@@ -41,20 +41,24 @@ properties: - - const: config - - clocks: -+ minItems: 5 - items: - - description: AHB clock for PCIe master - - description: AHB clock for PCIe slave - - description: AHB clock for PCIe dbi - - description: APB clock for PCIe - - description: Auxiliary clock for PCIe -+ - description: PIPE clock - - clock-names: -+ minItems: 5 - items: - - const: aclk_mst - - const: aclk_slv - - const: aclk_dbi - - const: pclk - - const: aux -+ - const: pipe - - interrupts: - maxItems: 5 -@@ -97,13 +101,19 @@ properties: - maxItems: 1 - - ranges: -- maxItems: 2 -+ minItems: 2 -+ maxItems: 3 - - resets: -- maxItems: 1 -+ minItems: 1 -+ maxItems: 2 - - reset-names: -- const: pipe -+ oneOf: -+ - const: pipe -+ - items: -+ - const: pwr -+ - const: pipe - - vpcie3v3-supply: true - --- -2.41.0 - - -From 83fbcafeea18de93601461ffd14311ea1ef8a433 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Fri, 16 Jun 2023 19:00:22 +0200 -Subject: [PATCH 4/4] arm64: dts: rockchip: rk3588: add PCIe2 support +Date: Mon, 17 Apr 2023 20:03:08 +0200 +Subject: [PATCH 3/3] arm64: dts: rockchip: rk3588: add PCIe2 support Add all three PCIe2 IP blocks to the RK3588 DT. Note, that RK3588 also has two PCIe3 IP blocks, that will be handled separately. @@ -248,7 +175,7 @@ Signed-off-by: Sebastian Reichel 2 files changed, 162 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -index b9508cea34f1..40fee1367b34 100644 +index b9508cea34f1..5c61cce52a21 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -80,6 +80,60 @@ i2s10_8ch: i2s@fde00000 { @@ -291,7 +218,7 @@ index b9508cea34f1..40fee1367b34 100644 + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, -+ <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; ++ <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + reg = <0xa 0x40800000 0x0 0x00400000>, + <0x0 0xfe170000 0x0 0x00010000>, + <0x0 0xf2000000 0x0 0x00100000>; @@ -313,10 +240,10 @@ index b9508cea34f1..40fee1367b34 100644 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index ee091f0a3ca3..973fd6e8aa36 100644 +index 7e6c08817284..a009c4414256 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1133,6 +1133,114 @@ qos_vop_m1: qos@fdf82200 { +@@ -1679,6 +1679,114 @@ qos_vop_m1: qos@fdf82200 { reg = <0x0 0xfdf82200 0x0 0x20>; }; @@ -356,7 +283,7 @@ index ee091f0a3ca3..973fd6e8aa36 100644 + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, -+ <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; ++ <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + reg = <0xa 0x40c00000 0x0 0x00400000>, + <0x0 0xfe180000 0x0 0x00010000>, + <0x0 0xf3000000 0x0 0x00100000>; @@ -410,7 +337,7 @@ index ee091f0a3ca3..973fd6e8aa36 100644 + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, -+ <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; ++ <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0xa 0x41000000 0x0 0x00400000>, + <0x0 0xfe190000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; diff --git a/patch/kernel/rockchip-rk3588-edge/0023-Add-RK3588-OTP-memory-support.patch b/patch/kernel/rockchip-rk3588-edge/0023-Add-RK3588-OTP-memory-support.patch deleted file mode 100644 index 5dafc9896..000000000 --- a/patch/kernel/rockchip-rk3588-edge/0023-Add-RK3588-OTP-memory-support.patch +++ /dev/null @@ -1,847 +0,0 @@ -From a71fb1ef5b28f73ef42f4becc2c3fcb944797348 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Thu, 4 May 2023 23:06:41 +0300 -Subject: [PATCH 1/9] dt-bindings: nvmem: Convert rockchip-otp.txt to dt-schema - -Convert the Rockchip OTP memory bindings to dt-schema. - -Signed-off-by: Cristian Ciocaltea -Reviewed-by: Heiko Stuebner -Reviewed-by: Krzysztof Kozlowski ---- - .../bindings/nvmem/rockchip,otp.yaml | 82 +++++++++++++++++++ - .../bindings/nvmem/rockchip-otp.txt | 25 ------ - 2 files changed, 82 insertions(+), 25 deletions(-) - create mode 100644 Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml - delete mode 100644 Documentation/devicetree/bindings/nvmem/rockchip-otp.txt - -diff --git a/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml b/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml -new file mode 100644 -index 000000000000..4cd425ae2823 ---- /dev/null -+++ b/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml -@@ -0,0 +1,82 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Rockchip internal OTP (One Time Programmable) memory -+ -+maintainers: -+ - Heiko Stuebner -+ -+allOf: -+ - $ref: nvmem.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - rockchip,px30-otp -+ - rockchip,rk3308-otp -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ maxItems: 3 -+ -+ clock-names: -+ items: -+ - const: otp -+ - const: apb_pclk -+ - const: phy -+ -+ resets: -+ maxItems: 1 -+ -+ reset-names: -+ items: -+ - const: phy -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ otp: efuse@ff290000 { -+ compatible = "rockchip,px30-otp"; -+ reg = <0x0 0xff290000 0x0 0x4000>; -+ clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, -+ <&cru PCLK_OTP_PHY>; -+ clock-names = "otp", "apb_pclk", "phy"; -+ resets = <&cru SRST_OTP_PHY>; -+ reset-names = "phy"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ cpu_id: id@7 { -+ reg = <0x07 0x10>; -+ }; -+ -+ cpu_leakage: cpu-leakage@17 { -+ reg = <0x17 0x1>; -+ }; -+ -+ performance: performance@1e { -+ reg = <0x1e 0x1>; -+ bits = <4 3>; -+ }; -+ }; -+ }; -diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt b/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt -deleted file mode 100644 -index 40f649f7c2e5..000000000000 ---- a/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt -+++ /dev/null -@@ -1,25 +0,0 @@ --Rockchip internal OTP (One Time Programmable) memory device tree bindings -- --Required properties: --- compatible: Should be one of the following. -- - "rockchip,px30-otp" - for PX30 SoCs. -- - "rockchip,rk3308-otp" - for RK3308 SoCs. --- reg: Should contain the registers location and size --- clocks: Must contain an entry for each entry in clock-names. --- clock-names: Should be "otp", "apb_pclk" and "phy". --- resets: Must contain an entry for each entry in reset-names. -- See ../../reset/reset.txt for details. --- reset-names: Should be "phy". -- --See nvmem.txt for more information. -- --Example: -- otp: otp@ff290000 { -- compatible = "rockchip,px30-otp"; -- reg = <0x0 0xff290000 0x0 0x4000>; -- #address-cells = <1>; -- #size-cells = <1>; -- clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, -- <&cru PCLK_OTP_PHY>; -- clock-names = "otp", "apb_pclk", "phy"; -- }; --- -2.41.0 - - -From 3282bc8fec63200ed6a3c485bb39b3c094117209 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Thu, 4 May 2023 23:06:42 +0300 -Subject: [PATCH 2/9] dt-bindings: nvmem: rockchip,otp: Add compatible for - RK3588 - -Document the OTP memory found on Rockchip RK3588 SoC. - -Since RK3588 uses different clocks & resets configurations than PX30 / -RK3308, provide the required changes in the binding to be able to handle -both variants. - -Signed-off-by: Cristian Ciocaltea -Reviewed-by: Heiko Stuebner -Reviewed-by: Krzysztof Kozlowski ---- - .../bindings/nvmem/rockchip,otp.yaml | 54 ++++++++++++++++--- - 1 file changed, 47 insertions(+), 7 deletions(-) - -diff --git a/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml b/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml -index 4cd425ae2823..9c6eff788928 100644 ---- a/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml -+++ b/Documentation/devicetree/bindings/nvmem/rockchip,otp.yaml -@@ -9,33 +9,35 @@ title: Rockchip internal OTP (One Time Programmable) memory - maintainers: - - Heiko Stuebner - --allOf: -- - $ref: nvmem.yaml# -- - properties: - compatible: - enum: - - rockchip,px30-otp - - rockchip,rk3308-otp -+ - rockchip,rk3588-otp - - reg: - maxItems: 1 - - clocks: -- maxItems: 3 -+ minItems: 3 -+ maxItems: 4 - - clock-names: -+ minItems: 3 - items: - - const: otp - - const: apb_pclk - - const: phy -+ - const: arb - - resets: -- maxItems: 1 -+ minItems: 1 -+ maxItems: 3 - - reset-names: -- items: -- - const: phy -+ minItems: 1 -+ maxItems: 3 - - required: - - compatible -@@ -45,6 +47,44 @@ required: - - resets - - reset-names - -+allOf: -+ - $ref: nvmem.yaml# -+ -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - rockchip,px30-otp -+ - rockchip,rk3308-otp -+ then: -+ properties: -+ clocks: -+ maxItems: 3 -+ resets: -+ maxItems: 1 -+ reset-names: -+ items: -+ - const: phy -+ -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - rockchip,rk3588-otp -+ then: -+ properties: -+ clocks: -+ minItems: 4 -+ resets: -+ minItems: 3 -+ reset-names: -+ items: -+ - const: otp -+ - const: apb -+ - const: arb -+ - unevaluatedProperties: false - - examples: --- -2.41.0 - - -From e4131e9dc168176bf647116e998f34e53cf7233f Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Thu, 4 May 2023 23:06:43 +0300 -Subject: [PATCH 3/9] nvmem: rockchip-otp: Add clks and reg_read to - rockchip_data - -In preparation to support new Rockchip OTP memory devices with different -clock configurations and register layout, extend rockchip_data struct -with the related members: clks, num_clks, reg_read. - -Additionally, to avoid managing redundant driver data, drop num_clks -member from rockchip_otp struct and update all references to point to -the equivalent member in rockchip_data. - -Signed-off-by: Cristian Ciocaltea -Tested-by: Vincent Legoll -Reviewed-by: Heiko Stuebner ---- - drivers/nvmem/rockchip-otp.c | 79 ++++++++++++++++++++++-------------- - 1 file changed, 49 insertions(+), 30 deletions(-) - -diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c -index 9f53bcce2f87..b5a84b379da4 100644 ---- a/drivers/nvmem/rockchip-otp.c -+++ b/drivers/nvmem/rockchip-otp.c -@@ -54,21 +54,19 @@ - - #define OTPC_TIMEOUT 10000 - -+struct rockchip_data { -+ int size; -+ const char * const *clks; -+ int num_clks; -+ nvmem_reg_read_t reg_read; -+}; -+ - struct rockchip_otp { - struct device *dev; - void __iomem *base; -- struct clk_bulk_data *clks; -- int num_clks; -+ struct clk_bulk_data *clks; - struct reset_control *rst; --}; -- --/* list of required clocks */ --static const char * const rockchip_otp_clocks[] = { -- "otp", "apb_pclk", "phy", --}; -- --struct rockchip_data { -- int size; -+ const struct rockchip_data *data; - }; - - static int rockchip_otp_reset(struct rockchip_otp *otp) -@@ -132,29 +130,23 @@ static int rockchip_otp_ecc_enable(struct rockchip_otp *otp, bool enable) - return ret; - } - --static int rockchip_otp_read(void *context, unsigned int offset, -- void *val, size_t bytes) -+static int px30_otp_read(void *context, unsigned int offset, -+ void *val, size_t bytes) - { - struct rockchip_otp *otp = context; - u8 *buf = val; -- int ret = 0; -- -- ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks); -- if (ret < 0) { -- dev_err(otp->dev, "failed to prepare/enable clks\n"); -- return ret; -- } -+ int ret; - - ret = rockchip_otp_reset(otp); - if (ret) { - dev_err(otp->dev, "failed to reset otp phy\n"); -- goto disable_clks; -+ return ret; - } - - ret = rockchip_otp_ecc_enable(otp, false); - if (ret < 0) { - dev_err(otp->dev, "rockchip_otp_ecc_enable err\n"); -- goto disable_clks; -+ return ret; - } - - writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); -@@ -174,8 +166,28 @@ static int rockchip_otp_read(void *context, unsigned int offset, - - read_end: - writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); --disable_clks: -- clk_bulk_disable_unprepare(otp->num_clks, otp->clks); -+ -+ return ret; -+} -+ -+static int rockchip_otp_read(void *context, unsigned int offset, -+ void *val, size_t bytes) -+{ -+ struct rockchip_otp *otp = context; -+ int ret; -+ -+ if (!otp->data || !otp->data->reg_read) -+ return -EINVAL; -+ -+ ret = clk_bulk_prepare_enable(otp->data->num_clks, otp->clks); -+ if (ret < 0) { -+ dev_err(otp->dev, "failed to prepare/enable clks\n"); -+ return ret; -+ } -+ -+ ret = otp->data->reg_read(context, offset, val, bytes); -+ -+ clk_bulk_disable_unprepare(otp->data->num_clks, otp->clks); - - return ret; - } -@@ -189,8 +201,15 @@ static struct nvmem_config otp_config = { - .reg_read = rockchip_otp_read, - }; - -+static const char * const px30_otp_clocks[] = { -+ "otp", "apb_pclk", "phy", -+}; -+ - static const struct rockchip_data px30_data = { - .size = 0x40, -+ .clks = px30_otp_clocks, -+ .num_clks = ARRAY_SIZE(px30_otp_clocks), -+ .reg_read = px30_otp_read, - }; - - static const struct of_device_id rockchip_otp_match[] = { -@@ -225,21 +244,21 @@ static int rockchip_otp_probe(struct platform_device *pdev) - if (!otp) - return -ENOMEM; - -+ otp->data = data; - otp->dev = dev; - otp->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(otp->base)) - return PTR_ERR(otp->base); - -- otp->num_clks = ARRAY_SIZE(rockchip_otp_clocks); -- otp->clks = devm_kcalloc(dev, otp->num_clks, -- sizeof(*otp->clks), GFP_KERNEL); -+ otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks), -+ GFP_KERNEL); - if (!otp->clks) - return -ENOMEM; - -- for (i = 0; i < otp->num_clks; ++i) -- otp->clks[i].id = rockchip_otp_clocks[i]; -+ for (i = 0; i < data->num_clks; ++i) -+ otp->clks[i].id = data->clks[i]; - -- ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks); -+ ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks); - if (ret) - return ret; - --- -2.41.0 - - -From a0cad270a253d54eaea3643f9d8426dbb436ec2c Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Thu, 4 May 2023 23:06:44 +0300 -Subject: [PATCH 4/9] nvmem: rockchip-otp: Generalize - rockchip_otp_wait_status() - -In preparation to support additional Rockchip OTP memory devices with -different register layout, generalize rockchip_otp_wait_status() to -accept a new parameter for specifying the offset of the status register. - -Signed-off-by: Cristian Ciocaltea -Tested-by: Vincent Legoll -Reviewed-by: Heiko Stuebner ---- - drivers/nvmem/rockchip-otp.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - -diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c -index b5a84b379da4..b62e001f9116 100644 ---- a/drivers/nvmem/rockchip-otp.c -+++ b/drivers/nvmem/rockchip-otp.c -@@ -90,18 +90,19 @@ static int rockchip_otp_reset(struct rockchip_otp *otp) - return 0; - } - --static int rockchip_otp_wait_status(struct rockchip_otp *otp, u32 flag) -+static int rockchip_otp_wait_status(struct rockchip_otp *otp, -+ unsigned int reg, u32 flag) - { - u32 status = 0; - int ret; - -- ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status, -+ ret = readl_poll_timeout_atomic(otp->base + reg, status, - (status & flag), 1, OTPC_TIMEOUT); - if (ret) - return ret; - - /* clean int status */ -- writel(flag, otp->base + OTPC_INT_STATUS); -+ writel(flag, otp->base + reg); - - return 0; - } -@@ -123,7 +124,7 @@ static int rockchip_otp_ecc_enable(struct rockchip_otp *otp, bool enable) - - writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL); - -- ret = rockchip_otp_wait_status(otp, OTPC_SBPI_DONE); -+ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_SBPI_DONE); - if (ret < 0) - dev_err(otp->dev, "timeout during ecc_enable\n"); - -@@ -156,7 +157,7 @@ static int px30_otp_read(void *context, unsigned int offset, - otp->base + OTPC_USER_ADDR); - writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK, - otp->base + OTPC_USER_ENABLE); -- ret = rockchip_otp_wait_status(otp, OTPC_USER_DONE); -+ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE); - if (ret < 0) { - dev_err(otp->dev, "timeout during read setup\n"); - goto read_end; --- -2.41.0 - - -From f993ae18db25b7033c4453225d4063775048d9e0 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Thu, 4 May 2023 23:06:45 +0300 -Subject: [PATCH 5/9] nvmem: rockchip-otp: Use - devm_reset_control_array_get_exclusive() - -In preparation to support new Rockchip OTP memory devices having -specific reset configurations, switch devm_reset_control_get() to -devm_reset_control_array_get_exclusive(). - -Signed-off-by: Cristian Ciocaltea -Tested-by: Vincent Legoll -Reviewed-by: Heiko Stuebner ---- - drivers/nvmem/rockchip-otp.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c -index b62e001f9116..439aea1f8874 100644 ---- a/drivers/nvmem/rockchip-otp.c -+++ b/drivers/nvmem/rockchip-otp.c -@@ -263,7 +263,7 @@ static int rockchip_otp_probe(struct platform_device *pdev) - if (ret) - return ret; - -- otp->rst = devm_reset_control_get(dev, "phy"); -+ otp->rst = devm_reset_control_array_get_exclusive(dev); - if (IS_ERR(otp->rst)) - return PTR_ERR(otp->rst); - --- -2.41.0 - - -From 1db5714fc59aa0b0b829155493389429cc497ddb Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Thu, 4 May 2023 23:06:46 +0300 -Subject: [PATCH 6/9] nvmem: rockchip-otp: Improve probe error handling - -Enhance error handling in the probe function by making use of -dev_err_probe(), which ensures the error code is always printed, in -addition to the specified error message. - -Signed-off-by: Cristian Ciocaltea -Tested-by: Vincent Legoll -Reviewed-by: Heiko Stuebner ---- - drivers/nvmem/rockchip-otp.c | 21 ++++++++++++--------- - 1 file changed, 12 insertions(+), 9 deletions(-) - -diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c -index 439aea1f8874..84bf956cc4e1 100644 ---- a/drivers/nvmem/rockchip-otp.c -+++ b/drivers/nvmem/rockchip-otp.c -@@ -235,10 +235,8 @@ static int rockchip_otp_probe(struct platform_device *pdev) - int ret, i; - - data = of_device_get_match_data(dev); -- if (!data) { -- dev_err(dev, "failed to get match data\n"); -- return -EINVAL; -- } -+ if (!data) -+ return dev_err_probe(dev, -EINVAL, "failed to get match data\n"); - - otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp), - GFP_KERNEL); -@@ -249,7 +247,8 @@ static int rockchip_otp_probe(struct platform_device *pdev) - otp->dev = dev; - otp->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(otp->base)) -- return PTR_ERR(otp->base); -+ return dev_err_probe(dev, PTR_ERR(otp->base), -+ "failed to ioremap resource\n"); - - otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks), - GFP_KERNEL); -@@ -261,18 +260,22 @@ static int rockchip_otp_probe(struct platform_device *pdev) - - ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks); - if (ret) -- return ret; -+ return dev_err_probe(dev, ret, "failed to get clocks\n"); - - otp->rst = devm_reset_control_array_get_exclusive(dev); - if (IS_ERR(otp->rst)) -- return PTR_ERR(otp->rst); -+ return dev_err_probe(dev, PTR_ERR(otp->rst), -+ "failed to get resets\n"); - - otp_config.size = data->size; - otp_config.priv = otp; - otp_config.dev = dev; -- nvmem = devm_nvmem_register(dev, &otp_config); - -- return PTR_ERR_OR_ZERO(nvmem); -+ nvmem = devm_nvmem_register(dev, &otp_config); -+ if (IS_ERR(nvmem)) -+ return dev_err_probe(dev, PTR_ERR(nvmem), -+ "failed to register nvmem device\n"); -+ return 0; - } - - static struct platform_driver rockchip_otp_driver = { --- -2.41.0 - - -From a3266c7a0d896cd793a070b18fd456c9dfcf48f6 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Thu, 4 May 2023 23:06:47 +0300 -Subject: [PATCH 7/9] nvmem: rockchip-otp: Add support for RK3588 - -Add support for the OTP memory device found on the Rockchip RK3588 SoC. - -While here, remove the unnecessary 'void *' casts in the OF device ID -table. - -Co-developed-by: Finley Xiao -Signed-off-by: Finley Xiao -Signed-off-by: Cristian Ciocaltea -Tested-by: Vincent Legoll -Reviewed-by: Heiko Stuebner ---- - drivers/nvmem/rockchip-otp.c | 78 +++++++++++++++++++++++++++++++++++- - 1 file changed, 76 insertions(+), 2 deletions(-) - -diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c -index 84bf956cc4e1..cb9aa5428350 100644 ---- a/drivers/nvmem/rockchip-otp.c -+++ b/drivers/nvmem/rockchip-otp.c -@@ -54,6 +54,19 @@ - - #define OTPC_TIMEOUT 10000 - -+/* RK3588 Register */ -+#define RK3588_OTPC_AUTO_CTRL 0x04 -+#define RK3588_OTPC_AUTO_EN 0x08 -+#define RK3588_OTPC_INT_ST 0x84 -+#define RK3588_OTPC_DOUT0 0x20 -+#define RK3588_NO_SECURE_OFFSET 0x300 -+#define RK3588_NBYTES 4 -+#define RK3588_BURST_NUM 1 -+#define RK3588_BURST_SHIFT 8 -+#define RK3588_ADDR_SHIFT 16 -+#define RK3588_AUTO_EN BIT(0) -+#define RK3588_RD_DONE BIT(1) -+ - struct rockchip_data { - int size; - const char * const *clks; -@@ -171,6 +184,52 @@ static int px30_otp_read(void *context, unsigned int offset, - return ret; - } - -+static int rk3588_otp_read(void *context, unsigned int offset, -+ void *val, size_t bytes) -+{ -+ struct rockchip_otp *otp = context; -+ unsigned int addr_start, addr_end, addr_len; -+ int ret, i = 0; -+ u32 data; -+ u8 *buf; -+ -+ addr_start = round_down(offset, RK3588_NBYTES) / RK3588_NBYTES; -+ addr_end = round_up(offset + bytes, RK3588_NBYTES) / RK3588_NBYTES; -+ addr_len = addr_end - addr_start; -+ addr_start += RK3588_NO_SECURE_OFFSET; -+ -+ buf = kzalloc(array_size(addr_len, RK3588_NBYTES), GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ while (addr_len--) { -+ writel((addr_start << RK3588_ADDR_SHIFT) | -+ (RK3588_BURST_NUM << RK3588_BURST_SHIFT), -+ otp->base + RK3588_OTPC_AUTO_CTRL); -+ writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN); -+ -+ ret = rockchip_otp_wait_status(otp, RK3588_OTPC_INT_ST, -+ RK3588_RD_DONE); -+ if (ret < 0) { -+ dev_err(otp->dev, "timeout during read setup\n"); -+ goto read_end; -+ } -+ -+ data = readl(otp->base + RK3588_OTPC_DOUT0); -+ memcpy(&buf[i], &data, RK3588_NBYTES); -+ -+ i += RK3588_NBYTES; -+ addr_start++; -+ } -+ -+ memcpy(val, buf + offset % RK3588_NBYTES, bytes); -+ -+read_end: -+ kfree(buf); -+ -+ return ret; -+} -+ - static int rockchip_otp_read(void *context, unsigned int offset, - void *val, size_t bytes) - { -@@ -213,14 +272,29 @@ static const struct rockchip_data px30_data = { - .reg_read = px30_otp_read, - }; - -+static const char * const rk3588_otp_clocks[] = { -+ "otp", "apb_pclk", "phy", "arb", -+}; -+ -+static const struct rockchip_data rk3588_data = { -+ .size = 0x400, -+ .clks = rk3588_otp_clocks, -+ .num_clks = ARRAY_SIZE(rk3588_otp_clocks), -+ .reg_read = rk3588_otp_read, -+}; -+ - static const struct of_device_id rockchip_otp_match[] = { - { - .compatible = "rockchip,px30-otp", -- .data = (void *)&px30_data, -+ .data = &px30_data, - }, - { - .compatible = "rockchip,rk3308-otp", -- .data = (void *)&px30_data, -+ .data = &px30_data, -+ }, -+ { -+ .compatible = "rockchip,rk3588-otp", -+ .data = &rk3588_data, - }, - { /* sentinel */ }, - }; --- -2.41.0 - - -From 4e3178487898d3e21deb144dfa967b4f8c71c8f3 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Thu, 4 May 2023 23:06:48 +0300 -Subject: [PATCH 8/9] arm64: dts: rockchip: Add rk3588 OTP node - -Add DT node for Rockchip RK3588/RK3588S OTP memory. - -Co-developed-by: Finley Xiao -Signed-off-by: Finley Xiao -Signed-off-by: Cristian Ciocaltea -Tested-by: Vincent Legoll ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 54 +++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 7b93abd8f65c..977ed617f59e 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1841,6 +1841,60 @@ spi4: spi@fecb0000 { - status = "disabled"; - }; - -+ otp: efuse@fecc0000 { -+ compatible = "rockchip,rk3588-otp"; -+ reg = <0x0 0xfecc0000 0x0 0x400>; -+ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, -+ <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; -+ clock-names = "otp", "apb_pclk", "phy", "arb"; -+ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, -+ <&cru SRST_OTPC_ARB>; -+ reset-names = "otp", "apb", "arb"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ cpu_code: cpu-code@2 { -+ reg = <0x02 0x2>; -+ }; -+ -+ otp_id: id@7 { -+ reg = <0x07 0x10>; -+ }; -+ -+ otp_cpu_version: cpu-version@1c { -+ reg = <0x1c 0x1>; -+ bits = <3 3>; -+ }; -+ -+ cpub0_leakage: cpu-leakage@17 { -+ reg = <0x17 0x1>; -+ }; -+ -+ cpub1_leakage: cpu-leakage@18 { -+ reg = <0x18 0x1>; -+ }; -+ -+ cpul_leakage: cpu-leakage@19 { -+ reg = <0x19 0x1>; -+ }; -+ -+ log_leakage: log-leakage@1a { -+ reg = <0x1a 0x1>; -+ }; -+ -+ gpu_leakage: gpu-leakage@1b { -+ reg = <0x1b 0x1>; -+ }; -+ -+ npu_leakage: npu-leakage@28 { -+ reg = <0x28 0x1>; -+ }; -+ -+ codec_leakage: codec-leakage@29 { -+ reg = <0x29 0x1>; -+ }; -+ }; -+ - dmac2: dma-controller@fed10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfed10000 0x0 0x4000>; --- -2.41.0 - - -From 39e135bbe54da0a6ddf98d183c0b4f3f248b17b1 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sun, 4 Jun 2023 20:13:45 +0300 -Subject: [PATCH 9/9] arm64: defconfig: Enable Rockchip OTP memory driver - -The Rockchip one-time programmable memory driver provides access to -various SoC specific information, e.g. leakage currents of the -CPU/GPU/NPU components found on a RK3588 SoC. - -Enable the driver as built-in to allow client device drivers (e.g. -cpufreq) to access the required data for proper settings adjustment. - -Signed-off-by: Cristian Ciocaltea ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index a24609e14d50..6ef220d383d3 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -1385,6 +1385,7 @@ CONFIG_NVMEM_MTK_EFUSE=y - CONFIG_NVMEM_QCOM_QFPROM=y - CONFIG_NVMEM_RMEM=m - CONFIG_NVMEM_ROCKCHIP_EFUSE=y -+CONFIG_NVMEM_ROCKCHIP_OTP=y - CONFIG_NVMEM_SNVS_LPGPR=y - CONFIG_NVMEM_SPMI_SDAM=m - CONFIG_NVMEM_SUNXI_SID=y --- -2.41.0 - diff --git a/patch/kernel/rockchip-rk3588-edge/0026-Add-RK3588-USB3-Support.patch b/patch/kernel/rockchip-rk3588-edge/0023-Add-RK3588-USB3-Support.patch similarity index 98% rename from patch/kernel/rockchip-rk3588-edge/0026-Add-RK3588-USB3-Support.patch rename to patch/kernel/rockchip-rk3588-edge/0023-Add-RK3588-USB3-Support.patch index 279c0e431..7f37e7d74 100644 --- a/patch/kernel/rockchip-rk3588-edge/0026-Add-RK3588-USB3-Support.patch +++ b/patch/kernel/rockchip-rk3588-edge/0023-Add-RK3588-USB3-Support.patch @@ -1,4 +1,4 @@ -From 0a75395f2d9bac99a964668b560508daefbbd3cd Mon Sep 17 00:00:00 2001 +From 983b4443be14f1b62f2f0e5ccf3e7d3894f71081 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 25 Apr 2023 17:38:57 +0200 Subject: [PATCH 1/6] dt-bindings: phy: add rockchip usbdp combo phy document @@ -190,7 +190,7 @@ index 000000000000..dcca84d57e99 2.41.0 -From 22cd81086f9197d6b7f6aa851d6338625a426fd9 Mon Sep 17 00:00:00 2001 +From 98c5c2cdd1efd0d775f78af54f7b690b0f634e37 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 30 May 2023 16:40:02 +0200 Subject: [PATCH 2/6] dt-bindings: usb: rockchip,dwc3: Add RK3588 binding @@ -351,7 +351,7 @@ index 3159f9a6a0f7..0db4dc86e506 100644 2.41.0 -From e8991b26f1835f53c4e318eb02bb9953949595dc Mon Sep 17 00:00:00 2001 +From 099abe585ba9ed6376355d75bc0b79bd9b6cac94 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 30 May 2023 18:49:48 +0200 Subject: [PATCH 3/6] dt-bindings: soc: rockchip: add rk3588 USB3 syscon @@ -364,10 +364,10 @@ Signed-off-by: Sebastian Reichel 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml -index 65a2d5a4f28d..8d15c10a8f7e 100644 +index e4fa6a07b4fa..ce1fd5b0d669 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml -@@ -27,6 +27,9 @@ properties: +@@ -28,6 +28,9 @@ properties: - rockchip,rk3588-sys-grf - rockchip,rk3588-pcie3-phy-grf - rockchip,rk3588-pcie3-pipe-grf @@ -377,7 +377,7 @@ index 65a2d5a4f28d..8d15c10a8f7e 100644 - rockchip,rv1108-usbgrf - const: syscon - items: -@@ -62,6 +65,9 @@ properties: +@@ -64,6 +67,9 @@ properties: reg: maxItems: 1 @@ -387,7 +387,7 @@ index 65a2d5a4f28d..8d15c10a8f7e 100644 "#address-cells": const: 1 -@@ -242,6 +248,22 @@ allOf: +@@ -245,6 +251,22 @@ allOf: unevaluatedProperties: false @@ -414,7 +414,7 @@ index 65a2d5a4f28d..8d15c10a8f7e 100644 2.41.0 -From 50e9c28ab2696125dfef1f12db3a835b70a05b7f Mon Sep 17 00:00:00 2001 +From 76dce9a4e101c5f961f91a3ddef99660081cadd5 Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Tue, 25 Apr 2023 15:55:54 +0200 Subject: [PATCH 4/6] phy: rockchip: add usbdp combo phy driver @@ -2207,7 +2207,7 @@ index 000000000000..414081b1247d 2.41.0 -From 1a7e20bc463d7907be231c481b79bdfc5b43edd3 Mon Sep 17 00:00:00 2001 +From 15e8ed9380726e7f27c886faa43df7be484f61e8 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 25 Apr 2023 17:49:04 +0200 Subject: [PATCH 5/6] arm64: dts: rockchip: rk3588s: Add USBDP phy nodes @@ -2221,7 +2221,7 @@ Signed-off-by: Sebastian Reichel 2 files changed, 137 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -index 40fee1367b34..53a6650640ff 100644 +index 5c61cce52a21..1add38695816 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -12,6 +12,38 @@ pipe_phy1_grf: syscon@fd5c0000 { @@ -2302,10 +2302,10 @@ index 40fee1367b34..53a6650640ff 100644 compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee10000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 37e323ec9d74..a4a8ac4208b9 100644 +index a009c4414256..598cc3500e1f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -448,6 +448,33 @@ sys_grf: syscon@fd58c000 { +@@ -890,6 +890,33 @@ sys_grf: syscon@fd58c000 { reg = <0x0 0xfd58c000 0x0 0x1000>; }; @@ -2339,7 +2339,7 @@ index 37e323ec9d74..a4a8ac4208b9 100644 usb2phy2_grf: syscon@fd5d8000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; reg = <0x0 0xfd5d8000 0x0 0x4000>; -@@ -473,6 +500,17 @@ u2phy2_host: host-port { +@@ -915,6 +942,17 @@ u2phy2_host: host-port { }; }; @@ -2357,7 +2357,7 @@ index 37e323ec9d74..a4a8ac4208b9 100644 usb2phy3_grf: syscon@fd5dc000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; reg = <0x0 0xfd5dc000 0x0 0x4000>; -@@ -513,6 +551,11 @@ pipe_phy2_grf: syscon@fd5c4000 { +@@ -965,6 +1003,11 @@ pipe_phy2_grf: syscon@fd5c4000 { reg = <0x0 0xfd5c4000 0x0 0x100>; }; @@ -2369,7 +2369,7 @@ index 37e323ec9d74..a4a8ac4208b9 100644 ioc: syscon@fd5f0000 { compatible = "rockchip,rk3588-ioc", "syscon"; reg = <0x0 0xfd5f0000 0x0 0x10000>; -@@ -2166,6 +2209,37 @@ dmac2: dma-controller@fed10000 { +@@ -2655,6 +2698,37 @@ dmac2: dma-controller@fed10000 { #dma-cells = <1>; }; @@ -2411,7 +2411,7 @@ index 37e323ec9d74..a4a8ac4208b9 100644 2.41.0 -From aa1ed927eddcfd728bdca5dbab9e4980b7dd5085 Mon Sep 17 00:00:00 2001 +From c062260a0e652da798f7130ec25c6452957456d5 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 25 Apr 2023 18:17:19 +0200 Subject: [PATCH 6/6] arm64: dts: rockchip: rk3588s: Add USB3 controllers @@ -2425,7 +2425,7 @@ Signed-off-by: Sebastian Reichel 2 files changed, 87 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi -index 53a6650640ff..e0992662b9c6 100644 +index 1add38695816..7b7891771438 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,34 @@ @@ -2472,10 +2472,10 @@ index 53a6650640ff..e0992662b9c6 100644 u2phy1_otg: otg-port { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index a4a8ac4208b9..b46574358dd1 100644 +index 598cc3500e1f..5a2469d05356 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -399,6 +399,36 @@ scmi_shmem: sram@0 { +@@ -841,6 +841,36 @@ scmi_shmem: sram@0 { }; }; @@ -2512,7 +2512,7 @@ index a4a8ac4208b9..b46574358dd1 100644 usb_host0_ehci: usb@fc800000 { compatible = "rockchip,rk3588-ehci", "generic-ehci"; reg = <0x0 0xfc800000 0x0 0x40000>; -@@ -443,6 +473,35 @@ usb_host1_ohci: usb@fc8c0000 { +@@ -885,6 +915,35 @@ usb_host1_ohci: usb@fc8c0000 { status = "disabled"; }; @@ -2548,7 +2548,7 @@ index a4a8ac4208b9..b46574358dd1 100644 sys_grf: syscon@fd58c000 { compatible = "rockchip,rk3588-sys-grf", "syscon"; reg = <0x0 0xfd58c000 0x0 0x1000>; -@@ -465,7 +524,6 @@ u2phy0: usb2-phy@0 { +@@ -907,7 +966,6 @@ u2phy0: usb2-phy@0 { clock-names = "phyclk"; clock-output-names = "usb480m_phy0"; #clock-cells = <0>; diff --git a/patch/kernel/rockchip-rk3588-edge/0024-enable-ethernet-for-rock-5b.patch b/patch/kernel/rockchip-rk3588-edge/0024-enable-ethernet-for-rock-5b.patch deleted file mode 100644 index a73fa3109..000000000 --- a/patch/kernel/rockchip-rk3588-edge/0024-enable-ethernet-for-rock-5b.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 2ca760c84e3764248233fe8891133f811d16aa2e Mon Sep 17 00:00:00 2001 -From: Lucas Tanure -Date: Thu, 23 Mar 2023 12:27:19 +0000 -Subject: [PATCH] arm64: defconfig: Enable ethernet for Rock 5B - -Signed-off-by: Lucas Tanure ---- - arch/arm64/configs/defconfig | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 0777bcae9104b..2982169691f31 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -221,6 +221,7 @@ CONFIG_PCIE_ALTERA=y - CONFIG_PCIE_ALTERA_MSI=y - CONFIG_PCI_HOST_THUNDER_PEM=y - CONFIG_PCI_HOST_THUNDER_ECAM=y -+CONFIG_PCIE_ROCKCHIP_DW_HOST=y - CONFIG_PCIE_ROCKCHIP_HOST=m - CONFIG_PCIE_MEDIATEK_GEN3=m - CONFIG_PCIE_BRCMSTB=m -@@ -1385,6 +1386,7 @@ CONFIG_PHY_RCAR_GEN3_PCIE=y - CONFIG_PHY_RCAR_GEN3_USB2=y - CONFIG_PHY_RCAR_GEN3_USB3=m - CONFIG_PHY_ROCKCHIP_EMMC=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y - CONFIG_PHY_ROCKCHIP_INNO_HDMI=m - CONFIG_PHY_ROCKCHIP_INNO_USB2=y - CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m --- -GitLab - diff --git a/patch/kernel/rockchip-rk3588-edge/0028-arm64-dts-rockchip-rk3588-add-sfc-node.patch b/patch/kernel/rockchip-rk3588-edge/0025-arm64-dts-rockchip-rk3588-add-sfc-node.patch similarity index 100% rename from patch/kernel/rockchip-rk3588-edge/0028-arm64-dts-rockchip-rk3588-add-sfc-node.patch rename to patch/kernel/rockchip-rk3588-edge/0025-arm64-dts-rockchip-rk3588-add-sfc-node.patch diff --git a/patch/kernel/rockchip-rk3588-edge/0027-Add-Support-for-RK3588s-Indiedroid-Nova.patch b/patch/kernel/rockchip-rk3588-edge/0027-Add-Support-for-RK3588s-Indiedroid-Nova.patch deleted file mode 100644 index f933b7b9b..000000000 --- a/patch/kernel/rockchip-rk3588-edge/0027-Add-Support-for-RK3588s-Indiedroid-Nova.patch +++ /dev/null @@ -1,968 +0,0 @@ -From 091209864a90c83e11926cf484dbc4a86c34bcfe Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Wed, 31 May 2023 11:12:16 -0500 -Subject: [PATCH 1/5] arm64: dts: rockchip: add default pinctrl for rk3588 emmc - -Add a default pinctrl definition for the rk3588 emmc. - -Signed-off-by: Chris Morgan -Reviewed-by: Sebastian Reichel ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index a3124bd2e092..03462ae13ac7 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1196,6 +1196,9 @@ sdhci: mmc@fe2e0000 { - <&cru TMCLK_EMMC>; - clock-names = "core", "bus", "axi", "block", "timer"; - max-frequency = <200000000>; -+ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, -+ <&emmc_cmd>, <&emmc_data_strobe>; -+ pinctrl-names = "default"; - resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, - <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, - <&cru SRST_T_EMMC>; --- -2.41.0 - - -From 9ac1b750fa33e5a340eaee65cf1085cad9ede25d Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Wed, 31 May 2023 11:12:17 -0500 -Subject: [PATCH 2/5] arm64: dts: rockchip: Add sdio node to rk3588 - -Add SDIO node for rk3588/rk3588s. - -Signed-off-by: Chris Morgan -Reviewed-by: Sebastian Reichel ---- - arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -index 03462ae13ac7..7b93abd8f65c 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi -@@ -1185,6 +1185,21 @@ sdmmc: mmc@fe2c0000 { - status = "disabled"; - }; - -+ sdio: mmc@fe2d0000 { -+ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; -+ reg = <0x00 0xfe2d0000 0x00 0x4000>; -+ interrupts = ; -+ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, -+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; -+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -+ fifo-depth = <0x100>; -+ max-frequency = <200000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdiom1_pins>; -+ power-domains = <&power RK3588_PD_SDIO>; -+ status = "disabled"; -+ }; -+ - sdhci: mmc@fe2e0000 { - compatible = "rockchip,rk3588-dwcmshc"; - reg = <0x0 0xfe2e0000 0x0 0x10000>; --- -2.41.0 - - -From 5799db8897382289eb29505050b6940ef5587628 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Wed, 31 May 2023 11:12:18 -0500 -Subject: [PATCH 3/5] dt-bindings: vendor-prefixes: add Indiedroid - -Indiedroid is a sub-brand of Ameridroid for their line of single board -computers. -https://indiedroid.us/ - -Signed-off-by: Chris Morgan -Acked-by: Krzysztof Kozlowski ---- - Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml -index 82d39ab0231b..580f32086d55 100644 ---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml -+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -617,6 +617,8 @@ patternProperties: - description: Integrated Micro-Electronics Inc. - "^incircuit,.*": - description: In-Circuit GmbH -+ "^indiedroid,.*": -+ description: Indiedroid - "^inet-tek,.*": - description: Shenzhen iNet Mobile Internet Technology Co., Ltd - "^infineon,.*": --- -2.41.0 - - -From abebfc368ca4c72ae0f789fb72a62a00fcb417f5 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Wed, 31 May 2023 11:12:19 -0500 -Subject: [PATCH 4/5] dt-bindings: arm: rockchip: Add Indiedroid Nova - -Add Indiedroid Nova, an rk3588s based single board computer. - -Signed-off-by: Chris Morgan -Acked-by: Conor Dooley ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index ec141c937b8b..3c5a204bcd81 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -542,6 +542,11 @@ properties: - - khadas,edge-v - - const: rockchip,rk3399 - -+ - description: Indiedroid Nova SBC -+ items: -+ - const: indiedroid,nova -+ - const: rockchip,rk3588s -+ - - description: Khadas Edge2 series boards - items: - - const: khadas,edge2 --- -2.41.0 - - -From 6b199a6dfde0f0f521d88b45df884dc3b5743571 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Wed, 31 May 2023 11:12:20 -0500 -Subject: [PATCH 5/5] arm64: dts: rockchip: Add Indiedroid Nova board - -The Indiedroid Nova is an SBC from a sub-brand of Ameridroid that -includes the following hardware: - - - A 40-pin GPIO header - - 2 USB-A 3.0 ports - - 2 USB-A 2.0 ports - - A USB-C 2.0 OTG port (used for USB power delivery) - - A USB-C 3.0 port that can do display port output. - - A Micro HDMI 2.1 port. - - A 1GB ethernet port. - - An RT8821CS based WiFi/Bluetooth module. - - A user replaceable eMMC module. - - An SDMMC card slot. - - A MIPI DSI connector. - - A MIPI CSI connector. - - A 3.5mm TRRS audio jack with microphone input. - - An 2 pin socket for an RTC battery. - - A 4 pin socket for a debug port. - - A power button (connected to PMIC), a reset button (connected to SoC - reset), a boot button, and a recovery button (both connected to the - ADC). - - 4GB, 8GB, or 16GB of system RAM. - -This initial devicetree includes support for the WiFi, bluetooth, -analog audio out/in, SDMMC, eMMC, RTC, UART debugging, and has -the regulator values from the schematics. ADC, graphics output, GPU, -USB, and wired ethernet are still pending additional upstream changes. - -Analog audio will require changes to handle a difference between the -requested clock frequency of 12288000 and the actual clock freqency -of 12287999 before it will work properly. This will be done in a -subsequent patch series. - -Signed-off-by: Chris Morgan ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../dts/rockchip/rk3588s-indiedroid-nova.dts | 764 ++++++++++++++++++ - 2 files changed, 765 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 2d585bbb8f3a..99f11db8158d 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -94,5 +94,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts -new file mode 100644 -index 000000000000..add15cdafe76 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts -@@ -0,0 +1,764 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include "rk3588s.dtsi" -+ -+/ { -+ model = "Indiedroid Nova"; -+ compatible = "indiedroid,nova", "rockchip,rk3588s"; -+ -+ aliases { -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc; -+ mmc2 = &sdio; -+ serial2 = &uart2; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clock-names = "ext_clock"; -+ clocks = <&rtc_hym8563>; -+ pinctrl-0 = <&wifi_enable_h>; -+ pinctrl-names = "default"; -+ post-power-on-delay-ms = <200>; -+ reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; -+ }; -+ -+ sound { -+ compatible = "audio-graph-card"; -+ label = "rockchip,es8388-codec"; -+ widgets = "Microphone", "Mic Jack", -+ "Headphone", "Headphones"; -+ routing = "LINPUT2", "Mic Jack", -+ "Headphones", "LOUT1", -+ "Headphones", "ROUT1"; -+ dais = <&i2s0_8ch_p0>; -+ }; -+ -+ vbus5v0_typec: vbus5v0-typec { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&typec5v_pwren>; -+ pinctrl-names = "default"; -+ regulator-name = "vbus5v0_typec"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <1100000>; -+ regulator-min-microvolt = <1100000>; -+ regulator-name = "vcc_1v1_nldo_s3"; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ /* Regulator is enabled whenever vcc_1v8_s0 is above 1.6v */ -+ vcc_3v3_s0: vcc-3v3-s0 { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <3300000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-name = "vcc_3v3_s0"; -+ vin-supply = <&vcc_3v3_s3>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <5000000>; -+ regulator-min-microvolt = <5000000>; -+ regulator-name = "vcc5v0_sys"; -+ }; -+ -+ vcc5v0_usb: vcc5v0-usb { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <5000000>; -+ regulator-min-microvolt = <5000000>; -+ regulator-name = "vcc5v0_usb"; -+ vin-supply = <&vcc5v0_usbdcin>; -+ }; -+ -+ vcc5v0_usbdcin: vcc5v0-usbdcin { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <5000000>; -+ regulator-min-microvolt = <5000000>; -+ regulator-name = "vcc5v0_usbdcin"; -+ }; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_b0{ -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b1{ -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b2{ -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_b3{ -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+/* -+ * Add labels for each GPIO pin exposed on the 40 pin header. Note that -+ * voltage of each GPIO pin could be either 3.3v or 1.8v (as noted by -+ * label). -+ */ -+&gpio0 { -+ gpio-line-names = /* GPIO0 A0-A7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO0 B0-B7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO0 C0-C7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO0 D0-D7 */ -+ "HEADER_12_1v8", "", "", "HEADER_24_1v8", -+ "", "", "", ""; -+}; -+ -+&gpio1 { -+ gpio-line-names = /* GPIO1 A0-A7 */ -+ "HEADER_27_3v3", "HEADER_28_3v3", "", "", -+ "HEADER_29_1v8", "", "HEADER_7_1v8", "", -+ /* GPIO1 B0-B7 */ -+ "", "HEADER_31_1v8", "HEADER_33_1v8", "", -+ "HEADER_11_1v8", "HEADER_13_1v8", "", "", -+ /* GPIO1 C0-C7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO1 D0-D7 */ -+ "", "", "", "", -+ "", "", "HEADER_5_3v3", "HEADER_3_3v3"; -+}; -+ -+&gpio3 { -+ gpio-line-names = /* GPIO3 A0-A7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO3 B0-B7 */ -+ "HEADER_16_1v8", "HEADER_18_1v8", "", "", -+ "", "", "", "HEADER_19_1v8", -+ /* GPIO3 C0-C7 */ -+ "HEADER_21_1v8", "HEADER_23_1v8", "", "HEADER_26_1v8", -+ "HEADER_15_1v8", "HEADER_22_1v8", "", "", -+ /* GPIO3 D0-D7 */ -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = /* GPIO4 A0-A7 */ -+ "", "", "HEADER_37_3v3", "HEADER_32_3v3", -+ "HEADER_36_3v3", "", "HEADER_35_3v3", "HEADER_38_3v3", -+ /* GPIO4 B0-B7 */ -+ "", "", "", "HEADER_40_3v3", -+ "HEADER_8_3v3", "HEADER_10_3v3", "", "", -+ /* GPIO4 C0-C7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO4 D0-D7 */ -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&i2c0 { -+ pinctrl-0 = <&i2c0m2_xfer>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ vdd_cpu_big0_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <1050000>; -+ regulator-min-microvolt = <550000>; -+ regulator-name = "vdd_cpu_big0_s0"; -+ regulator-ramp-delay = <2300>; -+ fcs,suspend-voltage-selector = <1>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big1_s0: regulator@43 { -+ compatible = "rockchip,rk8603", "rockchip,rk8602"; -+ reg = <0x43>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <1050000>; -+ regulator-min-microvolt = <550000>; -+ regulator-name = "vdd_cpu_big1_s0"; -+ regulator-ramp-delay = <2300>; -+ fcs,suspend-voltage-selector = <1>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ status = "okay"; -+ -+ vdd_npu_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <950000>; -+ regulator-min-microvolt = <550000>; -+ regulator-name = "vdd_npu_s0"; -+ regulator-ramp-delay = <2300>; -+ fcs,suspend-voltage-selector = <1>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c6 { -+ pinctrl-0 = <&i2c6m3_xfer>; -+ status = "okay"; -+ -+ fusb302: typec-portc@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-0 = <&usbc0_int>; -+ pinctrl-names = "default"; -+ vbus-supply = <&vbus5v0_typec>; -+ -+ connector { -+ compatible = "usb-c-connector"; -+ data-role = "dual"; -+ label = "USB-C"; -+ power-role = "dual"; -+ try-power-role = "sink"; -+ source-pdos = ; -+ sink-pdos = ; -+ op-sink-microwatt = <1000000>; -+ }; -+ }; -+ -+ rtc_hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ clock-output-names = "hym8563"; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-0 = <&hym8563_int>; -+ pinctrl-names = "default"; -+ wakeup-source; -+ }; -+}; -+ -+&i2c7 { -+ pinctrl-0 = <&i2c7m0_xfer>; -+ status = "okay"; -+ -+ es8388: audio-codec@11 { -+ compatible = "everest,es8388"; -+ reg = <0x11>; -+ assigned-clock-rates = <12288000>; -+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; -+ AVDD-supply = <&vcc_3v3_s3>; -+ clock-names = "mclk"; -+ clocks = <&cru I2S0_8CH_MCLKOUT>; -+ DVDD-supply = <&vcc_1v8_s3>; -+ HPVDD-supply = <&vcc_3v3_s3>; -+ PVDD-supply = <&vcc_1v8_s3>; -+ #sound-dai-cells = <0>; -+ -+ port { -+ es8388_p0_0: endpoint { -+ remote-endpoint = <&i2s0_8ch_p0_0>; -+ }; -+ }; -+ }; -+}; -+ -+&i2s0_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s0_lrck -+ &i2s0_mclk -+ &i2s0_sclk -+ &i2s0_sdi0 -+ &i2s0_sdo0>; -+ status = "okay"; -+ -+ i2s0_8ch_p0: port { -+ i2s0_8ch_p0_0: endpoint { -+ dai-format = "i2s"; -+ mclk-fs = <256>; -+ remote-endpoint = <&es8388_p0_0>; -+ }; -+ }; -+}; -+ -+ -+&pinctrl { -+ bluetooth-pins { -+ bt_reset: bt-reset { -+ rockchip,pins = -+ <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_dev: bt-wake-dev { -+ rockchip,pins = -+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_wake_host: bt-wake-host { -+ rockchip,pins = -+ <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ hym8563 { -+ -+ hym8563_int: hym8563-int { -+ rockchip,pins = -+ <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = -+ <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb-typec { -+ usbc0_int: usbc0-int { -+ rockchip,pins = -+ <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ typec5v_pwren: typec5v-pwren { -+ rockchip,pins = -+ <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+/* HS400 modes seemed to cause io errors. */ -+&sdhci { -+ bus-width = <8>; -+ no-mmc-hs400; -+ no-sd; -+ no-sdio; -+ non-removable; -+ max-frequency = <200000000>; -+ vmmc-supply = <&vcc_3v3_s0>; -+ vqmmc-supply = <&vcc_1v8_s3>; -+ status = "okay"; -+}; -+ -+&sdio { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ disable-wp; -+ keep-power-in-suspend; -+ max-frequency = <100000000>; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ no-mmc; -+ no-sd; -+ non-removable; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3_s3>; -+ vqmmc-supply = <&vcc_1v8_s3>; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ max-frequency = <200000000>; -+ no-sdio; -+ no-mmc; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3_s3>; -+ vqmmc-supply = <&vccio_sd_s0>; -+ status = "okay"; -+}; -+ -+&spi2 { -+ #address-cells = <1>; -+ assigned-clocks = <&cru CLK_SPI2>; -+ assigned-clock-rates = <200000000>; -+ num-cs = <1>; -+ pinctrl-0 = <&spi2m2_pins>, <&spi2m2_cs0>; -+ pinctrl-names = "default"; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ reg = <0x0>; -+ #gpio-cells = <2>; -+ gpio-controller; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -+ <&rk806_dvs2_null>, <&rk806_dvs3_null>; -+ pinctrl-names = "default"; -+ spi-max-frequency = <1000000>; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc5v0_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc5v0_sys>; -+ vcc13-supply = <&vcc_1v1_nldo_s3>; -+ vcc14-supply = <&vcc_1v1_nldo_s3>; -+ vcca-supply = <&vcc5v0_sys>; -+ -+ rk806_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ regulators { -+ vdd_gpu_s0: dcdc-reg1 { -+ regulator-boot-on; -+ regulator-enable-ramp-delay = <400>; -+ regulator-max-microvolt = <950000>; -+ regulator-min-microvolt = <550000>; -+ regulator-name = "vdd_gpu_s0"; -+ regulator-ramp-delay = <12500>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_s0: dcdc-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <950000>; -+ regulator-min-microvolt = <550000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_lit_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_logic_s0: dcdc-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <750000>; -+ regulator-min-microvolt = <675000>; -+ regulator-name = "vdd_logic_s0"; -+ regulator-ramp-delay = <12500>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: dcdc-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <950000>; -+ regulator-min-microvolt = <550000>; -+ regulator-name = "vdd_vdenc_s0"; -+ regulator-ramp-delay = <12500>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_s0: dcdc-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <850000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_ddr_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vdd2_ddr_s3: dcdc-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <1100000>; -+ regulator-min-microvolt = <1100000>; -+ regulator-name = "vdd2_ddr_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <2000000>; -+ regulator-min-microvolt = <2000000>; -+ regulator-name = "vdd_2v0_pldo_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vcc_3v3_s3: dcdc-reg8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <3300000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-name = "vcc_3v3_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vddq_ddr_s0: dcdc-reg9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <600000>; -+ regulator-min-microvolt = <600000>; -+ regulator-name = "vddq_ddr_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s3: dcdc-reg10 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_1v8_s0: pldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca_1v8_s0: pldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-name = "vcca_1v8_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdda_1v2_s0: pldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <1200000>; -+ regulator-min-microvolt = <1200000>; -+ regulator-name = "vdda_1v2_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca_3v3_s0: pldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <3300000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-name = "vcca_3v3_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <3300000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-name = "vccio_sd_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s3_pldo6: pldo-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s3_pldo6"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <750000>; -+ regulator-min-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s3"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdda_ddr_pll_s0: nldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <850000>; -+ regulator-min-microvolt = <850000>; -+ regulator-name = "vdda_ddr_pll_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ avdd_0v75_s0: nldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <750000>; -+ regulator-min-microvolt = <750000>; -+ regulator-name = "avdd_0v75_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v85_s0: nldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdda_0v85_s0"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ /* Schematics show not in use */ -+ nldo-reg5 { -+ }; -+ }; -+ }; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m0_xfer>; -+ status = "okay"; -+}; -+ -+/* DMA seems to interfere with bluetooth device normal operation. */ -+&uart9 { -+ pinctrl-0 = <&uart9m2_xfer>, <&uart9m2_ctsn>, <&uart9m2_rtsn>; -+ pinctrl-names = "default"; -+ /delete-property/ dma-names; -+ /delete-property/ dmas; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "realtek,rtl8821cs-bt", -+ "realtek,rtl8723bs-bt"; -+ device-wake-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; -+ enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ host-wake-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&bt_reset>, <&bt_wake_dev>, <&bt_wake_host>; -+ pinctrl-names = "default"; -+ }; -+}; --- -2.41.0 -