9e29827ad9
- `risc-v`: rework RichNeese's boards, reduce families, move tweaks to boards - `risc-v`/`starfive`: `CONFIG_MOTORCOMM_PHY=m` for the onboard Ethernet - `risc-v`/`starfive`: use mainline kernel 6.1.y, with StarFive's rebased patches against `v6.1.5` - from https://github.com/starfive-tech/linux/commits/visionfive - contention point: `1022-soc-sifive-ccache-Add-StarFive-JH71x0-support.patch` which I merged half-assed, need review/fixes? - `risc-v`/`starfive`: update kernel config, sans changes - `risc-v`/`starfive`: switch from `grub` to `extlinux` - `risc-v`/`starfive`: new `starfive` family with their (vendor) kernel Co-authored-by: Richard Neese <r.neese@gmail.com>
42 lines
1.5 KiB
Diff
42 lines
1.5 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: "sw.multimedia" <sw.multimedia@starfivetech.com>
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Date: Tue, 31 Aug 2021 16:48:57 +0800
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Subject: drm/i2c/tda998x: Hardcode register values for Starlight
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A proper solution to this hack should be found.
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Signed-off-by: jack.zhu <jack.zhu@starfivetech.com>
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Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>
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---
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drivers/gpu/drm/i2c/tda998x_drv.c | 7 +++++--
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1 file changed, 5 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
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index d444e7fffb54..bf40966518fd 100644
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--- a/drivers/gpu/drm/i2c/tda998x_drv.c
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+++ b/drivers/gpu/drm/i2c/tda998x_drv.c
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@@ -1604,7 +1604,9 @@ static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
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reg |= VIP_CNTRL_3_H_TGL;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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reg |= VIP_CNTRL_3_V_TGL;
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- reg_write(priv, REG_VIP_CNTRL_3, reg);
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+ //reg_write(priv, REG_VIP_CNTRL_3, reg);
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+ reg_write(priv, REG_VIP_CNTRL_3, 0x26);
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+ reg_write(priv, REG_VIDFORMAT, 0x06);
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reg_write(priv, REG_VIDFORMAT, 0x00);
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reg_write16(priv, REG_REFPIX_MSB, ref_pix);
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@@ -1642,7 +1644,8 @@ static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
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reg |= TBG_CNTRL_1_H_TGL;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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reg |= TBG_CNTRL_1_V_TGL;
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- reg_write(priv, REG_TBG_CNTRL_1, reg);
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+ //reg_write(priv, REG_TBG_CNTRL_1, reg);
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+ reg_write(priv, REG_TBG_CNTRL_1, 0x46);
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/* must be last register set: */
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reg_write(priv, REG_TBG_CNTRL_0, 0);
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--
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Armbian
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