From 5869ca83ae4826e719a0b317a9fc90cb436a72f8 Mon Sep 17 00:00:00 2001 From: Banana Pi -BPI Date: Sun, 29 Oct 2023 16:34:49 +0800 Subject: [PATCH] v2021.07 (pi) --- .azure-pipelines.yml | 454 --------------- .checkpatch.conf | 36 -- .gitattributes | 5 - .github/pull_request_template.md | 6 - .gitlab-ci.yml | 340 ------------ .mailmap | 53 -- .readthedocs.yml | 19 - arch/arm/Kconfig | 2 + arch/arm/dts/Makefile | 17 +- arch/arm/dts/sun50i-a64-olinuxino.dts | 10 + arch/arm/dts/sun50i-a64-orangepi-win.dts | 20 + arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts | 125 +++++ arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts | 126 +++++ arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts | 113 ++++ arch/arm/dts/sun50i-h6-orangepi-3.dts | 256 ++------- arch/arm/dts/sun50i-h6-pine-h64-model-b.dts | 1 + arch/arm/dts/sun50i-h616-orangepi-zero2-b.dts | 248 +++++++++ .../dts/sun50i-h616-orangepi-zero2-lts.dts | 248 +++++++++ arch/arm/dts/sun50i-h616-orangepi-zero2.dts | 6 +- arch/arm/dts/sun50i-h616-orangepi-zero2w.dts | 181 ++++++ arch/arm/dts/sun50i-h616-orangepi-zero3.dts | 194 +++++++ arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts | 98 ++++ arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 8 + arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts | 220 ++++++++ arch/arm/dts/sun8i-h3-beelink-x2.dts | 161 +----- arch/arm/dts/sun8i-h3-nanopi-duo2.dts | 173 ++---- arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 17 + arch/arm/dts/sun8i-h3-nanopi-neo.dts | 10 + arch/arm/dts/sun8i-h3-nanopi-r1.dts | 102 ++++ arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts | 92 ++- arch/arm/dts/sun8i-h3-zeropi.dts | 100 ++++ arch/arm/include/asm/arch-sunxi/boot0.h | 21 +- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + .../include/asm/arch-sunxi/dram_sun50i_h616.h | 6 +- arch/arm/mach-sunxi/Kconfig | 71 ++- arch/arm/mach-sunxi/board.c | 17 +- arch/arm/mach-sunxi/clock_sun6i.c | 15 +- arch/arm/mach-sunxi/dram_sun50i_h616.c | 522 ++++++++++++++---- arch/arm/mach-sunxi/dram_timings/Makefile | 5 +- .../arm/mach-sunxi/dram_timings/h616_lpddr3.c | 95 ++++ .../arm/mach-sunxi/dram_timings/h616_lpddr4.c | 97 ++++ arch/arm/mach-sunxi/pmic_bus.c | 7 + arch/arm/mach-sunxi/spl_spi_sunxi.c | 38 +- board/sunxi/board.c | 119 +++- cmd/Kconfig | 1 + cmd/fdt.c | 6 +- common/Kconfig.boot | 3 +- configs/Awsom_defconfig | 31 ++ configs/Bananapi_M2_Ultra_defconfig | 1 + configs/Bananapi_defconfig | 3 +- configs/Bananapi_m2m_defconfig | 1 + configs/Bananapro_defconfig | 2 +- configs/Cubieboard2_defconfig | 4 +- configs/Cubieboard_defconfig | 3 +- configs/Cubietruck_defconfig | 4 +- configs/Lamobo_R1_defconfig | 2 +- configs/Linksprite_pcDuino3_defconfig | 2 +- configs/Mele_A1000_defconfig | 1 + configs/Merrii_Hummingbird_A20_defconfig | 22 + configs/Orangepi_defconfig | 2 +- configs/Orangepi_mini_defconfig | 3 +- configs/Sinovoip_BPI_M3_defconfig | 2 +- configs/a64-olinuxino-emmc_defconfig | 1 + configs/a64-olinuxino_defconfig | 5 + configs/bananapi_m1_plus_defconfig | 1 + configs/bananapi_m2_plus_h3_defconfig | 1 + configs/bananapi_m2_plus_h5_defconfig | 1 + configs/bananapi_m2_zero_defconfig | 1 + configs/bananapi_m64_defconfig | 1 + configs/beelink_x2_defconfig | 19 +- configs/libretech_all_h3_cc_h2_plus_defconfig | 1 + configs/libretech_all_h3_cc_h3_defconfig | 1 + configs/libretech_all_h3_cc_h5_defconfig | 1 + configs/libretech_all_h5_cc_h5_defconfig | 1 + configs/nanopi_a64_defconfig | 1 + configs/nanopi_duo2_defconfig | 21 + configs/nanopi_duo_defconfig | 21 + configs/nanopi_k1_plus_defconfig | 24 + configs/nanopi_m1_defconfig | 1 + configs/nanopi_m1_plus2_defconfig | 23 + configs/nanopi_m1_plus_defconfig | 2 +- configs/nanopi_neo2_defconfig | 4 +- configs/nanopi_neo_air_defconfig | 2 + configs/nanopi_neo_core2_defconfig | 19 + configs/nanopi_neo_defconfig | 2 + configs/nanopi_neo_plus2_defconfig | 2 +- configs/nanopi_r1_defconfig | 22 + configs/orangepi_2_defconfig | 2 + configs/orangepi_3_defconfig | 16 +- configs/orangepi_lite2_defconfig | 1 + configs/orangepi_lite_defconfig | 1 + configs/orangepi_one_defconfig | 1 + configs/orangepi_one_plus_defconfig | 1 + configs/orangepi_pc2_defconfig | 4 +- configs/orangepi_pc_defconfig | 1 + configs/orangepi_plus2e_defconfig | 5 +- configs/orangepi_plus_defconfig | 5 +- configs/orangepi_prime_defconfig | 6 +- configs/orangepi_win_defconfig | 4 + configs/orangepi_zero2_b_defconfig | 17 + configs/orangepi_zero2_defconfig | 2 + configs/orangepi_zero2_lts_defconfig | 20 + configs/orangepi_zero2w_defconfig | 18 + configs/orangepi_zero3_defconfig | 19 + configs/orangepi_zero_defconfig | 4 +- configs/orangepi_zero_plus2_defconfig | 2 +- configs/orangepi_zero_plus2_h3_defconfig | 21 +- configs/orangepi_zero_plus_defconfig | 2 + configs/pine64-lts_defconfig | 1 + configs/pine64_plus_defconfig | 1 + configs/pine_h64-model-b_defconfig | 18 + configs/pine_h64_defconfig | 1 + configs/sunvell_r69_defconfig | 20 + configs/zeropi_defconfig | 21 + drivers/mtd/spi/spi-nor-ids.c | 2 + drivers/power/Kconfig | 14 +- drivers/power/Makefile | 1 + drivers/power/axp313a.c | 86 +++ drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/sun4i_spi.c | 456 +++++++++++++++ drivers/video/bridge/anx6345.c | 92 ++- dts/Kconfig | 6 + include/axp313a.h | 17 + include/axp_pmic.h | 3 + include/config_distro_bootcmd.h | 9 + include/configs/sun8i.h | 2 + include/configs/sunxi-common.h | 15 + lib/efi_loader/efi_var_seed.S | 17 - tools/binman/test/descriptor.bin | Bin 4096 -> 0 bytes tools/patman/test/0000-cover-letter.patch | 23 - .../0001-pci-Correct-cast-for-sandbox.patch | 51 -- ...-for-sandbox-in-fdtdec_setup_mem_siz.patch | 83 --- 133 files changed, 4012 insertions(+), 1811 deletions(-) delete mode 100644 .azure-pipelines.yml delete mode 100644 .checkpatch.conf delete mode 100644 .gitattributes delete mode 100644 .github/pull_request_template.md delete mode 100644 .gitlab-ci.yml delete mode 100644 .mailmap delete mode 100644 .readthedocs.yml create mode 100644 arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts create mode 100644 arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts create mode 100644 arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts create mode 120000 arch/arm/dts/sun50i-h6-pine-h64-model-b.dts create mode 100644 arch/arm/dts/sun50i-h616-orangepi-zero2-b.dts create mode 100644 arch/arm/dts/sun50i-h616-orangepi-zero2-lts.dts create mode 100644 arch/arm/dts/sun50i-h616-orangepi-zero2w.dts create mode 100644 arch/arm/dts/sun50i-h616-orangepi-zero3.dts create mode 100644 arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts create mode 100644 arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts create mode 100644 arch/arm/dts/sun8i-h3-zeropi.dts create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr4.c create mode 100644 configs/Awsom_defconfig create mode 100644 configs/Merrii_Hummingbird_A20_defconfig create mode 100644 configs/nanopi_duo2_defconfig create mode 100644 configs/nanopi_duo_defconfig create mode 100644 configs/nanopi_k1_plus_defconfig create mode 100644 configs/nanopi_m1_plus2_defconfig create mode 100644 configs/nanopi_neo_core2_defconfig create mode 100644 configs/nanopi_r1_defconfig create mode 100644 configs/orangepi_zero2_b_defconfig create mode 100644 configs/orangepi_zero2_lts_defconfig create mode 100644 configs/orangepi_zero2w_defconfig create mode 100644 configs/orangepi_zero3_defconfig create mode 100644 configs/pine_h64-model-b_defconfig create mode 100644 configs/sunvell_r69_defconfig create mode 100644 configs/zeropi_defconfig create mode 100644 drivers/power/axp313a.c create mode 100644 drivers/spi/sun4i_spi.c create mode 100644 include/axp313a.h delete mode 100644 lib/efi_loader/efi_var_seed.S delete mode 100644 tools/binman/test/descriptor.bin delete mode 100644 tools/patman/test/0000-cover-letter.patch delete mode 100644 tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch delete mode 100644 tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml deleted file mode 100644 index 221e600806..0000000000 --- a/.azure-pipelines.yml +++ /dev/null @@ -1,454 +0,0 @@ -variables: - windows_vm: vs2017-win2016 - ubuntu_vm: ubuntu-18.04 - macos_vm: macOS-10.15 - ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200807-02Sep2020 - # Add '-u 0' options for Azure pipelines, otherwise we get "permission - # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", - # since our $(ci_runner_image) user is not root. - container_option: -u 0 - work_dir: /u - -jobs: - - job: tools_only_windows - displayName: 'Ensure host tools build for Windows' - pool: - vmImage: $(windows_vm) - steps: - - powershell: | - (New-Object Net.WebClient).DownloadFile("https://github.com/msys2/msys2-installer/releases/download/2021-06-04/msys2-base-x86_64-20210604.sfx.exe", "sfx.exe") - displayName: 'Install MSYS2' - - script: | - sfx.exe -y -o%CD:~0,2%\ - %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syyuu" - displayName: 'Update MSYS2' - - script: | - %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel" - displayName: 'Install Toolchain' - - script: | - echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh - %CD:~0,2%\msys64\usr\bin\bash -lc "bash build-tools.sh" - displayName: 'Build Host Tools' - env: - # Tell MSYS2 we need a POSIX emulation layer - MSYSTEM: MSYS - # Tell MSYS2 not to ‘cd’ our startup directory to HOME - CHERE_INVOKING: yes - - - job: tools_only_macOS - displayName: 'Ensure host tools build for macOS X' - pool: - vmImage: $(macos_vm) - steps: - - script: brew install make - displayName: Brew install dependencies - - script: | - gmake tools-only_config tools-only NO_SDL=1 \ - HOSTCFLAGS="-I/usr/local/opt/openssl@1.1/include" \ - HOSTLDFLAGS="-L/usr/local/opt/openssl@1.1/lib" \ - -j$(sysctl -n hw.logicalcpu) - displayName: 'Perform tools-only build' - - - job: cppcheck - displayName: 'Static code analysis with cppcheck' - pool: - vmImage: $(ubuntu_vm) - container: - image: $(ci_runner_image) - options: $(container_option) - steps: - - script: cppcheck -j$(nproc) --force --quiet --inline-suppr . - - - job: htmldocs - displayName: 'Build HTML documentation' - pool: - vmImage: $(ubuntu_vm) - container: - image: $(ci_runner_image) - options: $(container_option) - steps: - - script: | - virtualenv -p /usr/bin/python3 /tmp/venvhtml - . /tmp/venvhtml/bin/activate - pip install -r doc/sphinx/requirements.txt - make htmldocs - - - job: todo - displayName: 'Search for TODO within source tree' - pool: - vmImage: $(ubuntu_vm) - container: - image: $(ci_runner_image) - options: $(container_option) - steps: - - script: grep -r TODO . - - script: grep -r FIXME . - - script: grep -r HACK . | grep -v HACKKIT - - - job: sloccount - displayName: 'Some statistics about the code base' - pool: - vmImage: $(ubuntu_vm) - container: - image: $(ci_runner_image) - options: $(container_option) - steps: - - script: sloccount . - - - job: maintainers - displayName: 'Ensure all configs have MAINTAINERS entries' - pool: - vmImage: $(ubuntu_vm) - container: - image: $(ci_runner_image) - options: $(container_option) - steps: - - script: | - if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi - - - job: tools_only - displayName: 'Ensure host tools build' - pool: - vmImage: $(ubuntu_vm) - container: - image: $(ci_runner_image) - options: $(container_option) - steps: - - script: | - make tools-only_config tools-only -j$(nproc) - - - job: envtools - displayName: 'Ensure env tools build' - pool: - vmImage: $(ubuntu_vm) - container: - image: $(ci_runner_image) - options: $(container_option) - steps: - - script: | - make tools-only_config envtools -j$(nproc) - - - job: utils - displayName: 'Run binman, buildman, dtoc, Kconfig and patman testsuites' - pool: - vmImage: $(ubuntu_vm) - steps: - - script: | - cat << EOF > build.sh - set -ex - cd ${WORK_DIR} - EOF - cat << "EOF" >> build.sh - git config --global user.name "Azure Pipelines" - git config --global user.email bmeng.cn@gmail.com - export USER=azure - virtualenv -p /usr/bin/python3 /tmp/venv - . /tmp/venv/bin/activate - pip install -r test/py/requirements.txt - export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl - export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt - export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH} - ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl - ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test - ./tools/buildman/buildman -t - ./tools/dtoc/dtoc -t - ./tools/patman/patman test - make O=${UBOOT_TRAVIS_BUILD_DIR} testconfig - EOF - cat build.sh - # We cannot use "container" like other jobs above, as buildman - # seems to hang forever with pre-configured "container" environment - docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh - - - job: nokia_rx51_test - displayName: 'Run tests for Nokia RX-51 (aka N900)' - pool: - vmImage: $(ubuntu_vm) - container: - image: $(ci_runner_image) - options: $(container_option) - steps: - - script: | - ./tools/buildman/buildman --fetch-arch arm - export PATH=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/:$PATH - test/nokia_rx51_test.sh - - - job: test_py - displayName: 'test.py' - pool: - vmImage: $(ubuntu_vm) - strategy: - matrix: - sandbox: - TEST_PY_BD: "sandbox" - sandbox_clang: - TEST_PY_BD: "sandbox" - OVERRIDE: "-O clang-10" - sandbox_spl: - TEST_PY_BD: "sandbox_spl" - TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl" - sandbox_noinst: - TEST_PY_BD: "sandbox_noinst" - TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl" - sandbox_flattree: - TEST_PY_BD: "sandbox_flattree" - evb_ast2500: - TEST_PY_BD: "evb-ast2500" - TEST_PY_ID: "--id qemu" - integratorcp_cm926ejs: - TEST_PY_BD: "integratorcp_cm926ejs" - TEST_PY_ID: "--id qemu" - TEST_PY_TEST_SPEC: "not sleep" - qemu_arm: - TEST_PY_BD: "qemu_arm" - TEST_PY_TEST_SPEC: "not sleep" - qemu_arm64: - TEST_PY_BD: "qemu_arm64" - TEST_PY_TEST_SPEC: "not sleep" - qemu_malta: - TEST_PY_BD: "malta" - TEST_PY_ID: "--id qemu" - TEST_PY_TEST_SPEC: "not sleep and not efi" - qemu_maltael: - TEST_PY_BD: "maltael" - TEST_PY_ID: "--id qemu" - TEST_PY_TEST_SPEC: "not sleep and not efi" - qemu_malta64: - TEST_PY_BD: "malta64" - TEST_PY_ID: "--id qemu" - TEST_PY_TEST_SPEC: "not sleep and not efi" - qemu_malta64el: - TEST_PY_BD: "malta64el" - TEST_PY_ID: "--id qemu" - TEST_PY_TEST_SPEC: "not sleep and not efi" - qemu_ppce500: - TEST_PY_BD: "qemu-ppce500" - TEST_PY_TEST_SPEC: "not sleep" - qemu_riscv32: - TEST_PY_BD: "qemu-riscv32" - TEST_PY_TEST_SPEC: "not sleep" - qemu_riscv64: - TEST_PY_BD: "qemu-riscv64" - TEST_PY_TEST_SPEC: "not sleep" - qemu_riscv32_spl: - TEST_PY_BD: "qemu-riscv32_spl" - TEST_PY_TEST_SPEC: "not sleep" - qemu_riscv64_spl: - TEST_PY_BD: "qemu-riscv64_spl" - TEST_PY_TEST_SPEC: "not sleep" - qemu_x86: - TEST_PY_BD: "qemu-x86" - TEST_PY_TEST_SPEC: "not sleep" - qemu_x86_64: - TEST_PY_BD: "qemu-x86_64" - TEST_PY_TEST_SPEC: "not sleep" - r2dplus_i82557c: - TEST_PY_BD: "r2dplus" - TEST_PY_ID: "--id i82557c_qemu" - r2dplus_pcnet: - TEST_PY_BD: "r2dplus" - TEST_PY_ID: "--id pcnet_qemu" - r2dplus_rtl8139: - TEST_PY_BD: "r2dplus" - TEST_PY_ID: "--id rtl8139_qemu" - r2dplus_tulip: - TEST_PY_BD: "r2dplus" - TEST_PY_ID: "--id tulip_qemu" - xilinx_zynq_virt: - TEST_PY_BD: "xilinx_zynq_virt" - TEST_PY_ID: "--id qemu" - TEST_PY_TEST_SPEC: "not sleep" - xilinx_versal_virt: - TEST_PY_BD: "xilinx_versal_virt" - TEST_PY_ID: "--id qemu" - TEST_PY_TEST_SPEC: "not sleep" - xtfpga: - TEST_PY_BD: "xtfpga" - TEST_PY_ID: "--id qemu" - TEST_PY_TEST_SPEC: "not sleep" - steps: - - script: | - cat << EOF > test.sh - set -ex - # make environment variables available as tests are running inside a container - export WORK_DIR="${WORK_DIR}" - export TEST_PY_BD="${TEST_PY_BD}" - export TEST_PY_ID="${TEST_PY_ID}" - export TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}" - export OVERRIDE="${OVERRIDE}" - EOF - cat << "EOF" >> test.sh - # the below corresponds to .gitlab-ci.yml "before_script" - cd ${WORK_DIR} - git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname` - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname` - grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; - fi - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; - fi - # the below corresponds to .gitlab-ci.yml "script" - cd ${WORK_DIR} - export UBOOT_TRAVIS_BUILD_DIR=/tmp/${TEST_PY_BD}; - tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board ${TEST_PY_BD} ${OVERRIDE} - cp ~/grub_x86.efi ${UBOOT_TRAVIS_BUILD_DIR}/ - cp ~/grub_x64.efi ${UBOOT_TRAVIS_BUILD_DIR}/ - cp /opt/grub/grubriscv64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi - cp /opt/grub/grubriscv32.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv32.efi - cp /opt/grub/grubaa64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi - cp /opt/grub/grubarm.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi - virtualenv -p /usr/bin/python3 /tmp/venv - . /tmp/venv/bin/activate - pip install -r test/py/requirements.txt - export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH}; - export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci; - # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not - ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} --build-dir "$UBOOT_TRAVIS_BUILD_DIR"; - # the below corresponds to .gitlab-ci.yml "after_script" - rm -rf /tmp/uboot-test-hooks /tmp/venv - EOF - cat test.sh - # make current directory writeable to uboot user inside the container - # as sandbox testing need create files like spi flash images, etc. - # (TODO: clean up this in the future) - chmod 777 . - docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/test.sh - - - job: build_the_world - displayName: 'Build the World' - pool: - vmImage: $(ubuntu_vm) - strategy: - # Use almost the same target division in .travis.yml, only merged - # 4 small build jobs (arc/microblaze/nds32/xtensa) into one. - matrix: - arc_microblaze_nds32_xtensa: - BUILDMAN: "arc microblaze nds32 xtensa" - arm11_arm7_arm920t_arm946es: - BUILDMAN: "arm11 arm7 arm920t arm946es" - arm926ejs: - BUILDMAN: "arm926ejs -x freescale,siemens,at91,kirkwood,spear,omap" - at91_non_armv7: - BUILDMAN: "at91 -x armv7" - at91_non_arm926ejs: - BUILDMAN: "at91 -x arm926ejs" - boundary_engicam_toradex: - BUILDMAN: "boundary engicam toradex" - arm_bcm: - BUILDMAN: "bcm -x mips" - nxp_arm32: - BUILDMAN: "freescale -x powerpc,m68k,aarch64,ls101,ls102,ls104,ls108,ls20,lx216" - nxp_ls101x: - BUILDMAN: "freescale&ls101" - nxp_ls102x: - BUILDMAN: "freescale&ls102" - nxp_ls104x: - BUILDMAN: "freescale&ls104" - nxp_ls108x: - BUILDMAN: "freescale&ls108" - nxp_ls20xx: - BUILDMAN: "freescale&ls20" - nxp_lx216x: - BUILDMAN: "freescale&lx216" - imx6: - BUILDMAN: "mx6 -x boundary,engicam,freescale,technexion,toradex" - imx: - BUILDMAN: "mx -x mx6,freescale,technexion,toradex" - keystone2_keystone3: - BUILDMAN: "k2 k3" - samsung_socfpga: - BUILDMAN: "samsung socfpga" - spear: - BUILDMAN: "spear" - sun4i: - BUILDMAN: "sun4i" - sun5i: - BUILDMAN: "sun5i" - sun6i: - BUILDMAN: "sun6i" - sun7i: - BUILDMAN: "sun7i" - sun8i_32bit: - BUILDMAN: "sun8i&armv7" - sun8i_64bit: - BUILDMAN: "sun8i&aarch64" - sun9i: - BUILDMAN: "sun9i" - sun50i: - BUILDMAN: "sun50i" - arm_catch_all: - BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,renesas,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rk,toradex,socfpga,k2,k3,zynq" - sandbox_x86: - BUILDMAN: "sandbox x86" - technexion: - BUILDMAN: "technexion" - kirkwood: - BUILDMAN: "kirkwood" - mvebu: - BUILDMAN: "mvebu" - m68k: - BUILDMAN: "m68k" - mips: - BUILDMAN: "mips" - non_fsl_ppc: - BUILDMAN: "powerpc -x freescale" - mpc85xx_freescale: - BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*" - t208xrdb_corenet_ds: - BUILDMAN: "t208xrdb corenet_ds" - fsl_ppc: - BUILDMAN: "t4qds b4860qds mpc83xx&freescale mpc86xx&freescale" - t102x: - BUILDMAN: "t102*" - p1_p2_rdb_pc: - BUILDMAN: "p1_p2_rdb_pc" - p1010rdb_bsc91: - BUILDMAN: "p1010rdb bsc91" - siemens: - BUILDMAN: "siemens" - tegra: - BUILDMAN: "tegra -x toradex" - am33xx_no_siemens: - BUILDMAN: "am33xx -x siemens" - omap: - BUILDMAN: "omap" - uniphier: - BUILDMAN: "uniphier" - aarch64_catch_all: - BUILDMAN: "aarch64 -x bcm,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq" - rockchip: - BUILDMAN: "rk" - renesas: - BUILDMAN: "renesas" - zynq: - BUILDMAN: "zynq&armv7" - zynqmp_versal: - BUILDMAN: "versal|zynqmp&aarch64" - riscv: - BUILDMAN: "riscv" - steps: - - script: | - cat << EOF > build.sh - set -ex - cd ${WORK_DIR} - # make environment variables available as tests are running inside a container - export BUILDMAN="${BUILDMAN}" - EOF - cat << "EOF" >> build.sh - if [[ "${BUILDMAN}" != "" ]]; then - ret=0; - tools/buildman/buildman -o /tmp -P -E -W ${BUILDMAN} ${OVERRIDE} || ret=$?; - if [[ $ret -ne 0 ]]; then - tools/buildman/buildman -o /tmp -seP ${BUILDMAN}; - exit $ret; - fi; - fi - EOF - cat build.sh - docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh diff --git a/.checkpatch.conf b/.checkpatch.conf deleted file mode 100644 index 9e40ea060b..0000000000 --- a/.checkpatch.conf +++ /dev/null @@ -1,36 +0,0 @@ -# Not Linux, so don't expect a Linux tree. ---no-tree - -# Temporary for false positive in checkpatch ---ignore COMPLEX_MACRO - -# For CONFIG_SYS_I2C_NOPROBES ---ignore MULTISTATEMENT_MACRO_USE_DO_WHILE - -# For simple_strtoul ---ignore CONSIDER_KSTRTO - -# For min/max ---ignore MINMAX - -# enable more tests ---strict - -# Not Linux, so we don't recommend usleep_range() over udelay() ---ignore USLEEP_RANGE - -# Ignore networking block comment style ---ignore NETWORKING_BLOCK_COMMENT_STYLE - -# Ignore "WARNING: Prefer ether_addr_copy() over memcpy() if the Ethernet -# addresses are __aligned(2)". ---ignore PREFER_ETHER_ADDR_COPY - -# ENOSYS is a conventionally used error, even though U-Boot lacks system calls. ---ignore ENOSYS - -# A bit shorter of a description is OK with us. ---min-conf-desc-length=2 - -# Extra checks for U-Boot ---u-boot diff --git a/.gitattributes b/.gitattributes deleted file mode 100644 index 899473ab0f..0000000000 --- a/.gitattributes +++ /dev/null @@ -1,5 +0,0 @@ -# Declare files that always have LF line endings on checkout -* text eol=lf -# Denote all files that are truly binary and should not be modified -*.bmp binary -*.ttf binary diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md deleted file mode 100644 index ae91252a00..0000000000 --- a/.github/pull_request_template.md +++ /dev/null @@ -1,6 +0,0 @@ -Please do not submit a Pull Request via github. Our project makes use of -mailing lists for patch submission and review. For more details please -see https://www.denx.de/wiki/U-Boot/Patches - -The only exception to this is in order to trigger a CI loop on Azure prior -to posting of patches. diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml deleted file mode 100644 index d072e833a3..0000000000 --- a/.gitlab-ci.yml +++ /dev/null @@ -1,340 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -# Grab our configured image. The source for this is found at: -# https://source.denx.de/u-boot/gitlab-ci-runner -image: trini/u-boot-gitlab-ci-runner:bionic-20200807-02Sep2020 - -# We run some tests in different order, to catch some failures quicker. -stages: - - testsuites - - test.py - - world build - -.buildman_and_testpy_template: &buildman_and_testpy_dfn - stage: test.py - before_script: - # Clone uboot-test-hooks - - git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks - - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname` - - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname` - - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; - fi - - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; - fi - - after_script: - - rm -rf /tmp/uboot-test-hooks /tmp/venv - script: - # If we've been asked to use clang only do one configuration. - - export UBOOT_TRAVIS_BUILD_DIR=/tmp/${TEST_PY_BD} - - tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e - --board ${TEST_PY_BD} ${OVERRIDE} - - cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/ - - cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/ - - cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi - - cp /opt/grub/grubriscv32.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv32.efi - - cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi - - cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi - - virtualenv -p /usr/bin/python3 /tmp/venv - - . /tmp/venv/bin/activate - - pip install -r test/py/requirements.txt - # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not - - export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH}; - export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci; - ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} - ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} - --build-dir "$UBOOT_TRAVIS_BUILD_DIR" - -build all 32bit ARM platforms: - stage: world build - script: - - ret=0; - ./tools/buildman/buildman -o /tmp -P -E -W arm -x aarch64 || ret=$?; - if [[ $ret -ne 0 ]]; then - ./tools/buildman/buildman -o /tmp -seP; - exit $ret; - fi; - -build all 64bit ARM platforms: - stage: world build - script: - - virtualenv -p /usr/bin/python3 /tmp/venv - - . /tmp/venv/bin/activate - - pip install pyelftools - - ret=0; - ./tools/buildman/buildman -o /tmp -P -E -W aarch64 || ret=$?; - if [[ $ret -ne 0 ]]; then - ./tools/buildman/buildman -o /tmp -seP; - exit $ret; - fi; - -build all PowerPC platforms: - stage: world build - script: - - ret=0; - ./tools/buildman/buildman -o /tmp -P -E -W powerpc || ret=$?; - if [[ $ret -ne 0 ]]; then - ./tools/buildman/buildman -o /tmp -seP; - exit $ret; - fi; - -build all other platforms: - stage: world build - script: - - ret=0; - ./tools/buildman/buildman -o /tmp -P -E -W -x arm,powerpc || ret=$?; - if [[ $ret -ne 0 ]]; then - ./tools/buildman/buildman -o /tmp -seP; - exit $ret; - fi; - -# QA jobs for code analytics -# static code analysis with cppcheck (we can add --enable=all later) -cppcheck: - stage: testsuites - script: - - cppcheck -j$(nproc) --force --quiet --inline-suppr . - -# search for TODO within source tree -grep TODO/FIXME/HACK: - stage: testsuites - script: - - grep -r TODO . - - grep -r FIXME . - # search for HACK within source tree and ignore HACKKIT board - - grep -r HACK . | grep -v HACKKIT - -# build HTML documentation -htmldocs: - stage: testsuites - script: - - virtualenv -p /usr/bin/python3 /tmp/venvhtml - - . /tmp/venvhtml/bin/activate - - pip install -r doc/sphinx/requirements.txt - - make htmldocs - -# some statistics about the code base -sloccount: - stage: testsuites - script: - - sloccount . - -# ensure all configs have MAINTAINERS entries -Check for configs without MAINTAINERS entry: - stage: testsuites - script: - - if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi - -# Ensure host tools build -Build tools-only: - stage: testsuites - script: - - make tools-only_config tools-only -j$(nproc) - -# Ensure env tools build -Build envtools: - stage: testsuites - script: - - make tools-only_config envtools -j$(nproc) - -Run binman, buildman, dtoc, Kconfig and patman testsuites: - stage: testsuites - script: - - git config --global user.name "GitLab CI Runner"; - git config --global user.email trini@konsulko.com; - export USER=gitlab; - virtualenv -p /usr/bin/python3 /tmp/venv; - . /tmp/venv/bin/activate; - pip install -r test/py/requirements.txt; - export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl; - export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"; - export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"; - ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w - --board sandbox_spl; - ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test; - ./tools/buildman/buildman -t; - ./tools/dtoc/dtoc -t; - ./tools/patman/patman test; - make testconfig - -Run tests for Nokia RX-51 (aka N900): - stage: testsuites - script: - - ./tools/buildman/buildman --fetch-arch arm; - export PATH=~/.buildman-toolchains/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/:$PATH; - test/nokia_rx51_test.sh - -# Test sandbox with test.py -sandbox test.py: - variables: - TEST_PY_BD: "sandbox" - <<: *buildman_and_testpy_dfn - -sandbox with clang test.py: - variables: - TEST_PY_BD: "sandbox" - OVERRIDE: "-O clang-10" - <<: *buildman_and_testpy_dfn - -sandbox_spl test.py: - variables: - TEST_PY_BD: "sandbox_spl" - TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl" - <<: *buildman_and_testpy_dfn - -sandbox_noinst_test.py: - variables: - TEST_PY_BD: "sandbox_noinst" - TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl" - <<: *buildman_and_testpy_dfn - -evb-ast2500 test.py: - variables: - TEST_PY_BD: "evb-ast2500" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -sandbox_flattree test.py: - variables: - TEST_PY_BD: "sandbox_flattree" - <<: *buildman_and_testpy_dfn - -integratorcp_cm926ejs test.py: - variables: - TEST_PY_BD: "integratorcp_cm926ejs" - TEST_PY_TEST_SPEC: "not sleep" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -qemu_arm test.py: - variables: - TEST_PY_BD: "qemu_arm" - TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - -qemu_arm64 test.py: - variables: - TEST_PY_BD: "qemu_arm64" - TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - -qemu_malta test.py: - variables: - TEST_PY_BD: "malta" - TEST_PY_TEST_SPEC: "not sleep and not efi" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -qemu_maltael test.py: - variables: - TEST_PY_BD: "maltael" - TEST_PY_TEST_SPEC: "not sleep and not efi" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -qemu_malta64 test.py: - variables: - TEST_PY_BD: "malta64" - TEST_PY_TEST_SPEC: "not sleep and not efi" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -qemu_malta64el test.py: - variables: - TEST_PY_BD: "malta64el" - TEST_PY_TEST_SPEC: "not sleep and not efi" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -qemu-ppce500 test.py: - variables: - TEST_PY_BD: "qemu-ppce500" - TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - -qemu-riscv32 test.py: - variables: - TEST_PY_BD: "qemu-riscv32" - TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - -qemu-riscv64 test.py: - variables: - TEST_PY_BD: "qemu-riscv64" - TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - -qemu-riscv32_spl test.py: - variables: - TEST_PY_BD: "qemu-riscv32_spl" - TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - -qemu-riscv64_spl test.py: - variables: - TEST_PY_BD: "qemu-riscv64_spl" - TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - -qemu-x86 test.py: - variables: - TEST_PY_BD: "qemu-x86" - TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - -qemu-x86_64 test.py: - variables: - TEST_PY_BD: "qemu-x86_64" - TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - -r2dplus_i82557c test.py: - variables: - TEST_PY_BD: "r2dplus" - TEST_PY_ID: "--id i82557c_qemu" - <<: *buildman_and_testpy_dfn - -r2dplus_pcnet test.py: - variables: - TEST_PY_BD: "r2dplus" - TEST_PY_ID: "--id pcnet_qemu" - <<: *buildman_and_testpy_dfn - -r2dplus_rtl8139 test.py: - variables: - TEST_PY_BD: "r2dplus" - TEST_PY_ID: "--id rtl8139_qemu" - <<: *buildman_and_testpy_dfn - -r2dplus_tulip test.py: - variables: - TEST_PY_BD: "r2dplus" - TEST_PY_ID: "--id tulip_qemu" - <<: *buildman_and_testpy_dfn - -xilinx_zynq_virt test.py: - variables: - TEST_PY_BD: "xilinx_zynq_virt" - TEST_PY_TEST_SPEC: "not sleep" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -xilinx_versal_virt test.py: - variables: - TEST_PY_BD: "xilinx_versal_virt" - TEST_PY_TEST_SPEC: "not sleep" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn - -xtfpga test.py: - variables: - TEST_PY_BD: "xtfpga" - TEST_PY_TEST_SPEC: "not sleep" - TEST_PY_ID: "--id qemu" - <<: *buildman_and_testpy_dfn diff --git a/.mailmap b/.mailmap deleted file mode 100644 index b76f02283c..0000000000 --- a/.mailmap +++ /dev/null @@ -1,53 +0,0 @@ -# -# This list is used by git-shortlog to fix a few botched name translations -# in the git archive, either because the author's full name was messed up -# and/or not always written the same way, making contributions from the -# same person appearing not to be so or badly displayed. -# -# This file is also used by scripts/get_maintainer.pl. -# -# This file can be modified by hand or updated by the following command: -# scripts/mailmapper > tmp; mv tmp .mailmap -# -# Entries in this file take one of the following forms: -# Proper Name -# -# Proper Name -# Proper Name Commit Name - -Alexander Graf -Allen Martin -Andreas Bießmann -Andreas Bießmann -Aneesh V -Boris Brezillon -Boris Brezillon -Dirk Behme -Fabio Estevam -Jagan Teki <402jagan@gmail.com> -Jagan Teki -Jagan Teki -Jagan Teki -Jagan Teki -Igor Opaniuk -Igor Opaniuk -Markus Klotzbuecher -Patrice Chotard -Patrick Delaunay -Paul Burton -Prabhakar Kushwaha -Rajeshwari Shinde -Ricardo Ribalda -Ricardo Ribalda -Ruchika Gupta -Sandeep Paulraj -Shaohui Xie -Stefan Roese -Stefano Babic -TsiChung Liew -Wolfgang Denk -York Sun -York Sun -Łukasz Majewski -Lukasz Majewski -Mirza diff --git a/.readthedocs.yml b/.readthedocs.yml deleted file mode 100644 index 44949ea239..0000000000 --- a/.readthedocs.yml +++ /dev/null @@ -1,19 +0,0 @@ -# .readthedocs.yml -# Read the Docs configuration file -# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details - -# Required -version: 2 - -# Build documentation in the docs/ directory with Sphinx -sphinx: - configuration: doc/conf.py - -# Optionally build your docs in additional formats such as PDF and ePub -formats: [] - -# Optionally set the version of Python and requirements required to build your docs -# python: -# version: 3.7 -# install: -# - requirements: docs/requirements.txt diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0448787b8b..ecae081180 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1012,6 +1012,8 @@ config ARCH_SUNXI select USB_KEYBOARD if DISTRO_DEFAULTS select USB_STORAGE if DISTRO_DEFAULTS select SPL_USE_TINY_PRINTF + imply AUTOBOOT_KEYED + imply AUTOBOOT_KEYED_CTRLC select USE_PREBOOT select SYS_RELOC_GD_ENV_ADDR imply BOARD_LATE_INIT diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9fb38682e6..b47bdc2515 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -589,6 +589,9 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h2-plus-libretech-all-h3-cc.dtb \ sun8i-h2-plus-orangepi-r1.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h2-plus-nanopi-duo.dtb \ + sun8i-h2-plus-sunvell-r69.dtb \ + sun8i-h3-zeropi.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-bananapi-m2-plus-v1.2.dtb \ sun8i-h3-beelink-x2.dtb \ @@ -600,9 +603,13 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h3-nanopi-m1-plus.dtb \ sun8i-h3-nanopi-neo.dtb \ sun8i-h3-nanopi-neo-air.dtb \ + sun8i-h3-nanopi-r1.dtb \ + sun8i-h3-nanopi-duo2.dtb \ sun8i-h3-orangepi-2.dtb \ sun8i-h3-orangepi-lite.dtb \ sun8i-h3-orangepi-one.dtb \ + sun8i-h3-beelink-x2.dtb \ + sun8i-h3-orangepi-zero-plus2.dtb \ sun8i-h3-orangepi-pc.dtb \ sun8i-h3-orangepi-pc-plus.dtb \ sun8i-h3-orangepi-plus.dtb \ @@ -621,10 +628,13 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-libretech-all-h3-cc.dtb \ sun50i-h5-libretech-all-h3-it.dtb \ sun50i-h5-libretech-all-h5-cc.dtb \ + sun50i-h5-nanopi-m1-plus2.dtb \ sun50i-h5-nanopi-neo2.dtb \ + sun50i-h5-nanopi-neo-core2.dtb \ sun50i-h5-nanopi-neo-plus2.dtb \ sun50i-h5-orangepi-zero-plus.dtb \ sun50i-h5-orangepi-pc2.dtb \ + sun50i-h5-nanopi-k1-plus.dtb \ sun50i-h5-orangepi-prime.dtb \ sun50i-h5-orangepi-zero-plus2.dtb dtb-$(CONFIG_MACH_SUN50I_H6) += \ @@ -633,9 +643,14 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ sun50i-h6-orangepi-lite2.dtb \ sun50i-h6-orangepi-one-plus.dtb \ sun50i-h6-pine-h64.dtb \ + sun50i-h6-pine-h64-model-b.dtb \ sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_MACH_SUN50I_H616) += \ - sun50i-h616-orangepi-zero2.dtb + sun50i-h616-orangepi-zero2.dtb \ + sun50i-h616-orangepi-zero2-b.dtb \ + sun50i-h616-orangepi-zero2-lts.dtb \ + sun50i-h616-orangepi-zero3.dtb \ + sun50i-h616-orangepi-zero2w.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ sun50i-a64-bananapi-m64.dtb \ diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts b/arch/arm/dts/sun50i-a64-olinuxino.dts index f3f8e177ab..adee3dffb4 100644 --- a/arch/arm/dts/sun50i-a64-olinuxino.dts +++ b/arch/arm/dts/sun50i-a64-olinuxino.dts @@ -142,6 +142,16 @@ }; }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + &ohci0 { status = "okay"; }; diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts index 70e31743f0..ddd363288a 100644 --- a/arch/arm/dts/sun50i-a64-orangepi-win.dts +++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts @@ -74,6 +74,19 @@ clocks = <&rtc 1>; clock-names = "ext_clock"; }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_vbus_pin_opiwin>; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; }; &codec { @@ -185,6 +198,13 @@ status = "okay"; }; +&pio { + usb1_vbus_pin_opiwin: usb1_vbus_pin@0 { + allwinner,pins = "PD7"; + allwinner,function = "gpio_out"; + }; +}; + &r_rsb { status = "okay"; diff --git a/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts b/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts new file mode 100644 index 0000000000..6aedb5fb69 --- /dev/null +++ b/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2017 Icenowy Zheng + * Copyright (C) 2017 Jagan Teki + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun50i-h5.dtsi" + +#include + +/ { + model = "FriendlyARM NanoPi K1 plus"; + compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + compatible = "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + diff --git a/arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts b/arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts new file mode 100644 index 0000000000..1e2ee2473e --- /dev/null +++ b/arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2017 Antony Antony + * Copyright (c) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun50i-h5.dtsi" + +#include + +/ { + model = "FriendlyARM Nanopi M1 Plus 2"; + compatible = "friendlyarm,nanopi-m1-plus2", "allwinner,sun50i-h5"; + + aliases { + serial0 = &uart0; + ethernet0 = &emac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x40000000 0x40000000>; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-mode = "rgmii"; + phy = <&phy1>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mmc0 { + compatible = "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts new file mode 100644 index 0000000000..5e727ef0e0 --- /dev/null +++ b/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2017 Antony Antony + * Copyright (c) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun50i-h5.dtsi" + +#include + +/ { + model = "FriendlyARM NanoPi NEO Core 2"; + compatible = "friendlyarm,nanopi-neo-core2", "allwinner,sun50i-h5"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x40000000 0x40000000>; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + compatible = "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts b/arch/arm/dts/sun50i-h6-orangepi-3.dts index 15c9dd8c44..e89896e541 100644 --- a/arch/arm/dts/sun50i-h6-orangepi-3.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts @@ -1,10 +1,12 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2019 Ondřej Jirman +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2018 Amarula Solutions + * Author: Jagan Teki + */ /dts-v1/; #include "sun50i-h6.dtsi" -#include "sun50i-h6-cpu-opp.dtsi" #include @@ -14,167 +16,51 @@ aliases { serial0 = &uart0; - serial1 = &uart1; + ethernet0 = &emac; }; chosen { stdout-path = "serial0:115200n8"; }; - - connector { - compatible = "hdmi-connector"; - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext_osc32k"; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "orangepi:red:power"; - gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - default-state = "on"; - }; - - status { - label = "orangepi:green:status"; - gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC jack */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc33_wifi: vcc33-wifi { - /* Always on 3.3V regulator for WiFi and BT */ - compatible = "regulator-fixed"; - regulator-name = "vcc33-wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_vcc5v>; - }; - - reg_vcc_wifi_io: vcc-wifi-io { - /* Always on 1.8V/300mA regulator for WiFi and BT IO */ - compatible = "regulator-fixed"; - regulator-name = "vcc-wifi-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <®_vcc33_wifi>; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; - clock-names = "ext_clock"; - reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ - post-power-on-delay-ms = <200>; - }; }; -&cpu0 { - cpu-supply = <®_dcdca>; -}; - -&de { +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_aldo2>; + allwinner,rx-delay-ps = <200>; + allwinner,tx-delay-ps = <200>; status = "okay"; }; -&dwc3 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&gpu { - mali-supply = <®_dcdcc>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; }; }; &mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; bus-width = <4>; status = "okay"; }; -&mmc1 { - vmmc-supply = <®_vcc33_wifi>; - vqmmc-supply = <®_vcc_wifi_io>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcm: sdio-wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ - interrupt-names = "host-wake"; - }; -}; - &mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_cldo1>; - vqmmc-supply = <®_bldo2>; - cap-mmc-hw-reset; non-removable; + cap-mmc-hw-reset; bus-width = <8>; status = "okay"; }; -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_bldo2>; - vcc-pd-supply = <®_cldo1>; - vcc-pg-supply = <®_vcc_wifi_io>; -}; - &r_i2c { status = "okay"; @@ -186,53 +72,47 @@ interrupt-controller; #interrupt-cells = <1>; x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; regulators { reg_aldo1: aldo1 { regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl-led-ir"; + regulator-name = "vcc-pl"; }; reg_aldo2: aldo2 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "vcc33-audio-tv-ephy-mac"; + regulator-name = "vcc-ac200"; }; - /* ALDO3 is shorted to CLDO1 */ reg_aldo3: aldo3 { regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1"; + regulator-name = "vcc25-dram"; }; reg_bldo1: bldo1 { regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc18-dram-bias-pll"; + regulator-name = "vcc-bias-pll"; }; reg_bldo2: bldo2 { regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc-efuse-pcie-hdmi-pc"; + regulator-name = "vcc-efuse-pcie-hdmi-io"; }; - bldo3 { - /* unused */ + reg_bldo3: bldo3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dcxoio"; }; bldo4 { @@ -243,30 +123,31 @@ regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2"; + regulator-name = "vcc-3v3"; }; - cldo2 { - /* unused */ + reg_cldo2: cldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; }; - cldo3 { - /* unused */ + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; }; reg_dcdca: dcdca { regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1160000>; - regulator-ramp-delay = <2500>; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; regulator-name = "vdd-cpu"; }; reg_dcdcc: dcdcc { - regulator-enable-ramp-delay = <32000>; regulator-min-microvolt = <810000>; regulator-max-microvolt = <1080000>; - regulator-ramp-delay = <2500>; regulator-name = "vdd-gpu"; }; @@ -291,55 +172,8 @@ }; }; -&r_ir { - status = "okay"; -}; - -&rtc { - clocks = <&ext_osc32k>; -}; - &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; - -/* There's the BT part of the AP6256 connected to that UART */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rtc 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ - host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ - shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ - max-speed = <1500000>; - }; -}; - -&usb2otg { - /* - * This board doesn't have a controllable VBUS even though it - * does have an ID pin. Using it as anything but a USB host is - * unsafe. - */ - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy { - usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */ - usb0_vbus-supply = <®_vcc5v>; - usb3_vbus-supply = <®_vcc5v>; - status = "okay"; -}; - -&usb3phy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts new file mode 120000 index 0000000000..7628022209 --- /dev/null +++ b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts @@ -0,0 +1 @@ +sun50i-h6-pine-h64.dts \ No newline at end of file diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2-b.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2-b.dts new file mode 100644 index 0000000000..1e1c540933 --- /dev/null +++ b/arch/arm/dts/sun50i-h616-orangepi-zero2-b.dts @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2020 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include +#include +#include + +/ { + model = "Orange Pi Zero2 B"; + compatible = "xunlong,orangepi-zero2-b", "allwinner,sun50i-h616"; + + aliases { + ethernet0 = &emac0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + default-state = "on"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + enable-active-high; + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ + status = "okay"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +/* USB 2 & 3 are on headers only. */ + +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dcdce>; + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + status = "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdce>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp305: pmic@745 { + compatible = "x-powers,axp305", "x-powers,axp805", + "x-powers,axp806"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x745>; + + x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-sys"; + }; + + reg_aldo2: aldo2 { /* 3.3V on headers */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3-ext"; + }; + + reg_aldo3: aldo3 { /* 3.3V on headers */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3-ext2"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + bldo3 { + /* unused */ + }; + + bldo4 { + /* unused */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-dram"; + }; + + reg_dcdce: dcdce { + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-eth-mmc"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2-lts.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2-lts.dts new file mode 100644 index 0000000000..75802b2ddc --- /dev/null +++ b/arch/arm/dts/sun50i-h616-orangepi-zero2-lts.dts @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2020 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include +#include +#include + +/ { + model = "OrangePi Zero2 LTS"; + compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; + + aliases { + ethernet0 = &emac0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + default-state = "on"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + enable-active-high; + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ + status = "okay"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +/* USB 2 & 3 are on headers only. */ + +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dcdce>; + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + status = "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdce>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp305: pmic@745 { + compatible = "x-powers,axp305", "x-powers,axp805", + "x-powers,axp806"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x745>; + + x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-sys"; + }; + + reg_aldo2: aldo2 { /* 3.3V on headers */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3-ext"; + }; + + reg_aldo3: aldo3 { /* 3.3V on headers */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3-ext2"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + bldo3 { + /* unused */ + }; + + bldo4 { + /* unused */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8-vcc-pg"; + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + + reg_dcdce: dcdce { + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-eth-mmc"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts index e6de49f89e..6705469887 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts @@ -194,8 +194,8 @@ reg_dcdcd: dcdcd { regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; regulator-name = "vdd-dram"; }; @@ -214,7 +214,7 @@ }; &spi0 { - status = "okay"; + status = "disable"; flash@0 { #address-cells = <1>; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2w.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2w.dts new file mode 100644 index 0000000000..2e6e740dc4 --- /dev/null +++ b/arch/arm/dts/sun50i-h616-orangepi-zero2w.dts @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2020 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" +#include +#include +#include + +/ { + model = "OrangePi Zero2 W"; + compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h616"; + + aliases { + ethernet0 = &emac0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + default-state = "on"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + enable-active-high; + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ + status = "okay"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +/* USB 2 & 3 are on headers only. */ + +&emac0 { + status = "disabled"; +}; + +&mmc0 { + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp313a: pmic@36 { + compatible = "x-powers,axp313a"; + status = "okay"; + reg = <0x36>; + wakeup-source; + + standby_param: standby_param { + vcc-dram = <0x4>; + }; + + regulators{ + reg_dcdc1: dcdc1 { + regulator-name = "axp313a-dcdc1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-always-on; + }; + + reg_dcdc2: dcdc2 { + regulator-name = "axp313a-dcdc2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1540000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-ramp-delay = <200>; + regulator-always-on; + }; + + reg_dcdc3: dcdc3 { + regulator-name = "axp313a-dcdc3"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-always-on; + }; + + reg_aldo1: aldo1 { + regulator-name = "axp313a-aldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-always-on; + }; + + reg_dldo1: dldo1 { + regulator-name = "axp313a-dldo1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-always-on; + }; + }; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero3.dts b/arch/arm/dts/sun50i-h616-orangepi-zero3.dts new file mode 100644 index 0000000000..d7486fa114 --- /dev/null +++ b/arch/arm/dts/sun50i-h616-orangepi-zero3.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2020 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" +#include +#include +#include + +/ { + model = "OrangePi Zero3"; + compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h616"; + + aliases { + ethernet0 = &emac0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + default-state = "on"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + enable-active-high; + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ + status = "okay"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +/* USB 2 & 3 are on headers only. */ + +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + status = "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp313a: pmic@36 { + compatible = "x-powers,axp313a"; + status = "okay"; + reg = <0x36>; + wakeup-source; + + standby_param: standby_param { + vcc-dram = <0x4>; + }; + + regulators{ + reg_dcdc1: dcdc1 { + regulator-name = "axp313a-dcdc1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-always-on; + }; + + reg_dcdc2: dcdc2 { + regulator-name = "axp313a-dcdc2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1540000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-ramp-delay = <200>; + regulator-always-on; + }; + + reg_dcdc3: dcdc3 { + regulator-name = "axp313a-dcdc3"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-always-on; + }; + + reg_aldo1: aldo1 { + regulator-name = "axp313a-aldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-always-on; + }; + + reg_dldo1: dldo1 { + regulator-name = "axp313a-dldo1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-step-delay-us = <25>; + regulator-final-delay-us = <50>; + regulator-always-on; + }; + }; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts b/arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts new file mode 100644 index 0000000000..644d377d27 --- /dev/null +++ b/arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts @@ -0,0 +1,98 @@ +/* + * adapted by , based on + * Copyright (C) 2017 Jelle van der Waa + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "FriendlyARM NanoPi DUO"; + compatible = "friendlyarm,nanopi-duo", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + status { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ + }; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts index f19ed981da..47b0047b6f 100644 --- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts @@ -124,6 +124,10 @@ status = "okay"; }; +&ehci2 { + status = "okay"; +}; + &emac { phy-handle = <&int_mii_phy>; phy-mode = "mii"; @@ -175,6 +179,10 @@ }; }; +&ohci2 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pa_pins>; diff --git a/arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts b/arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts new file mode 100644 index 0000000000..830990cec1 --- /dev/null +++ b/arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Based original Sunvell R69 FEX file (2019 karabek) + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Sunvell R69"; + compatible = "sunvell,sunvell-r69", "allwinner,sun8i-h2-plus"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + pwr_led { + label = "sunvell-r69:red:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "sunvell-r69:blue:status"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_vdd_cpux: vdd-cpux-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + enable-active-high; + gpios-states = <0x1>; + states = <1100000 0x0 + 1300000 0x1>; + }; + + reg_vcc_wifi: reg_vcc_wifi { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; + gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 0 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_vcc_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + xr819: sdio_wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase current from 30mA to 40mA for DDR eMMC */ + allwinner,drive = ; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + leds_opc: led_pins { + pins = "PA15"; + function = "gpio_out"; + }; +}; + +&r_pio { + leds_r_opc: led_pins { + pins = "PL10"; + function = "gpio_out"; + }; +}; + +®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts index 45a24441ff..cf6468230c 100644 --- a/arch/arm/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Marcus Cooper + * Copyright (C) 2016 Hans de Goede * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -40,126 +40,23 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include +/* The Orange Pi PC Plus is an extended version of the regular PC */ +#include "sun8i-h3-orangepi-pc.dts" / { model = "Beelink X2"; - compatible = "roofull,beelink-x2", "allwinner,sun8i-h3"; + compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3"; aliases { - serial0 = &uart0; - ethernet0 = &emac; - ethernet1 = &sdiowifi; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet1 = &rtl8189ftv; }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "beelink-x2:blue:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ - default-state = "on"; - }; - - red { - label = "beelink-x2:red:standby"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; - }; - - sound_spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - linux,rc-map-name = "rc-tanix-tx3mini"; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; }; &mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; non-removable; status = "okay"; @@ -168,7 +65,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - sdiowifi: sdio_wifi@1 { + rtl8189ftv: sdio_wifi@1 { reg = <1>; }; }; @@ -183,39 +80,9 @@ status = "okay"; }; -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - /* USB VBUS is always on except for the OTG port */ - status = "okay"; - usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */ - usb0_vbus-supply = <®_usb0_vbus>; +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + allwinner,drive = ; + /* eMMC is missing pull-ups */ + allwinner,pull = ; }; diff --git a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts index 6b149271ef..14cc2b9a37 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts @@ -1,6 +1,44 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (C) 2019 Karl Palsson + * adapted by Igor Pecovnik igor@armbian.com + * Copyright (C) 2017 Jelle van der Waa + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -8,10 +46,10 @@ #include "sunxi-common-regulators.dtsi" #include -#include +#include / { - model = "FriendlyARM NanoPi Duo2"; + model = "FriendlyARM NanoPi DUO 2"; compatible = "friendlyarm,nanopi-duo2", "allwinner,sun8i-h3"; aliases { @@ -26,114 +64,25 @@ compatible = "gpio-leds"; pwr { - label = "nanopi:red:pwr"; + label = "nanopi:green:pwr"; gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ default-state = "on"; }; status { - label = "nanopi:green:status"; + label = "nanopi:blue:status"; gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ }; }; - - r_gpio_keys { - compatible = "gpio-keys"; - - k1 { - label = "k1"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ - }; - }; - - reg_vdd_cpux: vdd-cpux-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <50>; /* 4ms */ - - enable-active-high; - enable-gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; - }; - - reg_vcc_dram: vcc-dram { - compatible = "regulator-fixed"; - regulator-name = "vcc-dram"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ - vin-supply = <®_vcc5v0>; - }; - - reg_vdd_sys: vdd-sys { - compatible = "regulator-fixed"; - regulator-name = "vdd-sys"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ - vin-supply = <®_vcc5v0>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; - }; - -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&ehci0 { - status = "okay"; }; &mmc0 { - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: sdio_wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -®_usb0_vbus { - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; status = "okay"; }; @@ -143,31 +92,7 @@ status = "okay"; }; -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_vcc3v3>; - vddio-supply = <®_vcc3v3>; - device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ - shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - }; -}; - -&usb_otg { - status = "okay"; - dr_mode = "otg"; -}; - &usbphy { - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; + /* USB VBUS is always on */ status = "okay"; }; diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts index 07867a0d56..6a973ef46a 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts @@ -103,6 +103,23 @@ }; }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + drive-strength = <40>; + /* eMMC is missing pull-ups */ + bias-pull-up; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pa_pins>; diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-nanopi-neo.dts index 9f33f6fae5..4a56e6a950 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts @@ -58,6 +58,16 @@ status = "okay"; }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + &ohci0 { status = "okay"; }; diff --git a/arch/arm/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/dts/sun8i-h3-nanopi-r1.dts new file mode 100644 index 0000000000..9c3c574e0f --- /dev/null +++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2019 Igor Pecovnik + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyARM NanoPi R1"; + compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + +}; + +&ehci0 { + status = "okay"; +}; + +&pio { + gmac_power_pin_nanopi: gmac_power_pin@0 { + pins = "PD6"; + function = "gpio_out"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; diff --git a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts index b8f46e2802..1e36deebe1 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts @@ -1,6 +1,8 @@ /* - * Copyright (C) 2017 Jagan Teki - * Copyright (C) 2018 Diego Rondini + * Copyright (C) 2016 Icenowy Zheng + * + * Based on sun8i-h3-orangepi-one.dts, which is: + * Copyright (C) 2016 Hans de Goede * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,70 +44,86 @@ */ /dts-v1/; - #include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" #include +#include +#include / { - model = "OrangePi Zero Plus2 H3"; - compatible = "xunlong,orangepi-zero-plus2-h3", "allwinner,sun8i-h3"; + model = "Xunlong Orange Pi Zero Plus 2"; + compatible = "xunlong,orangepi-zeroplus", "allwinner,sun8i-h3"; aliases { serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet1 = &brcmf; }; chosen { stdout-path = "serial0:115200n8"; }; - connector { - compatible = "hdmi-connector"; - type = "a"; + leds { + compatible = "gpio-leds"; - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; }; - }; - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; + }; }; wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ - post-power-on-delay-ms = <200>; + pinctrl-names = "default"; + reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <50>; }; }; -&de { +&ehci1 { status = "okay"; }; -&hdmi { +&ehci2 { status = "okay"; }; -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; +&ehci3 { + status = "okay"; +}; + +&emac { + phy = <&phy1>; + phy-mode = "mii"; + allwinner,use-internal-phy; + allwinner,leds-active-low; + status = "okay"; + phy1: ethernet-phy@1 { + reg = <1>; }; }; &mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; status = "okay"; }; &mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&wifi_pwrseq>; @@ -113,11 +131,11 @@ non-removable; status = "okay"; - brcmf: wifi@1 { + brcmf: bcrmf@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&r_pio>; - interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ + interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 / EINT7 */ interrupt-names = "host-wake"; }; }; @@ -132,8 +150,26 @@ status = "okay"; }; +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; + diff --git a/arch/arm/dts/sun8i-h3-zeropi.dts b/arch/arm/dts/sun8i-h3-zeropi.dts new file mode 100644 index 0000000000..c29240f25d --- /dev/null +++ b/arch/arm/dts/sun8i-h3-zeropi.dts @@ -0,0 +1,100 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyElec ZeroPi"; + compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3"; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_power_pin_nanopi>; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + gmac_power_pin_nanopi: gmac_power_pin@0 { + pins = "PD6"; + function = "gpio_out"; + }; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&usb_otg { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +}; diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index e8e8e38f05..8fb8083454 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -16,8 +16,8 @@ b reset .space 0x7c - .word 0xe28f0058 // add r0, pc, #88 - .word 0xe59f1054 // ldr r1, [pc, #84] + .word 0xe28f0070 // add r0, pc, #112 // @(fel_stash - .) + .word 0xe59f106c // ldr r1, [pc, #108] // fel_stash - . .word 0xe0800001 // add r0, r0, r1 .word 0xe580d000 // str sp, [r0] .word 0xe580e004 // str lr, [r0, #4] @@ -28,8 +28,12 @@ .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0} .word 0xe580e010 // str lr, [r0, #16] - .word 0xe59f1024 // ldr r1, [pc, #36] ; 0x170000a0 - .word 0xe59f0024 // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE + .word 0xe59f1034 // ldr r1, [pc, #52] ; RVBAR_ADDRESS + .word 0xe59f0034 // ldr r0, [pc, #52] ; SUNXI_SRAMC_BASE + .word 0xe5900024 // ldr r0, [r0, #36] ; SRAM_VER_REG + .word 0xe21000ff // ands r0, r0, #255 ; 0xff + .word 0x159f102c // ldrne r1, [pc, #44] ; RVBAR_ALTERNATIVE + .word 0xe59f002c // ldr r0, [pc, #44] ; CONFIG_*TEXT_BASE .word 0xe5810000 // str r0, [r1] .word 0xf57ff04f // dsb sy .word 0xf57ff06f // isb sy @@ -39,11 +43,10 @@ .word 0xf57ff06f // isb sy .word 0xe320f003 // wfi .word 0xeafffffd // b @wfi -#ifndef CONFIG_SUN50I_GEN_H6 - .word 0x017000a0 // writeable RVBAR mapping address -#else - .word 0x09010040 // writeable RVBAR mapping address -#endif + + .word CONFIG_SUNXI_RVBAR_ADDRESS // writable RVBAR mapping addr + .word SUNXI_SRAMC_BASE + .word CONFIG_SUNXI_RVBAR_ALTERNATIVE // address for die variant #ifdef CONFIG_SPL_BUILD .word CONFIG_SPL_TEXT_BASE #else diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index ee387127f3..296f9d11bc 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -208,6 +208,7 @@ struct sunxi_ccm_reg { #define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) #define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16) #define CCM_PLL1_CTRL_EN (0x1 << 31) +#define CCM_PLL1_CTRL_LOCK (0x1 << 28) #define CCM_PLL3_CTRL_M_SHIFT 0 #define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h index 134679d552..bd3f1b432b 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h @@ -36,7 +36,9 @@ struct sunxi_mctl_com_reg { u32 maer0; /* 0x020 master enable register 0 */ u32 maer1; /* 0x024 master enable register 1 */ u32 maer2; /* 0x028 master enable register 2 */ - u8 reserved_0x02c[468]; /* 0x02c */ + u8 reserved_0x02c[36]; /* 0x02c */ + u32 unk_0x050; /* 0x050 */ + u8 reserved_0x054[428]; /* 0x054 */ u32 bwcr; /* 0x200 bandwidth control register */ u8 reserved_0x204[12]; /* 0x204 */ /* @@ -130,6 +132,7 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240); #define MSTR_DEVICETYPE_LPDDR2 BIT(2) #define MSTR_DEVICETYPE_LPDDR3 BIT(3) #define MSTR_DEVICETYPE_DDR4 BIT(4) +#define MSTR_DEVICETYPE_LPDDR4 BIT(5) #define MSTR_DEVICETYPE_MASK GENMASK(5, 0) #define MSTR_2TMODE BIT(10) #define MSTR_BUSWIDTH_FULL (0 << 12) @@ -144,6 +147,7 @@ struct dram_para { u8 rows; u8 ranks; u8 bus_full_width; + bool size_fix; }; diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index bc8509b72a..060d71b177 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -86,6 +86,36 @@ config DRAM_SUN50I_H616_UNKNOWN_FEATURE ---help--- Select this when DRAM on your H616 board needs this unknown feature. + +config DRAM_SUN50I_H616_TRIM_SIZE + bool "H616 DRAM trim size" + help + Due to unknown issue, some H616 based boards may need to trim + size a bit. + +choice + prompt "H616 DRAM Type and Timing" + default SUNXI_DRAM_H616_DDR3_1333 + +config SUNXI_DRAM_H616_DDR3_1333 + bool "DDR3-1333 timings on the H616 DRAM controller" + help + This option is the DDR3-1333 timing used by the stock boot0 + by Allwinner. + +config SUNXI_DRAM_H616_LPDDR3 + bool "LPDDR3 timings on the H616 DRAM controller" + help + This option is the LPDDR3 timing used by the stock boot0 by + Allwinner. + +config SUNXI_DRAM_H616_LPDDR4 + bool "LPDDR4 timings on the H616 DRAM controller" + help + This option is the LPDDR4 timing used by the stock boot0 by + Allwinner. + +endchoice endif config SUN6I_P2WI @@ -130,6 +160,32 @@ config SUNXI_SRAM_ADDRESS Some newer SoCs map the boot ROM at address 0 instead and move the SRAM to a different address. +config SUNXI_RVBAR_ADDRESS + hex + depends on ARM64 + default 0x09010040 if SUN50I_GEN_H6 + default 0x017000a0 + ---help--- + The read-only RVBAR system register holds the address of the first + instruction to execute after a reset. Allwinner cores provide a + writable MMIO backing store for this register, to allow to set the + entry point when switching to AArch64. This store is on different + addresses, depending on the SoC. + +config SUNXI_RVBAR_ALTERNATIVE + hex + depends on ARM64 + default 0x08100040 if MACH_SUN50I_H616 + default SUNXI_RVBAR_ADDRESS + ---help--- + The H616 die exists in at least two variants, with one having the + RVBAR registers at a different address. If the SoC variant ID + (stored in SRAM_VER_REG[7:0]) is not 0, we need to use the + other address. + Set this alternative address to the same as the normal address + for all other SoCs, so the content of the SRAM_VER_REG becomes + irrelevant there, and we can use the same code. + config SUNXI_A64_TIMER_ERRATUM bool @@ -190,10 +246,10 @@ config MACH_SUNXI_H3_H5 select SUPPORT_SPL # TODO: try out A80's 8GiB DRAM space -# TODO: H616 supports 4 GiB DRAM space config SUNXI_DRAM_MAX_SIZE hex - default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 || MACH_SUN50I_H616 + default 0x100000000 if MACH_SUN50I_H616 + default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 default 0x80000000 choice @@ -469,7 +525,7 @@ config DRAM_CLK default 312 if MACH_SUN6I || MACH_SUN8I default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ MACH_SUN8I_V3S - default 672 if MACH_SUN50I + default 648 if MACH_SUN50I || MACH_SUN50I_H5 default 744 if MACH_SUN50I_H6 default 720 if MACH_SUN50I_H616 ---help--- @@ -642,6 +698,13 @@ config MACPWR Set the pin used to power the MAC. This takes a string in the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. +config PWRLED + string "Power led pin" + default "" + help + Set the pin used to power the led. This takes a string in the format + understood by sunxi_name_to_gpio, e.g. PC12 for pin 1 of port H. + config MMC0_CD_PIN string "Card detect pin for mmc0" default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I @@ -1054,7 +1117,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 9b84132eda..0537c29b22 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -27,6 +27,7 @@ #include #include #include +#include #include @@ -56,7 +57,7 @@ static struct mm_region sunxi_mem_map[] = { /* RAM */ .virt = 0x40000000UL, .phys = 0x40000000UL, - .size = 0xC0000000UL, + .size = CONFIG_SUNXI_DRAM_MAX_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -65,10 +66,24 @@ static struct mm_region sunxi_mem_map[] = { } }; struct mm_region *mem_map = sunxi_mem_map; + +ulong board_get_usable_ram_top(ulong total_size) +{ + /* Some devices (like the EMAC) have a 32-bit DMA limit. */ + if (gd->ram_top > (1ULL << 32)) + return 1ULL << 32; + + return gd->ram_top; +} #endif static int gpio_init(void) { +#if defined(CONFIG_MACH_SUNXI_H3_H5) + /* enable R_PIO GPIO access */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO); +#endif + __maybe_unused uint val; #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) #if defined(CONFIG_MACH_SUN4I) || \ diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 8e84062bd7..1b9afd574b 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -117,11 +117,10 @@ void clock_set_pll1(unsigned int clk) int k = 1; int m = 1; - if (clk > 1152000000) { - k = 2; - } else if (clk > 768000000) { + if (clk >= 1368000000) { k = 4; - m = 2; + } else if (clk >= 768000000) { + k = 2; } /* Switch to 24MHz clock while changing PLL1 */ @@ -137,11 +136,13 @@ void clock_set_pll1(unsigned int clk) writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); - sdelay(200); + + while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_CTRL_LOCK)) + ; /* Switch CPU to PLL1 */ - writel(AXI_DIV_3 << AXI_DIV_SHIFT | - ATB_DIV_2 << ATB_DIV_SHIFT | + writel(AXI_DIV_4 << AXI_DIV_SHIFT | + ATB_DIV_4 << ATB_DIV_SHIFT | CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, &ccm->cpu_axi_cfg); } diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index ef5876971c..205c78bb67 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -6,8 +6,6 @@ * unknown. That's why this driver has plenty of magic numbers. Some * meaning was nevertheless deduced from strings found in boot0 and * known meaning of some dram parameters. - * This driver only supports DDR3 memory and omits logic for all - * other supported types supported by hardware. * * (C) Copyright 2020 Jernej Skrabec * @@ -233,37 +231,79 @@ static const u8 phy_init[] = { 0x09, 0x05, 0x18 }; -static void mctl_phy_configure_odt(void) +static const u8 phy_init_lpddr3[] = { + 0x18, 0x06, 0x00, 0x05, 0x04, 0x03, 0x09, 0x02, + 0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07, + 0x17, 0x19, 0x1a +}; + +static const u8 phy_init_lpddr4[] = { + 0x02, 0x00, 0x17, 0x05, 0x04, 0x19, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01, + 0x18, 0x03, 0x1a +}; + +static void mctl_phy_configure_odt(struct dram_para *para) { - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x388); - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x38c); + unsigned int val; - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x3c8); - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x3cc); + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0xd; + else + val = 0xe; - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x408); - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x40c); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x388); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c8); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x408); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x448); - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x448); - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x44c); + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0xd; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x4; + else + val = 0xe; - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x340); - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x344); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x38c); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3cc); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x40c); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x44c); - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x348); - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x34c); + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0xd; + else + val = 0xe; - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x380); - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x384); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x340); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x344); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x348); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x34c); - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x3c0); - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x3c4); + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x0; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x7; + else + val = 0x8; - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x400); - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x404); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x380); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c0); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x400); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x440); - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x440); - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x444); + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x6; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x0; + else + val = 0x8; + + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x384); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c4); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x404); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x444); dmb(); } @@ -360,7 +400,7 @@ static bool mctl_phy_read_calibration(struct dram_para *para) } } - setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); } clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30); @@ -388,6 +428,11 @@ static bool mctl_phy_read_training(struct dram_para *para) bool result = true; int i; + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { + writel(0, SUNXI_DRAM_PHY0_BASE + 0x800); + writel(0, SUNXI_DRAM_PHY0_BASE + 0x81c); + } + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 3, 2); clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x804, 0x3f, 0xf); clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x808, 0x3f, 0xf); @@ -561,56 +606,118 @@ static bool mctl_phy_write_training(struct dram_para *para) static bool mctl_phy_bit_delay_compensation(struct dram_para *para) { - u32 *ptr; + u32 *ptr, val; int i; clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1); setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8); clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10); + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x4, 0x80); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x0a; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x23; + else + val = 0x16; ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x484); for (i = 0; i < 9; i++) { - writel_relaxed(0x16, ptr); - writel_relaxed(0x16, ptr + 0x30); + writel_relaxed(val, ptr); + writel_relaxed(val, ptr + 0x30); ptr += 2; } - writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4d0); - writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x590); - writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4cc); - writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x58c); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x10; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x14; + else + val = 0x1c; + + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x4d0); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x590); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x4cc); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x58c); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x0a; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x23; + else + val = 0x1a; ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x4d8); for (i = 0; i < 9; i++) { - writel_relaxed(0x1a, ptr); - writel_relaxed(0x1a, ptr + 0x30); + writel_relaxed(val, ptr); + writel_relaxed(val, ptr + 0x30); ptr += 2; } - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x524); - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e4); - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x520); - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e0); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x10; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x14; + else + val = 0x1e; + + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x524); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x5e4); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x520); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x5e0); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x0d; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x24; + else + val = 0x1a; ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x604); for (i = 0; i < 9; i++) { - writel_relaxed(0x1a, ptr); - writel_relaxed(0x1a, ptr + 0x30); + writel_relaxed(val, ptr); + writel_relaxed(val, ptr + 0x30); ptr += 2; } - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x650); - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x710); - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x64c); - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x70c); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x12; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x14; + else + val = 0x1e; + + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x650); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x710); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x64c); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x70c); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x0d; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x24; + else + val = 0x1a; ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x658); for (i = 0; i < 9; i++) { - writel_relaxed(0x1a, ptr); - writel_relaxed(0x1a, ptr + 0x30); + writel_relaxed(val, ptr); + writel_relaxed(val, ptr + 0x30); ptr += 2; } - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a4); - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x764); - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a0); - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x760); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x12; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x14; + else + val = 0x1a; + + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x6a4); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x764); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x6a0); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x760); dmb(); @@ -620,45 +727,98 @@ static bool mctl_phy_bit_delay_compensation(struct dram_para *para) clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80); clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 4); + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x0a; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x0e; + else + val = 0x10; + ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x480); for (i = 0; i < 9; i++) { - writel_relaxed(0x10, ptr); - writel_relaxed(0x10, ptr + 0x30); + writel_relaxed(val, ptr); + writel_relaxed(val, ptr + 0x30); ptr += 2; } - writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x528); - writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x5e8); - writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x4c8); - writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x588); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x1c; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x1c; + else + val = 0x18; + + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x528); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x5e8); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x4c8); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x588); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x0b; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x0e; + else + val = 0x12; ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x4d4); for (i = 0; i < 9; i++) { - writel_relaxed(0x12, ptr); - writel_relaxed(0x12, ptr + 0x30); + writel_relaxed(val, ptr); + writel_relaxed(val, ptr + 0x30); ptr += 2; } - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x52c); - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5ec); - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x51c); - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5dc); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x1c; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x1c; + else + val = 0x1a; + + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x52c); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x5ec); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x51c); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x5dc); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x0e; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x0e; + else + val = 0x12; ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x600); for (i = 0; i < 9; i++) { - writel_relaxed(0x12, ptr); - writel_relaxed(0x12, ptr + 0x30); + writel_relaxed(val, ptr); + writel_relaxed(val, ptr + 0x30); ptr += 2; } - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x6a8); - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x768); - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x648); - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x708); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x1c; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x1c; + else + val = 0x1a; + + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x6a8); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x768); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x648); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x708); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0x0d; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x0e; + else + val = 0x14; ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x654); for (i = 0; i < 9; i++) { - writel_relaxed(0x14, ptr); - writel_relaxed(0x14, ptr + 0x30); + writel_relaxed(val, ptr); + writel_relaxed(val, ptr + 0x30); ptr += 2; } + writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x6ac); writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x76c); writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x69c); @@ -677,38 +837,60 @@ static bool mctl_phy_init(struct dram_para *para) (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - u32 val, *ptr; + u32 val, *ptr, pat1, pat2; int i; + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x4, 0x80); + if (para->bus_full_width) val = 0xf; else val = 3; clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3c, 0xf, val); - writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x14); - writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x35c); - writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x368); - writel(0xd, SUNXI_DRAM_PHY0_BASE + 0x374); + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) { + pat1 = 0xe; + pat2 = 0x8; + } else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { + pat1 = 0x14; + pat2 = 0xa; + } else { + pat1 = 0xd; + pat2 = 0x9; + } + + writel(pat1, SUNXI_DRAM_PHY0_BASE + 0x14); + writel(pat1, SUNXI_DRAM_PHY0_BASE + 0x35c); + writel(pat1, SUNXI_DRAM_PHY0_BASE + 0x368); + writel(pat1, SUNXI_DRAM_PHY0_BASE + 0x374); writel(0, SUNXI_DRAM_PHY0_BASE + 0x18); writel(0, SUNXI_DRAM_PHY0_BASE + 0x360); writel(0, SUNXI_DRAM_PHY0_BASE + 0x36c); writel(0, SUNXI_DRAM_PHY0_BASE + 0x378); - writel(9, SUNXI_DRAM_PHY0_BASE + 0x1c); - writel(9, SUNXI_DRAM_PHY0_BASE + 0x364); - writel(9, SUNXI_DRAM_PHY0_BASE + 0x370); - writel(9, SUNXI_DRAM_PHY0_BASE + 0x37c); + writel(pat2, SUNXI_DRAM_PHY0_BASE + 0x1c); + writel(pat2, SUNXI_DRAM_PHY0_BASE + 0x364); + writel(pat2, SUNXI_DRAM_PHY0_BASE + 0x370); + writel(pat2, SUNXI_DRAM_PHY0_BASE + 0x37c); ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xc0); - for (i = 0; i < ARRAY_SIZE(phy_init); i++) - writel(phy_init[i], &ptr[i]); + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + for (i = 0; i < ARRAY_SIZE(phy_init_lpddr3); i++) + writel(phy_init_lpddr3[i], &ptr[i]); + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + for (i = 0; i < ARRAY_SIZE(phy_init_lpddr4); i++) + writel(phy_init_lpddr4[i], &ptr[i]); + else + for (i = 0; i < ARRAY_SIZE(phy_init); i++) + writel(phy_init[i], &ptr[i]); - if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE)) { + if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE) && + para->type == SUNXI_DRAM_TYPE_DDR3) { ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x780); for (i = 0; i < 32; i++) - writel(0x16, &ptr[i]); + writel(0xc, &ptr[i]); writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x78c); writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7a4); writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7b8); @@ -717,13 +899,51 @@ static bool mctl_phy_init(struct dram_para *para) writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7e0); } - writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc); - writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c); + if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE) && + para->type == SUNXI_DRAM_TYPE_LPDDR3) { + ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x780); + for (i = 0; i < 32; i++) + writel(0x4, &ptr[i]); + writel(0x12, SUNXI_DRAM_PHY0_BASE + 0x7dc); + writel(0x12, SUNXI_DRAM_PHY0_BASE + 0x7e0); + writel(0x8, SUNXI_DRAM_PHY0_BASE + 0x7e8); + if (para->ranks == 2) + writel(0x8, SUNXI_DRAM_PHY0_BASE + 0x7f8); + } - if (IS_ENABLED(DRAM_ODT_EN)) - mctl_phy_configure_odt(); + if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE) && + para->type == SUNXI_DRAM_TYPE_LPDDR4) { + ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x780); + for (i = 0; i < 32; i++) + writel(0xc, &ptr[i]); + /* TODO: check! */ + writel(0x6, SUNXI_DRAM_PHY0_BASE + 0x7d8); + writel(0x6, SUNXI_DRAM_PHY0_BASE + 0x7dc); + writel(0x6, SUNXI_DRAM_PHY0_BASE + 0x7e0); + writel(0x6, SUNXI_DRAM_PHY0_BASE + 0x7f4); + } - clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, 0xa); + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0xb2; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0x44; + else + val = 0x80; + + writel(val, SUNXI_DRAM_PHY0_BASE + 0x3dc); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x45c); + + if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) + mctl_phy_configure_odt(para); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + val = 0xb; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + val = 0xd; + else + val = 0xa; + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, val); if (para->clk <= 672) writel(0xf, SUNXI_DRAM_PHY0_BASE + 0x20); @@ -765,21 +985,72 @@ static bool mctl_phy_init(struct dram_para *para) writel(1, &mctl_ctl->swctl); mctl_await_completion(&mctl_ctl->swstat, 1, 1); - writel(0x1f14, &mctl_ctl->mrctrl1); - writel(0x80000030, &mctl_ctl->mrctrl0); - mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + if (para->type == SUNXI_DRAM_TYPE_DDR3) { + writel(0x1f14, &mctl_ctl->mrctrl1); + writel(0x80000030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); - writel(4, &mctl_ctl->mrctrl1); - writel(0x80001030, &mctl_ctl->mrctrl0); - mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + writel(4, &mctl_ctl->mrctrl1); + writel(0x80001030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); - writel(0x20, &mctl_ctl->mrctrl1); - writel(0x80002030, &mctl_ctl->mrctrl0); - mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + writel(0x20, &mctl_ctl->mrctrl1); + writel(0x80002030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); - writel(0, &mctl_ctl->mrctrl1); - writel(0x80003030, &mctl_ctl->mrctrl0); - mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + writel(0, &mctl_ctl->mrctrl1); + writel(0x80003030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + } + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) { + writel(0x83 | 0x100, &mctl_ctl->mrctrl1); + writel(0x80000030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x1c | 0x200, &mctl_ctl->mrctrl1); + writel(0x80000030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x01 | 0x300, &mctl_ctl->mrctrl1); + writel(0x80000030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + } + + /* FIXME: check! */ + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { + writel(0x34 | 0x100, &mctl_ctl->mrctrl1); + writel(0x80000030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x1b | 0x200, &mctl_ctl->mrctrl1); + writel(0x80000030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x33 | 0x300, &mctl_ctl->mrctrl1); + writel(0x80000030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x03 | 0x400, &mctl_ctl->mrctrl1); + writel(0x80000030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x04 | 0xb00, &mctl_ctl->mrctrl1); + writel(0x80000030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x72 | 0xc00, &mctl_ctl->mrctrl1); + writel(0x80000030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x09 | 0xe00, &mctl_ctl->mrctrl1); + writel(0x80000030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x24 | 0x1600, &mctl_ctl->mrctrl1); + writel(0x80000030, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + } writel(0, SUNXI_DRAM_PHY0_BASE + 0x54); @@ -848,14 +1119,25 @@ static bool mctl_ctrl_init(struct dram_para *para) setbits_le32(&mctl_com->unk_0x008, 0xff00); + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + mctl_com->unk_0x050 = 1; + clrsetbits_le32(&mctl_ctl->sched[0], 0xff00, 0x3000); writel(0, &mctl_ctl->hwlpctl); setbits_le32(&mctl_com->unk_0x008, 0xff00); - reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks); - reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE; + reg_val = MSTR_ACTIVE_RANKS(para->ranks); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) + reg_val |= MSTR_BURST_LENGTH(8) | MSTR_DEVICETYPE_LPDDR3; + else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + reg_val |= MSTR_BURST_LENGTH(16) | MSTR_DEVICETYPE_LPDDR4; + else + reg_val |= MSTR_BURST_LENGTH(8) | + MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE; + if (para->bus_full_width) reg_val |= MSTR_BUSWIDTH_FULL; else @@ -867,12 +1149,22 @@ static bool mctl_ctrl_init(struct dram_para *para) else writel(0x0201, &mctl_ctl->odtmap); - writel(0x06000400, &mctl_ctl->odtcfg); - writel(0x06000400, &mctl_ctl->unk_0x2240); - writel(0x06000400, &mctl_ctl->unk_0x3240); - writel(0x06000400, &mctl_ctl->unk_0x4240); + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) { + u32 wr_delay = (para->clk >= 400) ? 4 : 3; + u32 ru = (7 * para->clk) / 2000; + reg_val = ((ru + 7) << 24) | ((wr_delay - ru) << 16) | 0x400; + } else if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { + reg_val = 0x04000400; + } else { + reg_val = 0x06000400; + } - setbits_le32(&mctl_com->cr, BIT(31)); + writel(reg_val, &mctl_ctl->odtcfg); + writel(reg_val, &mctl_ctl->unk_0x2240); + writel(reg_val, &mctl_ctl->unk_0x3240); + writel(reg_val, &mctl_ctl->unk_0x4240); + + writel(BIT(31), &mctl_com->cr); mctl_set_addrmap(para); @@ -994,19 +1286,33 @@ static void mctl_auto_detect_dram_size(struct dram_para *para) static unsigned long mctl_calc_size(struct dram_para *para) { u8 width = para->bus_full_width ? 4 : 2; + unsigned long size; /* 8 banks */ - return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks; + size = (1ULL << (para->cols + para->rows + 3)) * width * para->ranks; + + if (para->size_fix) + size = (size * 3) / 4; + + return size; } unsigned long sunxi_dram_init(void) { struct dram_para para = { .clk = CONFIG_DRAM_CLK, - .type = SUNXI_DRAM_TYPE_DDR3, }; unsigned long size; + if (IS_ENABLED(CONFIG_SUNXI_DRAM_H616_DDR3_1333)) + para.type = SUNXI_DRAM_TYPE_DDR3; + if (IS_ENABLED(CONFIG_SUNXI_DRAM_H616_LPDDR3)) + para.type = SUNXI_DRAM_TYPE_LPDDR3; + if (IS_ENABLED(CONFIG_SUNXI_DRAM_H616_LPDDR4)) + para.type = SUNXI_DRAM_TYPE_LPDDR4; + if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_TRIM_SIZE)) + para.size_fix = true; + setbits_le32(0x7010310, BIT(8)); clrbits_le32(0x7010318, 0x3f); diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile index 39a8756c29..08b891e4a0 100644 --- a/arch/arm/mach-sunxi/dram_timings/Makefile +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -3,5 +3,6 @@ obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3) += h6_lpddr3.o obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333) += h6_ddr3_1333.o -# currently only DDR3 is supported on H616 -obj-$(CONFIG_MACH_SUN50I_H616) += h616_ddr3_1333.o +obj-$(CONFIG_SUNXI_DRAM_H616_DDR3_1333) += h616_ddr3_1333.o +obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR4) += h616_lpddr4.o +obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR3) += h616_lpddr3.o diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c new file mode 100644 index 0000000000..a59a8aa87f --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c @@ -0,0 +1,95 @@ +/* + * sun50i H616 DDR3-1333 timings, as programmed by Allwinner's boot0 + * + * The chips are probably able to be driven by a faster clock, but boot0 + * uses a more conservative timing (as usual). + * + * (C) Copyright 2020 Jernej Skrabec + * Based on H6 DDR3 timings: + * (C) Copyright 2018,2019 Arm Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void mctl_set_timing_params(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 tccd = 2; /* JEDEC: 4nCK */ + u8 tfaw = max(ns_to_t(50), 4); /* JEDEC: 30 ns w/ 1K pages */ + u8 trrd = max(ns_to_t(10), 1); /* JEDEC: max(6 ns, 4nCK) */ + u8 trcd = max(ns_to_t(24), 2); /* JEDEC: 13.5 ns */ + u8 trc = ns_to_t(70); /* JEDEC: 49.5 ns */ + u8 txp = max(ns_to_t(8), 2); /* JEDEC: max(6 ns, 3nCK) */ + u8 trtp = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */ + u8 trp = ns_to_t(27); /* JEDEC: >= 13.75 ns */ + u8 tras = ns_to_t(42); /* JEDEC >= 36 ns, <= 9*trefi */ + u16 trefi = ns_to_t(3900) / 32; /* JEDEC: 7.8us@Tcase <= 85C */ + u16 trfc = ns_to_t(210); /* JEDEC: 160 ns for 2Gb */ + u16 txsr = ns_to_t(220); /* ? */ + + u8 tmrw = 5; /* ? */ + u8 tmrd = 5; /* JEDEC: 4nCK */ + u8 tmod = 12; /* JEDEC: max(15 ns, 12nCK) */ + u8 tcke = 3; /* JEDEC: max(5.625 ns, 3nCK) */ + u8 tcksrx = 5; /* JEDEC: max(10 ns, 5nCK) */ + u8 tcksre = 5; /* JEDEC: max(10 ns, 5nCK) */ + u8 tckesr = 5; /* JEDEC: tCKE(min) + 1nCK */ + u8 trasmax = 24; /* JEDEC: tREFI * 9 */ + u8 txs = 4; /* JEDEC: max(5nCK,tRFC+10ns) */ + u8 txsdll = 16; /* JEDEC: 512 nCK */ + u8 txsabort = 4; /* ? */ + u8 txsfast = 4; /* ? */ + u8 tcl = 7; /* JEDEC: CL / 2 => 6 */ + u8 tcwl = 4; /* JEDEC: 8 */ + u8 t_rdata_en = 0xc; /* ? */ + + u8 twtp = 16; /* (WL + BL / 2 + tWR) / 2 */ + u8 twr2rd = trtp + 9; /* (WL + BL / 2 + tWTR) / 2 */ + u8 trd2wr = 13; /* (RL + BL / 2 + 2 - WL) / 2 */ + + /* set DRAM timing */ + writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, + &mctl_ctl->dramtmg[0]); + writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); + writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, + &mctl_ctl->dramtmg[2]); + writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); + writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, + &mctl_ctl->dramtmg[4]); + writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, + &mctl_ctl->dramtmg[5]); + /* Value suggested by ZynqMP manual and used by libdram */ + writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); + writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs, + &mctl_ctl->dramtmg[8]); + writel(0x00020208, &mctl_ctl->dramtmg[9]); + writel(0xE0C05, &mctl_ctl->dramtmg[10]); + writel(0x440C021C, &mctl_ctl->dramtmg[11]); + writel(8, &mctl_ctl->dramtmg[12]); + writel(0xA100002, &mctl_ctl->dramtmg[13]); + writel(txsr, &mctl_ctl->dramtmg[14]); + + //clrsetbits_le32(&mctl_ctl->init[0], 0x3C00FFFF, 0x4F0000); + writel(0x4f0112, &mctl_ctl->init[0]); + writel(0x420000, &mctl_ctl->init[1]); + writel(0xd05, &mctl_ctl->init[2]); + writel(0x83001c, &mctl_ctl->init[3]); + writel(0x10000, &mctl_ctl->init[4]); + + writel(0, &mctl_ctl->dfimisc); + clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); + + /* Configure DFI timing */ + writel((tcl - 1) | 0x2000000 | (t_rdata_en << 16) | 0x808000, + &mctl_ctl->dfitmg0); + writel(0x100202, &mctl_ctl->dfitmg1); + + /* set refresh timing */ + writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg); +} diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4.c new file mode 100644 index 0000000000..ca36899fe7 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4.c @@ -0,0 +1,97 @@ +/* + * sun50i H616 DDR3-1333 timings, as programmed by Allwinner's boot0 + * + * The chips are probably able to be driven by a faster clock, but boot0 + * uses a more conservative timing (as usual). + * + * (C) Copyright 2020 Jernej Skrabec + * Based on H6 DDR3 timings: + * (C) Copyright 2018,2019 Arm Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void mctl_set_timing_params(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 tccd = 4; /* JEDEC: 4nCK */ + u8 tfaw = ns_to_t(40); /* JEDEC: 40 ns w/ 1K pages */ + u8 trrd = max(ns_to_t(10), 2); /* JEDEC: max(10 ns, 2nCK) */ + u8 trcd = max(ns_to_t(18), 2); /* JEDEC: 13.5 ns */ + u8 trc = ns_to_t(65); /* JEDEC: 49.5 ns */ + u8 txp = max(ns_to_t(8), 2); /* JEDEC: max(6 ns, 3nCK) */ + u8 trtp = max(ns_to_t(8), 4); /* JEDEC: max(7.5 ns, 4nCK) */ + u8 trp = ns_to_t(21); /* JEDEC: >= 13.75 ns */ + u8 tras = ns_to_t(42); /* JEDEC >= 36 ns, <= 9*trefi */ + u16 trefi = ns_to_t(3904) / 32; /* JEDEC: 7.8us@Tcase <= 85C */ + u16 trfc = ns_to_t(180); /* JEDEC: 160 ns for 2Gb */ + u16 txsr = ns_to_t(190); /* ? */ + + u8 tmrw = max(ns_to_t(14), 5); /* ? */ + u8 tmrd = tmrw; /* JEDEC: 4nCK */ + u8 tmod = 12; /* JEDEC: max(15 ns, 12nCK) */ + u8 tcke = max(ns_to_t(15), 2); /* JEDEC: max(5.625 ns, 3nCK) */ + u8 tcksrx = max(ns_to_t(2), 2); /* JEDEC: max(10 ns, 5nCK) */ + u8 tcksre = max(ns_to_t(5), 2); /* JEDEC: max(10 ns, 5nCK) */ + u8 tckesr = tcke; /* JEDEC: tCKE(min) + 1nCK */ + u8 trasmax = (trefi * 9) / 32; /* JEDEC: tREFI * 9 */ + u8 txs = 4; /* JEDEC: max(5nCK,tRFC+10ns) */ + u8 txsdll = 16; /* JEDEC: 512 nCK */ + u8 txsabort = 4; /* ? */ + u8 txsfast = 4; /* ? */ + u8 tcl = 10; /* JEDEC: CL / 2 => 6 */ + u8 tcwl = 5; /* JEDEC: 8 */ + u8 t_rdata_en = 17; /* ? */ + u8 tphy_wrlat = 5; + + u8 twtp = 24; /* (WL + BL / 2 + tWR) / 2 */ + u8 twr2rd = max(trrd, (u8)4) + 14;/* (WL + BL / 2 + tWTR) / 2 */ + u8 trd2wr = (ns_to_t(4) + 17) - ns_to_t(1);/* (RL + BL / 2 + 2 - WL) / 2 */ + + /* set DRAM timing */ + writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, + &mctl_ctl->dramtmg[0]); + writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); + writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, + &mctl_ctl->dramtmg[2]); + writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); + writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, + &mctl_ctl->dramtmg[4]); + writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, + &mctl_ctl->dramtmg[5]); + /* Value suggested by ZynqMP manual and used by libdram */ + writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); + writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs, + &mctl_ctl->dramtmg[8]); + writel(0x00020208, &mctl_ctl->dramtmg[9]); + writel(0xE0C05, &mctl_ctl->dramtmg[10]); + writel(0x440C021C, &mctl_ctl->dramtmg[11]); + writel(8, &mctl_ctl->dramtmg[12]); + writel(0xA100002, &mctl_ctl->dramtmg[13]); + writel(txsr, &mctl_ctl->dramtmg[14]); + + clrsetbits_le32(&mctl_ctl->init[0], 0xC0000FFF, 0x3f0); + writel(0x01f20000, &mctl_ctl->init[1]); + writel(0x00000d05, &mctl_ctl->init[2]); + writel(0, &mctl_ctl->dfimisc); + writel(0x0034001b, &mctl_ctl->init[3]); + writel(0x00330000, &mctl_ctl->init[4]); + writel(0x00040072, &mctl_ctl->init[6]); + writel(0x00240009, &mctl_ctl->init[7]); + + clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); + + /* Configure DFI timing */ + writel(tphy_wrlat | 0x2000000 | (t_rdata_en << 16) | 0x808000, + &mctl_ctl->dfitmg0); + writel(0x100202, &mctl_ctl->dfitmg1); + + /* set refresh timing */ + writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg); +} diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 0394ce8564..74d14e4053 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -19,6 +19,7 @@ #define AXP209_I2C_ADDR 0x34 #define AXP305_I2C_ADDR 0x36 +#define AXP313A_I2C_ADDR 0x36 #define AXP221_CHIP_ADDR 0x68 #define AXP221_CTRL_ADDR 0x3e @@ -68,6 +69,9 @@ int pmic_bus_read(u8 reg, u8 *data) return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); #elif defined CONFIG_AXP305_POWER return i2c_read(AXP305_I2C_ADDR, reg, 1, data, 1); +#elif defined CONFIG_AXP313A_POWER + return i2c_read(AXP313A_I2C_ADDR, reg, 1, data, 1); +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER #elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I return p2wi_read(reg, data); @@ -87,6 +91,9 @@ int pmic_bus_write(u8 reg, u8 data) return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); #elif defined CONFIG_AXP305_POWER return i2c_write(AXP305_I2C_ADDR, reg, 1, &data, 1); +#elif defined CONFIG_AXP313A_POWER + return i2c_write(AXP313A_I2C_ADDR, reg, 1, &data, 1); +#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER #elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I return p2wi_write(reg, data); diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 15e86cbac8..53b7c0324b 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -77,7 +78,7 @@ #define CCM_AHB_GATING0 (0x01C20000 + 0x60) #define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c) -#ifdef CONFIG_MACH_SUN50I_H6 +#ifdef CONFIG_SUN50I_GEN_H6 #define CCM_SPI0_CLK (0x03001000 + 0x940) #else #define CCM_SPI0_CLK (0x01C20000 + 0xA0) @@ -95,7 +96,7 @@ /* * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. - * The H6 uses PC0, PC2, PC3, PC5. + * The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4. */ static void spi0_pinmux_setup(unsigned int pin_function) { @@ -103,12 +104,16 @@ static void spi0_pinmux_setup(unsigned int pin_function) sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); - /* All chips except H6 use PC1, and only H6 uses PC5. */ - if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + /* All chips except H6 and H616 use PC1. */ + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); - else + + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); + if (IS_ENABLED(CONFIG_SUN50I_GEN_H616)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); + /* Older generations use PC23 for CS, newer ones use PC3. */ if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || IS_ENABLED(CONFIG_MACH_SUN8I_R40)) @@ -120,7 +125,7 @@ static void spi0_pinmux_setup(unsigned int pin_function) static bool is_sun6i_gen_spi(void) { return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || - IS_ENABLED(CONFIG_MACH_SUN50I_H6); + IS_ENABLED(CONFIG_SUN50I_GEN_H6); } static uintptr_t spi0_base_address(void) @@ -128,7 +133,7 @@ static uintptr_t spi0_base_address(void) if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) return 0x01C05000; - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) return 0x05010000; if (!is_sun6i_gen_spi()) @@ -145,14 +150,14 @@ static void spi0_enable_clock(void) uintptr_t base = spi0_base_address(); /* Deassert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); else if (is_sun6i_gen_spi()) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); /* Open the SPI0 gate */ - if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Divide by 4 */ @@ -193,11 +198,11 @@ static void spi0_disable_clock(void) writel(0, CCM_SPI0_CLK); /* Close the SPI0 gate */ - if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Assert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); else if (is_sun6i_gen_spi()) clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, @@ -209,7 +214,7 @@ static void spi0_init(void) unsigned int pin_function = SUNXI_GPC_SPI0; if (IS_ENABLED(CONFIG_MACH_SUN50I) || - IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + IS_ENABLED(CONFIG_SUN50I_GEN_H6)) pin_function = SUN50I_GPC_SPI0; spi0_pinmux_setup(pin_function); @@ -326,10 +331,13 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, int ret = 0; struct image_header *header; header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); + int load_offset = readl(SPL_ADDR + 0x10); + + load_offset = max(load_offset, CONFIG_SYS_SPI_U_BOOT_OFFS); spi0_init(); - spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40); + spi0_read_data((void *)header, load_offset, 0x40); if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && image_get_magic(header) == FDT_MAGIC) { @@ -342,14 +350,14 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, load.bl_len = 1; load.read = spi_load_read; ret = spl_load_simple_fit(spl_image, &load, - CONFIG_SYS_SPI_U_BOOT_OFFS, header); + load_offset, header); } else { ret = spl_parse_image_header(spl_image, header); if (ret) return ret; spi0_read_data((void *)spl_image->load_addr, - CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size); + load_offset, spl_image->size); } spi0_deinit(); diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 21651a1bfc..a5b0e4f152 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -233,7 +233,7 @@ static void mmc_pinmux_setup(int sdc); /* add board specific code here */ int board_init(void) { - __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin; + __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin, pwrled_pin; gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); @@ -293,6 +293,24 @@ int board_init(void) } } + if (CONFIG_PWRLED[0]) { + pwrled_pin = sunxi_name_to_gpio(CONFIG_PWRLED); + if (pwrled_pin >= 0) { + gpio_request(pwrled_pin, "pwrled"); + gpio_direction_output(pwrled_pin, 1); + } + } + +#if CONFIG_MACH_SUN50I_H616 + /* + * The bit[16] of register reg[0x03000000] must be zero for the THS + * driver to work properly in the kernel. The BSP u-boot is putting + * the whole register to zero so we are doing the same. + */ + writel(0x0, SUNXI_SRAMC_BASE); + writel(0x0, 0x07010254); +#endif + #if CONFIG_IS_ENABLED(DM_I2C) /* * Temporary workaround for enabling I2C clocks until proper sunxi DM @@ -645,24 +663,34 @@ void sunxi_board_init(void) { int power_failed = 0; +#ifdef CONFIG_MACH_SUN8I_H3 + /* turn on power LED (PL10) on H3 boards */ + gpio_direction_output(SUNXI_GPL(10), 1); +#endif + #ifdef CONFIG_SY8106A_POWER power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); #endif #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \ - defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER + defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER || \ + defined CONFIG_AXP313A_POWER power_failed = axp_init(); #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ defined CONFIG_AXP818_POWER power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); #endif -#if !defined(CONFIG_AXP305_POWER) +#if !defined(CONFIG_AXP305_POWER) && !defined(CONFIG_AXP313A_POWER) power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); #endif -#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) +#if defined(CONFIG_AXP313A_POWER) + power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); +#endif +#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) && \ + !defined(CONFIG_AXP313A_POWER) power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); #endif #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ @@ -674,10 +702,11 @@ void sunxi_board_init(void) defined CONFIG_AXP818_POWER power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); #endif -#if !defined(CONFIG_AXP305_POWER) +#if !defined(CONFIG_AXP305_POWER) && !defined(CONFIG_AXP313A_POWER) power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); #endif -#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER) +#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER) && \ + !defined(CONFIG_AXP313A_POWER) power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); #endif #ifdef CONFIG_AXP209_POWER @@ -888,6 +917,74 @@ static void setup_environment(const void *fdt) } } +#if defined(CONFIG_BOOT_PROCESS_MULTI_DTB) && !defined(CONFIG_SPL_BUILD) + +#define NP_NEO2_DT_SS "nanopi-neo2." + +#define NP_NEO2_DT_EXT_V1_1 "-v1.1.dtb" + +#define NP_NEO2_BOARD_ID_GPIO "PL3" +#define NP_NEO2_BOARD_ID_1_0 1 +#define NP_NEO2_BOARD_ID_1_1 0 + +void boot_process_multi_dtb(void) +{ + const char *fdtfile = env_get("fdtfile"); + if (fdtfile == NULL) { + return; + } + + /* check for a NanoPi NEO2 */ + if (strstr(fdtfile, NP_NEO2_DT_SS) != NULL) { + int board_id_pin, prev_cfg, ret, rev_1_1; + + /* NEO2 DT found; process board revision and select corresponding DT */ + + board_id_pin = sunxi_name_to_gpio(NP_NEO2_BOARD_ID_GPIO); + if (board_id_pin < 0) { + return; + } + + ret = gpio_request(board_id_pin, "board_id_pin"); + if (ret) { + return; + } + + prev_cfg = sunxi_gpio_get_cfgpin(board_id_pin); + + gpio_direction_input(board_id_pin); + sunxi_gpio_set_pull(board_id_pin, SUNXI_GPIO_PULL_DISABLE); + + mdelay(2); + + rev_1_1 = gpio_get_value(board_id_pin) == NP_NEO2_BOARD_ID_1_1; + + sunxi_gpio_set_cfgpin(board_id_pin, prev_cfg); + gpio_free(board_id_pin); + + printf("NanoPi NEO2 v1.%d detected\n", rev_1_1); + + if (rev_1_1) { + int ddt_len = sizeof(CONFIG_DEFAULT_DEVICE_TREE); + int fdt_len = strlen(fdtfile); + + char *n_fdtfile = (char *)malloc(max(fdt_len, ddt_len) + sizeof(NP_NEO2_DT_EXT_V1_1) + 1); + if (n_fdtfile != NULL) { + char *cp = strstr(strcpy(n_fdtfile, fdtfile), CONFIG_DEFAULT_DEVICE_TREE); + if (cp != NULL) { + cp[ddt_len - 1] = '\0'; + strcat(cp, NP_NEO2_DT_EXT_V1_1); + + env_set("fdtfile", n_fdtfile); + } + + free(n_fdtfile); + } + } + } +} +#endif + int misc_init_r(void) { const char *spl_dt_name; @@ -930,6 +1027,10 @@ int board_late_init(void) usb_ether_init(); #endif +#if defined(CONFIG_BOOT_PROCESS_MULTI_DTB) && !defined(CONFIG_SPL_BUILD) + boot_process_multi_dtb(); +#endif + return 0; } @@ -970,10 +1071,12 @@ int ft_board_setup(void *blob, struct bd_info *bd) int __maybe_unused r; /* - * Call setup_environment again in case the boot fdt has - * ethernet aliases the u-boot copy does not have. + * Call setup_environment and fdt_fixup_ethernet again + * in case the boot fdt has ethernet aliases the u-boot + * copy does not have. */ setup_environment(blob); + fdt_fixup_ethernet(blob); bluetooth_dt_fixup(blob); diff --git a/cmd/Kconfig b/cmd/Kconfig index a9fb4eead2..da9524447f 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1653,6 +1653,7 @@ menu "Misc commands" config CMD_BMP bool "Enable 'bmp' command" depends on LCD || DM_VIDEO || VIDEO + default y help This provides a way to obtain information about a BMP-format image and to display it. BMP (which presumably stands for BitMaP) is a diff --git a/cmd/fdt.c b/cmd/fdt.c index f1e2fc2fd8..1f6e5e510c 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -18,6 +18,7 @@ #include #include #include +#include #define MAX_LEVEL 32 /* how deeply nested we will go */ #define SCRATCHPAD 1024 /* bytes of scratchpad memory */ @@ -771,7 +772,10 @@ static int fdt_parse_prop(char * const *newval, int count, char *data, int *len) cp = newp; tmp = simple_strtoul(cp, &newp, 0); if (*cp != '?') - *(fdt32_t *)data = cpu_to_fdt32(tmp); + { + tmp = cpu_to_fdt32(tmp); + put_unaligned(tmp, (fdt32_t *)data); + } else newp++; diff --git a/common/Kconfig.boot b/common/Kconfig.boot index 89a3161f1f..c89c6afea4 100644 --- a/common/Kconfig.boot +++ b/common/Kconfig.boot @@ -793,7 +793,7 @@ config AUTOBOOT_KEYED config AUTOBOOT_PROMPT string "Autoboot stop prompt" depends on AUTOBOOT_KEYED - default "Autoboot in %d seconds\\n" + default "Autoboot in %d seconds, press to stop\\n" help This string is displayed before the boot delay selected by CONFIG_BOOTDELAY starts. If it is not defined there is no @@ -833,6 +833,7 @@ config AUTOBOOT_DELAY_STR config AUTOBOOT_STOP_STR string "Stop autobooting via specific input key / string" depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION + default " " help This option enables stopping (aborting) of the automatic boot feature only by issuing a specific input key or diff --git a/configs/Awsom_defconfig b/configs/Awsom_defconfig new file mode 100644 index 0000000000..9589deed82 --- /dev/null +++ b/configs/Awsom_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=480 +CONFIG_DRAM_ZQ=127 +CONFIG_DRAM_EMR1=4 +CONFIG_MMC0_CD_PIN="PB9" +CONFIG_SATAPWR="PB8" +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2" +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SUN7I_GMAC=y +CONFIG_DM_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index e0adffd120..182fcf42ac 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -20,3 +20,4 @@ CONFIG_AXP_ELDO3_VOLT=1200 CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 50c8adca59..758582cfd1 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi" CONFIG_SPL=y CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=432 +CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH23" CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 @@ -20,3 +20,4 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig index bad38a6656..681b0f5ece 100644 --- a/configs/Bananapi_m2m_defconfig +++ b/configs/Bananapi_m2m_defconfig @@ -15,3 +15,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_FUNCTION_MASS_STORAGE=y +CONFIG_VIDEO_DE2=n diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index 5447bea0bb..651a899059 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro" CONFIG_SPL=y CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=432 +CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH23" CONFIG_USB1_VBUS_PIN="PH0" CONFIG_USB2_VBUS_PIN="PH1" diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index 65cf621479..187286d8db 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2" CONFIG_SPL=y CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=480 +CONFIG_DRAM_CLK=432 CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y @@ -17,3 +17,5 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_VIDEO_DE2=n diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index b5a28ab539..c38883ef07 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard" CONFIG_SPL=y CONFIG_MACH_SUN4I=y -CONFIG_DRAM_CLK=480 +CONFIG_DRAM_CLK=432 CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y @@ -15,3 +15,4 @@ CONFIG_SUN4I_EMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index 0929997736..abb96ab368 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck" CONFIG_SPL=y CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=432 +CONFIG_DRAM_CLK=384 CONFIG_MMC0_CD_PIN="PH1" CONFIG_USB0_VBUS_PIN="PH17" CONFIG_USB0_VBUS_DET="PH22" @@ -28,3 +28,5 @@ CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_VIDEO_DE2=n diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index c7bea1ce83..bdcded38e4 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1" CONFIG_SPL=y CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=432 +CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH23" CONFIG_MMC0_CD_PIN="PH10" CONFIG_SATAPWR="PB3" diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index e278e27918..1ca3485c7e 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" CONFIG_SPL=y CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=480 +CONFIG_DRAM_CLK=408 CONFIG_DRAM_ZQ=122 CONFIG_SATAPWR="PH2" CONFIG_AHCI=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index dd441efb48..9bbe5d9d57 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -15,3 +15,4 @@ CONFIG_SUN4I_EMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/Merrii_Hummingbird_A20_defconfig b/configs/Merrii_Hummingbird_A20_defconfig new file mode 100644 index 0000000000..3bdf8d047e --- /dev/null +++ b/configs/Merrii_Hummingbird_A20_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=432 +CONFIG_MMC0_CD_PIN="PH1" +CONFIG_SATAPWR="PB8" +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-hummingbird" +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_SCSI_AHCI=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SUN7I_GMAC=y +CONFIG_SCSI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index a6f427068d..64732a961e 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi" CONFIG_SPL=y CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=432 +CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH23" CONFIG_USB1_VBUS_PIN="PH26" CONFIG_USB2_VBUS_PIN="PH22" diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index cf0b95bec2..e8ca7a0329 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini" CONFIG_SPL=y CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=432 +CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH23" CONFIG_MMC0_CD_PIN="PH10" CONFIG_MMC3_CD_PIN="PH11" @@ -24,3 +24,4 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index d27f495f48..d3aa2e04ba 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-bananapi-m3" CONFIG_SPL=y CONFIG_MACH_SUN8I_A83T=y CONFIG_DRAM_TYPE=7 -CONFIG_DRAM_CLK=480 +CONFIG_DRAM_CLK=384 CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig index 8ec9eb3e9c..4ccb4c8467 100644 --- a/configs/a64-olinuxino-emmc_defconfig +++ b/configs/a64-olinuxino-emmc_defconfig @@ -10,3 +10,4 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig index 16cef18bee..13504f31df 100644 --- a/configs/a64-olinuxino_defconfig +++ b/configs/a64-olinuxino_defconfig @@ -2,10 +2,15 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino" CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUNXI=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_DRAM_CLK=624 +CONFIG_DRAM_ZQ=3881949 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index 777a249ff9..26ae48f255 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -20,3 +20,4 @@ CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig index 26ced59fb0..a723dc4847 100644 --- a/configs/bananapi_m2_plus_h3_defconfig +++ b/configs/bananapi_m2_plus_h3_defconfig @@ -11,3 +11,4 @@ CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y +CONFIG_VIDEO_DE2=n diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig index fb6c945919..2e4ecdfbe8 100644 --- a/configs/bananapi_m2_plus_h5_defconfig +++ b/configs/bananapi_m2_plus_h5_defconfig @@ -11,3 +11,4 @@ CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y +CONFIG_VIDEO_DE2=n diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig index ac3f8f5ab8..58ce3e170f 100644 --- a/configs/bananapi_m2_zero_defconfig +++ b/configs/bananapi_m2_zero_defconfig @@ -6,3 +6,4 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 CONFIG_MMC0_CD_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_VIDEO_DE2=n diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig index 292044d7b8..0d47ca6415 100644 --- a/configs/bananapi_m64_defconfig +++ b/configs/bananapi_m64_defconfig @@ -11,3 +11,4 @@ CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y +CONFIG_VIDEO_DE2=n diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig index 6206d90900..45355dc39e 100644 --- a/configs/beelink_x2_defconfig +++ b/configs/beelink_x2_defconfig @@ -1,10 +1,23 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2" -CONFIG_SPL=y +CONFIG_SYS_TEXT_BASE=0x4a000000 CONFIG_MACH_SUN8I_H3=y -CONFIG_DRAM_CLK=567 +CONFIG_DRAM_CLK=624 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y +CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +CONFIG_VIDEO_DE2=n diff --git a/configs/libretech_all_h3_cc_h2_plus_defconfig b/configs/libretech_all_h3_cc_h2_plus_defconfig index 8725fe64cd..e2b58e47f5 100644 --- a/configs/libretech_all_h3_cc_h2_plus_defconfig +++ b/configs/libretech_all_h3_cc_h2_plus_defconfig @@ -9,3 +9,4 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig index 5275fdc36d..11cd4e0fe3 100644 --- a/configs/libretech_all_h3_cc_h3_defconfig +++ b/configs/libretech_all_h3_cc_h3_defconfig @@ -9,3 +9,4 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig index 9627401949..6fefb6756d 100644 --- a/configs/libretech_all_h3_cc_h5_defconfig +++ b/configs/libretech_all_h3_cc_h5_defconfig @@ -9,3 +9,4 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/libretech_all_h5_cc_h5_defconfig b/configs/libretech_all_h5_cc_h5_defconfig index 25bfe52b32..3abfa6e2f6 100644 --- a/configs/libretech_all_h5_cc_h5_defconfig +++ b/configs/libretech_all_h5_cc_h5_defconfig @@ -14,3 +14,4 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig index 70fc257eeb..3eb285ee98 100644 --- a/configs/nanopi_a64_defconfig +++ b/configs/nanopi_a64_defconfig @@ -8,3 +8,4 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/nanopi_duo2_defconfig b/configs/nanopi_duo2_defconfig new file mode 100644 index 0000000000..bfeae46b58 --- /dev/null +++ b/configs/nanopi_duo2_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SYS_TEXT_BASE=0x4a000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +# CONFIG_VIDEO_DE2 is not set +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-duo2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +CONFIG_SPL=y +CONFIG_SYS_CLK_FREQ=480000000 +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_SPL_SPI_SUNXI=y +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_duo_defconfig b/configs/nanopi_duo_defconfig new file mode 100644 index 0000000000..79175965b5 --- /dev/null +++ b/configs/nanopi_duo_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SYS_TEXT_BASE=0x4a000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +# CONFIG_VIDEO_DE2 is not set +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-nanopi-duo" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +CONFIG_SPL=y +CONFIG_SYS_CLK_FREQ=480000000 +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_SPL_SPI_SUNXI=y +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_k1_plus_defconfig b/configs/nanopi_k1_plus_defconfig new file mode 100644 index 0000000000..bcbc8da2a1 --- /dev/null +++ b/configs/nanopi_k1_plus_defconfig @@ -0,0 +1,24 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SYS_TEXT_BASE=0x4a000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_MACH_SUN50I_H5=y +CONFIG_DRAM_CLK=504 +CONFIG_DRAM_ZQ=3881977 +CONFIG_MACPWR="PD6" +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-k1-plus" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_SPI_SUNXI=y +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +CONFIG_VIDEO_DE2=n diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig index dc2dbd6290..5abf34aa34 100644 --- a/configs/nanopi_m1_defconfig +++ b/configs/nanopi_m1_defconfig @@ -7,3 +7,4 @@ CONFIG_DRAM_CLK=408 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/nanopi_m1_plus2_defconfig b/configs/nanopi_m1_plus2_defconfig new file mode 100644 index 0000000000..9968747722 --- /dev/null +++ b/configs/nanopi_m1_plus2_defconfig @@ -0,0 +1,23 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SYS_TEXT_BASE=0x4a000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_MACH_SUN50I_H5=y +CONFIG_DRAM_CLK=576 +CONFIG_DRAM_ZQ=3881977 +CONFIG_MACPWR="PD6" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-m1-plus2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_SPI_SUNXI=y +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +CONFIG_VIDEO_DE2=n diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index 37b7817d86..4953e09c18 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus" CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y -CONFIG_DRAM_CLK=408 +CONFIG_DRAM_CLK=576 CONFIG_MACPWR="PD6" CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig index 95dd56aa04..30bcdffbf4 100644 --- a/configs/nanopi_neo2_defconfig +++ b/configs/nanopi_neo2_defconfig @@ -3,10 +3,12 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y -CONFIG_DRAM_CLK=672 +CONFIG_DRAM_CLK=504 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_BOOT_PROCESS_MULTI_DTB=y diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig index 806d95c1cc..b865f6707a 100644 --- a/configs/nanopi_neo_air_defconfig +++ b/configs/nanopi_neo_air_defconfig @@ -7,5 +7,7 @@ CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SYS_CLK_FREQ=480000000 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/configs/nanopi_neo_core2_defconfig b/configs/nanopi_neo_core2_defconfig new file mode 100644 index 0000000000..f3f1b7e16f --- /dev/null +++ b/configs/nanopi_neo_core2_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I_H5=y +CONFIG_DRAM_CLK=504 +CONFIG_DRAM_ZQ=3881977 +CONFIG_MACPWR="PD6" +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-core2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_SD_BOOT=y diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig index c025519638..9c49358405 100644 --- a/configs/nanopi_neo_defconfig +++ b/configs/nanopi_neo_defconfig @@ -7,6 +7,8 @@ CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SYS_CLK_FREQ=480000000 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 \ No newline at end of file diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig index 924ff38f17..5171cb4800 100644 --- a/configs/nanopi_neo_plus2_defconfig +++ b/configs/nanopi_neo_plus2_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2" CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y -CONFIG_DRAM_CLK=408 +CONFIG_DRAM_CLK=504 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set CONFIG_MACPWR="PD6" diff --git a/configs/nanopi_r1_defconfig b/configs/nanopi_r1_defconfig new file mode 100644 index 0000000000..e028b41a46 --- /dev/null +++ b/configs/nanopi_r1_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +CONFIG_MACPWR="PD6" +# CONFIG_VIDEO_DE2 is not set +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +CONFIG_SYS_CLK_FREQ=480000000 +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-r1" +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index 6f8ceb0fb7..4f1ae803cb 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -12,3 +12,5 @@ CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_VIDEO_DE2=n diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig index c243a58200..d82b80827a 100644 --- a/configs/orangepi_3_defconfig +++ b/configs/orangepi_3_defconfig @@ -1,12 +1,18 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-3" -CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y CONFIG_SUNXI_DRAM_H6_LPDDR3=y +CONFIG_SUNXI_DRAM_DDR3=n +CONFIG_DRAM_ODT_EN=y CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_BLUETOOTH_DT_DEVICE_FIXUP="brcm,bcm4345c5" +CONFIG_HDMI_DDC_EN="PH2" +# CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-3" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_OHCI_HCD=y +CONFIG_SPL=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig index 75c97d6b89..389687a456 100644 --- a/configs/orangepi_lite2_defconfig +++ b/configs/orangepi_lite2_defconfig @@ -9,3 +9,4 @@ CONFIG_MMC0_CD_PIN="PF6" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig index 96bbd1bab6..0d2514d4e3 100644 --- a/configs/orangepi_lite_defconfig +++ b/configs/orangepi_lite_defconfig @@ -7,3 +7,4 @@ CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig index 1064b4a39d..473ec71cd5 100644 --- a/configs/orangepi_one_defconfig +++ b/configs/orangepi_one_defconfig @@ -8,3 +8,4 @@ CONFIG_DRAM_CLK=672 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index 55a8b003fb..19db83a680 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -9,3 +9,4 @@ CONFIG_MMC0_CD_PIN="PF6" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 5a538e133f..64e00ea0b2 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -3,8 +3,9 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2" CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y -CONFIG_DRAM_CLK=672 +CONFIG_DRAM_CLK=504 CONFIG_DRAM_ZQ=3881977 +CONFIG_DRAM_ODT_EN=y # CONFIG_DRAM_ODT_EN is not set CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y @@ -13,3 +14,4 @@ CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y +CONFIG_VIDEO_DE2=n diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index f971ed1977..2416c6e99e 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -10,3 +10,4 @@ CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index 21f3c73ba6..43bb8e0b17 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -3,7 +3,9 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e" CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y -CONFIG_DRAM_CLK=672 +CONFIG_DRAM_CLK=624 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -12,3 +14,4 @@ CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index b17f640ca3..ad80a6bfee 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -3,7 +3,9 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus" CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y -CONFIG_DRAM_CLK=672 +CONFIG_DRAM_CLK=624 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PG13" @@ -14,3 +16,4 @@ CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 95a82e20f3..09891d12de 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -3,11 +3,15 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime" CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y -CONFIG_DRAM_CLK=672 +CONFIG_DRAM_CLK=504 CONFIG_DRAM_ZQ=3881977 +CONFIG_DRAM_ODT_EN=y # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_MACPWR="PD6" +CONFIG_SPL_SPI_SUNXI=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y +CONFIG_VIDEO_DE2=n diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index 8c2179ba8b..195398085d 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -8,6 +8,10 @@ CONFIG_MACPWR="PD14" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_PHY_REALTEK=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_USB1_VBUS_PIN="PD7" +CONFIG_USB_HOST=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/orangepi_zero2_b_defconfig b/configs/orangepi_zero2_b_defconfig new file mode 100644 index 0000000000..649939187a --- /dev/null +++ b/configs/orangepi_zero2_b_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-orangepi-zero2-b" +CONFIG_SPL=y +CONFIG_DRAM_CLK=672 +CONFIG_SUNXI_DRAM_H616_LPDDR3=y +CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y +CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE=y +CONFIG_DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION=y +CONFIG_MACH_SUN50I_H616=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_AXP_DCDC4_VOLT=1200 +CONFIG_SUN8I_EMAC=y +CONFIG_PWRLED="PC12" diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index 72574a89a2..bf5284e2ca 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -11,5 +11,7 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_R_I2C_ENABLE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_SUNXI=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y +CONFIG_PWRLED="PC12" diff --git a/configs/orangepi_zero2_lts_defconfig b/configs/orangepi_zero2_lts_defconfig new file mode 100644 index 0000000000..58627081a8 --- /dev/null +++ b/configs/orangepi_zero2_lts_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-orangepi-zero2-lts" +CONFIG_SPL=y +CONFIG_DRAM_CLK=792 +CONFIG_SUNXI_DRAM_H616_LPDDR4=y +CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y +CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE=y +CONFIG_DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION=y +CONFIG_DRAM_SUN50I_H616_TRIM_SIZE=y +CONFIG_MACH_SUN50I_H616=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_AXP_DCDC4_VOLT=1100 +CONFIG_SUN8I_EMAC=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_SUNXI=y +CONFIG_PHY_REALTEK=y +CONFIG_PWRLED="PC12" diff --git a/configs/orangepi_zero2w_defconfig b/configs/orangepi_zero2w_defconfig new file mode 100644 index 0000000000..7bec5462d8 --- /dev/null +++ b/configs/orangepi_zero2w_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-orangepi-zero2w" +CONFIG_SPL=y +CONFIG_DRAM_CLK=792 +CONFIG_SUNXI_DRAM_H616_LPDDR4=y +CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y +CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE=y +CONFIG_DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION=y +# CONFIG_DRAM_SUN50I_H616_TRIM_SIZE is not set +CONFIG_MACH_SUN50I_H616=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_AXP_DCDC3_VOLT=1100 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_AXP313A_POWER=y +CONFIG_SPL_SPI_SUNXI=y diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig new file mode 100644 index 0000000000..c99e1a8b23 --- /dev/null +++ b/configs/orangepi_zero3_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-orangepi-zero3" +CONFIG_SPL=y +CONFIG_DRAM_CLK=792 +CONFIG_SUNXI_DRAM_H616_LPDDR4=y +CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y +CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE=y +CONFIG_DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION=y +# CONFIG_DRAM_SUN50I_H616_TRIM_SIZE is not set +CONFIG_MACH_SUN50I_H616=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_AXP_DCDC3_VOLT=1100 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_AXP313A_POWER=y +CONFIG_SPL_SPI_SUNXI=y +CONFIG_PWRLED="PC12" diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index 332cd4739e..6768139cdd 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -3,7 +3,9 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero" CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y -CONFIG_DRAM_CLK=624 +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y # CONFIG_VIDEO_DE2 is not set CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig index 9583d24c8d..77a3ad5b83 100644 --- a/configs/orangepi_zero_plus2_defconfig +++ b/configs/orangepi_zero_plus2_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus2" CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y -CONFIG_DRAM_CLK=672 +CONFIG_DRAM_CLK=504 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set CONFIG_MMC0_CD_PIN="PH13" diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig index 55a251374a..98c7e0a0e3 100644 --- a/configs/orangepi_zero_plus2_h3_defconfig +++ b/configs/orangepi_zero_plus2_h3_defconfig @@ -1,13 +1,20 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zero-plus2" -CONFIG_SPL=y +CONFIG_SYS_TEXT_BASE=0x4a000000 CONFIG_MACH_SUN8I_H3=y -CONFIG_DRAM_CLK=672 -# CONFIG_DRAM_ODT_EN is not set -CONFIG_MMC0_CD_PIN="PH13" +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zero-plus2" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SUN8I_EMAC=y +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUNXI=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_EHCI_HCD=y -CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig index f3ecf35eee..affa91984f 100644 --- a/configs/orangepi_zero_plus_defconfig +++ b/configs/orangepi_zero_plus_defconfig @@ -7,6 +7,8 @@ CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_MACPWR="PD6" +CONFIG_SPL_SPI_SUNXI=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index 6209e68e2d..119572884c 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -13,3 +13,4 @@ CONFIG_SPL_SPI_SUNXI=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index d1c2c3c3cc..33442a2f4c 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -12,3 +12,4 @@ CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_VIDEO_DE2=n diff --git a/configs/pine_h64-model-b_defconfig b/configs/pine_h64-model-b_defconfig new file mode 100644 index 0000000000..ace3e84e33 --- /dev/null +++ b/configs/pine_h64-model-b_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_MACH_SUN50I_H6=y +CONFIG_SUNXI_DRAM_H6_LPDDR3=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_USB3_VBUS_PIN="PL5" +# CONFIG_PSCI_RESET is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64-model-b" +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 4e621db0c0..e5a64c8cca 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64" CONFIG_SPL=y +CONFIG_VIDEO_DE2=n CONFIG_MACH_SUN50I_H6=y CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MACPWR="PC16" diff --git a/configs/sunvell_r69_defconfig b/configs/sunvell_r69_defconfig new file mode 100644 index 0000000000..f1fc8f126e --- /dev/null +++ b/configs/sunvell_r69_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-sunvell-r69" +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_SYS_CLK_FREQ=480000000 +CONFIG_VIDEO_DE2=n diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig new file mode 100644 index 0000000000..8bc773a048 --- /dev/null +++ b/configs/zeropi_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +CONFIG_MACPWR="PD6" +# CONFIG_VIDEO_DE2 is not set +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +CONFIG_SPL=y +CONFIG_SYS_CLK_FREQ=480000000 +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 2b57797954..45dabc94dc 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -337,5 +337,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif + { INFO("zb25vq128a", 0x5e4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("zb25vq16as", 0x5e6015, 0, 64 * 1024, 32, SECT_4K) }, { }, }; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index c5fbf1f832..ccef04121b 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -58,6 +58,15 @@ config AXP305_POWER Select this to enable support for the axp305 pmic found on most H616 boards. +config AXP313A_POWER + bool "axp313a pmic support" + depends on MACH_SUN50I_H616 + select AXP_PMIC_BUS + select CMD_POWEROFF + ---help--- + Select this to enable support for the axp313a pmic found on most + H616 boards. + config AXP809_POWER bool "axp809 pmic support" depends on MACH_SUN9I @@ -118,11 +127,11 @@ config AXP_DCDC2_VOLT config AXP_DCDC3_VOLT int "axp pmic dcdc3 voltage" - depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER + depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313A_POWER default 900 if AXP809_POWER || AXP818_POWER default 1500 if AXP152_POWER default 1250 if AXP209_POWER - default 1100 if MACH_SUN8I_R40 + default 1100 if MACH_SUN8I_R40 || AXP313A_POWER default 1200 if MACH_SUN6I || MACH_SUN8I ---help--- Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to @@ -130,6 +139,7 @@ config AXP_DCDC3_VOLT On A10(s) / A13 / A20 boards with an axp209 dcdc3 is VDD-INT-DLL and should be 1.25V. On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V. + On H616 boards with an axp313a dcdc3 is VCC-DRAM(LPDDR4) and should be 1.1V. On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V. On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V. On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 0bef06920a..24a9113942 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_AXP221_POWER) += axp221.o obj-$(CONFIG_AXP305_POWER) += axp305.o obj-$(CONFIG_AXP809_POWER) += axp809.o obj-$(CONFIG_AXP818_POWER) += axp818.o +obj-$(CONFIG_AXP313A_POWER) += axp313a.o obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o obj-$(CONFIG_SY8106A_POWER) += sy8106a.o diff --git a/drivers/power/axp313a.c b/drivers/power/axp313a.c new file mode 100644 index 0000000000..b3bcb2bef9 --- /dev/null +++ b/drivers/power/axp313a.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AXP313a driver + * + * (C) Copyright 2020 Jernej Skrabec + * + * Based on axp221.c + * (C) Copyright 2014 Hans de Goede + * (C) Copyright 2013 Oliver Schinagl + */ + +#include +#include +#include +#include +#include + +#define AXP313A_DCDC4_1600MV_OFFSET 46 + +static u8 axp313a_mvolt_to_cfg(int mvolt, int min, int max, int div) +{ + if (mvolt < min) + mvolt = min; + else if (mvolt > max) + mvolt = max; + + return (mvolt - min) / div; +} + +#define AXP313A_DCDC3_1200MV_OFFSET 71 +int axp_set_dcdc3(unsigned int mvolt) +{ + int ret; + u8 cfg; + + if (mvolt >= 1220) + cfg = AXP313A_DCDC3_1200MV_OFFSET + + axp313a_mvolt_to_cfg(mvolt, 1220, 1840, 20); + else + cfg = axp313a_mvolt_to_cfg(mvolt, 500, 1200, 10); + + if (mvolt == 0) + return pmic_bus_clrbits(AXP313A_OUTPUT_CTRL1, + AXP313A_OUTPUT_CTRL1_DCDCD_EN); + + ret = pmic_bus_write(AXP313A_DCDCD_VOLTAGE, cfg); + if (ret) + return ret; + + return pmic_bus_setbits(AXP313A_OUTPUT_CTRL1, + 0x1f); +} + +int axp_init(void) +{ + u8 axp_chip_id; + int ret; + + ret = pmic_bus_init(); + if (ret) + return ret; + + ret = pmic_bus_read(AXP313A_CHIP_VERSION, &axp_chip_id); + if (ret) + return ret; + + if ((axp_chip_id & AXP313A_CHIP_VERSION_MASK) != 0x4b) + return -ENODEV; + + //printf("axp313a pmic id is 0x%x\n",axp_chip_id); + + return ret; +} + +#ifndef CONFIG_PSCI_RESET +int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + pmic_bus_write(AXP313A_SHUTDOWN, AXP313A_POWEROFF); + + /* infinite loop during shutdown */ + while (1) {} + + /* not reached */ + return 0; +} +#endif diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 1494c91763..c5080c1c5b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -383,6 +383,11 @@ config STM32_SPI SoCs. This uses driver model and requires a device tree binding to operate. +config SUN4I_SPI + bool "Allwinner A10 SoCs SPI controller" + help + SPI driver for Allwinner sun4i, sun5i and sun7i SoCs + config TEGRA114_SPI bool "nVidia Tegra114 SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index cfe4fae1d4..e452bf0d77 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o obj-$(CONFIG_STM32_SPI) += stm32_spi.o +obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c new file mode 100644 index 0000000000..b86b5a00ad --- /dev/null +++ b/drivers/spi/sun4i_spi.c @@ -0,0 +1,456 @@ +/* + * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V. + * S.J.R. van Schaik + * M.B.W. Wajer + * + * (C) Copyright 2017 Olimex Ltd.. + * Stefan Mavrodiev + * + * Based on linux spi driver. Original copyright follows: + * linux/drivers/spi/spi-sun4i.c + * + * Copyright (C) 2012 - 2014 Allwinner Tech + * Pan Nan + * + * Copyright (C) 2014 Maxime Ripard + * Maxime Ripard + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#define SUN4I_FIFO_DEPTH 64 + +#define SUN4I_RXDATA_REG 0x00 + +#define SUN4I_TXDATA_REG 0x04 + +#define SUN4I_CTL_REG 0x08 +#define SUN4I_CTL_ENABLE BIT(0) +#define SUN4I_CTL_MASTER BIT(1) +#define SUN4I_CTL_CPHA BIT(2) +#define SUN4I_CTL_CPOL BIT(3) +#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4) +#define SUN4I_CTL_LMTF BIT(6) +#define SUN4I_CTL_TF_RST BIT(8) +#define SUN4I_CTL_RF_RST BIT(9) +#define SUN4I_CTL_XCH_MASK 0x0400 +#define SUN4I_CTL_XCH BIT(10) +#define SUN4I_CTL_CS_MASK 0x3000 +#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK) +#define SUN4I_CTL_DHB BIT(15) +#define SUN4I_CTL_CS_MANUAL BIT(16) +#define SUN4I_CTL_CS_LEVEL BIT(17) +#define SUN4I_CTL_TP BIT(18) + +#define SUN4I_INT_CTL_REG 0x0c +#define SUN4I_INT_CTL_RF_F34 BIT(4) +#define SUN4I_INT_CTL_TF_E34 BIT(12) +#define SUN4I_INT_CTL_TC BIT(16) + +#define SUN4I_INT_STA_REG 0x10 + +#define SUN4I_DMA_CTL_REG 0x14 + +#define SUN4I_WAIT_REG 0x18 + +#define SUN4I_CLK_CTL_REG 0x1c +#define SUN4I_CLK_CTL_CDR2_MASK 0xff +#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK) +#define SUN4I_CLK_CTL_CDR1_MASK 0xf +#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8) +#define SUN4I_CLK_CTL_DRS BIT(12) + +#define SUN4I_MAX_XFER_SIZE 0xffffff + +#define SUN4I_BURST_CNT_REG 0x20 +#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) + +#define SUN4I_XMIT_CNT_REG 0x24 +#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) + +#define SUN4I_FIFO_STA_REG 0x28 +#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f +#define SUN4I_FIFO_STA_RF_CNT_BITS 0 +#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f +#define SUN4I_FIFO_STA_TF_CNT_BITS 16 + +#define SUN4I_SPI_MAX_RATE 24000000 +#define SUN4I_SPI_MIN_RATE 3000 +#define SUN4I_SPI_DEFAULT_RATE 1000000 +#define SUN4I_SPI_TIMEOUT_US 1000000 + +/* sun4i spi register set */ +struct sun4i_spi_regs { + u32 rxdata; + u32 txdata; + u32 ctl; + u32 intctl; + u32 st; + u32 dmactl; + u32 wait; + u32 cctl; + u32 bc; + u32 tc; + u32 fifo_sta; +}; + +struct sun4i_spi_platdata { + u32 base_addr; + u32 max_hz; +}; + +struct sun4i_spi_priv { + struct sun4i_spi_regs *regs; + u32 freq; + u32 mode; + + const u8 *tx_buf; + u8 *rx_buf; +}; + +DECLARE_GLOBAL_DATA_PTR; + +static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len) +{ + u8 byte; + + while (len--) { + byte = readb(&priv->regs->rxdata); + *priv->rx_buf++ = byte; + } +} + +static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len) +{ + u8 byte; + + while (len--) { + byte = priv->tx_buf ? *priv->tx_buf++ : 0; + writeb(byte, &priv->regs->txdata); + } +} + +static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable) +{ + struct sun4i_spi_priv *priv = dev_get_priv(bus); + u32 reg; + + reg = readl(&priv->regs->ctl); + + reg &= ~SUN4I_CTL_CS_MASK; + reg |= SUN4I_CTL_CS(cs); + + if (enable) + reg &= ~SUN4I_CTL_CS_LEVEL; + else + reg |= SUN4I_CTL_CS_LEVEL; + + writel(reg, &priv->regs->ctl); +} + +static int sun4i_spi_parse_pins(struct udevice *dev) +{ + const void *fdt = gd->fdt_blob; + const char *pin_name; + const fdt32_t *list; + u32 phandle; + int drive, pull = 0, pin, i; + int offset; + int size; + + list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size); + if (!list) { + printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n"); + return -EINVAL; + } + + while (size) { + phandle = fdt32_to_cpu(*list++); + size -= sizeof(*list); + + offset = fdt_node_offset_by_phandle(fdt, phandle); + if (offset < 0) + return offset; + + drive = fdt_getprop_u32_default_node(fdt, offset, 0, + "drive-strength", 0); + if (drive) { + if (drive <= 10) + drive = 0; + else if (drive <= 20) + drive = 1; + else if (drive <= 30) + drive = 2; + else + drive = 3; + } else { + drive = fdt_getprop_u32_default_node(fdt, offset, 0, + "allwinner,drive", + 0); + drive = min(drive, 3); + } + + if (fdt_get_property(fdt, offset, "bias-disable", NULL)) + pull = 0; + else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL)) + pull = 1; + else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL)) + pull = 2; + else + pull = fdt_getprop_u32_default_node(fdt, offset, 0, + "allwinner,pull", + 0); + pull = min(pull, 2); + + for (i = 0; ; i++) { + pin_name = fdt_stringlist_get(fdt, offset, + "pins", i, NULL); + if (!pin_name) { + pin_name = fdt_stringlist_get(fdt, offset, + "allwinner,pins", + i, NULL); + if (!pin_name) + break; + } + + pin = name_to_gpio(pin_name); + if (pin < 0) + break; + + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0); + sunxi_gpio_set_drv(pin, drive); + sunxi_gpio_set_pull(pin, pull); + } + } + return 0; +} + +static inline void sun4i_spi_enable_clock(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *const)SUNXI_CCM_BASE; + + setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0)); + writel((1 << 31), &ccm->spi0_clk_cfg); +} + +static int sun4i_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct sun4i_spi_platdata *plat = dev_get_platdata(bus); + int node = dev_of_offset(bus); + + plat->base_addr = devfdt_get_addr(bus); + plat->max_hz = fdtdec_get_int(gd->fdt_blob, node, + "spi-max-frequency", + SUN4I_SPI_DEFAULT_RATE); + + if (plat->max_hz > SUN4I_SPI_MAX_RATE) + plat->max_hz = SUN4I_SPI_MAX_RATE; + + return 0; +} + +static int sun4i_spi_probe(struct udevice *bus) +{ + struct sun4i_spi_platdata *plat = dev_get_platdata(bus); + struct sun4i_spi_priv *priv = dev_get_priv(bus); + + sun4i_spi_enable_clock(); + sun4i_spi_parse_pins(bus); + + priv->regs = (struct sun4i_spi_regs *)(uintptr_t)plat->base_addr; + priv->freq = plat->max_hz; + + return 0; +} + +static int sun4i_spi_claim_bus(struct udevice *dev) +{ + struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); + + writel(SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP | + SUN4I_CTL_CS_MANUAL | SUN4I_CTL_CS_ACTIVE_LOW, + &priv->regs->ctl); + return 0; +} + +static int sun4i_spi_release_bus(struct udevice *dev) +{ + struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); + u32 reg; + + reg = readl(&priv->regs->ctl); + reg &= ~SUN4I_CTL_ENABLE; + writel(reg, &priv->regs->ctl); + + return 0; +} + +static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct sun4i_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + + u32 len = bitlen / 8; + u32 reg; + u8 nbytes; + int ret; + + priv->tx_buf = dout; + priv->rx_buf = din; + + if (bitlen % 8) { + debug("%s: non byte-aligned SPI transfer.\n", __func__); + return -ENAVAIL; + } + + if (flags & SPI_XFER_BEGIN) + sun4i_spi_set_cs(bus, slave_plat->cs, true); + + reg = readl(&priv->regs->ctl); + + /* Reset FIFOs */ + writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl); + + while (len) { + /* Setup the transfer now... */ + nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1)); + + /* Setup the counters */ + writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc); + writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc); + + /* Fill the TX FIFO */ + sun4i_spi_fill_fifo(priv, nbytes); + + /* Start the transfer */ + reg = readl(&priv->regs->ctl); + writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl); + + /* Wait transfer to complete */ + ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK, + false, SUN4I_SPI_TIMEOUT_US, false); + if (ret) { + printf("ERROR: sun4i_spi: Timeout transferring data\n"); + sun4i_spi_set_cs(bus, slave_plat->cs, false); + return ret; + } + + /* Drain the RX FIFO */ + sun4i_spi_drain_fifo(priv, nbytes); + + len -= nbytes; + } + + if (flags & SPI_XFER_END) + sun4i_spi_set_cs(bus, slave_plat->cs, false); + + return 0; +} + +static int sun4i_spi_set_speed(struct udevice *dev, uint speed) +{ + struct sun4i_spi_platdata *plat = dev_get_platdata(dev); + struct sun4i_spi_priv *priv = dev_get_priv(dev); + unsigned int div; + u32 reg; + + if (speed > plat->max_hz) + speed = plat->max_hz; + + if (speed < SUN4I_SPI_MIN_RATE) + speed = SUN4I_SPI_MIN_RATE; + /* + * Setup clock divider. + * + * We have two choices there. Either we can use the clock + * divide rate 1, which is calculated thanks to this formula: + * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1)) + * Or we can use CDR2, which is calculated with the formula: + * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) + * Whether we use the former or the latter is set through the + * DRS bit. + * + * First try CDR2, and if we can't reach the expected + * frequency, fall back to CDR1. + */ + + div = SUN4I_SPI_MAX_RATE / (2 * speed); + reg = readl(&priv->regs->cctl); + + if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { + if (div > 0) + div--; + + reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS); + reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; + } else { + div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed); + reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS); + reg |= SUN4I_CLK_CTL_CDR1(div); + } + + priv->freq = speed; + writel(reg, &priv->regs->cctl); + + return 0; +} + +static int sun4i_spi_set_mode(struct udevice *dev, uint mode) +{ + struct sun4i_spi_priv *priv = dev_get_priv(dev); + u32 reg; + + reg = readl(&priv->regs->ctl); + reg &= ~(SUN4I_CTL_CPOL | SUN4I_CTL_CPHA); + + if (mode & SPI_CPOL) + reg |= SUN4I_CTL_CPOL; + + if (mode & SPI_CPHA) + reg |= SUN4I_CTL_CPHA; + + priv->mode = mode; + writel(reg, &priv->regs->ctl); + + return 0; +} + +static const struct dm_spi_ops sun4i_spi_ops = { + .claim_bus = sun4i_spi_claim_bus, + .release_bus = sun4i_spi_release_bus, + .xfer = sun4i_spi_xfer, + .set_speed = sun4i_spi_set_speed, + .set_mode = sun4i_spi_set_mode, +}; + +static const struct udevice_id sun4i_spi_ids[] = { + { .compatible = "allwinner,sun4i-a10-spi" }, + { } +}; + +U_BOOT_DRIVER(sun4i_spi) = { + .name = "sun4i_spi", + .id = UCLASS_SPI, + .of_match = sun4i_spi_ids, + .ops = &sun4i_spi_ops, + .ofdata_to_platdata = sun4i_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct sun4i_spi_platdata), + .priv_auto_alloc_size = sizeof(struct sun4i_spi_priv), + .probe = sun4i_spi_probe, +}; diff --git a/drivers/video/bridge/anx6345.c b/drivers/video/bridge/anx6345.c index 93fa25f16e..0fa56c75a2 100644 --- a/drivers/video/bridge/anx6345.c +++ b/drivers/video/bridge/anx6345.c @@ -3,6 +3,8 @@ * Copyright (C) 2017 Vasily Khoruzhick */ +#define DEBUG + #include #include #include @@ -250,13 +252,77 @@ static int anx6345_read_dpcd(struct udevice *dev, u32 reg, u8 *val) return 0; } +static u8 pinebook14_edid[] = { + /* Header */ + 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, + /* ID Manufacturer Name */ + 0x09, 0xe5, + /* ID Product Code */ + 0x37, 0x00, + /* 32-bit serial No. */ + 0x00, 0x00, 0x00, 0x00, + /* Week of manufacture */ + 0x01, + /* Year of manufacture */ + 0x16, + /* EDID Structure Ver. */ + 0x01, + /* EDID revision # */ + 0x04, + /* Video input definition */ + 0x80, + /* Max H image size */ + 0x1f, + /* Max V image size */ + 0x11, + /* Display Gamma */ + 0x78, + /* Feature support */ + 0x0a, + /* Color bits */ + 0xb0, 0x90, 0x97, 0x58, 0x54, 0x92, 0x26, 0x1d, 0x50, 0x54, + /* Established timings */ + 0x00, 0x00, 0x00, + /* Standard timings */ + 0x01, 0x01, + 0x01, 0x01, + 0x01, 0x01, + 0x01, 0x01, + 0x01, 0x01, + 0x01, 0x01, + 0x01, 0x01, + 0x01, 0x01, + /* Detailed timing/monitor descriptor #1 */ + 0x3e, 0x1c, 0x56, 0xa0, 0x50, 0x00, 0x16, 0x30, + 0x30, 0x20, 0x36, 0x00, 0x35, 0xad, 0x10, 0x00, + 0x00, 0x1a, + /* Detailed timing/monitor descriptor #2 */ + 0x3e, 0x1c, 0x56, 0xa0, 0x50, 0x00, 0x16, 0x30, + 0x30, 0x20, 0x36, 0x00, 0x35, 0xad, 0x10, 0x00, + 0x00, 0x1a, + /* Detailed timing/monitor descriptor #3 */ + 0x00, 0x00, 0x00, 0xfe, 0x00, 0x42, 0x4f, 0x45, + 0x20, 0x48, 0x46, 0x0a, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, + /* Detailed timing/monitor descriptor #4 */ + 0x00, 0x00, 0x00, 0xfe, 0x00, 0x48, 0x42, 0x31, + 0x34, 0x30, 0x57, 0x58, 0x31, 0x2d, 0x35, 0x30, + 0x31, 0x0a, + /* Extension flag */ + 0x00, + /* Checksum */ + 0x81 +}; + static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size) { - struct anx6345_priv *priv = dev_get_priv(dev); - if (size > EDID_SIZE) size = EDID_SIZE; - memcpy(buf, priv->edid, size); + + if (anx6345_read_aux_i2c(dev, 0x50, 0x0, size, buf) != 0) { + debug("%s: EDID read failed, using static EDID\n", __func__); + memcpy(buf, pinebook14_edid, size); + } return size; } @@ -270,7 +336,7 @@ static int anx6345_attach(struct udevice *dev) static int anx6345_enable(struct udevice *dev) { u8 chipid, colordepth, lanes, data_rate, c; - int ret, i, bpp; + int ret, i; struct display_timing timing; struct anx6345_priv *priv = dev_get_priv(dev); @@ -338,27 +404,19 @@ static int anx6345_enable(struct udevice *dev) anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00); anx6345_write_r0(dev, 0xa7, 0x00); - anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid); - if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) { - debug("Failed to parse EDID\n"); - return -EIO; - } - debug("%s: panel found: %dx%d, bpp %d\n", __func__, - timing.hactive.typ, timing.vactive.typ, bpp); - if (bpp == 6) - colordepth = 0x00; /* 6 bit */ - else - colordepth = 0x10; /* 8 bit */ + /* XXXJDM hard-coded for HB140WX1-501 14" TFT-LCD */ + colordepth = 0x00; /* 6 bit */ + anx6345_write_r1(dev, ANX9804_VID_CTRL2_REG, colordepth); if (anx6345_read_dpcd(dev, DP_MAX_LINK_RATE, &data_rate)) { debug("%s: Failed to DP_MAX_LINK_RATE\n", __func__); - return -EIO; + data_rate = 10; } debug("%s: data_rate: %d\n", __func__, (int)data_rate); if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) { debug("%s: Failed to read DP_MAX_LANE_COUNT\n", __func__); - return -EIO; + lanes = 1; } lanes &= DP_MAX_LANE_COUNT_MASK; debug("%s: lanes: %d\n", __func__, (int)lanes); diff --git a/dts/Kconfig b/dts/Kconfig index dabe0080c1..e382f2c52e 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -259,6 +259,12 @@ config SPL_OF_LIST device tree files (without the directory or .dtb suffix) separated by . +if ARCH_SUNXI +config BOOT_PROCESS_MULTI_DTB + bool "Adjust default board DT as necessary at boot" + default n +endif + choice prompt "SPL OF LIST compression" depends on SPL_MULTI_DTB_FIT diff --git a/include/axp313a.h b/include/axp313a.h new file mode 100644 index 0000000000..7aa72ff368 --- /dev/null +++ b/include/axp313a.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2020 Jernej Skrabec + */ + +enum axp313a_reg { + AXP313A_CHIP_VERSION = 0x3, + AXP313A_OUTPUT_CTRL1 = 0x10, + AXP313A_DCDCD_VOLTAGE = 0x15, + AXP313A_SHUTDOWN = 0x32, +}; + +#define AXP313A_CHIP_VERSION_MASK 0xcf + +#define AXP313A_OUTPUT_CTRL1_DCDCD_EN (1 << 3) + +#define AXP313A_POWEROFF (1 << 7) diff --git a/include/axp_pmic.h b/include/axp_pmic.h index 405044c3a3..fa3946f895 100644 --- a/include/axp_pmic.h +++ b/include/axp_pmic.h @@ -18,6 +18,9 @@ #ifdef CONFIG_AXP305_POWER #include #endif +#ifdef CONFIG_AXP313A_POWER +#include +#endif #ifdef CONFIG_AXP809_POWER #include #endif diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 2627c2a6a5..96f0e89135 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -430,6 +430,15 @@ BOOTENV_SHARED_EFI \ BOOTENV_SHARED_VIRTIO \ "boot_prefixes=/ /boot/\0" \ + "splashpos=m,m\0" \ + "splashimage=66000000\0" \ + "loadsplash= " \ + "for prefix in ${boot_prefixes}; do " \ + "if test -e mmc 0 ${prefix}boot.bmp; then " \ + "load mmc 0 ${splashimage} ${prefix}boot.bmp; " \ + "bmp d ${splashimage}; " \ + "fi; " \ + "done\0" \ "boot_scripts=boot.scr.uimg boot.scr\0" \ "boot_script_dhcp=boot.scr.uimg\0" \ BOOTENV_BOOT_TARGETS \ diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index 9b4675e4c3..221761ee47 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -17,4 +17,6 @@ */ #include +#define CONFIG_MACH_TYPE (0x1029) + #endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 9e37e99684..eb9ccf47c8 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -223,6 +223,16 @@ extern int soft_i2c_gpio_scl; #define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */ #endif +#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP +#define CONFIG_VIDEO_BMP_RLE8 +#endif + /* Ethernet support */ #ifdef CONFIG_USB_EHCI_HCD @@ -396,6 +406,11 @@ extern int soft_i2c_gpio_scl; #ifdef CONFIG_USB_KEYBOARD #define CONSOLE_STDIN_SETTINGS \ "stdin=serial,usbkbd\0" +#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO +#define CONSOLE_STDIN_SETTINGS \ + "preboot=run loadsplash; usb start\0" \ + "stdin=serial,usbkbd\0" +#endif #else #define CONSOLE_STDIN_SETTINGS \ "stdin=serial\0" diff --git a/lib/efi_loader/efi_var_seed.S b/lib/efi_loader/efi_var_seed.S deleted file mode 100644 index e0a40cf46c..0000000000 --- a/lib/efi_loader/efi_var_seed.S +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Predefined UEFI variables - * - * Copyright (c) 2020, Heinrich Schuchardt - */ - -#include - -.section .rodata.efi_seed.init,"a" -.balign 16 -.global __efi_var_file_begin -__efi_var_file_begin: -.incbin CONFIG_EFI_VAR_SEED_FILE -.global __efi_var_file_end -__efi_var_file_end: -.balign 16 diff --git a/tools/binman/test/descriptor.bin b/tools/binman/test/descriptor.bin deleted file mode 100644 index 3d549436c27c76f0a3b6289a16f68de4c14d70f6..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4096 zcmezW9~DF`{lL%6z{14FBp{@~sK}toz`%g4LWRM=6DR}*AaO8*=|4Lo!+*yA@<6p9 zj06}MxVab@czGlkIXIAn2Mx37ngRzuBghwFV6QMdI02!N$Ocvh0~ZEIhUp9pGm(TD z><&YCOh9VTc!)%YfP6rrmQm%SAut*OqaiRF0;3@?8UmvsFd71*Aut*OLnH*`-5D4} a6+{)@JBTx|DzGXH5ogoHnfF;n`#t~xJ!6po diff --git a/tools/patman/test/0000-cover-letter.patch b/tools/patman/test/0000-cover-letter.patch deleted file mode 100644 index c99e635623..0000000000 --- a/tools/patman/test/0000-cover-letter.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 5ab48490f03051875ab13d288a4bf32b507d76fd Mon Sep 17 00:00:00 2001 -From: Simon Glass -Date: Sat, 27 May 2017 20:52:11 -0600 -Subject: [RFC 0/2] *** SUBJECT HERE *** -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -*** BLURB HERE *** - -Simon Glass (2): - pci: Correct cast for sandbox - fdt: Correct cast for sandbox in fdtdec_setup_mem_size_base() - - cmd/pci.c | 3 ++- - fs/fat/fat.c | 1 + - lib/efi_loader/efi_memory.c | 1 + - lib/fdtdec.c | 3 ++- - 4 files changed, 6 insertions(+), 2 deletions(-) - --- -2.7.4 - diff --git a/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch b/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch deleted file mode 100644 index 038943c2c9..0000000000 --- a/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch +++ /dev/null @@ -1,51 +0,0 @@ -From b9da5f937bd5ea4931ea17459bf79b2905d9594d Mon Sep 17 00:00:00 2001 -From: Simon Glass -Date: Sat, 15 Apr 2017 15:39:08 -0600 -Subject: [RFC 1/2] pci: Correct cast for sandbox -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This gives a warning with some native compilers: - -cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type - ‘long long unsigned int’, but argument 3 has type - ‘u64 {aka long unsigned int}’ [-Wformat=] - -Fix it with a cast. - -Signed-off-by: Simon Glass -Commit-changes: 2 -- Changes only for this commit - -Series-notes: -some notes -about some things -from the first commit -END - -Commit-notes: -Some notes about -the first commit -END ---- - cmd/pci.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/cmd/pci.c b/cmd/pci.c -index 41b4fff..fe27b4f 100644 ---- a/cmd/pci.c -+++ b/cmd/pci.c -@@ -150,7 +150,8 @@ int pci_bar_show(struct udevice *dev) - if ((!is_64 && size_low) || (is_64 && size)) { - size = ~size + 1; - printf(" %d %#016llx %#016llx %d %s %s\n", -- bar_id, base, size, is_64 ? 64 : 32, -+ bar_id, (unsigned long long)base, -+ (unsigned long long)size, is_64 ? 64 : 32, - is_io ? "I/O" : "MEM", - prefetchable ? "Prefetchable" : ""); - } --- -2.7.4 - diff --git a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch deleted file mode 100644 index 56278a6ce9..0000000000 --- a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 5ab48490f03051875ab13d288a4bf32b507d76fd Mon Sep 17 00:00:00 2001 -From: Simon Glass -Date: Sat, 15 Apr 2017 15:39:08 -0600 -Subject: [RFC 2/2] fdt: Correct cast for sandbox in fdtdec_setup_mem_size_base() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This gives a warning with some native compilers: - -lib/fdtdec.c:1203:8: warning: format ‘%llx’ expects argument of type - ‘long long unsigned int’, but argument 3 has type - ‘long unsigned int’ [-Wformat=] - -Fix it with a cast. - -Signed-off-by: Simon Glass -Series-to: u-boot -Series-prefix: RFC -Series-cc: Stefan Brüns -Cover-letter-cc: Lord Mëlchett -Series-version: 3 -Patch-cc: fred -Series-process-log: sort, uniq -Series-changes: 4 -- Some changes -- Multi - line - change - -Commit-changes: 2 -- Changes only for this commit - -Cover-changes: 4 -- Some notes for the cover letter - -Cover-letter: -test: A test patch series -This is a test of how the cover -letter -works -END ---- - fs/fat/fat.c | 1 + - lib/efi_loader/efi_memory.c | 1 + - lib/fdtdec.c | 3 ++- - 3 files changed, 4 insertions(+), 1 deletion(-) - -diff --git a/fs/fat/fat.c b/fs/fat/fat.c -index a71bad1..ba169dc 100644 ---- a/fs/fat/fat.c -+++ b/fs/fat/fat.c -@@ -1,3 +1,4 @@ -+ - /* - * fat.c - * -diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c -index db2ae19..05f75d1 100644 ---- a/lib/efi_loader/efi_memory.c -+++ b/lib/efi_loader/efi_memory.c -@@ -1,3 +1,4 @@ -+ - /* - * EFI application memory management - * -diff --git a/lib/fdtdec.c b/lib/fdtdec.c -index c072e54..942244f 100644 ---- a/lib/fdtdec.c -+++ b/lib/fdtdec.c -@@ -1200,7 +1200,8 @@ int fdtdec_setup_mem_size_base(void) - } - - gd->ram_size = (phys_size_t)(res.end - res.start + 1); -- debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size); -+ debug("%s: Initial DRAM size %llx\n", __func__, -+ (unsigned long long)gd->ram_size); - - return 0; - } --- -2.7.4 -