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merge into: Qubot:v2021.07-sunxi
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Qubot:v2018.05-sunxi
Qubot:v2018.05-sunxi-factory
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Qubot:master-patch
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pull from: Qubot:master-patch
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Qubot:v2021.07-sunxi
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519
.azure-pipelines.yml Normal file
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variables:
windows_vm: windows-2019
ubuntu_vm: ubuntu-22.04
macos_vm: macOS-12
ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240125-12Feb2024
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
container_option: -u 0
work_dir: /u
stages:
- stage: testsuites
jobs:
- job: tools_only_windows
displayName: 'Ensure host tools build for Windows'
pool:
vmImage: $(windows_vm)
steps:
- powershell: |
(New-Object Net.WebClient).DownloadFile("https://github.com/msys2/msys2-installer/releases/download/2021-06-04/msys2-base-x86_64-20210604.sfx.exe", "sfx.exe")
displayName: 'Install MSYS2'
- script: |
sfx.exe -y -o%CD:~0,2%\
%CD:~0,2%\msys64\usr\bin\bash -lc " "
%CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syuu"
%CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syuu"
displayName: 'Update MSYS2'
- script: |
%CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel"
displayName: 'Install Toolchain'
- script: |
echo make tools-only_defconfig tools-only > build-tools.sh
%CD:~0,2%\msys64\usr\bin\bash -lc "bash build-tools.sh"
displayName: 'Build Host Tools'
env:
# Tell MSYS2 we need a POSIX emulation layer
MSYSTEM: MSYS
# Tell MSYS2 not to ‘cd’ our startup directory to HOME
CHERE_INVOKING: yes
- job: tools_only_macOS
displayName: 'Ensure host tools build for macOS X'
pool:
vmImage: $(macos_vm)
steps:
- script: brew install make ossp-uuid
displayName: Brew install dependencies
- script: |
gmake tools-only_config tools-only \
HOSTCFLAGS="-I/usr/local/opt/openssl@1.1/include" \
HOSTLDFLAGS="-L/usr/local/opt/openssl@1.1/lib" \
-j$(sysctl -n hw.logicalcpu)
displayName: 'Perform tools-only build'
- job: check_for_new_CONFIG_symbols_outside_Kconfig
displayName: 'Check for new CONFIG symbols outside Kconfig'
pool:
vmImage: $(ubuntu_vm)
container:
image: $(ci_runner_image)
options: $(container_option)
steps:
# If grep succeeds and finds a match the test fails as we should
# have no matches.
- script: git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
:^doc/ :^arch/arm/dts/ :^scripts/kconfig/lkc.h
:^include/linux/kconfig.h :^tools/ && exit 1 || exit 0
- job: docs
displayName: 'Build documentation'
pool:
vmImage: $(ubuntu_vm)
container:
image: $(ci_runner_image)
options: $(container_option)
steps:
- script: |
virtualenv -p /usr/bin/python3 /tmp/venvhtml
. /tmp/venvhtml/bin/activate
pip install -r doc/sphinx/requirements.txt
make htmldocs KDOC_WERROR=1
make infodocs
- job: maintainers
displayName: 'Ensure all configs have MAINTAINERS entries'
pool:
vmImage: $(ubuntu_vm)
container:
image: $(ci_runner_image)
options: $(container_option)
steps:
- script: |
./tools/buildman/buildman --maintainer-check
- job: tools_only
displayName: 'Ensure host tools and env tools build'
pool:
vmImage: $(ubuntu_vm)
container:
image: $(ci_runner_image)
options: $(container_option)
steps:
- script: |
make tools-only_config tools-only -j$(nproc)
make mrproper
make tools-only_config envtools -j$(nproc)
- job: utils
displayName: 'Run binman, buildman, dtoc, Kconfig and patman testsuites'
pool:
vmImage: $(ubuntu_vm)
steps:
- script: |
cat << "EOF" > build.sh
cd $(work_dir)
git config --global user.name "Azure Pipelines"
git config --global user.email bmeng.cn@gmail.com
git config --global --add safe.directory $(work_dir)
export USER=azure
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt
pip install -r tools/buildman/requirements.txt
export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board tools-only
set -ex
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test
./tools/buildman/buildman -t
./tools/dtoc/dtoc -t
./tools/patman/patman test
make O=${UBOOT_TRAVIS_BUILD_DIR} testconfig
EOF
cat build.sh
# We cannot use "container" like other jobs above, as buildman
# seems to hang forever with pre-configured "container" environment
docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh
- job: pylint
displayName: Check for any pylint regressions
pool:
vmImage: $(ubuntu_vm)
container:
image: $(ci_runner_image)
options: $(container_option)
steps:
- script: |
git config --global --add safe.directory $(work_dir)
export USER=azure
pip install -r test/py/requirements.txt
pip install -r tools/buildman/requirements.txt
pip install asteval pylint==2.12.2 pyopenssl
export PATH=${PATH}:~/.local/bin
echo "[MASTER]" >> .pylintrc
echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board tools-only
set -ex
pylint --version
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
make pylint_err
- job: check_for_pre_schema_tags
displayName: 'Check for pre-schema driver model tags'
pool:
vmImage: $(ubuntu_vm)
container:
image: $(ci_runner_image)
options: $(container_option)
steps:
# If grep succeeds and finds a match the test fails as we should
# have no matches.
- script: git grep u-boot,dm- -- '*.dts*' && exit 1 || exit 0
- job: check_packing_of_python_tools
displayName: 'Check we can package the Python tools'
pool:
vmImage: $(ubuntu_vm)
container:
image: $(ci_runner_image)
options: $(container_option)
steps:
- script: make pip
- job: create_test_py_wrapper_script
displayName: 'Create and stage a wrapper for test.py runs'
pool:
vmImage: $(ubuntu_vm)
steps:
- checkout: none
- script: |
cat << EOF > test.sh
#!/bin/bash
set -ex
# the below corresponds to .gitlab-ci.yml "before_script"
cd \${WORK_DIR}
git config --global --add safe.directory \${WORK_DIR}
git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
ln -s travis-ci /tmp/uboot-test-hooks/bin/\`hostname\`
ln -s travis-ci /tmp/uboot-test-hooks/py/\`hostname\`
grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
# the below corresponds to .gitlab-ci.yml "script"
cd \${WORK_DIR}
export UBOOT_TRAVIS_BUILD_DIR=/tmp/\${TEST_PY_BD}
if [ -n "\${BUILD_ENV}" ]; then
export \${BUILD_ENV};
fi
pip install -r tools/buildman/requirements.txt
tools/buildman/buildman -o \${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board \${TEST_PY_BD} \${OVERRIDE}
cp ~/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
cp ~/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/
cp /opt/grub/grubriscv64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
cp /opt/grub/grubaa64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
cp /opt/grub/grubarm.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
# create sdcard / spi-nor images for sifive unleashed using genimage
if [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]]; then
mkdir -p root;
cp \${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
cp \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
rm -rf tmp;
genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
cp images/sdcard.img \${UBOOT_TRAVIS_BUILD_DIR}/;
rm -rf tmp;
genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
cp images/spi-nor.img \${UBOOT_TRAVIS_BUILD_DIR}/;
fi
if [[ "\${TEST_PY_BD}" == "coreboot" ]]; then
cp /opt/coreboot/coreboot.rom \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
/opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
/opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
fi
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt
pip install pytest-azurepipelines
export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH}
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
# "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not
./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR"
# the below corresponds to .gitlab-ci.yml "after_script"
rm -rf /tmp/uboot-test-hooks /tmp/venv
EOF
- task: CopyFiles@2
displayName: 'Copy test.sh for later usage'
inputs:
contents: 'test.sh'
targetFolder: '$(Build.ArtifactStagingDirectory)'
- publish: '$(Build.ArtifactStagingDirectory)/test.sh'
displayName: 'Publish test.sh'
artifact: testsh
- stage: test_py_sandbox
jobs:
- job: test_py_sandbox
displayName: 'test.py for sandbox'
pool:
vmImage: $(ubuntu_vm)
strategy:
matrix:
sandbox:
TEST_PY_BD: "sandbox"
sandbox_asan:
TEST_PY_BD: "sandbox"
OVERRIDE: "-a ASAN"
TEST_PY_TEST_SPEC: "version"
sandbox_clang:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-16"
sandbox_clang_asan:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-16 -a ASAN"
TEST_PY_TEST_SPEC: "version"
sandbox64:
TEST_PY_BD: "sandbox64"
sandbox64_clang:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-16"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
sandbox_vpl:
TEST_PY_BD: "sandbox_vpl"
TEST_PY_TEST_SPEC: "vpl or test_spl"
sandbox_noinst:
TEST_PY_BD: "sandbox_noinst"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
sandbox_noinst_load_fit_full:
TEST_PY_BD: "sandbox_noinst"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
OVERRIDE: "-a CONFIG_SPL_LOAD_FIT_FULL=y"
sandbox_flattree:
TEST_PY_BD: "sandbox_flattree"
sandbox_trace:
TEST_PY_BD: "sandbox"
BUILD_ENV: "FTRACE=1 NO_LTO=1"
TEST_PY_TEST_SPEC: "trace"
OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000 -a CONFIG_TRACE_BUFFER_SIZE=0x02000000"
steps:
- download: current
artifact: testsh
- script: |
# make current directory writeable to uboot user inside the container
# as sandbox testing need create files like spi flash images, etc.
# (TODO: clean up this in the future)
chmod 777 .
chmod 755 $(Pipeline.Workspace)/testsh/test.sh
# Filesystem tests need extra docker args to run
set --
# mount -o loop needs the loop devices
if modprobe loop; then
for d in $(find /dev -maxdepth 1 -name 'loop*'); do
set -- "$@" --device $d:$d
done
fi
# Needed for mount syscall (for guestmount as well)
set -- "$@" --cap-add SYS_ADMIN
# Default apparmor profile denies mounts
set -- "$@" --security-opt apparmor=unconfined
# Some tests using libguestfs-tools need the fuse device to run
docker run "$@" --device /dev/fuse:/dev/fuse \
-v $PWD:$(work_dir) \
-v $(Pipeline.Workspace):$(Pipeline.Workspace) \
-e WORK_DIR="${WORK_DIR}" \
-e TEST_PY_BD="${TEST_PY_BD}" \
-e TEST_PY_ID="${TEST_PY_ID}" \
-e TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}" \
-e OVERRIDE="${OVERRIDE}" \
-e BUILD_ENV="${BUILD_ENV}" $(ci_runner_image) \
$(Pipeline.Workspace)/testsh/test.sh
- stage: test_py_qemu
jobs:
- job: test_py_qemu
displayName: 'test.py for QEMU platforms'
pool:
vmImage: $(ubuntu_vm)
strategy:
matrix:
coreboot:
TEST_PY_BD: "coreboot"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
evb_ast2500:
TEST_PY_BD: "evb-ast2500"
TEST_PY_ID: "--id qemu"
evb_ast2600:
TEST_PY_BD: "evb-ast2600"
TEST_PY_ID: "--id qemu"
vexpress_ca9x4:
TEST_PY_BD: "vexpress_ca9x4"
TEST_PY_ID: "--id qemu"
integratorcp_cm926ejs:
TEST_PY_BD: "integratorcp_cm926ejs"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
qemu_arm:
TEST_PY_BD: "qemu_arm"
TEST_PY_TEST_SPEC: "not sleep"
qemu_arm64:
TEST_PY_BD: "qemu_arm64"
TEST_PY_TEST_SPEC: "not sleep"
qemu_m68k:
TEST_PY_BD: "M5208EVBE"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
qemu_malta:
TEST_PY_BD: "malta"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_maltael:
TEST_PY_BD: "maltael"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_malta64:
TEST_PY_BD: "malta64"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_malta64el:
TEST_PY_BD: "malta64el"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_ppce500:
TEST_PY_BD: "qemu-ppce500"
TEST_PY_TEST_SPEC: "not sleep"
qemu_riscv32:
TEST_PY_BD: "qemu-riscv32"
TEST_PY_TEST_SPEC: "not sleep"
qemu_riscv64:
TEST_PY_BD: "qemu-riscv64"
TEST_PY_TEST_SPEC: "not sleep"
qemu_riscv32_spl:
TEST_PY_BD: "qemu-riscv32_spl"
TEST_PY_TEST_SPEC: "not sleep"
qemu_riscv64_spl:
TEST_PY_BD: "qemu-riscv64_spl"
TEST_PY_TEST_SPEC: "not sleep"
qemu_x86:
TEST_PY_BD: "qemu-x86"
TEST_PY_TEST_SPEC: "not sleep"
qemu_x86_64:
TEST_PY_BD: "qemu-x86_64"
TEST_PY_TEST_SPEC: "not sleep"
r2dplus_i82557c:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id i82557c_qemu"
r2dplus_pcnet:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id pcnet_qemu"
r2dplus_rtl8139:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id rtl8139_qemu"
r2dplus_tulip:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id tulip_qemu"
sifive_unleashed_sdcard:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id sdcard_qemu"
sifive_unleashed_spi-nor:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id spi-nor_qemu"
xilinx_zynq_virt:
TEST_PY_BD: "xilinx_zynq_virt"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
xilinx_versal_virt:
TEST_PY_BD: "xilinx_versal_virt"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
xtfpga:
TEST_PY_BD: "xtfpga"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
steps:
- download: current
artifact: testsh
- script: |
# make current directory writeable to uboot user inside the container
# as sandbox testing need create files like spi flash images, etc.
# (TODO: clean up this in the future)
chmod 777 .
chmod 755 $(Pipeline.Workspace)/testsh/test.sh
# Some tests using libguestfs-tools need the fuse device to run
docker run "$@" --device /dev/fuse:/dev/fuse \
-v $PWD:$(work_dir) \
-v $(Pipeline.Workspace):$(Pipeline.Workspace) \
-e WORK_DIR="${WORK_DIR}" \
-e TEST_PY_BD="${TEST_PY_BD}" \
-e TEST_PY_ID="${TEST_PY_ID}" \
-e TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}" \
-e OVERRIDE="${OVERRIDE}" \
-e BUILD_ENV="${BUILD_ENV}" $(ci_runner_image) \
$(Pipeline.Workspace)/testsh/test.sh
retryCountOnTaskFailure: 2 # QEMU may be too slow, etc.
- stage: world_build
jobs:
- job: build_the_world
timeoutInMinutes: 0 # Use the maximum allowed
displayName: 'Build the World'
pool:
vmImage: $(ubuntu_vm)
strategy:
# Use almost the same target division in .travis.yml, only merged
# 3 small build jobs (arc/microblaze/xtensa) into one.
matrix:
am33xx_at91_kirkwood_mvebu_omap:
BUILDMAN: "am33xx at91_kirkwood mvebu omap -x siemens"
amlogic_bcm_boundary_engicam_siemens_technexion_oradex:
BUILDMAN: "amlogic bcm boundary engicam siemens technexion toradex -x mips"
arm_nxp_minus_imx:
BUILDMAN: "freescale -x powerpc,m68k,imx,mx"
imx:
BUILDMAN: "mx imx -x boundary,engicam,technexion,toradex"
rk:
BUILDMAN: "rk"
sunxi:
BUILDMAN: "sunxi"
powerpc:
BUILDMAN: "powerpc"
arm_catch_all:
BUILDMAN: "arm -x aarch64,am33xx,at91,bcm,ls1,kirkwood,mvebu,omap,rk,siemens,mx,sunxi,technexion,toradex"
aarch64_catch_all:
BUILDMAN: "aarch64 -x amlogic,bcm,engicam,imx,ls1,ls2,lx216,mvebu,rk,siemens,sunxi,toradex"
everything_but_arm_and_powerpc:
BUILDMAN: "-x arm,powerpc"
steps:
- script: |
cat << EOF > build.sh
set -ex
cd ${WORK_DIR}
# make environment variables available as tests are running inside a container
export BUILDMAN="${BUILDMAN}"
git config --global --add safe.directory ${WORK_DIR}
pip install -r tools/buildman/requirements.txt
EOF
cat << "EOF" >> build.sh
if [[ "${BUILDMAN}" != "" ]]; then
ret=0;
tools/buildman/buildman -o /tmp -PEWM ${BUILDMAN} ${OVERRIDE} || ret=$?;
if [[ $ret -ne 0 ]]; then
tools/buildman/buildman -o /tmp -seP ${BUILDMAN};
exit $ret;
fi;
fi
EOF
cat build.sh
docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh

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.checkpatch.conf Normal file
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# Not Linux, so don't expect a Linux tree.
--no-tree
# Temporary for false positive in checkpatch
--ignore COMPLEX_MACRO
# For CFG_SYS_I2C_NOPROBES
--ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
# For simple_strtoul
--ignore CONSIDER_KSTRTO
# For min/max
--ignore MINMAX
# enable more tests
--strict
# Not Linux, so we don't recommend usleep_range() over udelay()
--ignore USLEEP_RANGE
# Ignore networking block comment style
--ignore NETWORKING_BLOCK_COMMENT_STYLE
# Ignore "WARNING: Prefer ether_addr_copy() over memcpy() if the Ethernet
# addresses are __aligned(2)".
--ignore PREFER_ETHER_ADDR_COPY
# ENOSYS is a conventionally used error, even though U-Boot lacks system calls.
--ignore ENOSYS
# A bit shorter of a description is OK with us.
--min-conf-desc-length=2
# Extra checks for U-Boot
--u-boot

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.get_maintainer.conf Normal file
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--find-maintainer-files --git --maintainer-path=.

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.get_maintainer.ignore Normal file
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"Pali Rohár" <pali@kernel.org>

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.gitattributes vendored Normal file
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# Declare files that always have LF line endings on checkout
* text eol=lf
# Denote all files that are truly binary and should not be modified
*.bin binary
*.bmp binary
*.ttf binary
*.gz binary
*.png binary

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.github/pull_request_template.md vendored Normal file
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@ -0,0 +1,6 @@
Please do not submit a Pull Request via github. Our project makes use of
mailing lists for patch submission and review. For more details please
see https://u-boot.readthedocs.io/en/latest/develop/sending_patches.html
The only exception to this is in order to trigger a CI loop on Azure prior
to posting of patches.

25
.gitignore vendored
View File

@ -6,10 +6,12 @@
# Normal rules (sorted alphabetically)
#
.*
!.checkpatch.conf
*.a
*.asn1.[ch]
*.bin
*.cfgout
*.cover
*.dtb
*.dtbo
*.dtb.S
@ -22,6 +24,7 @@
*.lex.c
*.lst
*.mod.c
*.mbx
*.o
*.o.*
*.order
@ -32,7 +35,7 @@
*.tab.[ch]
# Build tree
/build-*
/build*
#
# Top-level generic files
@ -41,8 +44,10 @@ fit-dtb.blob*
/MLO*
/SPL*
/System.map
/u-boot*
/boards.cfg
/mkimage-in-simple-bin*
/simple-bin*
/u-boot*
/*.log
#
@ -50,6 +55,7 @@ fit-dtb.blob*
#
!.gitignore
!.mailmap
!.get_maintainer.*
#
# Generated files
@ -61,6 +67,8 @@ fit-dtb.blob*
#
# Generated include files
#
/include/autoconf.mk*
/include/config.h
/include/config/
/include/generated/
@ -95,3 +103,16 @@ GTAGS
# Python cache
__pycache__
# Python code coverage output (python3-coverage html)
/htmlcov/
# pylint files
/pylint.cur
/pylint.out/
# qconfig database
/qconfig.db
# Clang's compilation database file
/compile_commands.json

483
.gitlab-ci.yml Normal file
View File

@ -0,0 +1,483 @@
# SPDX-License-Identifier: GPL-2.0+
variables:
DEFAULT_TAG: ""
MIRROR_DOCKER: docker.io
default:
tags:
- ${DEFAULT_TAG}
# Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile
image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240125-12Feb2024
# We run some tests in different order, to catch some failures quicker.
stages:
- testsuites
- test.py
- world build
.buildman_and_testpy_template: &buildman_and_testpy_dfn
stage: test.py
retry: 2 # QEMU may be too slow, etc.
rules:
- when: always
before_script:
# Clone uboot-test-hooks
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
- git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
- grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
after_script:
- cp -v /tmp/${TEST_PY_BD}/*.{html,css} .
- rm -rf /tmp/uboot-test-hooks /tmp/venv
script:
# If we've been asked to use clang only do one configuration.
- export UBOOT_TRAVIS_BUILD_DIR=/tmp/${TEST_PY_BD}
- echo BUILD_ENV ${BUILD_ENV}
- if [ -n "${BUILD_ENV}" ]; then
export ${BUILD_ENV};
fi
- tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e
--board ${TEST_PY_BD} ${OVERRIDE}
- cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
- cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/
- cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi
- cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi
- cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi
# create sdcard / spi-nor images for sifive unleashed using genimage
- if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
mkdir -p root;
cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
rm -rf tmp;
genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/;
rm -rf tmp;
genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
fi
- if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
cp /opt/coreboot/coreboot.rom ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
/opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
/opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
fi
- virtualenv -p /usr/bin/python3 /tmp/venv
- . /tmp/venv/bin/activate
- pip install -r test/py/requirements.txt
# "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
- export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID}
${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
--build-dir "$UBOOT_TRAVIS_BUILD_DIR"
artifacts:
when: always
paths:
- "*.html"
- "*.css"
expire_in: 1 week
.world_build:
stage: world build
rules:
- when: always
build all 32bit ARM platforms:
extends: .world_build
script:
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
pip install -r tools/buildman/requirements.txt;
./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 || ret=$?;
if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP;
exit $ret;
fi;
build all 64bit ARM platforms:
extends: .world_build
script:
- virtualenv -p /usr/bin/python3 /tmp/venv
- . /tmp/venv/bin/activate
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
pip install -r tools/buildman/requirements.txt;
./tools/buildman/buildman -o /tmp -PEWM aarch64 || ret=$?;
if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP;
exit $ret;
fi;
build all PowerPC platforms:
extends: .world_build
script:
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
./tools/buildman/buildman -o /tmp -P -E -W powerpc || ret=$?;
if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP;
exit $ret;
fi;
build all other platforms:
extends: .world_build
script:
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
./tools/buildman/buildman -o /tmp -PEWM -x arm,powerpc || ret=$?;
if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP;
exit $ret;
fi;
.testsuites:
stage: testsuites
rules:
- when: always
check for new CONFIG symbols outside Kconfig:
extends: .testsuites
script:
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
# If grep succeeds and finds a match the test fails as we should
# have no matches.
- git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
:^doc/ :^arch/arm/dts/ :^scripts/kconfig/lkc.h
:^include/linux/kconfig.h :^tools/ && exit 1 || exit 0
# build documentation
docs:
extends: .testsuites
script:
- virtualenv -p /usr/bin/python3 /tmp/venvhtml
- . /tmp/venvhtml/bin/activate
- pip install -r doc/sphinx/requirements.txt
- make htmldocs KDOC_WERROR=1
- make infodocs
# ensure all configs have MAINTAINERS entries
Check for configs without MAINTAINERS entry:
extends: .testsuites
script:
- ./tools/buildman/buildman --maintainer-check
# Ensure host tools build
Build tools-only and envtools:
extends: .testsuites
script:
- make tools-only_config tools-only -j$(nproc);
make mrproper;
make tools-only_config envtools -j$(nproc)
Run binman, buildman, dtoc, Kconfig and patman testsuites:
extends: .testsuites
script:
- git config --global user.name "GitLab CI Runner";
git config --global user.email trini@konsulko.com;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
export USER=gitlab;
virtualenv -p /usr/bin/python3 /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt;
pip install -r tools/buildman/requirements.txt;
export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
set +e;
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
--board tools-only;
set -e;
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
./tools/buildman/buildman -t;
./tools/dtoc/dtoc -t;
./tools/patman/patman test;
make testconfig
# Check for any pylint regressions
Run pylint:
extends: .testsuites
script:
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
- pip install -r test/py/requirements.txt
- pip install -r tools/buildman/requirements.txt
- pip install asteval pylint==2.12.2 pyopenssl
- export PATH=${PATH}:~/.local/bin
- echo "[MASTER]" >> .pylintrc
- echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
- export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
- set +e
- ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
--board tools-only
- set -e
- pylint --version
- export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
- make pylint_err
# Check for pre-schema driver model tags
Check for pre-schema tags:
extends: .testsuites
script:
- git config --global --add safe.directory "${CI_PROJECT_DIR}";
# If grep succeeds and finds a match the test fails as we should
# have no matches.
- git grep u-boot,dm- -- '*.dts*' && exit 1 || exit 0
# Check we can package the Python tools
Check packing of Python tools:
extends: .testsuites
script:
- make pip
# Test sandbox with test.py
sandbox test.py:
variables:
TEST_PY_BD: "sandbox"
<<: *buildman_and_testpy_dfn
sandbox with clang test.py:
variables:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-16"
<<: *buildman_and_testpy_dfn
sandbox64 test.py:
variables:
TEST_PY_BD: "sandbox64"
<<: *buildman_and_testpy_dfn
sandbox64 with clang test.py:
variables:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-16"
<<: *buildman_and_testpy_dfn
sandbox_spl test.py:
variables:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
<<: *buildman_and_testpy_dfn
sandbox_noinst_test.py:
variables:
TEST_PY_BD: "sandbox_noinst"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
<<: *buildman_and_testpy_dfn
sandbox_noinst with LOAD_FIT_FULL test.py:
variables:
TEST_PY_BD: "sandbox_noinst"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
OVERRIDE: "-a CONFIG_SPL_LOAD_FIT_FULL=y"
<<: *buildman_and_testpy_dfn
sandbox_vpl test.py:
variables:
TEST_PY_BD: "sandbox_vpl"
TEST_PY_TEST_SPEC: "vpl or test_spl"
<<: *buildman_and_testpy_dfn
# Enable tracing and disable LTO, to ensure functions are not elided
sandbox trace_test.py:
variables:
TEST_PY_BD: "sandbox"
BUILD_ENV: "FTRACE=1 NO_LTO=1"
TEST_PY_TEST_SPEC: "trace"
OVERRIDE: "-a CONFIG_TRACE=y -a CONFIG_TRACE_EARLY=y -a CONFIG_TRACE_EARLY_SIZE=0x01000000 -a CONFIG_TRACE_BUFFER_SIZE=0x02000000"
<<: *buildman_and_testpy_dfn
evb-ast2500 test.py:
variables:
TEST_PY_BD: "evb-ast2500"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
evb-ast2600 test.py:
variables:
TEST_PY_BD: "evb-ast2600"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
sandbox_flattree test.py:
variables:
TEST_PY_BD: "sandbox_flattree"
<<: *buildman_and_testpy_dfn
vexpress_ca9x4 test.py:
variables:
TEST_PY_BD: "vexpress_ca9x4"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
integratorcp_cm926ejs test.py:
variables:
TEST_PY_BD: "integratorcp_cm926ejs"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu_arm test.py:
variables:
TEST_PY_BD: "qemu_arm"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu_arm64 test.py:
variables:
TEST_PY_BD: "qemu_arm64"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu_m68k test.py:
variables:
TEST_PY_BD: "M5208EVBE"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
<<: *buildman_and_testpy_dfn
qemu_malta test.py:
variables:
TEST_PY_BD: "malta"
TEST_PY_TEST_SPEC: "not sleep and not efi"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu_maltael test.py:
variables:
TEST_PY_BD: "maltael"
TEST_PY_TEST_SPEC: "not sleep and not efi"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu_malta64 test.py:
variables:
TEST_PY_BD: "malta64"
TEST_PY_TEST_SPEC: "not sleep and not efi"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu_malta64el test.py:
variables:
TEST_PY_BD: "malta64el"
TEST_PY_TEST_SPEC: "not sleep and not efi"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu-ppce500 test.py:
variables:
TEST_PY_BD: "qemu-ppce500"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu-riscv32 test.py:
variables:
TEST_PY_BD: "qemu-riscv32"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu-riscv64 test.py:
variables:
TEST_PY_BD: "qemu-riscv64"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu-riscv32_spl test.py:
variables:
TEST_PY_BD: "qemu-riscv32_spl"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu-riscv64_spl test.py:
variables:
TEST_PY_BD: "qemu-riscv64_spl"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu-x86 test.py:
variables:
TEST_PY_BD: "qemu-x86"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu-x86_64 test.py:
variables:
TEST_PY_BD: "qemu-x86_64"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
r2dplus_i82557c test.py:
variables:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id i82557c_qemu"
<<: *buildman_and_testpy_dfn
r2dplus_pcnet test.py:
variables:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id pcnet_qemu"
<<: *buildman_and_testpy_dfn
r2dplus_rtl8139 test.py:
variables:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id rtl8139_qemu"
<<: *buildman_and_testpy_dfn
r2dplus_tulip test.py:
variables:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id tulip_qemu"
<<: *buildman_and_testpy_dfn
sifive_unleashed_sdcard test.py:
variables:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id sdcard_qemu"
<<: *buildman_and_testpy_dfn
sifive_unleashed_spi-nor test.py:
variables:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id spi-nor_qemu"
<<: *buildman_and_testpy_dfn
xilinx_zynq_virt test.py:
variables:
TEST_PY_BD: "xilinx_zynq_virt"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
xilinx_versal_virt test.py:
variables:
TEST_PY_BD: "xilinx_versal_virt"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
xtfpga test.py:
variables:
TEST_PY_BD: "xtfpga"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
coreboot test.py:
variables:
TEST_PY_BD: "coreboot"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn

134
.mailmap Normal file
View File

@ -0,0 +1,134 @@
#
# This list is used by git-shortlog to fix a few botched name translations
# in the git archive, either because the author's full name was messed up
# and/or not always written the same way, making contributions from the
# same person appearing not to be so or badly displayed.
#
# This file is also used by scripts/get_maintainer.pl.
#
# This file can be modified by hand or updated by the following command:
# scripts/mailmapper > tmp; mv tmp .mailmap
#
# Entries in this file take one of the following forms:
# Proper Name <commit@email.xx>
# <proper@email.xx> <commit@email.xx>
# Proper Name <proper@email.xx> <commit@email.xx>
# Proper Name <proper@email.xx> Commit Name <commit@email.xx>
Alexander Graf <agraf@csgraf.de> <agraf@suse.de>
Allen Martin <amartin@nvidia.com>
Amanda Baze <amanda.baze@amd.com> <nicole.baze@xilinx.com>
Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> <amit.kumar-mahapatra@xilinx.com>
Andreas Bießmann <andreas.devel@googlemail.com>
Andreas Bießmann <andreas@biessmann.org>
Aneesh V <aneesh@ti.com>
Anup Patel <anup@brainfault.org> <anup.patel@wdc.com>
Anurag Kumar Vulisha <AnuragKumar.Vulisha@amd.com> <anurag.kumar.vulisha@xilinx.com>
Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> <appana.durga.rao@xilinx.com>
Ashok Reddy Soma <ashok.reddy.soma@amd.com> <ashok.reddy.soma@xilinx.com>
Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharat.kumar.gogada@xilinx.com>
Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharatku@xilinx.com>
Bhargava Sreekantappa Gayathri <bhargava.sreekantappa-gayathri@amd.com> <bhargava.sreekantappa-gayathri@xilinx.com>
Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com>
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com>
Dirk Behme <dirk.behme@googlemail.com>
Durga Challa <durga.challa@amd.com> <vnsl.durga.challa@xilinx.com>
Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com>
Fabio Estevam <fabio.estevam@nxp.com>
Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> <ibai.erkiaga-elorza@xilinx.com>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com> <izhar.ameer.shaikh@xilinx.com>
Jagan Teki <402jagan@gmail.com>
Jagan Teki <jaganna@gmail.com>
Jagan Teki <jaganna@xilinx.com>
Jagan Teki <jagannadh.teki@gmail.com>
Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com>
Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
John Linn <john.linn@amd.com> <john.linn@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com>
Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org>
Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com>
Lukasz Majewski <lukma@denx.de>
Marek Behún <kabel@kernel.org> <marek.behun@nic.cz>
Marek Behún <kabel@kernel.org> Marek Behun <marek.behun@nic.cz>
Marek Vasut <marex@denx.de> <marek.vasut+renesas@gmail.com>
Marek Vasut <marex@denx.de> <marek.vasut@gmail.com>
Marek Vasut <marex@denx.de> <marex at denx.de>
Markus Klotzbuecher <mk@denx.de>
Masahiro Yamada <masahiroy@kernel.org> <yamada.masahiro@socionext.com>
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Michal Simek <michal.simek@amd.com> <Monstr@seznam.cz>
Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
Michal Simek <michal.simek@amd.com> <monstr@monstr.eu>
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Neal Frager <neal.frager@amd.com> <neal.frager@xilinx.com>
Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
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Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
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Prabhakar Kushwaha <prabhakar@freescale.com>
Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@amd.com> <punnaiah.choudary.kalluri@xilinx.com>
Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> <radhey.shyam.pandey@xilinx.com>
Rajeshwari Shinde <rajeshwari.s@samsung.com>
Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com> <raju.kumar-pothuraju@xilinx.com>
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Shravya Kumbham <shravya.kumbham@amd.com> <shravya.kumbham@xilinx.com>
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Tom Rini <trini@konsulko.com> <trini@ti.com>
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TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Varalaxmi Bingi <varalaxmi.bingi@amd.com> <varalaxmi.bingi@xilinx.com>
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Vikhyat Goyal <vikhyat.goyal@amd.com> <vikhyat.goyal@xilinx.com>
Vishal Patel <vishal.patel@amd.com> <vishal.patel@xilinx.com>
Wolfgang Denk <wd@denx.de> <wd@atlas.denx.de>
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Łukasz Majewski <l.majewski@samsung.com>

24
.readthedocs.yml Normal file
View File

@ -0,0 +1,24 @@
# .readthedocs.yml
# Read the Docs configuration file
# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
# Required
version: 2
build:
os: "ubuntu-20.04"
apt_packages:
- python3-six
tools:
python: "3.9"
# Build documentation in the docs/ directory with Sphinx
sphinx:
configuration: doc/conf.py
# Optionally build your docs in additional formats such as PDF and ePub
formats: []
python:
install:
- requirements: doc/sphinx/requirements.txt

446
Kconfig
View File

@ -57,18 +57,49 @@ config LOCALVERSION_AUTO
which is done within the script "scripts/setlocalversion".)
config CC_IS_GCC
def_bool $(success,$(CC) --version | head -n 1 | grep -q gcc)
config GCC_VERSION
int
default $(shell,$(srctree)/scripts/gcc-version.sh -p $(CC) | sed 's/^0*//') if CC_IS_GCC
default 0
config CC_IS_CLANG
def_bool $(success,$(CC) --version | head -n 1 | grep -q clang)
config CLANG_VERSION
int
default $(shell,$(srctree)/scripts/clang-version.sh $(CC))
choice
prompt "Optimization level"
default CC_OPTIMIZE_FOR_SIZE
config CC_OPTIMIZE_FOR_SIZE
bool "Optimize for size"
default y
help
Enabling this option will pass "-Os" instead of "-O2" to gcc
resulting in a smaller U-Boot image.
Enabling this option will pass "-Os" to gcc, resulting in a smaller
U-Boot image.
This option is enabled by default for U-Boot.
config CC_OPTIMIZE_FOR_SPEED
bool "Optimize for speed"
help
Enabling this option will pass "-O2" to gcc, resulting in a faster
U-Boot image.
config CC_OPTIMIZE_FOR_DEBUG
bool "Optimize for debugging"
help
Enabling this option will pass "-Og" to gcc, enabling optimizations
which don't interfere with debugging.
endchoice
config OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in full U-Boot"
default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
@ -78,7 +109,6 @@ config OPTIMIZE_INLINING
config SPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in SPL"
depends on SPL
default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
@ -91,7 +121,6 @@ config ARCH_SUPPORTS_LTO
config LTO
bool "Enable Link Time Optimizations"
depends on ARCH_SUPPORTS_LTO
default n
help
This option enables Link Time Optimization (LTO), a mechanism which
allows the compiler to optimize between different compilation units.
@ -112,7 +141,6 @@ config LTO
config TPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in TPL"
depends on TPL
default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
@ -126,11 +154,29 @@ config CC_COVERAGE
Enabling this option will pass "--coverage" to gcc to compile
and link code instrumented for coverage analysis.
config ASAN
bool "Enable AddressSanitizer"
depends on SANDBOX
help
Enables AddressSanitizer to discover out-of-bounds accesses,
use-after-free, double-free and memory leaks.
config FUZZ
bool "Enable fuzzing"
depends on CC_IS_CLANG
depends on DM_FUZZING_ENGINE
select ASAN
help
Enables the fuzzing infrastructure to generate fuzzing data and run
fuzz tests.
config CC_HAS_ASM_INLINE
def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) -x c - -c -o /dev/null)
config XEN
bool "Select U-Boot be run as a bootloader for XEN Virtual Machine"
depends on ARM64
select SSCANF
help
Enabling this option will make U-Boot be run as a bootloader
for XEN [1] Virtual Machine.
@ -147,33 +193,6 @@ config XEN
[1] - https://xenproject.org/
config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux distributions"
select AUTO_COMPLETE
select CMDLINE_EDITING
select CMD_BOOTI if ARM64
select CMD_BOOTZ if ARM && !ARM64
select CMD_DHCP if CMD_NET
select CMD_ENV_EXISTS
select CMD_EXT2
select CMD_EXT4
select CMD_FAT
select CMD_FS_GENERIC
select CMD_PART if PARTITIONS
select CMD_PING if CMD_NET
select CMD_PXE if NET
select CMD_SYSBOOT
select ENV_VARS_UBOOT_CONFIG
select HUSH_PARSER
select SUPPORT_RAW_INITRD
select SYS_LONGHELP
imply CMD_MII if NET
imply USB_STORAGE
imply USE_BOOTCOMMAND
help
Select this to enable various options and commands which are suitable
for building u-boot for booting general purpose Linux distributions.
config ENV_VARS_UBOOT_CONFIG
bool "Add arch, board, vendor and soc variables to default environment"
help
@ -200,12 +219,38 @@ config SYS_BOOT_GET_CMDLINE
Enables allocating and saving kernel cmdline in space between
"bootm_low" and "bootm_low" + BOOTMAPSZ.
config SYS_BARGSIZE
int "Size of kernel command line buffer in bytes"
depends on SYS_BOOT_GET_CMDLINE
default 512
help
Buffer size for Boot Arguments which are passed to the application
(usually a Linux kernel) when it is booted
config SYS_BOOT_GET_KBD
bool "Enable kernel board information setup"
help
Enables allocating and saving a kernel copy of the bd_info in
space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
config HAS_CUSTOM_SYS_INIT_SP_ADDR
bool "Use a custom location for the initial stack pointer address"
depends on ARC || (ARM && !INIT_SP_RELATIVE) || MIPS || PPC || RISCV
default y if TFABOOT
help
Typically, we use an initial stack pointer address that is calculated
by taking the statically defined CFG_SYS_INIT_RAM_ADDR, adding the
statically defined CFG_SYS_INIT_RAM_SIZE and then subtracting the
build-time constant of GENERATED_GBL_DATA_SIZE. On MIPS a different
but statica calculation is performed. However, some platforms will
take a different approach. Say Y here to define the address statically
instead.
config CUSTOM_SYS_INIT_SP_ADDR
hex "Static location for the initial stack pointer"
depends on HAS_CUSTOM_SYS_INIT_SP_ADDR
default TEXT_BASE if TFABOOT
config SYS_MALLOC_F
bool "Enable malloc() pool before relocation"
default y if DM
@ -219,51 +264,121 @@ config SYS_MALLOC_F
config SYS_MALLOC_F_LEN
hex "Size of malloc() pool before relocation"
depends on SYS_MALLOC_F
default 0x1000 if AM33XX
default 0x4000 if SANDBOX
default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \
ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \
ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI || ARCH_OWL)
default 0x400
default 0x400 if M68K || PPC || ROCKCHIP_PX30 || ROCKCHIP_RK3036 || \
ROCKCHIP_RK3308 || ROCKCHIP_RV1108
default 0x600 if ARCH_ZYNQMP_R5 || ARCH_ZYNQMP
default 0x800 if ARCH_ZYNQ || ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \
ROCKCHIP_RK322X || X86
default 0x1000 if ARCH_MESON || ARCH_BMIPS || ARCH_MTMIPS
default 0x1800 if ARCH_TEGRA
default 0x4000 if SANDBOX || RISCV || ARCH_APPLE || ROCKCHIP_RK3368 || \
ROCKCHIP_RK3399
default 0x8000 if RCAR_GEN3
default 0x10000 if ARCH_IMX8 || ARCH_IMX8M
default 0x2000
help
Before relocation, memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
Size of the malloc() pool for use before relocation. If
this is defined, then a very simple malloc() implementation
will become available before relocation. The address is just
below the global data, and the stack is moved down to make
space.
This feature allocates regions with increasing addresses
within the region. calloc() is supported, but realloc()
is not available. free() is supported but does nothing.
The memory will be freed (or in fact just forgotten) when
U-Boot relocates itself.
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP
default 0x2000000 if ARCH_ROCKCHIP
default 0x4000000 if SANDBOX
default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
default 0x200000 if ARCH_BMIPS || X86
default 0x4020000 if SUNXI_MINIMUM_DRAM_MB >= 256
default 0x220000 if SUNXI_MINIMUM_DRAM_MB >= 64
default 0x120000 if SUNXI_MINIMUM_DRAM_MB >= 32
default 0x400000
help
This defines memory to be allocated for Dynamic allocation
TODO: Use for other architectures
config SPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in SPL"
depends on SYS_MALLOC_F && SPL
default 0x2800 if RCAR_GEN3
default SYS_MALLOC_F_LEN
config SPL_SYS_MALLOC_F
bool "Enable malloc() pool in SPL"
depends on SPL_FRAMEWORK && SYS_MALLOC_F && SPL
default y
help
In SPL memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new
config SPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in SPL"
depends on SPL_SYS_MALLOC_F
default 0x2800 if RCAR_GEN3
default 0x2000 if IMX8MQ
default SYS_MALLOC_F_LEN
help
Sets the size of the malloc() pool in SPL. This is used for
driver model and other features, which must allocate memory for
data structures.
It is possible to enable CFG_SPL_SYS_MALLOC_START to start a new
malloc() region in SDRAM once it is inited.
config TPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in TPL"
config TPL_SYS_MALLOC_F
bool "Enable malloc() pool in TPL"
depends on SYS_MALLOC_F && TPL
default SPL_SYS_MALLOC_F_LEN
default y if SPL_SYS_MALLOC_F
help
In TPL memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
config TPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in TPL"
depends on TPL_SYS_MALLOC_F
default SPL_SYS_MALLOC_F_LEN
help
Sets the size of the malloc() pool in TPL. This is used for
driver model and other features, which must allocate memory for
data structures.
config VALGRIND
bool "Inform valgrind about memory allocations"
depends on !RISCV
help
Valgrind is an instrumentation framework for building dynamic analysis
tools. In particular, it may be used to detect memory management bugs
in U-Boot. It relies on knowing when heap blocks are allocated in
order to give accurate results. This happens automatically for
standard allocator functions provided by the host OS. However, this
doesn't automatically happen for U-Boot's malloc implementation.
Enable this option to annotate U-Boot's malloc implementation so that
it can be handled accurately by Valgrind. If you aren't planning on
using valgrind to debug U-Boot, say 'n'.
config VPL_SYS_MALLOC_F
bool "Enable malloc() pool in VPL"
depends on SYS_MALLOC_F && VPL
default y if SPL_SYS_MALLOC_F
help
In VPL memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
config VPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in VPL before relocation"
depends on VPL_SYS_MALLOC_F
default SPL_SYS_MALLOC_F_LEN
help
Sets the size of the malloc() pool in VPL. This is used for
driver model and other features, which must allocate memory for
data structures.
menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
default y
@ -290,9 +405,19 @@ if EXPERT
When disabling this, please check if malloc calls, maybe
should be replaced by calloc - if one expects zeroed memory.
config SPL_SYS_MALLOC_CLEAR_ON_INIT
bool "Init with zeros the memory reserved for malloc (slow) in SPL"
depends on SPL
default SYS_MALLOC_CLEAR_ON_INIT
help
Same as SYS_MALLOC_CLEAR_ON_INIT, but for SPL. It's possible to
Enable it without SYS_MALLOC_CLEAR_ON_INIT. It's useful for boards
that must have particular memory regions zero'ed before first use.
If SYS_SPL_MALLOC_START is configured to be in such region, this
option should be enabled.
config SYS_MALLOC_DEFAULT_TO_INIT
bool "Default malloc to init while reserving the memory for it"
default n
help
It may happen that one needs to move the dynamic allocation
from one to another memory range, eg. when moving the malloc
@ -316,11 +441,19 @@ endif # EXPERT
config PHYS_64BIT
bool "64bit physical address support"
select FDT_64BIT
help
Say Y here to support 64bit physical memory address.
This can be used not only for 64bit SoCs, but also for
large physical address extension on 32bit SoCs.
config FDT_64BIT
bool "64bit fdt address support"
help
Say Y here to support 64bit fdt addresses.
This can be used not only for 64bit SoCs, but also
for large address extensions on 32bit SoCs.
config HAS_ROM
bool
select BINMAN
@ -328,27 +461,6 @@ config HAS_ROM
Enables building of a u-boot.rom target. This collects U-Boot and
any necessary binary blobs.
config ROM_NEEDS_BLOBS
bool
depends on HAS_ROM
help
Enable this if building the u-boot.rom target needs binary blobs, and
so cannot be done normally. In this case, U-Boot will only build the
ROM if the required blobs exist. If not, you will see an warning like:
Image 'main-section' is missing external blobs and is non-functional:
intel-descriptor intel-me intel-refcode intel-vga intel-mrc
config BUILD_ROM
bool "Build U-Boot as BIOS replacement"
depends on HAS_ROM
default y if !ROM_NEEDS_BLOBS
help
This option allows to build a ROM version of U-Boot.
The build process generally requires several binary blobs
which are not shipped in the U-Boot source tree.
Please, see doc/arch/x86.rst for details.
config SPL_IMAGE
string "SPL image used in the combined SPL+U-Boot image"
default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
@ -360,17 +472,25 @@ config SPL_IMAGE
used to generate a combined image with SPL and main U-Boot
proper as one single image.
config REMAKE_ELF
bool "Recreate an ELF image from raw U-Boot binary"
help
Enable this to recreate an ELF image (u-boot.elf) from the raw
U-Boot binary (u-boot.bin), which may already have been statically
relocated and may already have a device-tree appended to it.
config BUILD_TARGET
string "Build target special images"
default "u-boot-elf.srec" if RCAR_64
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
default "u-boot-with-spl.kwb" if ARMADA_32BIT && SPL
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
default "u-boot.kwb" if ARCH_KIRKWOOD
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
RISCV || ARCH_ZYNQMP)
default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL
help
Some SoCs need special image types (e.g. U-Boot binary
with a special header) as build targets. By defining
@ -378,6 +498,24 @@ config BUILD_TARGET
special image will be automatically built upon calling
make / buildman.
config HAS_BOARD_SIZE_LIMIT
bool "Define a maximum size for the U-Boot image"
default y if RCAR_32 || RCAR_64
help
In some cases, we need to enforce a hard limit on how big the U-Boot
image itself can be.
config BOARD_SIZE_LIMIT
int "Maximum size of the U-Boot image in bytes"
default 524288 if RCAR_32
default 1048576 if RCAR_64
depends on HAS_BOARD_SIZE_LIMIT
help
Maximum size of the U-Boot image. When defined, the build system
checks that the actual size does not exceed it. This does not
include SPL nor TPL, on platforms that use that functionality, they
have a separate option to restict size.
config SYS_CUSTOM_LDSCRIPT
bool "Use a custom location for the U-Boot linker script"
help
@ -395,6 +533,21 @@ config SYS_LDSCRIPT
Path within the source tree to the linker script to use for the
main U-Boot binary.
config SYS_LOAD_ADDR
hex "Address in memory to use by default"
default 0x01000000 if ARCH_SOCFPGA
default 0x02000000 if PPC || X86
default 0x81000000 if MACH_SUNIV
default 0x22000000 if MACH_SUN9I
default 0x42000000 if ARCH_SUNXI
default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL)
default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL)
default 0x80800000 if ARCH_MX7
default 0x90000000 if FSL_LSCH2 || FSL_LSCH3
help
Address in memory to use as the default safe load address.
config ERR_PTR_OFFSET
hex
default 0x0
@ -416,7 +569,7 @@ config PLATFORM_ELFENTRY
config STACK_SIZE
hex "Define max stack size that can be used by U-Boot"
default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
default 0x4000000 if ARCH_VERSAL_NET || ARCH_VERSAL || ARCH_ZYNQMP
default 0x200000 if MICROBLAZE
default 0x1000000
help
@ -424,12 +577,22 @@ config STACK_SIZE
by the UEFI sub-system. On some boards initrd_high is calculated as
base stack pointer minus this stack size.
config SYS_MEM_TOP_HIDE
hex "Exclude some memory from U-Boot / OS information"
default 0x0
help
If set, this specified memory area will get subtracted from the top
(end) of RAM and won't get "touched" at all by U-Boot. By fixing up
gd->ram_size the OS / next stage should gets passed the now
"corrected" memory size and won't touch it either.
WARNING: Please make sure that this value is a multiple of the OS
page size.
config SYS_HAS_SRAM
bool
default y if TARGET_PIC32MZDASK
default y if TARGET_DEVKIT8000
default y if TARGET_TRICORDER
default n
help
Enable this to allow support for the on board SRAM.
SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
@ -449,17 +612,114 @@ config SYS_SRAM_SIZE
default 0x10000 if TARGET_TRICORDER
default 0x0
config EXAMPLES
bool "Compile API examples"
depends on !SANDBOX
default y if ARCH_QEMU
config SYS_MONITOR_LEN
int "Maximum size in bytes reserved for U-Boot in memory"
default 1048576 if X86
default 786432 if ARCH_SUNXI
default 0
help
U-Boot provides an API for standalone applications. Examples are
provided in directory examples/.
Size of memory reserved for monitor code, used to determine
_at_compile_time_ (!) if the environment is embedded within the
U-Boot image, or in a separate flash sector, among other uses where
we need to set a maximum size of the U-Boot binary itself that will
be loaded.
config MP
bool "Support for multiprocessor"
help
This provides an option to bringup different processors
in multiprocessor cases.
config HAVE_TEXT_BASE
bool
depends on !NIOS2 && !XTENSA
depends on !EFI_APP
default y
config TEXT_BASE
depends on HAVE_TEXT_BASE
default 0x0 if POSITION_INDEPENDENT
default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
default 0x81700000 if MACH_SUNIV
default 0x2a000000 if MACH_SUN9I
default 0x4a000000 if SUNXI_MINIMUM_DRAM_MB >= 256
default 0x42e00000 if SUNXI_MINIMUM_DRAM_MB >= 64
hex "Text Base"
help
The address in memory that U-Boot will be copied and executed from
initially.
config HAVE_SYS_UBOOT_START
bool "Use custom U-Boot Start"
depends on HAVE_TEXT_BASE
help
By default, the address in memory that U-Boot will be copied from
(TEXT_BASE) and the entry point are the same. Select this to start the
execution of U-Boot from a different address.
This may be required if a header or vector table needs to be copied
but not executed.
config SYS_UBOOT_START
hex
depends on HAVE_TEXT_BASE
default TEXT_BASE
prompt "U-Boot entry" if HAVE_SYS_UBOOT_START
help
If TEXT_BASE differs from the start of execution, this sets the
address in memory that U-Boot will start execution from initially.
config HAVE_SYS_MONITOR_BASE
bool
depends on ARC || MIPS || M68K || NIOS2 || PPC || XTENSA || X86 \
|| ENV_IS_IN_FLASH || MTD_NOR_FLASH
depends on !EFI_APP
default y
config SYS_MONITOR_BASE
depends on HAVE_SYS_MONITOR_BASE
hex "Physical start address of boot monitor code"
default TEXT_BASE
help
The physical start address of boot monitor code (which is the same as
CONFIG_TEXT_BASE when linking) and the same as CFG_SYS_FLASH_BASE
when booting from flash.
config SPL_SYS_MONITOR_BASE
depends on MPC85xx && SPL && HAVE_SYS_MONITOR_BASE
hex "Physical start address of SPL monitor code"
default SPL_TEXT_BASE
config TPL_SYS_MONITOR_BASE
depends on MPC85xx && TPL && HAVE_SYS_MONITOR_BASE
hex "Physical start address of TPL monitor code"
config DYNAMIC_SYS_CLK_FREQ
bool "Determine CPU clock frequency at run-time"
help
Implement a get_board_sys_clk function that will determine the CPU
clock frequency at run time, rather than define it statically.
config SYS_CLK_FREQ
depends on !DYNAMIC_SYS_CLK_FREQ
int "CPU clock frequency"
default 125000000 if ARCH_LS1012A
default 100000000 if ARCH_P2020 || ARCH_T1024 || ARCH_T1042 || \
ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
default 66666666 if ARCH_P1010 || ARCH_P1020 || ARCH_T4240
default 66660000 if ARCH_T2080
default 33333333 if RCAR_GEN3
default 24000000 if ARCH_EXYNOS
default 20000000 if RCAR_GEN2
default 0
help
A static value for the CPU frequency. Note that if not required
for a given SoC, this can be left at 0.
source "api/Kconfig"
endmenu # General setup
source "api/Kconfig"
source "boot/Kconfig"
source "common/Kconfig"

12
Licenses/Exceptions
View File

@ -7,9 +7,13 @@ use U-Boot services by means of the jump table provided by U-Boot
exactly for this purpose - this is merely considered normal use of
U-Boot, and does *not* fall under the heading of "derived work".
The header files "include/image.h" and "arch/*/include/asm/u-boot.h"
define interfaces to U-Boot. Including these (unmodified) header
files in another file is considered normal use of U-Boot, and does
*not* fall under the heading of "derived work".
The following files define interfaces to U-Boot:
* include/image.h
* include/export.h
* arch/*/include/asm/u-boot.h
* examples/standalone/stubs.c
Including these (unmodified) files in another file is considered normal
use of U-Boot, and does *not* fall under the heading of "derived work".
-- Wolfgang Denk

1
Licenses/README
View File

@ -139,6 +139,7 @@ License identifier syntax
Full name SPDX Identifier OSI Approved File name URI
=======================================================================================================================================
bzip2 and libbzip2 License v1.0.6 bzip2-1.0.6 bzip2-1.0.6.txt https://spdx.org/licenses/bzip2-1.0.6.html
GNU General Public License v2.0 only GPL-2.0 Y gpl-2.0.txt http://www.gnu.org/licenses/gpl-2.0.txt
GNU General Public License v2.0 or later GPL-2.0+ Y gpl-2.0.txt http://www.gnu.org/licenses/gpl-2.0.txt
GNU Library General Public License v2 or later LGPL-2.0+ Y lgpl-2.0.txt http://www.gnu.org/licenses/old-licenses/lgpl-2.0.txt

30
Licenses/bzip2-1.0.6.txt Normal file
View File

@ -0,0 +1,30 @@
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. The origin of this software must not be misrepresented; you must
not claim that you wrote the original software. If you use this
software in a product, an acknowledgment in the product
documentation would be appreciated but is not required.
3. Altered source versions must be plainly marked as such, and must
not be misrepresented as being the original software.
4. The name of the author may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

2
Licenses/lgpl-2.0.txt
View File

@ -133,7 +133,7 @@ such a program is covered only if its contents constitute a work based
on the Library (independent of the use of the Library in a tool for
writing it). Whether that is true depends on what the Library does
and what the program that uses the Library does.
1. You may copy and distribute verbatim copies of the Library's
complete source code as you receive it, in any medium, provided that
you conspicuously and appropriately publish on each copy an

691
MAINTAINERS
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676
Makefile
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2203
README
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39
api/Kconfig
View File

@ -1,9 +1,42 @@
menu "API"
config API
bool "Enable U-Boot API"
default n
depends on CC_IS_GCC
help
This option enables the U-Boot API. See api/README for more information.
menu "API"
depends on API
config SYS_MMC_MAX_DEVICE
int "Maximum number of MMC devices exposed via the API"
default 1
config EXAMPLES
bool "Compile API examples"
depends on !SANDBOX
default y if ARCH_QEMU
help
U-Boot provides an API for standalone applications. Examples are
provided in directory examples/.
config STANDALONE_LOAD_ADDR
depends on EXAMPLES
hex "Address in memory to link standalone applications to"
default 0xffffffff80200000 if MIPS && 64BIT
default 0x8c000000 if SH
default 0x82000000 if ARC
default 0x80f00000 if MICROBLAZE
default 0x80300000 if ARCH_OMAP2PLUS || FSL_LSCH2 || FSL_LSCH3
default 0x80200000 if MIPS && 32BIT
default 0x0c100000 if ARM
default 0x02000000 if NIOS2
default 0x00040000 if PPC || X86
default 0x00020000 if M68K
default 0x0 if RISCV
default SYS_LOAD_ADDR
help
This option defines a board specific value for the address where
standalone program gets loaded, thus overwriting the architecture
dependent default settings.
endmenu

22
api/api_display.c
View File

@ -5,14 +5,7 @@
#include <common.h>
#include <api_public.h>
#include <lcd.h>
#include <log.h>
#include <video_font.h> /* Get font width and height */
/* lcd.h needs BMP_LOGO_HEIGHT to calculate CONSOLE_ROWS */
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
#include <bmp_logo.h>
#endif
/* TODO(clchiou): add support of video device */
@ -26,14 +19,6 @@ int display_get_info(int type, struct display_info *di)
debug("%s: unsupport display device type: %d\n",
__FILE__, type);
return API_ENODEV;
#ifdef CONFIG_LCD
case DISPLAY_TYPE_LCD:
di->pixel_width = panel_info.vl_col;
di->pixel_height = panel_info.vl_row;
di->screen_rows = lcd_get_screen_rows();
di->screen_cols = lcd_get_screen_columns();
break;
#endif
}
di->type = type;
@ -44,16 +29,9 @@ int display_draw_bitmap(ulong bitmap, int x, int y)
{
if (!bitmap)
return API_EINVAL;
#ifdef CONFIG_LCD
return lcd_display_bitmap(bitmap, x, y);
#else
return API_ENODEV;
#endif
}
void display_clear(void)
{
#ifdef CONFIG_LCD
lcd_clear();
#endif
}

12
api/api_storage.c
View File

@ -9,6 +9,7 @@
#include <common.h>
#include <api_public.h>
#include <part.h>
#include <scsi.h>
#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
#include <usb.h>
@ -43,10 +44,6 @@ struct stor_spec {
static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
#ifndef CONFIG_SYS_MMC_MAX_DEVICE
#define CONFIG_SYS_MMC_MAX_DEVICE 1
#endif
void dev_stor_init(void)
{
#if defined(CONFIG_IDE)
@ -70,13 +67,6 @@ void dev_stor_init(void)
specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
specs[ENUM_SATA].name = "sata";
#endif
#if defined(CONFIG_SCSI)
specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
specs[ENUM_SCSI].enum_started = 0;
specs[ENUM_SCSI].enum_ended = 0;
specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;
specs[ENUM_SCSI].name = "scsi";
#endif
#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;
specs[ENUM_USB].enum_started = 0;

241
arch/Kconfig
View File

@ -1,12 +1,34 @@
config ARCH_MAP_SYSMEM
depends on SANDBOX
def_bool y
config CREATE_ARCH_SYMLINK
bool
config HAVE_ARCH_IOREMAP
bool
config NEEDS_MANUAL_RELOC
config SYS_CACHE_SHIFT_4
bool
config SYS_CACHE_SHIFT_5
bool
config SYS_CACHE_SHIFT_6
bool
config SYS_CACHE_SHIFT_7
bool
config SYS_CACHELINE_SIZE
int
default 128 if SYS_CACHE_SHIFT_7
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
default 16 if SYS_CACHE_SHIFT_4
# Fall-back for MIPS
default 32 if MIPS
config LINKER_LIST_ALIGN
int
default 32 if SANDBOX
@ -29,43 +51,49 @@ config ARC
select DM
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
select SYS_CACHE_SHIFT_7
select TIMER
select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
config ARM
bool "ARM architecture"
select ARCH_SUPPORTS_LTO
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC if !ARM64
select SUPPORT_ACPI
select SUPPORT_OF_CONTROL
config M68K
bool "M68000 architecture"
select HAVE_PRIVATE_LIBGCC
select NEEDS_MANUAL_RELOC
select USE_PRIVATE_LIBGCC
select SYS_BOOT_GET_CMDLINE
select SYS_BOOT_GET_KBD
select SYS_CACHE_SHIFT_4
select SUPPORT_OF_CONTROL
config MICROBLAZE
bool "MicroBlaze architecture"
select NEEDS_MANUAL_RELOC
select SUPPORT_OF_CONTROL
imply CMD_IRQ
imply CMD_TIMER
imply SPL_REGMAP if SPL
imply SPL_TIMER if SPL
imply TIMER
imply XILINX_TIMER
config MIPS
bool "MIPS architecture"
select HAVE_ARCH_IOREMAP
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
config NDS32
bool "NDS32 architecture"
select SUPPORT_OF_CONTROL
select SPL_SEPARATE_BSS if SPL
config NIOS2
bool "Nios II architecture"
select CPU
select DM
select DM_EVENT
select OF_CONTROL
select SUPPORT_OF_CONTROL
imply CMD_DM
@ -80,11 +108,13 @@ config PPC
config RISCV
bool "RISC-V architecture"
select CREATE_ARCH_SYMLINK
select SUPPORT_ACPI
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
select DM_EVENT
imply SPL_SEPARATE_BSS if SPL
imply DM_SERIAL
imply DM_ETH
imply DM_MMC
imply DM_SPI
imply DM_SPI_FLASH
@ -97,7 +127,7 @@ config RISCV
imply SPL_OF_CONTROL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_SERIAL_SUPPORT
imply SPL_SERIAL
imply SPL_TIMER
config SANDBOX
@ -105,8 +135,10 @@ config SANDBOX
select ARCH_SUPPORTS_LTO
select BOARD_LATE_INIT
select BZIP2
select CMD_POWEROFF
select CMD_POWEROFF if CMDLINE
select DM
select DM_EVENT
select DM_FUZZING_ENGINE
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
@ -115,15 +147,18 @@ config SANDBOX
select DM_SPI
select DM_SPI_FLASH
select GZIP_COMPRESSED
select HAVE_BLOCK_DEVICE
select IO_TRACE
select LZO
select MTD
select OF_BOARD_SETUP
select PCI_ENDPOINT
select SPI
select SUPPORT_OF_CONTROL
select SYSRESET_CMD_POWEROFF
select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
select SYS_CACHE_SHIFT_4
select IRQ
select SUPPORT_EXTENSION_SCAN
select SUPPORT_EXTENSION_SCAN if CMDLINE
select SUPPORT_ACPI
imply BITREVERSE
select BLOBLIST
imply LTO
@ -134,19 +169,19 @@ config SANDBOX
imply CMD_IO
imply CMD_IOTRACE
imply CMD_LZMADEC
imply CMD_SATA
imply CMD_SF
imply CMD_SF_TEST
imply CRC32_VERIFY
imply FAT_WRITE
imply FIRMWARE
imply FUZZING_ENGINE_SANDBOX
imply HASH_VERIFY
imply LZMA
imply SCSI
imply TEE
imply AVB_VERIFY
imply LIBAVB
imply CMD_AVB
imply PARTITION_TYPE_GUID
imply SCP03
imply CMD_SCP03
imply UDP_FUNCTION_FASTBOOT
@ -161,6 +196,7 @@ config SANDBOX
imply PHYLIB
imply DM_MDIO
imply DM_MDIO_MUX
imply ACPI
imply ACPI_PMC
imply ACPI_PMC_SANDBOX
imply CMD_PMC
@ -170,6 +206,15 @@ config SANDBOX
imply PHY_FIXED
imply DM_DSA
imply CMD_EXTENSION
imply KEYBOARD
imply PHYSMEM
imply GENERATE_ACPI_TABLE
imply BINMAN
imply CMD_MBR
imply CMD_MMC
imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE
imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE
imply CMD_SYSBOOT if BOOTSTD_FULL
config SH
bool "SuperH architecture"
@ -182,12 +227,13 @@ config X86
select SUPPORT_TPL
select CREATE_ARCH_SYMLINK
select DM
select DM_PCI
select HAVE_ARCH_IOMAP
select HAVE_PRIVATE_LIBGCC
select OF_CONTROL
select PCI
select SUPPORT_ACPI
select SUPPORT_OF_CONTROL
select SYS_CACHE_SHIFT_6
select TIMER
select USE_PRIVATE_LIBGCC
select X86_TSC_TIMER
@ -203,17 +249,18 @@ config X86
imply CMD_SF
imply CMD_SF_TEST
imply CMD_ZBOOT
imply DM_ETH
imply DM_GPIO
imply DM_KEYBOARD
imply DM_MMC
imply DM_RTC
imply DM_SCSI
imply SCSI
imply DM_SERIAL
imply MTD
imply DM_SPI
imply DM_SPI_FLASH
imply DM_USB
imply DM_VIDEO
imply LAST_STAGE_INIT
imply VIDEO
imply SYSRESET
imply SPL_SYSRESET
imply SYSRESET_X86
@ -221,34 +268,37 @@ config X86
imply USB_ETHER_SMSC95XX
imply USB_HOST_ETHER
imply PCH
imply PHYSMEM
imply RTC_MC146818
imply ACPIGEN if !QEMU
imply ACPI
imply ACPIGEN if !QEMU && !EFI_APP
imply SYSINFO if GENERATE_SMBIOS_TABLE
imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
imply TIMESTAMP
# Thing to enable for when SPL/TPL are enabled: SPL
imply SPL_DM
imply SPL_OF_LIBFDT
imply SPL_DRIVERS_MISC_SUPPORT
imply SPL_GPIO_SUPPORT
imply SPL_DRIVERS_MISC
imply SPL_GPIO
imply SPL_PINCTRL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_SERIAL_SUPPORT
imply SPL_SERIAL
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
imply SPL_SPI
imply SPL_OF_CONTROL
imply SPL_TIMER
imply SPL_REGMAP
imply SPL_SYSCON
# TPL
imply TPL_DM
imply TPL_DRIVERS_MISC_SUPPORT
imply TPL_GPIO_SUPPORT
imply TPL_DRIVERS_MISC
imply TPL_GPIO
imply TPL_PINCTRL
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_SERIAL_SUPPORT
imply TPL_SERIAL
imply TPL_OF_CONTROL
imply TPL_TIMER
imply TPL_REGMAP
@ -326,12 +376,115 @@ config SYS_DISABLE_DCACHE_OPS
Note that, its up to the individual architectures to implement
this functionality.
config SYS_IMMR
hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
default 0xFF000000 if MPC8xx
default 0xF0000000 if ARCH_MPC8313
default 0xE0000000 if MPC83xx && !ARCH_MPC8313
default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
ARCH_P2020
default SYS_CCSRBAR_DEFAULT
help
Address for the Internal Memory-Mapped Registers (IMMR) window used
to configure the features of many Freescale / NXP SoCs.
config MONITOR_IS_IN_RAM
bool "U-Boot is loaded in to RAM by a pre-loader"
depends on M68K || NIOS2
menu "Skipping low level initialization functions"
depends on ARM || MIPS || RISCV
config SKIP_LOWLEVEL_INIT
bool "Skip calls to certain low level initialization functions"
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
itself into RAM.
Normally this variable MUST NOT be defined. The only exception is
when U-Boot is loaded (to RAM) by some other boot loader or by a
debugger which performs these initializations itself.
config SPL_SKIP_LOWLEVEL_INIT
bool "Skip calls to certain low level initialization functions in SPL"
depends on SPL
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
itself into RAM.
Normally this variable MUST NOT be defined. The only exception is
when U-Boot is loaded (to RAM) by some other boot loader or by a
debugger which performs these initializations itself.
config TPL_SKIP_LOWLEVEL_INIT
bool "Skip calls to certain low level initialization functions in TPL"
depends on SPL && ARM
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
itself into RAM.
Normally this variable MUST NOT be defined. The only exception is
when U-Boot is loaded (to RAM) by some other boot loader or by a
debugger which performs these initializations itself.
config SKIP_LOWLEVEL_INIT_ONLY
bool "Skip call to lowlevel_init during early boot ONLY"
depends on ARM
help
This allows just the call to lowlevel_init() to be skipped. The
normal CP15 init (such as enabling the instruction cache) is still
performed.
config SPL_SKIP_LOWLEVEL_INIT_ONLY
bool "Skip call to lowlevel_init during early SPL boot ONLY"
depends on SPL && ARM
help
This allows just the call to lowlevel_init() to be skipped. The
normal CP15 init (such as enabling the instruction cache) is still
performed.
config TPL_SKIP_LOWLEVEL_INIT_ONLY
bool "Skip call to lowlevel_init during early TPL boot ONLY"
depends on TPL && ARM
help
This allows just the call to lowlevel_init() to be skipped. The
normal CP15 init (such as enabling the instruction cache) is still
performed.
endmenu
config SYS_HAS_NONCACHED_MEMORY
bool "Enable reserving a non-cached memory area for drivers"
depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
help
This is useful for drivers that would otherwise require a lot of
explicit cache maintenance. For some drivers it's also impossible to
properly maintain the cache. For example if the regions that need to
be flushed are not a multiple of the cache-line size, *and* padding
cannot be allocated between the regions to align them (i.e. if the
HW requires a contiguous array of regions, and the size of each
region is not cache-aligned), then a flush of one region may result
in overwriting data that hardware has written to another region in
the same cache-line. This can happen for example in network drivers
where descriptors for buffers are typically smaller than the CPU
cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
config SYS_NONCACHED_MEMORY
hex "Size in bytes of the non-cached memory area"
depends on SYS_HAS_NONCACHED_MEMORY
default 0x100000
help
Size of non-cached memory area. This area of memory will be typically
located right below the malloc() area and mapped uncached in the MMU.
source "arch/arc/Kconfig"
source "arch/arm/Kconfig"
source "arch/m68k/Kconfig"
source "arch/microblaze/Kconfig"
source "arch/mips/Kconfig"
source "arch/nds32/Kconfig"
source "arch/nios2/Kconfig"
source "arch/powerpc/Kconfig"
source "arch/sandbox/Kconfig"
@ -339,3 +492,33 @@ source "arch/sh/Kconfig"
source "arch/x86/Kconfig"
source "arch/xtensa/Kconfig"
source "arch/riscv/Kconfig"
if ARM || M68K || PPC
source "arch/Kconfig.nxp"
endif
source "board/keymile/Kconfig"
if MIPS || MICROBLAZE
choice
prompt "Endianness selection"
help
Some MIPS boards can be configured for either little or big endian
byte order. These modes require different U-Boot images. In general there
is one preferred byteorder for a particular system but some systems are
just as commonly used in the one or the other endianness.
config SYS_BIG_ENDIAN
bool "Big endian"
depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
config SYS_LITTLE_ENDIAN
bool "Little endian"
depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
endchoice
endif

298
arch/Kconfig.nxp Normal file
View File

@ -0,0 +1,298 @@
menu "Functionality shared between NXP SoCs"
config FSL_TRUST_ARCH_v1
bool
config NXP_ESBC
bool "NXP ESBC (secure boot) functionality"
select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
ARCH_P5040 || ARCH_P2041
help
Enable Freescale Secure Boot feature. Normally selected by defconfig.
If unsure, do not change.
menu "Chain of trust / secure boot options"
depends on !FIT_SIGNATURE && NXP_ESBC
config CHAIN_OF_TRUST
select FSL_CAAM
select ARCH_MISC_INIT
select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
select FSL_SEC_MON
select SPL_BOARD_INIT if (ARM && SPL)
select SPL_HASH if (ARM && SPL)
select SHA_HW_ACCEL
select SHA_PROG_HW_ACCEL
select ENV_IS_NOWHERE
select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
select CMD_EXT4 if ARM
select CMD_EXT4_WRITE if ARM
imply CMD_BLOB
imply CMD_HASH if ARM
def_bool y
config CMD_ESBC_VALIDATE
bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
default y
help
This option enables two commands used for secure booting:
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
config ESBC_HDR_LS
bool
config ESBC_ADDR_64BIT
def_bool y
depends on FSL_LAYERSCAPE
help
For Layerscape based platforms, ESBC image Address in Header is 64bit.
config FSL_ISBC_KEY_EXT
bool
help
The key used for verification of next level images is picked up from
an Extension Table which has been verified by the ISBC (Internal
Secure boot Code) in boot ROM of the SoC. The feature is only
applicable in case of NOR boot and is not applicable in case of
RAMBOOT (NAND, SD, SPI). For Layerscape, this feature is available
for all device if IE Table is copied to XIP memory Also, for
Layerscape, ISBC doesn't verify this table.
config SYS_FSL_SFP_BE
def_bool y
depends on PPC || FSL_LSCH2 || ARCH_LS1021A
config SYS_FSL_SFP_LE
def_bool y
depends on !SYS_FSL_SFP_BE
choice
prompt "SFP IP revision"
default SYS_FSL_SFP_VER_3_0 if PPC
default SYS_FSL_SFP_VER_3_4
config SYS_FSL_SFP_VER_3_0
bool "SFP version 3.0"
config SYS_FSL_SFP_VER_3_2
bool "SFP version 3.2"
config SYS_FSL_SFP_VER_3_4
bool "SFP version 3.4"
endchoice
config SPL_UBOOT_KEY_HASH
string "Non-SRK key hash for U-Boot public/private key pair"
depends on SPL
default ""
help
Set the key hash for U-Boot here if public/private key pair used to
sign U-Boot are different from the SRK hash put in the fuse. Example
of a key hash is
41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
Otherwise leave this empty.
if PPC
config BOOTSCRIPT_COPY_RAM
bool "Secure boot copies boot script to RAM"
help
On systems that support chain of trust booting, a number of addresses
are required to set variables that are used in the copying and then
verification of different parts of the system. If enabled, the subsequent
options are for what location to use in each step.
config BS_ADDR_DEVICE
hex "Address in RAM for bs_device"
depends on BOOTSCRIPT_COPY_RAM
config BS_SIZE
hex "The size of bs_size which is the amount read from bs_device"
depends on BOOTSCRIPT_COPY_RAM
config BS_ADDR_RAM
hex "Address in RAM for bs_ram"
depends on BOOTSCRIPT_COPY_RAM
config BS_HDR_ADDR_DEVICE
hex "Address in RAM for bs_hdr_device"
depends on BOOTSCRIPT_COPY_RAM
config BS_HDR_SIZE
hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
depends on BOOTSCRIPT_COPY_RAM
config BS_HDR_ADDR_RAM
hex "Address in RAM for bs_hdr_ram"
depends on BOOTSCRIPT_COPY_RAM
config BOOTSCRIPT_HDR_ADDR
hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
endif
config SYS_FSL_SRK_LE
def_bool y
depends on ARM
config KEY_REVOCATION
def_bool y
endmenu
config DEEP_SLEEP
bool "Enable SoC deep sleep feature"
depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
default y
help
Indicates this SoC supports deep sleep feature. If deep sleep is
supported, core will start to execute uboot when wakes up.
config LAYERSCAPE_NS_ACCESS
bool "Layerscape non-secure access support"
depends on ARCH_LS1021A || FSL_LSCH2
config PCIE1
bool "PCIe controller #1"
depends on LAYERSCAPE_NS_ACCESS || PPC
config PCIE2
bool "PCIe controller #2"
depends on LAYERSCAPE_NS_ACCESS || PPC
config PCIE3
bool "PCIe controller #3"
depends on LAYERSCAPE_NS_ACCESS || PPC
config PCIE4
bool "PCIe controller #4"
depends on LAYERSCAPE_NS_ACCESS || PPC
config FSL_USE_PCA9547_MUX
bool "Enable PCA9547 I2C Mux on Freescale boards"
depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
help
This option enables the PCA9547 I2C mux on Freescale boards.
config VID
bool "Enable Freescale VID"
depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
help
This option enables setting core voltage based on individual
values saved in SoC fuses.
config SPL_VID
bool "Enable Freescale VID in SPL"
depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
help
This option enables setting core voltage based on individual
values saved in SoC fuses, in SPL.
if VID || SPL_VID
config VID_FLS_ENV
string "Environment variable for overriding VDD"
help
This option allows for specifying the environment variable
to check to override VDD information.
config VOL_MONITOR_INA220
bool "Enable the INA220 voltage monitor read"
help
This option enables INA220 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_IR36021_READ
bool "Enable the IR36021 voltage monitor read"
help
This option enables IR36021 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_IR36021_SET
bool "Enable the IR36021 voltage monitor set"
help
This option enables IR36021 voltage monitor set
functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_READ
bool "Enable the LTC3882 voltage monitor read"
help
This option enables LTC3882 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_SET
bool "Enable the LTC3882 voltage monitor set"
help
This option enables LTC3882 voltage monitor set
functionality. It is used by the common VID driver.
config VOL_MONITOR_ISL68233_READ
bool "Enable the ISL68233 voltage monitor read"
help
This option enables ISL68233 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_ISL68233_SET
bool "Enable the ISL68233 voltage monitor set"
help
This option enables ISL68233 voltage monitor set
functionality. It is used by the common VID driver.
endif
config SYS_FSL_NUM_CC_PLLS
int "Number of clock control PLLs"
depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
default 6 if FSL_LSCH3 || MPC85xx
config SYS_FSL_ESDHC_BE
bool
config SYS_FSL_IFC_BE
bool
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
ARCH_T2080 || ARCH_C29X || ARCH_P1010 || ARCH_BSC9131 || \
ARCH_BSC9132
default 3 if ARCH_BSC9131 || ARCH_BSC9132
default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
ARCH_B4420 || ARCH_P1010
default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || \
ARCH_T1024 || ARCH_T2080 || ARCH_C29X
config FSL_QIXIS
bool "Enable QIXIS support"
depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
config QIXIS_I2C_ACCESS
bool "Access to QIXIS is over i2c"
depends on FSL_QIXIS
default y
config HAS_FSL_DR_USB
def_bool y
depends on USB_EHCI_HCD && PPC
config SYS_DPAA_FMAN
bool
config SYS_FSL_SRDS_1
bool
config SYS_FSL_SRDS_2
bool
config SYS_HAS_SERDES
bool
endmenu

12
arch/arc/Kconfig
View File

@ -102,15 +102,20 @@ config ARC_MMU_V4
endchoice
config ARC_MMU_VER
int
default 0 if ARC_MMU_ABSENT
default 2 if ARC_MMU_V2
default 3 if ARC_MMU_V3
default 4 if ARC_MMU_V4
config CPU_BIG_ENDIAN
bool "Enable Big Endian Mode"
default n
help
Build kernel for Big Endian Mode of ARC CPU
config SYS_ICACHE_OFF
bool "Do not enable icache"
default n
help
Do not enable instruction cache in U-Boot.
@ -123,7 +128,6 @@ config SPL_SYS_ICACHE_OFF
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
@ -136,14 +140,12 @@ config SPL_SYS_DCACHE_OFF
menuconfig ARC_DBG
bool "ARC debugging"
default n
if ARC_DBG
config ARC_DBG_IOC_ENABLE
bool "Enable IO coherency unit"
depends on CPU_ARCHS38
default n
help
Enable IO coherency unit to debug problems with caches and
DMA peripherals.

13
arch/arc/config.mk
View File

@ -2,12 +2,6 @@
#
# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
ifndef CONFIG_CPU_BIG_ENDIAN
CONFIG_SYS_LITTLE_ENDIAN = 1
else
CONFIG_SYS_BIG_ENDIAN = 1
endif
ifdef CONFIG_SYS_LITTLE_ENDIAN
KBUILD_LDFLAGS += -EL
PLATFORM_CPPFLAGS += -mlittle-endian
@ -18,15 +12,8 @@ KBUILD_LDFLAGS += -EB
PLATFORM_CPPFLAGS += -mbig-endian
endif
ifdef CONFIG_ARC_MMU_VER
CONFIG_MMU = 1
endif
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 -mno-sdata
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common
# Needed for relocation
LDFLAGS_FINAL += -pie --gc-sections
# Load address for standalone apps
CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000

6
arch/arc/cpu/u-boot.lds
View File

@ -10,7 +10,7 @@ OUTPUT_ARCH(arc)
ENTRY(_start)
SECTIONS
{
. = CONFIG_SYS_TEXT_BASE;
. = CONFIG_TEXT_BASE;
__image_copy_start = .;
. = ALIGN(1024);
__ivt_start = .;
@ -39,8 +39,8 @@ SECTIONS
}
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
}
. = ALIGN(4);

2
arch/arc/dts/Makefile
View File

@ -8,6 +8,8 @@ dtb-$(CONFIG_TARGET_EMSDP) += emsdp.dtb
dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb hsdk-4xd.dtb
dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000

2
arch/arc/dts/abilis_tb100.dts
View File

@ -18,7 +18,7 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <500000000>;
u-boot,dm-pre-reloc;
bootph-all;
};
};

2
arch/arc/dts/axc001.dtsi
View File

@ -11,7 +11,7 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <750000000>;
u-boot,dm-pre-reloc;
bootph-all;
};
};
};

2
arch/arc/dts/axc003.dtsi
View File

@ -11,7 +11,7 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
u-boot,dm-pre-reloc;
bootph-all;
};
};
};

6
arch/arc/dts/axs10x_mb.dtsi
View File

@ -13,11 +13,11 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0xe0000000 0x10000000>;
u-boot,dm-pre-reloc;
bootph-all;
clocks {
compatible = "simple-bus";
u-boot,dm-pre-reloc;
bootph-all;
apbclk: apbclk {
compatible = "fixed-clock";
@ -29,7 +29,7 @@
compatible = "fixed-clock";
clock-frequency = <33333333>;
#clock-cells = <0>;
u-boot,dm-pre-reloc;
bootph-all;
};
mmcclk_ciu: mmcclk-ciu {

2
arch/arc/dts/emsdp.dts
View File

@ -21,7 +21,7 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <40000000>;
u-boot,dm-pre-reloc;
bootph-all;
};
};

2
arch/arc/dts/hsdk-common.dtsi
View File

@ -23,7 +23,7 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <500000000>;
u-boot,dm-pre-reloc;
bootph-all;
};
};

2
arch/arc/dts/iot_devkit.dts
View File

@ -19,7 +19,7 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <144000000>;
u-boot,dm-pre-reloc;
bootph-all;
};
};

2
arch/arc/dts/nsim.dts
View File

@ -18,7 +18,7 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <70000000>;
u-boot,dm-pre-reloc;
bootph-all;
};
};

2
arch/arc/dts/skeleton.dtsi
View File

@ -14,7 +14,7 @@
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
u-boot,dm-pre-reloc;
bootph-all;
timer@0 {
compatible = "snps,arc-timer";

2
arch/arc/include/asm/arc-bcr.h
View File

@ -13,8 +13,6 @@
#define __ARC_BCR_H
#ifndef __ASSEMBLY__
#include <config.h>
union bcr_di_cache {
struct {
#ifdef CONFIG_CPU_BIG_ENDIAN

1
arch/arc/include/asm/arcregs.h
View File

@ -7,7 +7,6 @@
#define _ASM_ARC_ARCREGS_H
#include <asm/cache.h>
#include <config.h>
/*
* ARC architecture has additional address space - auxiliary registers.

15
arch/arc/include/asm/cache.h
View File

@ -6,8 +6,6 @@
#ifndef __ASM_ARC_CACHE_H
#define __ASM_ARC_CACHE_H
#include <config.h>
/*
* As of today we may handle any L1 cache line length right in software.
* For that essentially cache line length is a variable not constant.
@ -16,19 +14,6 @@
*/
#define ARCH_DMA_MINALIGN 128
/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
#if defined(ARC_MMU_ABSENT)
#define CONFIG_ARC_MMU_VER 0
#elif defined(CONFIG_ARC_MMU_V2)
#define CONFIG_ARC_MMU_VER 2
#elif defined(CONFIG_ARC_MMU_V3)
#define CONFIG_ARC_MMU_VER 3
#elif defined(CONFIG_ARC_MMU_V4)
#define CONFIG_ARC_MMU_VER 4
#endif
#ifndef __ASSEMBLY__
void cache_init(void);

2
arch/arc/include/asm/config.h
View File

@ -6,6 +6,4 @@
#ifndef __ASM_ARC_CONFIG_H_
#define __ASM_ARC_CONFIG_H_
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif /*__ASM_ARC_CONFIG_H_ */

2
arch/arc/include/asm/io.h
View File

@ -80,7 +80,7 @@ static inline void sync(void)
/*
* We add memory barriers for __raw_readX / __raw_writeX accessors same way as
* it is done for readX and writeX accessors as lots of U-boot driver uses
* it is done for readX and writeX accessors as lots of U-Boot driver uses
* __raw_readX / __raw_writeX instead of proper accessor with barrier.
*/
#define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); })

5
arch/arc/include/asm/sections.h
View File

@ -8,7 +8,8 @@
#include <asm-generic/sections.h>
extern ulong __ivt_start;
extern ulong __ivt_end;
extern char __ivt_start[];
extern char __ivt_end[];
extern char __text_end[];
#endif /* __ASM_ARC_SECTIONS_H */

52
arch/arc/lib/bootm.c
View File

@ -3,47 +3,17 @@
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
#include <common.h>
#include <bootm.h>
#include <bootstage.h>
#include <env.h>
#include <image.h>
#include <irq_func.h>
#include <lmb.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static ulong get_sp(void)
{
ulong ret;
asm("mov %0, sp" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
ulong sp;
/*
* Booting a (Linux) kernel image
*
* Allocate space for command line and board info - the
* address should be as high as possible within the reach of
* the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
* memory, which means far enough below the current stack
* pointer.
*/
sp = get_sp();
debug("## Current stack ends at 0x%08lx ", sp);
/* adjust sp by 4K to be safe */
sp -= 4096;
lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
}
static int cleanup_before_linux(void)
{
disable_interrupts();
@ -52,16 +22,18 @@ static int cleanup_before_linux(void)
return 0;
}
__weak int board_prep_linux(bootm_headers_t *images) { return 0; }
__weak int board_prep_linux(struct bootm_headers *images) { return 0; }
/* Subcommand: PREP */
static int boot_prep_linux(bootm_headers_t *images)
static int boot_prep_linux(struct bootm_headers *images)
{
int ret;
ret = image_setup_linux(images);
if (ret)
return ret;
if (IS_ENABLED(CONFIG_LMB)) {
ret = image_setup_linux(images);
if (ret)
return ret;
}
return board_prep_linux(images);
}
@ -77,7 +49,7 @@ __weak void board_jump_and_run(ulong entry, int zero, int arch, uint params)
}
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
static void boot_jump_linux(struct bootm_headers *images, int flag)
{
ulong kernel_entry;
unsigned int r0, r2;
@ -93,7 +65,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
r0 = 2;
r2 = (unsigned int)images->ft_addr;
} else {
@ -107,8 +79,10 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
board_jump_and_run(kernel_entry, r0, 0, r2);
}
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
int do_bootm_linux(int flag, struct bootm_info *bmi)
{
struct bootm_headers *images = bmi->images;
/* No need for those on ARC */
if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
return -1;

19
arch/arc/lib/cache.c
View File

@ -4,13 +4,13 @@
*/
#include <config.h>
#include <common.h>
#include <cpu_func.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <lmb.h>
#include <asm/arcregs.h>
#include <asm/arc-bcr.h>
#include <asm/cache.h>
@ -475,9 +475,9 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
static void arc_ioc_setup(void)
{
/* IOC Aperture start is equal to DDR start */
unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
unsigned int ap_base = CFG_SYS_SDRAM_BASE;
/* IOC Aperture size is equal to DDR size */
long ap_size = CONFIG_SYS_SDRAM_SIZE;
long ap_size = CFG_SYS_SDRAM_SIZE;
/* Unsupported configuration. See [ NOTE 2 ] for more details. */
if (!slc_exists())
@ -820,3 +820,16 @@ void sync_n_cleanup_cache_all(void)
__ic_entire_invalidate();
}
static ulong get_sp(void)
{
ulong ret;
asm("mov %0, sp" : "=r"(ret) : );
return ret;
}
void arch_lmb_reserve(struct lmb *lmb)
{
arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
}

7
arch/arc/lib/cpu.c
View File

@ -3,7 +3,8 @@
* Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved.
*/
#include <common.h>
#include <config.h>
#include <clock_legacy.h>
#include <init.h>
#include <malloc.h>
#include <vsprintf.h>
@ -18,8 +19,8 @@ int arch_cpu_init(void)
{
timer_init();
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
gd->cpu_clk = get_board_sys_clk();
gd->ram_size = CFG_SYS_SDRAM_SIZE;
cache_init();

1
arch/arc/lib/init_helpers.c
View File

@ -5,7 +5,6 @@
#include <init.h>
#include <asm/cache.h>
#include <common.h>
int init_cache_f_r(void)
{

2
arch/arc/lib/interrupts.c
View File

@ -3,8 +3,8 @@
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
#include <common.h>
#include <irq_func.h>
#include <vsprintf.h>
#include <asm/arcregs.h>
#include <asm/ptrace.h>

5
arch/arc/lib/ints_low.S
View File

@ -76,13 +76,8 @@
.endm
.macro SAVE_EXCEPTION_SOURCE
#ifdef CONFIG_MMU
/* If MMU exists exception faulting address is loaded in EFA reg */
lr %r0, [%efa]
#else
/* Otherwise in ERET (exception return) reg */
lr %r0, [%eret]
#endif
.endm
ENTRY(memory_error)

2
arch/arc/lib/libgcc2.h
View File

@ -35,7 +35,7 @@ typedef int HItype __attribute__ ((mode (HI)));
typedef unsigned int UHItype __attribute__ ((mode (HI)));
#if MIN_UNITS_PER_WORD > 1
/* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1. */
typedef int SItype __attribute__ ((mode (SI)));
typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
#if __SIZEOF_LONG_LONG__ > 4
/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2. */

38
arch/arc/lib/relocate.c
View File

@ -3,35 +3,29 @@
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
#include <common.h>
#include <elf.h>
#include <log.h>
#include <asm-generic/sections.h>
#include <asm/sections.h>
#include <asm/global_data.h>
extern ulong __image_copy_start;
extern ulong __ivt_start;
extern ulong __ivt_end;
extern ulong __text_end;
DECLARE_GLOBAL_DATA_PTR;
int copy_uboot_to_ram(void)
{
size_t len = (size_t)&__image_copy_end - (size_t)&__image_copy_start;
size_t len = (size_t)__image_copy_end - (size_t)__image_copy_start;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
memcpy((void *)gd->relocaddr, (void *)&__image_copy_start, len);
memcpy((void *)gd->relocaddr, (void *)__image_copy_start, len);
return 0;
}
int clear_bss(void)
{
ulong dst_addr = (ulong)&__bss_start + gd->reloc_off;
size_t len = (size_t)&__bss_end - (size_t)&__bss_start;
ulong dst_addr = (ulong)__bss_start + gd->reloc_off;
size_t len = (size_t)__bss_end - (size_t)__bss_start;
memset((void *)dst_addr, 0x00, len);
@ -43,8 +37,8 @@ int clear_bss(void)
*/
int do_elf_reloc_fixups(void)
{
Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start);
Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end);
Elf32_Rela *re_src = (Elf32_Rela *)__rel_dyn_start;
Elf32_Rela *re_end = (Elf32_Rela *)__rel_dyn_end;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
@ -60,8 +54,8 @@ int do_elf_reloc_fixups(void)
offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
/* Check that the location of the relocation is in .text */
if (offset_ptr_rom >= (Elf32_Addr *)&__image_copy_start &&
offset_ptr_rom < (Elf32_Addr *)&__image_copy_end) {
if (offset_ptr_rom >= (Elf32_Addr *)__image_copy_start &&
offset_ptr_rom < (Elf32_Addr *)__image_copy_end) {
unsigned int val, do_swap = 0;
/* Switch to the in-RAM version */
offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
@ -69,11 +63,11 @@ int do_elf_reloc_fixups(void)
#ifdef __LITTLE_ENDIAN__
/* If location in ".text" section swap value */
if (((u32)offset_ptr_rom >= (u32)&__text_start &&
(u32)offset_ptr_rom <= (u32)&__text_end)
if (((u32)offset_ptr_rom >= (u32)__text_start &&
(u32)offset_ptr_rom <= (u32)__text_end)
#if defined(__ARC700__) || defined(__ARC600__)
|| ((u32)offset_ptr_rom >= (u32)&__ivt_start &&
(u32)offset_ptr_rom <= (u32)&__ivt_end)
|| ((u32)offset_ptr_rom >= (u32)__ivt_start &&
(u32)offset_ptr_rom <= (u32)__ivt_end)
#endif
)
do_swap = 1;
@ -96,8 +90,8 @@ int do_elf_reloc_fixups(void)
val = (val << 16) | (val >> 16);
/* Check that the target points into executable */
if (val < (unsigned int)&__image_copy_start ||
val > (unsigned int)&__image_copy_end) {
if (val < (unsigned int)__image_copy_start ||
val > (unsigned int)__image_copy_end) {
/* TODO: Use panic() instead of debug()
*
* For some reason GCC might generate
@ -106,7 +100,7 @@ int do_elf_reloc_fixups(void)
* ----------------------->8--------------------
* static int setup_mon_len(void)
* {
* gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
* gd->mon_len = (ulong)__bss_end - CONFIG_SYS_MONITOR_BASE;
* return 0;
* }
* ----------------------->8--------------------

1
arch/arc/lib/reset.c
View File

@ -4,7 +4,6 @@
*/
#include <command.h>
#include <common.h>
#include <cpu_func.h>
__weak void reset_cpu(void)

3
arch/arc/lib/start.S
View File

@ -7,6 +7,7 @@
#include <config.h>
#include <linux/linkage.h>
#include <asm/arcregs.h>
#include <system-constants.h>
ENTRY(_start)
/* Setup interrupt vector base that matches "__text_start" */
@ -86,7 +87,7 @@ ENTRY(_start)
#endif
/* Establish C runtime stack and frame */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %sp, SYS_INIT_SP_ADDR
mov %fp, %sp
/* Allocate reserved area from current top of stack */

853
arch/arm/Kconfig
View File

File diff suppressed because it is too large Load Diff

32
arch/arm/Makefile
View File

@ -10,15 +10,17 @@ arch-$(CONFIG_CPU_ARM720T) =-march=armv4
arch-$(CONFIG_CPU_ARM920T) =-march=armv4t
arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te
arch-$(CONFIG_CPU_ARM946ES) =-march=armv5te
arch-$(CONFIG_CPU_SA1100) =-march=armv4
arch-$(CONFIG_CPU_PXA) =
arch-$(CONFIG_CPU_ARM1136) =-march=armv5t
arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \
$(call cc-option, -march=armv7))
arch-$(CONFIG_CPU_V7M) =-march=armv7-m
arch-$(CONFIG_CPU_V7R) =-march=armv7-r
ifeq ($(CONFIG_ARM64_CRC32),y)
arch-$(CONFIG_ARM64) =-march=armv8-a+crc
else
arch-$(CONFIG_ARM64) =-march=armv8-a
endif
# On Tegra systems we must build SPL for the armv4 core on the device
# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
@ -36,8 +38,6 @@ tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7tdmi
tune-$(CONFIG_CPU_ARM920T) =
tune-$(CONFIG_CPU_ARM926EJS) =
tune-$(CONFIG_CPU_ARM946ES) =
tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
tune-$(CONFIG_CPU_PXA) =-mcpu=xscale
tune-$(CONFIG_CPU_ARM1136) =
tune-$(CONFIG_CPU_ARM1176) =
tune-$(CONFIG_CPU_V7A) =-mtune=generic-armv7-a
@ -51,13 +51,17 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_APPLE) += apple
machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_BCM283X) += bcm283x
machine-$(CONFIG_ARCH_BCMBCA) += bcmbca
machine-$(CONFIG_ARCH_BCMSTB) += bcmstb
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_EXYNOS) += exynos
machine-$(CONFIG_ARCH_GXP) += hpe
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HISTB) += histb
machine-$(CONFIG_ARCH_IPQ40XX) += ipq40xx
machine-$(CONFIG_ARCH_K3) += k3
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
@ -67,10 +71,11 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_NEXELL) += nexell
machine-$(CONFIG_ARCH_NPCM) += npcm
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x
machine-$(CONFIG_ARCH_OWL) += owl
machine-$(CONFIG_ARCH_RMOBILE) += rmobile
machine-$(CONFIG_ARCH_RENESAS) += renesas
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon
@ -84,10 +89,13 @@ machine-$(CONFIG_ARCH_OCTEONTX) += octeontx
machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSAL) += versal
machine-$(CONFIG_ARCH_VERSAL_NET) += versal-net
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
machine-$(CONFIG_MACH_IMX) += imx
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
@ -97,8 +105,8 @@ libs-y += $(machdirs)
head-y := arch/arm/cpu/$(CPU)/start.o
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq ($(CONFIG_SPL_START_S_PATH),)
head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs")
head-y := arch/arm/cpu/arm926ejs/mxs/start.o
endif
endif
@ -106,16 +114,6 @@ libs-y += arch/arm/cpu/$(CPU)/
libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt))
libs-y += arch/arm/mach-imx/
endif
else
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imxrt vf610))
libs-y += arch/arm/mach-imx/
endif
endif
ifneq (,$(filter $(SOC), kirkwood))
libs-y += arch/arm/mach-mvebu/
endif

25
arch/arm/config.mk
View File

@ -3,28 +3,27 @@
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifndef CONFIG_STANDALONE_LOAD_ADDR
ifneq ($(CONFIG_ARCH_OMAP2PLUS),)
CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
ifeq ($(CONFIG_ARM64),y)
FIXED_REG := -ffixed-x18
else
CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
endif
FIXED_REG := -ffixed-r9
endif
CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
CFLAGS_NON_EFI := -fno-pic $(FIXED_REG) -ffunction-sections -fdata-sections \
-fstack-protector-strong
CFLAGS_EFI := -fpic -fshort-wchar
ifneq ($(CONFIG_LTO)$(CONFIG_USE_PRIVATE_LIBGCC),yy)
ifneq ($(LTO_ENABLE)$(CONFIG_USE_PRIVATE_LIBGCC),yy)
LDFLAGS_FINAL += --gc-sections
endif
ifndef CONFIG_LTO
ifneq ($(LTO_ENABLE),y)
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
endif
PLATFORM_RELFLAGS += -fno-common -ffixed-r9
PLATFORM_RELFLAGS += -fno-common $(FIXED_REG)
PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
$(call cc-option,-mgeneral-regs-only) \
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
# LLVM support
@ -140,11 +139,11 @@ endif
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
-j __u_boot_list -j .rela.dyn -j .got -j .got.plt \
-j .binman_sym_table -j .text_rest
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
-j .data -j .got -j .got.plt -j __u_boot_list -j .rel.dyn \
-j .binman_sym_table -j .text_rest
endif
@ -158,7 +157,8 @@ ifdef CONFIG_EFI_LOADER
OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel
endif
ifneq ($(CONFIG_IMX_CONFIG),)
ifdef CONFIG_MACH_IMX
ifneq ($(CONFIG_IMX_CONFIG),"")
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
INPUTS-y += SPL
@ -174,6 +174,7 @@ ifneq ($(CONFIG_VF610),)
INPUTS-y += u-boot.vyb
endif
endif
endif
EFI_LDS := elf_arm_efi.lds
EFI_CRT0 := crt0_arm_efi.o

6
arch/arm/cpu/arm11/cpu.c
View File

@ -20,6 +20,7 @@
#include <irq_func.h>
#include <asm/cache.h>
#include <asm/system.h>
#include <asm/arm11.h>
static void cache_flush(void);
@ -43,6 +44,11 @@ int cleanup_before_linux (void)
return 0;
}
void allow_unaligned(void)
{
arm11_arch_cp15_allow_unaligned();
}
static void cache_flush(void)
{
unsigned long i = 0;

6
arch/arm/cpu/arm11/sctlr.S
View File

@ -8,7 +8,7 @@
#include <linux/linkage.h>
/*
* void allow_unaligned(void) - allow unaligned access
* void arm11_arch_cp15_allow_unaligned(void) - allow unaligned access
*
* This routine sets the enable unaligned data support flag and clears the
* aligned flag in the system control register.
@ -16,10 +16,10 @@
* data abort or undefined behavior but is handled by the CPU.
* For details see the "ARM Architecture Reference Manual" for ARMv6.
*/
ENTRY(allow_unaligned)
ENTRY(arm11_arch_cp15_allow_unaligned)
mrc p15, 0, r0, c1, c0, 0 @ load system control register
orr r0, r0, #1 << 22 @ set unaligned data support flag
bic r0, r0, #2 @ clear aligned flag
mcr p15, 0, r0, c1, c0, 0 @ write system control register
bx lr @ return
ENDPROC(allow_unaligned)
ENDPROC(arm11_arch_cp15_allow_unaligned)

1
arch/arm/cpu/arm1136/Makefile
View File

@ -7,4 +7,3 @@ extra-y = start.o
obj-y += ../arm11/
obj-$(CONFIG_MX31) += mx31/
obj-$(CONFIG_MX35) += mx35/

11
arch/arm/cpu/arm1136/mx35/Makefile
View File

@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
obj-y += generic.o
obj-y += timer.o
obj-y += mx35_sdram.o
obj-y += relocate.o

530
arch/arm/cpu/arm1136/mx35/generic.c
View File

@ -1,530 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <clock_legacy.h>
#include <command.h>
#include <div64.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_FSL_ESDHC_IMX
#include <fsl_esdhc_imx.h>
#endif
#include <netdev.h>
#include <spl.h>
#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
#define CLK_CODE_PATH(c) ((c) & 0xFF)
#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
static int g_clk_mux_auto[8] = {
CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
};
static int g_clk_mux_consumer[16] = {
CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
-1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
-1, -1, CLK_CODE(4, 2, 0), -1,
};
static int hsp_div_table[3][16] = {
{4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
{-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
{3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
};
u32 get_cpu_rev(void)
{
int reg;
struct iim_regs *iim =
(struct iim_regs *)IIM_BASE_ADDR;
reg = readl(&iim->iim_srev);
if (!reg) {
reg = readw(ROMPATCH_REV);
reg <<= 4;
} else {
reg += CHIP_REV_1_0;
}
return 0x35000 + (reg & 0xFF);
}
static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
{
int *pclk_mux;
if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
pclk_mux = g_clk_mux_consumer +
((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
} else {
pclk_mux = g_clk_mux_auto +
((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
}
if ((*pclk_mux) == -1)
return -1;
if (fi && fd) {
if (!CLK_CODE_PATH(*pclk_mux)) {
*fi = *fd = 1;
return CLK_CODE_ARM(*pclk_mux);
}
if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
*fi = 3;
*fd = 4;
} else {
*fi = 2;
*fd = 3;
}
}
return CLK_CODE_ARM(*pclk_mux);
}
static int get_ahb_div(u32 pdr0)
{
int *pclk_mux;
pclk_mux = g_clk_mux_consumer +
((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
if ((*pclk_mux) == -1)
return -1;
return CLK_CODE_AHB(*pclk_mux);
}
static u32 decode_pll(u32 reg, u32 infreq)
{
u32 mfi = (reg >> 10) & 0xf;
s32 mfn = reg & 0x3ff;
u32 mfd = (reg >> 16) & 0x3ff;
u32 pd = (reg >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
mfn = mfn >= 512 ? mfn - 1024 : mfn;
mfd += 1;
pd += 1;
return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
mfd * pd);
}
static u32 get_mcu_main_clk(void)
{
u32 arm_div = 0, fi = 0, fd = 0;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
return fi / (arm_div * fd);
}
static u32 get_ipg_clk(void)
{
u32 freq = get_mcu_main_clk();
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 pdr0 = readl(&ccm->pdr0);
return freq / (get_ahb_div(pdr0) * 2);
}
static u32 get_ipg_per_clk(void)
{
u32 freq = get_mcu_main_clk();
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 pdr0 = readl(&ccm->pdr0);
u32 pdr4 = readl(&ccm->pdr4);
u32 div;
if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
div = CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_PER0_PODF_MASK,
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
} else {
div = CCM_GET_DIVIDER(pdr0,
MXC_CCM_PDR0_PER_PODF_MASK,
MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
div *= get_ahb_div(pdr0);
}
return freq / div;
}
u32 imx_get_uartclk(void)
{
u32 freq;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 pdr4 = readl(&ccm->pdr4);
if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
freq = get_mcu_main_clk();
else
freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
freq /= CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_UART_PODF_MASK,
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
return freq;
}
unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
{
u32 nfc_pdf, hsp_podf;
u32 pll, ret_val = 0, usb_podf;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 reg = readl(&ccm->pdr0);
u32 reg4 = readl(&ccm->pdr4);
reg |= 0x1;
switch (clk) {
case CPU_CLK:
ret_val = get_mcu_main_clk();
break;
case AHB_CLK:
ret_val = get_mcu_main_clk();
break;
case HSP_CLK:
if (reg & CLKMODE_CONSUMER) {
hsp_podf = (reg >> 20) & 0x3;
pll = get_mcu_main_clk();
hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
if (hsp_podf > 0) {
ret_val = pll / hsp_podf;
} else {
puts("mismatch HSP with ARM clock setting\n");
ret_val = 0;
}
} else {
ret_val = get_mcu_main_clk();
}
break;
case IPG_CLK:
ret_val = get_ipg_clk();
break;
case IPG_PER_CLK:
ret_val = get_ipg_per_clk();
break;
case NFC_CLK:
nfc_pdf = (reg4 >> 28) & 0xF;
pll = get_mcu_main_clk();
/* AHB/nfc_pdf */
ret_val = pll / (nfc_pdf + 1);
break;
case USB_CLK:
usb_podf = (reg4 >> 22) & 0x3F;
if (reg4 & 0x200)
pll = get_mcu_main_clk();
else
pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
ret_val = pll / (usb_podf + 1);
break;
default:
printf("Unknown clock: %d\n", clk);
break;
}
return ret_val;
}
unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
{
u32 ret_val = 0, pdf, pre_pdf, clk_sel;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 mpdr2 = readl(&ccm->pdr2);
u32 mpdr3 = readl(&ccm->pdr3);
u32 mpdr4 = readl(&ccm->pdr4);
switch (clk) {
case UART1_BAUD:
case UART2_BAUD:
case UART3_BAUD:
clk_sel = mpdr3 & (1 << 14);
pdf = (mpdr4 >> 10) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case SSI1_BAUD:
pre_pdf = (mpdr2 >> 24) & 0x7;
pdf = mpdr2 & 0x3F;
clk_sel = mpdr2 & (1 << 6);
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case SSI2_BAUD:
pre_pdf = (mpdr2 >> 27) & 0x7;
pdf = (mpdr2 >> 8) & 0x3F;
clk_sel = mpdr2 & (1 << 6);
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case CSI_BAUD:
clk_sel = mpdr2 & (1 << 7);
pdf = (mpdr2 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case MSHC_CLK:
pre_pdf = readl(&ccm->pdr1);
clk_sel = (pre_pdf & 0x80);
pdf = (pre_pdf >> 22) & 0x3F;
pre_pdf = (pre_pdf >> 28) & 0x7;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case ESDHC1_CLK:
clk_sel = mpdr3 & 0x40;
pdf = mpdr3 & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case ESDHC2_CLK:
clk_sel = mpdr3 & 0x40;
pdf = (mpdr3 >> 8) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case ESDHC3_CLK:
clk_sel = mpdr3 & 0x40;
pdf = (mpdr3 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case SPDIF_CLK:
clk_sel = mpdr3 & 0x400000;
pre_pdf = (mpdr3 >> 29) & 0x7;
pdf = (mpdr3 >> 23) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
default:
printf("%s(): This clock: %d not supported yet\n",
__func__, clk);
break;
}
return ret_val;
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return get_mcu_main_clk();
case MXC_AHB_CLK:
break;
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_IPG_PERCLK:
case MXC_I2C_CLK:
return get_ipg_per_clk();
case MXC_UART_CLK:
return imx_get_uartclk();
case MXC_ESDHC1_CLK:
return mxc_get_peri_clock(ESDHC1_CLK);
case MXC_ESDHC2_CLK:
return mxc_get_peri_clock(ESDHC2_CLK);
case MXC_ESDHC3_CLK:
return mxc_get_peri_clock(ESDHC3_CLK);
case MXC_USB_CLK:
return mxc_get_main_clock(USB_CLK);
case MXC_FEC_CLK:
return get_ipg_clk();
case MXC_CSPI_CLK:
return get_ipg_clk();
}
return -1;
}
#ifdef CONFIG_FEC_MXC
/*
* The MX35 has no fuse for MAC, return a NULL MAC
*/
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
memset(mac, 0, 6);
}
u32 imx_get_fecclk(void)
{
return mxc_get_clock(MXC_IPG_CLK);
}
#endif
int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
u32 cpufreq = get_mcu_main_clk();
printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
printf("ipg clock : %dHz\n", get_ipg_clk());
printf("ipg per clock : %dHz\n", get_ipg_per_clk());
printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
return 0;
}
U_BOOT_CMD(
clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
"display clocks",
""
);
#if defined(CONFIG_DISPLAY_CPUINFO)
static char *get_reset_cause(void)
{
/* read RCSR register from CCM module */
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 cause = readl(&ccm->rcsr) & 0x0F;
switch (cause) {
case 0x0000:
return "POR";
case 0x0002:
return "JTAG";
case 0x0004:
return "RST";
case 0x0008:
return "WDOG";
default:
return "unknown reset";
}
}
int print_cpuinfo(void)
{
u32 srev = get_cpu_rev();
printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
(srev & 0xF0) >> 4, (srev & 0x0F),
get_mcu_main_clk() / 1000000);
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(struct bd_info *bis)
{
int rc = -ENODEV;
#if defined(CONFIG_FEC_MXC)
rc = fecmxc_initialize(bis);
#endif
return rc;
}
#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
{
return fsl_esdhc_mmc_init(bis);
}
#endif
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
#endif
#endif
return 0;
}
#define RCSR_MEM_CTL_WEIM 0
#define RCSR_MEM_CTL_NAND 1
#define RCSR_MEM_CTL_ATA 2
#define RCSR_MEM_CTL_EXPANSION 3
#define RCSR_MEM_TYPE_NOR 0
#define RCSR_MEM_TYPE_ONENAND 2
#define RCSR_MEM_TYPE_SD 0
#define RCSR_MEM_TYPE_I2C 2
#define RCSR_MEM_TYPE_SPI 3
u32 spl_boot_device(void)
{
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 rcsr = readl(&ccm->rcsr);
u32 mem_type, mem_ctl;
/* In external mode, no boot device is returned */
if ((rcsr >> 10) & 0x03)
return BOOT_DEVICE_NONE;
mem_ctl = (rcsr >> 25) & 0x03;
mem_type = (rcsr >> 23) & 0x03;
switch (mem_ctl) {
case RCSR_MEM_CTL_WEIM:
switch (mem_type) {
case RCSR_MEM_TYPE_NOR:
return BOOT_DEVICE_NOR;
case RCSR_MEM_TYPE_ONENAND:
return BOOT_DEVICE_ONENAND;
default:
return BOOT_DEVICE_NONE;
}
case RCSR_MEM_CTL_NAND:
return BOOT_DEVICE_NAND;
case RCSR_MEM_CTL_EXPANSION:
switch (mem_type) {
case RCSR_MEM_TYPE_SD:
return BOOT_DEVICE_MMC1;
case RCSR_MEM_TYPE_I2C:
return BOOT_DEVICE_I2C;
case RCSR_MEM_TYPE_SPI:
return BOOT_DEVICE_SPI;
default:
return BOOT_DEVICE_NONE;
}
}
return BOOT_DEVICE_NONE;
}

120
arch/arm/cpu/arm1136/mx35/mx35_sdram.c
View File

@ -1,120 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
*/
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <linux/types.h>
#include <asm/arch/sys_proto.h>
#define ESDCTL_DDR2_EMR2 0x04000000
#define ESDCTL_DDR2_EMR3 0x06000000
#define ESDCTL_PRECHARGE 0x00000400
#define ESDCTL_DDR2_EN_DLL 0x02000400
#define ESDCTL_DDR2_RESET_DLL 0x00000333
#define ESDCTL_DDR2_MR 0x00000233
#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
enum {
SMODE_NORMAL = 0,
SMODE_PRECHARGE,
SMODE_AUTO_REFRESH,
SMODE_LOAD_REG,
SMODE_MANUAL_REFRESH
};
#define set_mode(x, en, m) (x | (en << 31) | (m << 28))
static inline void dram_wait(unsigned int count)
{
volatile unsigned int wait = count;
while (wait--)
;
}
void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
u32 row, u32 col, u32 dsize, u32 refresh)
{
struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
u32 *cfg_reg, *ctl_reg;
u32 val;
u32 ctlval;
switch (start_address) {
case CSD0_BASE_ADDR:
cfg_reg = &esdc->esdcfg0;
ctl_reg = &esdc->esdctl0;
break;
case CSD1_BASE_ADDR:
cfg_reg = &esdc->esdcfg1;
ctl_reg = &esdc->esdctl1;
break;
default:
return;
}
/* The MX35 supports 11 up to 14 rows */
if (row < 11 || row > 14 || col < 8 || col > 10)
return;
ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
/* Initialize MISC register for DDR2 */
val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
writel(val, &esdc->esdmisc);
val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
writel(val, &esdc->esdmisc);
/*
* according to DDR2 specs, wait a while before
* the PRECHARGE_ALL command
*/
dram_wait(0x20000);
/* Load DDR2 config and timing */
writel(ddr2_config, cfg_reg);
/* Precharge ALL */
writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
ctl_reg);
writel(0xda, start_address + ESDCTL_PRECHARGE);
/* Load mode */
writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
ctl_reg);
writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
/* Precharge ALL */
writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
ctl_reg);
writel(0xda, start_address + ESDCTL_PRECHARGE);
/* Set mode auto refresh : at least two refresh are required */
writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
ctl_reg);
writel(0xda, start_address);
writel(0xda, start_address);
writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
ctl_reg);
writeb(0xda, start_address + ESDCTL_DDR2_MR);
writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
/* OCD mode exit */
writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
/* Set normal mode */
writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
ctl_reg);
dram_wait(0x20000);
/* Do not set delay lines, only for MDDR */
}

22
arch/arm/cpu/arm1136/mx35/relocate.S
View File

@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX35-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <linux/linkage.h>
/*
* The i.MX35 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM, so let's avoid relocating the vectors.
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
bx lr
ENDPROC(relocate_vectors)

46
arch/arm/cpu/arm1136/mx35/timer.c
View File

@ -1,46 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/ptrace.h>
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
#define GPTCR_TEN (1) /* Timer enable */
/*
* nothing really to do with interrupts, just starts up a counter.
* The 32KHz 32-bit timer overruns in 134217 seconds
*/
int timer_init(void)
{
int i;
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
/* setup GP Timer 1 */
writel(GPTCR_SWR, &gpt->ctrl);
writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
for (i = 0; i < 100; i++)
writel(0, &gpt->ctrl); /* We have no udelay by now */
writel(0, &gpt->pre); /* prescaler = 1 */
/* Freerun Mode, 32KHz input */
writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
&gpt->ctrl);
writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
return 0;
}

8
arch/arm/cpu/arm1136/start.S
View File

@ -39,7 +39,7 @@ reset:
msr cpsr,r0
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -62,7 +62,7 @@ c_runtime_cpu_setup:
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
@ -81,7 +81,7 @@ cpu_init_crit:
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* Jump to board specific initialization... The Mask ROM will have already initialized
* basic memory. Go here to bump up clock rate and handle wake up conditions.
@ -91,4 +91,4 @@ cpu_init_crit:
mov lr, ip /* restore link */
#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

6
arch/arm/cpu/arm1176/start.S
View File

@ -17,10 +17,6 @@
#include <config.h>
#include <linux/linkage.h>
#ifndef CONFIG_SYS_PHY_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#endif
/*
*************************************************************************
*
@ -88,7 +84,7 @@ cpu_init_crit:
/* Prepare to disable the MMU */
adr r2, mmu_disable_phys
sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
sub r2, r2, #(CFG_SYS_UBOOT_BASE - CONFIG_TEXT_BASE)
b mmu_disable
.align 5

10
arch/arm/cpu/arm720t/start.S
View File

@ -37,8 +37,8 @@ reset:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
bl cpu_init_crit
#endif
@ -62,8 +62,8 @@ c_runtime_cpu_setup:
*************************************************************************
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
cpu_init_crit:
mov ip, lr
@ -76,4 +76,4 @@ cpu_init_crit:
mov lr, ip
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

3
arch/arm/cpu/arm920t/Makefile
View File

@ -7,9 +7,6 @@ extra-y = start.o
obj-y += cpu.o
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
# some files can only build in ARM mode
ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD

19
arch/arm/cpu/arm920t/ep93xx/Makefile
View File

@ -1,19 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Cirrus Logic EP93xx CPU-specific Makefile
#
# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
#
# Copyright (C) 2004, 2005
# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
#
# Copyright (C) 2006
# Dominic Rath <Dominic.Rath@gmx.de>
#
# Based on an original Makefile, which is
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y = cpu.o led.o speed.o timer.o
obj-y += lowlevel_init.o

37
arch/arm/cpu/arm920t/ep93xx/cpu.c
View File

@ -1,37 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Cirrus Logic EP93xx CPU-specific support.
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2004, 2005
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
extern void reset_cpu(void)
{
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
uint32_t value;
/* Unlock DeviceCfg and set SWRST */
writel(0xAA, &syscon->sysswlock);
value = readl(&syscon->devicecfg);
value |= SYSCON_DEVICECFG_SWRST;
writel(value, &syscon->devicecfg);
/* Unlock DeviceCfg and clear SWRST */
writel(0xAA, &syscon->sysswlock);
value = readl(&syscon->devicecfg);
value &= ~SYSCON_DEVICECFG_SWRST;
writel(value, &syscon->devicecfg);
/* Dying... */
while (1)
; /* noop */
}

85
arch/arm/cpu/arm920t/ep93xx/led.c
View File

@ -1,85 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
*/
#include <asm/io.h>
#include <asm/arch/ep93xx.h>
#include <config.h>
#include <status_led.h>
static uint8_t saved_state[2] = {CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF};
static uint32_t gpio_pin[2] = {1 << CONFIG_LED_STATUS_GREEN,
1 << CONFIG_LED_STATUS_RED};
static inline void switch_LED_on(uint8_t led)
{
register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
saved_state[led] = CONFIG_LED_STATUS_ON;
}
static inline void switch_LED_off(uint8_t led)
{
register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
saved_state[led] = CONFIG_LED_STATUS_OFF;
}
void red_led_on(void)
{
switch_LED_on(CONFIG_LED_STATUS_RED);
}
void red_led_off(void)
{
switch_LED_off(CONFIG_LED_STATUS_RED);
}
void green_led_on(void)
{
switch_LED_on(CONFIG_LED_STATUS_GREEN);
}
void green_led_off(void)
{
switch_LED_off(CONFIG_LED_STATUS_GREEN);
}
void __led_init(led_id_t mask, int state)
{
__led_set(mask, state);
}
void __led_toggle(led_id_t mask)
{
if (CONFIG_LED_STATUS_RED == mask) {
if (CONFIG_LED_STATUS_ON == saved_state[CONFIG_LED_STATUS_RED])
red_led_off();
else
red_led_on();
} else if (CONFIG_LED_STATUS_GREEN == mask) {
if (CONFIG_LED_STATUS_ON ==
saved_state[CONFIG_LED_STATUS_GREEN])
green_led_off();
else
green_led_on();
}
}
void __led_set(led_id_t mask, int state)
{
if (CONFIG_LED_STATUS_RED == mask) {
if (CONFIG_LED_STATUS_ON == state)
red_led_on();
else
red_led_off();
} else if (CONFIG_LED_STATUS_GREEN == mask) {
if (CONFIG_LED_STATUS_ON == state)
green_led_on();
else
green_led_off();
}
}

457
arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
View File

@ -1,457 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Low-level initialization for EP93xx
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
* Copyright (C) 2013
* Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
*
* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
* Copyright (C) 2006 Cirrus Logic Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#include <config.h>
#include <asm/arch-ep93xx/ep93xx.h>
/*
/* Configure the SDRAM based on the supplied settings.
*
* Input: r0 - SDRAM DEVCFG register
* r2 - configuration for SDRAM chips
* Output: none
* Modifies: r3, r4
*/
ep93xx_sdram_config:
/* Program the SDRAM device configuration register. */
ldr r3, =SDRAM_BASE
#ifdef CONFIG_EDB93XX_SDCS0
str r0, [r3, #SDRAM_OFF_DEVCFG0]
#endif
#ifdef CONFIG_EDB93XX_SDCS1
str r0, [r3, #SDRAM_OFF_DEVCFG1]
#endif
#ifdef CONFIG_EDB93XX_SDCS2
str r0, [r3, #SDRAM_OFF_DEVCFG2]
#endif
#ifdef CONFIG_EDB93XX_SDCS3
str r0, [r3, #SDRAM_OFF_DEVCFG3]
#endif
/* Set the Initialize and MRS bits (issue continuous NOP commands
* (INIT & MRS set))
*/
ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
str r4, [r3, #SDRAM_OFF_GLCONFIG]
/* Delay for 200us. */
mov r4, #0x3000
delay1:
subs r4, r4, #1
bne delay1
/* Clear the MRS bit to issue a precharge all. */
ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
str r4, [r3, #SDRAM_OFF_GLCONFIG]
/* Temporarily set the refresh timer to 0x10. Make it really low so
* that refresh cycles are generated.
*/
ldr r4, =0x10
str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
/* Delay for at least 80 SDRAM clock cycles. */
mov r4, #80
delay2:
subs r4, r4, #1
bne delay2
/* Set the refresh timer to the fastest required for any device
* that might be used. Set 9.6 ms refresh time.
*/
ldr r4, =0x01e0
str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
/* Select mode register update mode. */
ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
str r4, [r3, #SDRAM_OFF_GLCONFIG]
/* Program the mode register on the SDRAM by performing fake read */
ldr r4, [r2]
/* Select normal operating mode. */
ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
str r4, [r3, #SDRAM_OFF_GLCONFIG]
/* Return to the caller. */
mov pc, lr
/*
* Test to see if the SDRAM has been configured in a usable mode.
*
* Input: r0 - Test address of SDRAM
* Output: r0 - 0 -- Test OK, -1 -- Failed
* Modifies: r0-r5
*/
ep93xx_sdram_test:
/* Load the test patterns to be written to SDRAM. */
ldr r1, =0xf00dface
ldr r2, =0xdeadbeef
ldr r3, =0x08675309
ldr r4, =0xdeafc0ed
/* Store the test patterns to SDRAM. */
stmia r0, {r1-r4}
/* Load the test patterns from SDRAM one at a time and compare them
* to the actual pattern.
*/
ldr r5, [r0]
cmp r5, r1
ldreq r5, [r0, #0x0004]
cmpeq r5, r2
ldreq r5, [r0, #0x0008]
cmpeq r5, r3
ldreq r5, [r0, #0x000c]
cmpeq r5, r4
/* Return -1 if a mismatch was encountered, 0 otherwise. */
mvnne r0, #0xffffffff
moveq r0, #0x00000000
/* Return to the caller. */
mov pc, lr
/*
* Determine the size of the SDRAM. Use data=address for the scan.
*
* Input: r0 - Start SDRAM address
* Return: r0 - Single block size
* r1 - Valid block mask
* r2 - Total block count
* Modifies: r0-r5
*/
ep93xx_sdram_size:
/* Store zero at offset zero. */
str r0, [r0]
/* Start checking for an alias at 1MB into SDRAM. */
ldr r1, =0x00100000
/* Store the offset at the current offset. */
check_block_size:
str r1, [r0, r1]
/* Read back from zero. */
ldr r2, [r0]
/* Stop searching of an alias was found. */
cmp r1, r2
beq found_block_size
/* Advance to the next power of two boundary. */
mov r1, r1, lsl #1
/* Loop back if the size has not reached 256MB. */
cmp r1, #0x10000000
bne check_block_size
/* A full 256MB of memory was found, so return it now. */
ldr r0, =0x10000000
ldr r1, =0x00000000
ldr r2, =0x00000001
mov pc, lr
/* An alias was found. See if the first block is 128MB in size. */
found_block_size:
cmp r1, #0x08000000
/* The first block is 128MB, so there is no further memory. Return it
* now.
*/
ldreq r0, =0x08000000
ldreq r1, =0x00000000
ldreq r2, =0x00000001
moveq pc, lr
/* Save the block size, set the block address bits to zero, and
* initialize the block count to one.
*/
mov r3, r1
ldr r4, =0x00000000
ldr r5, =0x00000001
/* Look for additional blocks of memory by searching for non-aliases. */
find_blocks:
/* Store zero back to address zero. It may be overwritten. */
str r0, [r0]
/* Advance to the next power of two boundary. */
mov r1, r1, lsl #1
/* Store the offset at the current offset. */
str r1, [r0, r1]
/* Read back from zero. */
ldr r2, [r0]
/* See if a non-alias was found. */
cmp r1, r2
/* If a non-alias was found, then or in the block address bit and
* multiply the block count by two (since there are two unique
* blocks, one with this bit zero and one with it one).
*/
orrne r4, r4, r1
movne r5, r5, lsl #1
/* Continue searching if there are more address bits to check. */
cmp r1, #0x08000000
bne find_blocks
/* Return the block size, address mask, and count. */
mov r0, r3
mov r1, r4
mov r2, r5
/* Return to the caller. */
mov pc, lr
.globl lowlevel_init
lowlevel_init:
mov r6, lr
/* Make sure caches are off and invalidated. */
ldr r0, =0x00000000
mcr p15, 0, r0, c1, c0, 0
nop
nop
nop
nop
nop
/* Turn off the green LED and turn on the red LED. If the red LED
* is left on for too long, the external reset circuit described
* by application note AN258 will cause the system to reset.
*/
ldr r1, =EP93XX_LED_DATA
ldr r0, [r1]
bic r0, r0, #EP93XX_LED_GREEN_ON
orr r0, r0, #EP93XX_LED_RED_ON
str r0, [r1]
/* Undo the silly static memory controller programming performed
* by the boot rom.
*/
ldr r0, =SMC_BASE
/* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
ldr r1, =0x0000fbe0
/* Reset EP93XX_OFF_SMCBCR0 */
ldr r2, [r0]
orr r2, r2, r1
str r2, [r0]
ldr r2, [r0, #EP93XX_OFF_SMCBCR1]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR1]
ldr r2, [r0, #EP93XX_OFF_SMCBCR2]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR2]
ldr r2, [r0, #EP93XX_OFF_SMCBCR3]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR3]
ldr r2, [r0, #EP93XX_OFF_SMCBCR6]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR6]
ldr r2, [r0, #EP93XX_OFF_SMCBCR7]
orr r2, r2, r1
str r2, [r0, #EP93XX_OFF_SMCBCR7]
/* Set the PLL1 and processor clock. */
ldr r0, =SYSCON_BASE
#ifdef CONFIG_EDB9301
/* 332MHz, giving a 166MHz processor clock. */
ldr r1, = 0x02b49907
#else
#ifdef CONFIG_EDB93XX_INDUSTRIAL
/* 384MHz, giving a 196MHz processor clock. */
ldr r1, =0x02a4bb38
#else
/* 400MHz, giving a 200MHz processor clock. */
ldr r1, =0x02a4e39e
#endif
#endif
str r1, [r0, #SYSCON_OFF_CLKSET1]
nop
nop
nop
nop
nop
/* Need to make sure that SDRAM is configured correctly before
* coping the code into it.
*/
#ifdef CONFIG_EDB93XX_SDCS0
mov r11, #SDRAM_DEVCFG0_BASE
#endif
#ifdef CONFIG_EDB93XX_SDCS1
mov r11, #SDRAM_DEVCFG1_BASE
#endif
#ifdef CONFIG_EDB93XX_SDCS2
mov r11, #SDRAM_DEVCFG2_BASE
#endif
#ifdef CONFIG_EDB93XX_SDCS3
ldr r0, =SYSCON_BASE
ldr r0, [r0, #SYSCON_OFF_SYSCFG]
ands r0, r0, #SYSCON_SYSCFG_LASDO
moveq r11, #SDRAM_DEVCFG3_ASD0_BASE
movne r11, #SDRAM_DEVCFG3_ASD1_BASE
#endif
/* See Table 13-5 in EP93xx datasheet for more info about DRAM
* register mapping */
/* Try a 32-bit wide configuration of SDRAM. */
ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
/* Set burst count: 4 and CAS: 2
* Burst mode [A11:A10]; CAS [A16:A14]
*/
orr r2, r11, #0x00008800
bl ep93xx_sdram_config
/* Test the SDRAM. */
mov r0, r11
bl ep93xx_sdram_test
cmp r0, #0x00000000
beq ep93xx_sdram_done
/* Try a 16-bit wide configuration of SDRAM. */
ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
/* Set burst count: 8, CAS: 2, sequential burst
* Accoring to Table 13-3 for 16bit operations mapping must be shifted.
* Burst mode [A10:A9]; CAS [A15:A13]
*/
orr r2, r11, #0x00004600
bl ep93xx_sdram_config
/* Test the SDRAM. */
mov r0, r11
bl ep93xx_sdram_test
cmp r0, #0x00000000
beq ep93xx_sdram_done
/* Turn off the red LED. */
ldr r0, =EP93XX_LED_DATA
ldr r1, [r0]
bic r1, r1, #EP93XX_LED_RED_ON
str r1, [r0]
/* There is no SDRAM so flash the green LED. */
flash_green:
orr r1, r1, #EP93XX_LED_GREEN_ON
str r1, [r0]
ldr r2, =0x00010000
flash_green_delay_1:
subs r2, r2, #1
bne flash_green_delay_1
bic r1, r1, #EP93XX_LED_GREEN_ON
str r1, [r0]
ldr r2, =0x00010000
flash_green_delay_2:
subs r2, r2, #1
bne flash_green_delay_2
orr r1, r1, #EP93XX_LED_GREEN_ON
str r1, [r0]
ldr r2, =0x00010000
flash_green_delay_3:
subs r2, r2, #1
bne flash_green_delay_3
bic r1, r1, #EP93XX_LED_GREEN_ON
str r1, [r0]
ldr r2, =0x00050000
flash_green_delay_4:
subs r2, r2, #1
bne flash_green_delay_4
b flash_green
ep93xx_sdram_done:
ldr r1, =EP93XX_LED_DATA
ldr r0, [r1]
bic r0, r0, #EP93XX_LED_RED_ON
str r0, [r1]
/* Determine the size of the SDRAM. */
mov r0, r11
bl ep93xx_sdram_size
/* Save the SDRAM characteristics. */
mov r8, r0
mov r9, r1
mov r10, r2
/* Compute total memory size into r1 */
mul r1, r8, r10
#ifdef CONFIG_EDB93XX_SDCS0
ldr r2, [r0, #SDRAM_OFF_DEVCFG0]
#endif
#ifdef CONFIG_EDB93XX_SDCS1
ldr r2, [r0, #SDRAM_OFF_DEVCFG1]
#endif
#ifdef CONFIG_EDB93XX_SDCS2
ldr r2, [r0, #SDRAM_OFF_DEVCFG2]
#endif
#ifdef CONFIG_EDB93XX_SDCS3
ldr r2, [r0, #SDRAM_OFF_DEVCFG3]
#endif
/* Consider small DRAM size as:
* < 32Mb for 32bit bus
* < 64Mb for 16bit bus
*/
tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
moveq r1, r1, lsr #1
cmp r1, #0x02000000
#if defined(CONFIG_EDB9301)
/* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
movlt r1, #0x03f0
movge r1, #0x01e0
#else
/* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
movlt r1, #0x0600
movge r1, #0x2f0
#endif
str r1, [r0, #SDRAM_OFF_REFRSHTIMR]
/* Save the memory configuration information. */
orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
stmia r0, {r8-r11}
mov lr, r6
mov pc, lr

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arch/arm/cpu/arm920t/ep93xx/speed.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Cirrus Logic EP93xx PLL support.
*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
*/
#include <common.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
#include <div64.h>
/*
* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
*
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
*/
/*
* return the PLL output frequency
*
* PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
* / (X2IPD + 1) / 2^PS
*/
static ulong get_PLLCLK(uint32_t *pllreg)
{
uint8_t i;
const uint32_t clkset = readl(pllreg);
uint64_t rate = CONFIG_SYS_CLK_FREQ;
rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
rate >>= 1;
return (ulong)rate;
}
/* return FCLK frequency */
ulong get_FCLK(void)
{
const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
const uint32_t clkset1 = readl(&syscon->clkset1);
const uint8_t fclk_div =
fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
return fclk_rate;
}
/* return HCLK frequency */
ulong get_HCLK(void)
{
const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
const uint32_t clkset1 = readl(&syscon->clkset1);
const uint8_t hclk_div =
hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
return hclk_rate;
}
/* return PCLK frequency */
ulong get_PCLK(void)
{
const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
const uint32_t clkset1 = readl(&syscon->clkset1);
const uint8_t pclk_div =
pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
const ulong pclk_rate = get_HCLK() / pclk_div;
return pclk_rate;
}
/* return UCLK frequency */
ulong get_UCLK(void)
{
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
ulong uclk_rate;
const uint32_t value = readl(&syscon->pwrcnt);
if (value & SYSCON_PWRCNT_UART_BAUD)
uclk_rate = CONFIG_SYS_CLK_FREQ;
else
uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
return uclk_rate;
}

117
arch/arm/cpu/arm920t/ep93xx/timer.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Cirrus Logic EP93xx timer support.
*
* Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2004, 2005
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
*
* Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
* author unknown.
*/
#include <common.h>
#include <init.h>
#include <time.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
#include <div64.h>
#define TIMER_CLKSEL (1 << 3)
#define TIMER_ENABLE (1 << 7)
#define TIMER_FREQ 508469 /* ticks / second */
#define TIMER_MAX_VAL 0xFFFFFFFF
static struct ep93xx_timer
{
unsigned long long ticks;
unsigned long last_read;
} timer;
static inline unsigned long long usecs_to_ticks(unsigned long usecs)
{
unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
do_div(ticks, 1000 * 1000);
return ticks;
}
static inline void read_timer(void)
{
struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
if (now >= timer.last_read)
timer.ticks += now - timer.last_read;
else
/* an overflow occurred */
timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
timer.last_read = now;
}
/*
* Get the number of ticks (in CONFIG_SYS_HZ resolution)
*/
unsigned long long get_ticks(void)
{
unsigned long long sys_ticks;
read_timer();
sys_ticks = timer.ticks * CONFIG_SYS_HZ;
do_div(sys_ticks, TIMER_FREQ);
return sys_ticks;
}
unsigned long get_timer(unsigned long base)
{
return get_ticks() - base;
}
void __udelay(unsigned long usec)
{
unsigned long long target;
read_timer();
target = timer.ticks + usecs_to_ticks(usec);
while (timer.ticks < target)
read_timer();
}
int timer_init(void)
{
struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
/* use timer 3 with 508KHz and free running, not enabled now */
writel(TIMER_CLKSEL, &timer_regs->timer3.control);
/* set initial timer value */
writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
/* Enable the timer */
writel(TIMER_ENABLE | TIMER_CLKSEL,
&timer_regs->timer3.control);
/* Reset the timer */
read_timer();
timer.ticks = 0;
return 0;
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
unsigned long get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

8
arch/arm/cpu/arm920t/imx/Makefile
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# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += generic.o
obj-y += speed.o
obj-y += timer.o

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arch/arm/cpu/arm920t/imx/generic.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* arch/arm/mach-imx/generic.c
*
* author: Sascha Hauer
* Created: april 20th, 2004
* Copyright: Synertronixx GmbH
*
* Common code for i.MX machines
*/
#include <common.h>
#ifdef CONFIG_IMX
#include <asm/arch/imx-regs.h>
void imx_gpio_mode(int gpio_mode)
{
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10;
unsigned int tmp;
/* Pullup enable */
if(gpio_mode & GPIO_PUEN)
PUEN(port) |= (1<<pin);
else
PUEN(port) &= ~(1<<pin);
/* Data direction */
if(gpio_mode & GPIO_OUT)
DDIR(port) |= 1<<pin;
else
DDIR(port) &= ~(1<<pin);
/* Primary / alternate function */
if(gpio_mode & GPIO_AF)
GPR(port) |= (1<<pin);
else
GPR(port) &= ~(1<<pin);
/* use as gpio? */
if( ocr == 3 )
GIUS(port) |= (1<<pin);
else
GIUS(port) &= ~(1<<pin);
/* Output / input configuration */
/* FIXME: I'm not very sure about OCR and ICONF, someone
* should have a look over it
*/
if(pin<16) {
tmp = OCR1(port);
tmp &= ~( 3<<(pin*2));
tmp |= (ocr << (pin*2));
OCR1(port) = tmp;
if( gpio_mode & GPIO_AOUT )
ICONFA1(port) &= ~( 3<<(pin*2));
if( gpio_mode & GPIO_BOUT )
ICONFB1(port) &= ~( 3<<(pin*2));
} else {
tmp = OCR2(port);
tmp &= ~( 3<<((pin-16)*2));
tmp |= (ocr << ((pin-16)*2));
OCR2(port) = tmp;
if( gpio_mode & GPIO_AOUT )
ICONFA2(port) &= ~( 3<<((pin-16)*2));
if( gpio_mode & GPIO_BOUT )
ICONFB2(port) &= ~( 3<<((pin-16)*2));
}
}
#endif /* CONFIG_IMX */

85
arch/arm/cpu/arm920t/imx/speed.c
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// SPDX-License-Identifier: GPL-2.0+
/*
*
* (c) 2004 Sascha Hauer <sascha@saschahauer.de>
*/
#include <common.h>
#if defined (CONFIG_IMX)
#include <asm/arch/imx-regs.h>
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
* SH FIXME: 16780000 in our case
* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
* the specified bus in HZ.
*/
/* ------------------------------------------------------------------------- */
ulong get_systemPLLCLK(void)
{
/* FIXME: We assume System_SEL = 0 here */
u32 spctl0 = SPCTL0;
u32 mfi = (spctl0 >> 10) & 0xf;
u32 mfn = spctl0 & 0x3f;
u32 mfd = (spctl0 >> 16) & 0x3f;
u32 pd = (spctl0 >> 26) & 0xf;
mfi = mfi<=5 ? 5 : mfi;
return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
}
ulong get_mcuPLLCLK(void)
{
/* FIXME: We assume System_SEL = 0 here */
u32 mpctl0 = MPCTL0;
u32 mfi = (mpctl0 >> 10) & 0xf;
u32 mfn = mpctl0 & 0x3f;
u32 mfd = (mpctl0 >> 16) & 0x3f;
u32 pd = (mpctl0 >> 26) & 0xf;
mfi = mfi<=5 ? 5 : mfi;
return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
}
ulong get_FCLK(void)
{
return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
}
/* return HCLK frequency */
ulong get_HCLK(void)
{
u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
printf("bclkdiv: %d\n", bclkdiv);
return get_systemPLLCLK() / bclkdiv;
}
/* return BCLK frequency */
ulong get_BCLK(void)
{
return get_HCLK();
}
ulong get_PERCLK1(void)
{
return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
}
ulong get_PERCLK2(void)
{
return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
}
ulong get_PERCLK3(void)
{
return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
}
#endif /* defined (CONFIG_IMX) */

100
arch/arm/cpu/arm920t/imx/timer.c
View File

@ -1,100 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*/
#include <common.h>
#include <cpu_func.h>
#include <time.h>
#if defined (CONFIG_IMX)
#include <asm/arch/imx-regs.h>
#include <linux/delay.h>
int timer_init (void)
{
int i;
/* setup GP Timer 1 */
TCTL1 = TCTL_SWR;
for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
/* Reset the timer */
TCTL1 &= ~TCTL_TEN;
TCTL1 |= TCTL_TEN; /* Enable timer */
return (0);
}
/*
* timer without interrupts
*/
static ulong get_timer_masked (void)
{
return TCN1;
}
ulong get_timer (ulong base)
{
return get_timer_masked() - base;
}
void __udelay(unsigned long usec)
{
ulong endtime = get_timer_masked() + usec;
signed long diff;
do {
ulong now = get_timer_masked ();
diff = endtime - now;
} while (diff >= 0);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}
/*
* Reset the cpu by setting up the watchdog timer and let him time out
*/
void reset_cpu(void)
{
/* Disable watchdog and set Time-Out field to 0 */
WCR = 0x00000000;
/* Write Service Sequence */
WSR = 0x00005555;
WSR = 0x0000AAAA;
/* Enable watchdog */
WCR = 0x00000001;
while (1);
/*NOTREACHED*/
}
#endif /* defined (CONFIG_IMX) */

22
arch/arm/cpu/arm920t/start.S
View File

@ -35,25 +35,11 @@ reset:
orr r0, r0, #0xd3
msr cpsr, r0
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
/*
* relocate exception table
*/
ldr r0, =_start
ldr r1, =0x0
mov r2, #16
copyex:
subs r2, r2, #1
ldr r3, [r0], #4
str r3, [r1], #4
bne copyex
#endif
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -78,7 +64,7 @@ c_runtime_cpu_setup:
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
@ -97,7 +83,7 @@ cpu_init_crit:
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
@ -109,4 +95,4 @@ cpu_init_crit:
mov lr, ip
#endif
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

5
arch/arm/cpu/arm926ejs/Makefile
View File

@ -12,11 +12,8 @@ extra-y :=
endif
endif
obj-$(CONFIG_ARMADA100) += armada100/
obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
# some files can only build in ARM or THUMB2, not THUMB1

7
arch/arm/cpu/arm926ejs/armada100/Makefile
View File

@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2010
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
obj-y = cpu.o timer.o dram.o

93
arch/arm/cpu/arm926ejs/armada100/cpu.c
View File

@ -1,93 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/arch/cpu.h>
#include <asm/arch/armada100.h>
#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
#define SET_MRVL_ID (1<<8)
#define L2C_RAM_SEL (1<<4)
int arch_cpu_init(void)
{
u32 val;
struct armd1cpu_registers *cpuregs =
(struct armd1cpu_registers *) ARMD1_CPU_BASE;
struct armd1apb1_registers *apb1clkres =
(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
struct armd1mpmu_registers *mpmu =
(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
val = readl(&cpuregs->cpu_conf);
val = val | SET_MRVL_ID;
writel(val, &cpuregs->cpu_conf);
/* Enable Clocks for all hardware units */
writel(0xFFFFFFFF, &mpmu->acgr);
/* Turn on AIB and AIB-APB Functional clock */
writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
/* ensure L2 cache is not mapped as SRAM */
val = readl(&cpuregs->cpu_conf);
val = val & ~(L2C_RAM_SEL);
writel(val, &cpuregs->cpu_conf);
/* Enable GPIO clock */
writel(APBC_APBCLK, &apb1clkres->gpio);
#ifdef CONFIG_I2C_MV
/* Enable general I2C clock */
writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
/* Enable power I2C clock */
writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
#endif
/*
* Enable Functional and APB clock at 14.7456MHz
* for configured UART console
*/
#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
writel(UARTCLK14745KHZ, &apb1clkres->uart3);
#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
writel(UARTCLK14745KHZ, &apb1clkres->uart2);
#else
writel(UARTCLK14745KHZ, &apb1clkres->uart1);
#endif
icache_enable();
return 0;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u32 id;
struct armd1cpu_registers *cpuregs =
(struct armd1cpu_registers *) ARMD1_CPU_BASE;
id = readl(&cpuregs->chip_id);
printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
return 0;
}
#endif
#ifdef CONFIG_I2C_MV
void i2c_clk_enable(void)
{
}
#endif

117
arch/arm/cpu/arm926ejs/armada100/dram.c
View File

@ -1,117 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
* Contributor: Mahavir Jain <mjain@marvell.com>
*/
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/armada100.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* ARMADA100 DRAM controller supports upto 8 banks
* for chip select 0 and 1
*/
/*
* DDR Memory Control Registers
* Refer Datasheet Appendix A.17
*/
struct armd1ddr_map_registers {
u32 cs; /* Memory Address Map Register -CS */
u32 pad[3];
};
struct armd1ddr_registers {
u8 pad[0x100 - 0x000];
struct armd1ddr_map_registers mmap[2];
};
/*
* armd1_sdram_base - reads SDRAM Base Address Register
*/
u32 armd1_sdram_base(int chip_sel)
{
struct armd1ddr_registers *ddr_regs =
(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
u32 result = 0;
u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
if (!CS_valid)
return 0;
result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
return result;
}
/*
* armd1_sdram_size - reads SDRAM size
*/
u32 armd1_sdram_size(int chip_sel)
{
struct armd1ddr_registers *ddr_regs =
(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
u32 result = 0;
u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
if (!CS_valid)
return 0;
result = readl(&ddr_regs->mmap[chip_sel].cs);
result = (result >> 16) & 0xF;
if (result < 0x7) {
printf("Unknown DRAM Size\n");
return -1;
} else {
return ((0x8 << (result - 0x7)) * 1024 * 1024);
}
}
int dram_init(void)
{
int i;
gd->ram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = armd1_sdram_base(i);
gd->bd->bi_dram[i].size = armd1_sdram_size(i);
/*
* It is assumed that all memory banks are consecutive
* and without gaps.
* If the gap is found, ram_size will be reported for
* consecutive memory only
*/
if (gd->bd->bi_dram[i].start != gd->ram_size)
break;
gd->ram_size += gd->bd->bi_dram[i].size;
}
for (; i < CONFIG_NR_DRAM_BANKS; i++) {
/* If above loop terminated prematurely, we need to set
* remaining banks' start address & size as 0. Otherwise other
* u-boot functions and Linux kernel gets wrong values which
* could result in crash */
gd->bd->bi_dram[i].start = 0;
gd->bd->bi_dram[i].size = 0;
}
return 0;
}
/*
* If this function is not defined here,
* board.c alters dram bank zero configuration defined above.
*/
int dram_init_banksize(void)
{
dram_init();
return 0;
}

198
arch/arm/cpu/arm926ejs/armada100/timer.c
View File

@ -1,198 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <time.h>
#include <asm/arch/cpu.h>
#include <asm/arch/armada100.h>
#include <asm/global_data.h>
#include <linux/delay.h>
/*
* Timer registers
* Refer Section A.6 in Datasheet
*/
struct armd1tmr_registers {
u32 clk_ctrl; /* Timer clk control reg */
u32 match[9]; /* Timer match registers */
u32 count[3]; /* Timer count registers */
u32 status[3];
u32 ie[3];
u32 preload[3]; /* Timer preload value */
u32 preload_ctrl[3];
u32 wdt_match_en;
u32 wdt_match_r;
u32 wdt_val;
u32 wdt_sts;
u32 icr[3];
u32 wdt_icr;
u32 cer; /* Timer count enable reg */
u32 cmr;
u32 ilr[3];
u32 wcr;
u32 wfar;
u32 wsar;
u32 cvwr;
};
#define TIMER 0 /* Use TIMER 0 */
/* Each timer has 3 match registers */
#define MATCH_CMP(x) ((3 * TIMER) + x)
#define TIMER_LOAD_VAL 0xffffffff
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
/* For preventing risk of instability in reading counter value,
* first set read request to register cvwr and then read same
* register after it captures counter value.
*/
ulong read_timer(void)
{
struct armd1tmr_registers *armd1timers =
(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
volatile int loop=100;
writel(COUNT_RD_REQ, &armd1timers->cvwr);
while (loop--);
return(readl(&armd1timers->cvwr));
}
static ulong get_timer_masked(void)
{
ulong now = read_timer();
if (now >= gd->arch.tbl) {
/* normal mode */
gd->arch.tbu += now - gd->arch.tbl;
} else {
/* we have an overflow ... */
gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
}
gd->arch.tbl = now;
return gd->arch.tbu;
}
ulong get_timer(ulong base)
{
return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
base);
}
void __udelay(unsigned long usec)
{
ulong delayticks;
ulong endtime;
delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
endtime = get_timer_masked() + delayticks;
while (get_timer_masked() < endtime);
}
/*
* init the Timer
*/
int timer_init(void)
{
struct armd1apb1_registers *apb1clkres =
(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
struct armd1tmr_registers *armd1timers =
(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
/* Enable Timer clock at 3.25 MHZ */
writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
/* load value into timer */
writel(0x0, &armd1timers->clk_ctrl);
/* Use Timer 0 Match Resiger 0 */
writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
/* Preload value is 0 */
writel(0x0, &armd1timers->preload[TIMER]);
/* Enable match comparator 0 for Timer 0 */
writel(0x1, &armd1timers->preload_ctrl[TIMER]);
/* Enable timer 0 */
writel(0x1, &armd1timers->cer);
/* init the gd->arch.tbu and gd->arch.tbl value */
gd->arch.tbl = read_timer();
gd->arch.tbu = 0;
return 0;
}
#define MPMU_APRR_WDTR (1<<4)
#define TMR_WFAR 0xbaba /* WDT Register First key */
#define TMP_WSAR 0xeb10 /* WDT Register Second key */
/*
* This function uses internal Watchdog Timer
* based reset mechanism.
* Steps to write watchdog registers (protected access)
* 1. Write key value to TMR_WFAR reg.
* 2. Write key value to TMP_WSAR reg.
* 3. Perform write operation.
*/
void reset_cpu(void)
{
struct armd1mpmu_registers *mpmu =
(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
struct armd1tmr_registers *armd1timers =
(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
u32 val;
/* negate hardware reset to the WDT after system reset */
val = readl(&mpmu->aprr);
val = val | MPMU_APRR_WDTR;
writel(val, &mpmu->aprr);
/* reset/enable WDT clock */
writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
readl(&mpmu->wdtpcr);
writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
readl(&mpmu->wdtpcr);
/* clear previous WDT status */
writel(TMR_WFAR, &armd1timers->wfar);
writel(TMP_WSAR, &armd1timers->wsar);
writel(0, &armd1timers->wdt_sts);
/* set match counter */
writel(TMR_WFAR, &armd1timers->wfar);
writel(TMP_WSAR, &armd1timers->wsar);
writel(0xf, &armd1timers->wdt_match_r);
/* enable WDT reset */
writel(TMR_WFAR, &armd1timers->wfar);
writel(TMP_WSAR, &armd1timers->wsar);
writel(0x3, &armd1timers->wdt_match_en);
while(1);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return (ulong)CONFIG_SYS_HZ;
}

1
arch/arm/cpu/arm926ejs/cache.c
View File

@ -89,4 +89,3 @@ void enable_caches(void)
dcache_enable();
#endif
}

13
arch/arm/cpu/arm926ejs/cpu.c
View File

@ -21,6 +21,19 @@
static void cache_flush(void);
/************************************************************
* sdelay() - simple spin loop. Will be constant time as
* its generally used in bypass conditions only. This
* is necessary until timers are accessible.
*
* not inline to increase chances its in cache when called
*************************************************************/
void sdelay(unsigned long loops)
{
__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0"(loops));
}
int cleanup_before_linux (void)
{
/*

7
arch/arm/cpu/arm926ejs/mx25/Makefile
View File

@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
obj-y += generic.o timer.o reset.o relocate.o

274
arch/arm/cpu/arm926ejs/mx25/generic.c
View File

@ -1,274 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Based on mx27/generic.c:
* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
*/
#include <common.h>
#include <clock_legacy.h>
#include <div64.h>
#include <init.h>
#include <net.h>
#include <netdev.h>
#include <vsprintf.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#ifdef CONFIG_FSL_ESDHC_IMX
#include <fsl_esdhc_imx.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
/*
* get the system pll clock in Hz
*
* mfi + mfn / (mfd +1)
* f = 2 * f_ref * --------------------
* pd + 1
*/
static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
{
unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
& CCM_PLL_MFI_MASK;
int mfn = (pll >> CCM_PLL_MFN_SHIFT)
& CCM_PLL_MFN_MASK;
unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
& CCM_PLL_MFD_MASK;
unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
& CCM_PLL_PD_MASK;
mfi = mfi <= 5 ? 5 : mfi;
mfn = mfn >= 512 ? mfn - 1024 : mfn;
mfd += 1;
pd += 1;
return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
mfd * pd);
}
static ulong imx_get_mpllclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = MXC_HCLK;
return imx_decode_pll(readl(&ccm->mpctl), fref);
}
static ulong imx_get_upllclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = MXC_HCLK;
return imx_decode_pll(readl(&ccm->upctl), fref);
}
static ulong imx_get_armclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl(&ccm->cctl);
ulong fref = imx_get_mpllclk();
ulong div;
if (cctl & CCM_CCTL_ARM_SRC)
fref = lldiv((u64) fref * 3, 4);
div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
& CCM_CCTL_ARM_DIV_MASK) + 1;
return fref / div;
}
static ulong imx_get_ahbclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl(&ccm->cctl);
ulong fref = imx_get_armclk();
ulong div;
div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
& CCM_CCTL_AHB_DIV_MASK) + 1;
return fref / div;
}
static ulong imx_get_ipgclk(void)
{
return imx_get_ahbclk() / 2;
}
static ulong imx_get_perclk(int clk)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
imx_get_ahbclk();
ulong div;
div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
return fref / div;
}
int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
ulong div = (fref + freq - 1) / freq;
if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
return -EINVAL;
clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
div << CCM_PERCLK_SHIFT(clk));
if (from_upll)
setbits_le32(&ccm->mcr, 1 << clk);
else
clrbits_le32(&ccm->mcr, 1 << clk);
return 0;
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
if (clk >= MXC_CLK_NUM)
return -1;
switch (clk) {
case MXC_ARM_CLK:
return imx_get_armclk();
case MXC_AHB_CLK:
return imx_get_ahbclk();
case MXC_IPG_CLK:
case MXC_CSPI_CLK:
case MXC_FEC_CLK:
return imx_get_ipgclk();
default:
return imx_get_perclk(clk);
}
}
u32 get_cpu_rev(void)
{
u32 srev;
u32 system_rev = 0x25000;
/* read SREV register from IIM module */
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
srev = readl(&iim->iim_srev);
switch (srev) {
case 0x00:
system_rev |= CHIP_REV_1_0;
break;
case 0x01:
system_rev |= CHIP_REV_1_1;
break;
case 0x02:
system_rev |= CHIP_REV_1_2;
break;
default:
system_rev |= 0x8000;
break;
}
return system_rev;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
static char *get_reset_cause(void)
{
/* read RCSR register from CCM module */
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 cause = readl(&ccm->rcsr) & 0x0f;
if (cause == 0)
return "POR";
else if (cause == 1)
return "RST";
else if ((cause & 2) == 2)
return "WDOG";
else if ((cause & 4) == 4)
return "SW RESET";
else if ((cause & 8) == 8)
return "JTAG";
else
return "unknown reset";
}
int print_cpuinfo(void)
{
char buf[32];
u32 cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
((cpurev & 0x8000) ? " unknown" : ""),
strmhz(buf, imx_get_armclk()));
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
#if defined(CONFIG_FEC_MXC)
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(struct bd_info *bis)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong val;
val = readl(&ccm->cgr0);
val |= (1 << 23);
writel(val, &ccm->cgr0);
return fecmxc_initialize(bis);
}
#endif
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
#endif
#endif
return 0;
}
#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
{
return fsl_esdhc_mmc_init(bis);
}
#endif
#ifdef CONFIG_FEC_MXC
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
struct fuse_bank *bank = &iim->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
for (i = 0; i < 6; i++)
mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
}
#endif /* CONFIG_FEC_MXC */

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arch/arm/cpu/arm926ejs/mx25/relocate.S
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX25-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <linux/linkage.h>
/*
* The i.MX25 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM, so let's avoid relocating the vectors.
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
bx lr
ENDPROC(relocate_vectors)

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arch/arm/cpu/arm926ejs/mx25/reset.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu(void)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
writew(0, &regs->wcr);
/* Write Service Sequence */
writew(WSR_UNLOCK1, &regs->wsr);
writew(WSR_UNLOCK2, &regs->wsr);
/* Enable watchdog */
writew(WCR_WDE, &regs->wcr);
while (1) ;
}

50
arch/arm/cpu/arm926ejs/mx25/timer.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
* Add support for MX25
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/ptrace.h>
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32KHz 32-bit timer overruns in 134217 seconds */
int timer_init(void)
{
int i;
struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
/* setup GP Timer 1 */
writel(GPT_CTRL_SWR, &gpt->ctrl);
writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
for (i = 0; i < 100; i++)
writel(0, &gpt->ctrl); /* We have no udelay by now */
writel(0, &gpt->pre); /* prescaler = 1 */
/* Freerun Mode, 32KHz input */
writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
&gpt->ctrl);
writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
return 0;
}

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arch/arm/cpu/arm926ejs/mx27/Makefile
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# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
obj-y += generic.o timer.o reset.o relocate.o

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arch/arm/cpu/arm926ejs/mx27/generic.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
*/
#include <common.h>
#include <div64.h>
#include <net.h>
#include <netdev.h>
#include <vsprintf.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/mach-imx/sys_proto.h>
#ifdef CONFIG_MMC_MXC
#include <asm/arch/mxcmmc.h>
#endif
/*
* get the system pll clock in Hz
*
* mfi + mfn / (mfd +1)
* f = 2 * f_ref * --------------------
* pd + 1
*/
static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
{
unsigned int mfi = (pll >> 10) & 0xf;
unsigned int mfn = pll & 0x3ff;
unsigned int mfd = (pll >> 16) & 0x3ff;
unsigned int pd = (pll >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
(mfd + 1) * (pd + 1));
}
static ulong clk_in_32k(void)
{
return 1024 * CONFIG_MX27_CLK32;
}
static ulong clk_in_26m(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
/* divide by 1.5 */
return 26000000 * 2 / 3;
} else {
return 26000000;
}
}
static ulong imx_get_mpllclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref;
if (cscr & CSCR_MCU_SEL)
fref = clk_in_26m();
else
fref = clk_in_32k();
return imx_decode_pll(readl(&pll->mpctl0), fref);
}
static ulong imx_get_armclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref = imx_get_mpllclk();
ulong div;
if (!(cscr & CSCR_ARM_SRC_MPLL))
fref = lldiv((fref * 2), 3);
div = ((cscr >> 12) & 0x3) + 1;
return lldiv(fref, div);
}
static ulong imx_get_ahbclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref = imx_get_mpllclk();
ulong div;
div = ((cscr >> 8) & 0x3) + 1;
return lldiv(fref * 2, 3 * div);
}
static __attribute__((unused)) ulong imx_get_spllclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref;
if (cscr & CSCR_SP_SEL)
fref = clk_in_26m();
else
fref = clk_in_32k();
return imx_decode_pll(readl(&pll->spctl0), fref);
}
static ulong imx_decode_perclk(ulong div)
{
return lldiv((imx_get_mpllclk() * 2), (div * 3));
}
static ulong imx_get_perclk1(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
}
static ulong imx_get_perclk2(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
}
static __attribute__((unused)) ulong imx_get_perclk3(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
}
static __attribute__((unused)) ulong imx_get_perclk4(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return imx_get_armclk();
case MXC_I2C_CLK:
return imx_get_ahbclk()/2;
case MXC_UART_CLK:
return imx_get_perclk1();
case MXC_FEC_CLK:
return imx_get_ahbclk();
case MXC_ESDHC_CLK:
return imx_get_perclk2();
}
return -1;
}
u32 get_cpu_rev(void)
{
return MXC_CPU_MX27 << 12;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
char buf[32];
printf("CPU: Freescale i.MX27 at %s MHz\n\n",
strmhz(buf, imx_get_mpllclk()));
return 0;
}
#endif
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_FEC_MXC)
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
/* enable FEC clock */
writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
return fecmxc_initialize(bis);
#else
return 0;
#endif
}
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
{
#ifdef CONFIG_MMC_MXC
return mxc_mmc_init(bis);
#else
return 0;
#endif
}
void imx_gpio_mode(int gpio_mode)
{
struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
unsigned int tmp;
/* Pullup enable */
if (gpio_mode & GPIO_PUEN) {
writel(readl(&regs->port[port].puen) | (1 << pin),
&regs->port[port].puen);
} else {
writel(readl(&regs->port[port].puen) & ~(1 << pin),
&regs->port[port].puen);
}
/* Data direction */
if (gpio_mode & GPIO_OUT) {
writel(readl(&regs->port[port].gpio_dir) | 1 << pin,
&regs->port[port].gpio_dir);
} else {
writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin),
&regs->port[port].gpio_dir);
}
/* Primary / alternate function */
if (gpio_mode & GPIO_AF) {
writel(readl(&regs->port[port].gpr) | (1 << pin),
&regs->port[port].gpr);
} else {
writel(readl(&regs->port[port].gpr) & ~(1 << pin),
&regs->port[port].gpr);
}
/* use as gpio? */
if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
writel(readl(&regs->port[port].gius) | (1 << pin),
&regs->port[port].gius);
} else {
writel(readl(&regs->port[port].gius) & ~(1 << pin),
&regs->port[port].gius);
}
/* Output / input configuration */
if (pin < 16) {
tmp = readl(&regs->port[port].ocr1);
tmp &= ~(3 << (pin * 2));
tmp |= (ocr << (pin * 2));
writel(tmp, &regs->port[port].ocr1);
writel(readl(&regs->port[port].iconfa1) & ~(3 << (pin * 2)),
&regs->port[port].iconfa1);
writel(readl(&regs->port[port].iconfa1) | aout << (pin * 2),
&regs->port[port].iconfa1);
writel(readl(&regs->port[port].iconfb1) & ~(3 << (pin * 2)),
&regs->port[port].iconfb1);
writel(readl(&regs->port[port].iconfb1) | bout << (pin * 2),
&regs->port[port].iconfb1);
} else {
pin -= 16;
tmp = readl(&regs->port[port].ocr2);
tmp &= ~(3 << (pin * 2));
tmp |= (ocr << (pin * 2));
writel(tmp, &regs->port[port].ocr2);
writel(readl(&regs->port[port].iconfa2) & ~(3 << (pin * 2)),
&regs->port[port].iconfa2);
writel(readl(&regs->port[port].iconfa2) | aout << (pin * 2),
&regs->port[port].iconfa2);
writel(readl(&regs->port[port].iconfb2) & ~(3 << (pin * 2)),
&regs->port[port].iconfb2);
writel(readl(&regs->port[port].iconfb2) | bout << (pin * 2),
&regs->port[port].iconfb2);
}
}
#ifdef CONFIG_MXC_UART
void mx27_uart1_init_pins(void)
{
int i;
unsigned int mode[] = {
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
#endif /* CONFIG_MXC_UART */
#ifdef CONFIG_FEC_MXC
void mx27_fec_init_pins(void)
{
int i;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_CLR,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
struct fuse_bank *bank = &iim->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
for (i = 0; i < 6; i++)
mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
}
#endif /* CONFIG_FEC_MXC */
#ifdef CONFIG_MMC_MXC
void mx27_sd1_init_pins(void)
{
int i;
unsigned int mode[] = {
PE18_PF_SD1_D0,
PE19_PF_SD1_D1,
PE20_PF_SD1_D2,
PE21_PF_SD1_D3,
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
void mx27_sd2_init_pins(void)
{
int i;
unsigned int mode[] = {
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
#endif /* CONFIG_MMC_MXC */

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arch/arm/cpu/arm926ejs/mx27/relocate.S
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX27-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
/*
* The i.MX27 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM. Therefore, vectors cannot be changed at all.
*
* However, these ROM-based vectors actually just perform indirect
* calls through pointers located in RAM at SoC-specific addresses,
* as follows:
*
* Offset Exception Use by ROM code
* 0x00000000 reset indirect branch to [0x00000014]
* 0x00000004 undefined instruction indirect branch to [0xfffffef0]
* 0x00000008 software interrupt indirect branch to [0xfffffef4]
* 0x0000000c prefetch abort indirect branch to [0xfffffef8]
* 0x00000010 data abort indirect branch to [0xfffffefc]
* 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000
* 0x00000018 IRQ indirect branch to [0xffffff00]
* 0x0000001c FIQ indirect branch to [0xffffff04]
*
* In order to initialize exceptions on i.MX27, we must copy U-Boot's
* indirect (not exception!) vector table into 0xfffffef0..0xffffff04
* taking care not to copy vectors number 5 (reserved exception).
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
ldr r1, =32 /* size of vector table */
add r0, r0, r1 /* skip to indirect table */
ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */
ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */
stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */
bx lr
ENDPROC(relocate_vectors)

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arch/arm/cpu/arm926ejs/mx27/reset.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu(void)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
writew(0x0000, &regs->wcr);
/* Write Service Sequence */
writew(0x5555, &regs->wsr);
writew(0xAAAA, &regs->wsr);
/* Enable watchdog */
writew(WCR_WDE, &regs->wcr);
while (1);
/*NOTREACHED*/
}

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arch/arm/cpu/arm926ejs/mx27/timer.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*/
#include <common.h>
#include <div64.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/ptrace.h>
#include <linux/delay.h>
/* General purpose timers bitfields */
#define GPTCR_SWR (1 << 15) /* Software reset */
#define GPTCR_FRR (1 << 8) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
DECLARE_GLOBAL_DATA_PTR;
#define timestamp (gd->arch.tbl)
#define lastinc (gd->arch.lastinc)
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
* "tick" is internal timer period
*/
#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, CONFIG_MX27_CLK32);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
time *= CONFIG_MX27_CLK32;
do_div(time, CONFIG_SYS_HZ);
return time;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us = us * CONFIG_MX27_CLK32 + 999999;
do_div(us, 1000000);
return us;
}
#else
/* ~2% error */
#define TICK_PER_TIME ((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
CONFIG_SYS_HZ)
#define US_PER_TICK (1000000 / CONFIG_MX27_CLK32)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
do_div(tick, TICK_PER_TIME);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
return time * TICK_PER_TIME;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us += US_PER_TICK - 1;
do_div(us, US_PER_TICK);
return us;
}
#endif
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int timer_init(void)
{
int i;
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
/* setup GP Timer 1 */
writel(GPTCR_SWR, &regs->gpt_tctl);
writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
for (i = 0; i < 100; i++)
writel(0, &regs->gpt_tctl); /* We have no udelay by now */
writel(0, &regs->gpt_tprer); /* 32Khz */
/* Freerun Mode, PERCLK1 input */
writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
&regs->gpt_tctl);
writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl);
return 0;
}
unsigned long long get_ticks(void)
{
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
ulong now = readl(&regs->gpt_tcn); /* current tick value */
if (now >= lastinc) {
/*
* normal mode (non roll)
* move stamp forward with absolut diff ticks
*/
timestamp += (now - lastinc);
} else {
/* we have rollover of incrementer */
timestamp += (0xFFFFFFFF - lastinc) + now;
}
lastinc = now;
return timestamp;
}
static ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
return tick_to_time(get_ticks());
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
/* delay x useconds AND preserve advance timstamp value */
void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
tmo = us_to_tick(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
ulong get_tbclk(void)
{
return CONFIG_MX27_CLK32;
}

4
arch/arm/cpu/arm926ejs/mxs/Makefile
View File

@ -60,14 +60,14 @@ spl/u-boot-spl.ivt: spl/u-boot-spl.bin
u-boot.ivt: u-boot.bin
$(call if_changed,mkalign_mxs)
$(call if_changed,mkivt_mxs,$(CONFIG_SYS_TEXT_BASE),\
$(call if_changed,mkivt_mxs,$(CONFIG_TEXT_BASE),\
0x40001000,0x40001040)
spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf
$(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000)
u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf
$(call if_changed,mkcsfreq_mxs,$(CONFIG_SYS_TEXT_BASE),0x40001000)
$(call if_changed,mkcsfreq_mxs,$(CONFIG_TEXT_BASE),0x40001000)
%.sig: %.csf
$(call if_changed,mkcst_mxs)

6
arch/arm/cpu/arm926ejs/mxs/mxs.c
View File

@ -71,6 +71,7 @@ void reset_cpu(void)
* actually 0x20, this the associated <destination address>. Loading the PC
* register with an address performs a jump to that address.
*/
noinline __attribute__((target("arm")))
void mx28_fixup_vt(uint32_t start_addr)
{
/* ldr pc, [pc, #0x18] */
@ -85,6 +86,9 @@ void mx28_fixup_vt(uint32_t start_addr)
/* cppcheck-suppress nullPointer */
vt[i + 8] = start_addr + (4 * i);
}
/* Make sure ARM core points to low vectors */
set_cr(get_cr() & ~CR_V);
}
#ifdef CONFIG_ARCH_MISC_INIT
@ -100,7 +104,7 @@ int arch_cpu_init(void)
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
mx28_fixup_vt((uint32_t)&_start);
mx28_fixup_vt((uint32_t)_start);
/*
* Enable NAND clock

4
arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx28.cfg
View File

@ -2,5 +2,5 @@ DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
LOAD IVT 0x8000 0x1000
CALL HAB 0x8000 0x0
LOAD IVT 0xE000 0x1000
CALL HAB 0xE000 0x0

8
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
View File

@ -2,8 +2,8 @@ DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
LOAD IVT 0x8000 0x1000
CALL HAB 0x8000 0x0
LOAD IVT 0xE000 0x1000
CALL HAB 0xE000 0x0
LOAD 0x40002000 u-boot.bin
LOAD IVT 0x8000 0x40002000
CALL HAB 0x8000 0x0
LOAD IVT 0xE000 0x40002000
CALL HAB 0xE000 0x0

20
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
View File

@ -17,13 +17,14 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/sections.h>
#include <asm/system.h>
#include <linux/compiler.h>
#include "mxs_init.h"
DECLARE_GLOBAL_DATA_PTR;
static gd_t gdata __section(".data");
#ifdef CONFIG_SPL_SERIAL_SUPPORT
#ifdef CONFIG_SPL_SERIAL
static struct bd_info bdata __section(".data");
#endif
@ -93,7 +94,9 @@ static uint8_t mxs_get_bootmode_index(void)
return i;
}
static void mxs_spl_fixup_vectors(void)
static noinline
__attribute__((target("arm")))
void mxs_spl_fixup_vectors(void)
{
/*
* Copy our vector table to 0x0, since due to HAB, we cannot
@ -103,12 +106,15 @@ static void mxs_spl_fixup_vectors(void)
*/
/* cppcheck-suppress nullPointer */
memcpy(0x0, &_start, 0x60);
memcpy(0x0, _start, 0x60);
/* Make sure ARM core points to low vectors */
set_cr(get_cr() & ~CR_V);
}
static void mxs_spl_console_init(void)
{
#ifdef CONFIG_SPL_SERIAL_SUPPORT
#ifdef CONFIG_SPL_SERIAL
gd->bd = &bdata;
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
@ -128,8 +134,10 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
mxs_spl_console_init();
debug("SPL: Serial Console Initialised\n");
if (!CONFIG_IS_ENABLED(DM_SERIAL)) {
mxs_spl_console_init();
debug("SPL: Serial Console Initialised\n");
}
mxs_power_init();

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