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53
.gitignore vendored
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@ -3,33 +3,26 @@
# subdirectories here. Add them in the ".gitignore" file
# in that subdirectory instead.
#
# Normal rules (sorted alphabetically)
# Normal rules
#
.*
*.a
*.asn1.[ch]
*.bin
*.cfgout
*.dtb
*.dtbo
*.dtb.S
*.elf
*.exe
*.gcda
*.gcno
*.i
*.img
*.lex.c
*.lst
*.mod.c
*.o
*.o.*
*.order
*.patch
*.a
*.s
*.su
*.mod.c
*.i
*.lst
*.order
*.elf
*.swp
*.tab.[ch]
*.bin
*.patch
*.cfgtmp
# host programs on Cygwin
*.exe
# Build tree
/build-*
@ -37,13 +30,12 @@
#
# Top-level generic files
#
fit-dtb.blob*
fit-dtb.blob
/MLO*
/SPL*
/System.map
/u-boot*
/boards.cfg
/*.log
#
# git files that we don't want to ignore even it they are dot-files
@ -54,6 +46,7 @@ fit-dtb.blob*
#
# Generated files
#
/LOG
/spl/
/tpl/
/defconfig
@ -93,5 +86,17 @@ GTAGS
*~
\#*#
# Python cache
__pycache__
# gcc code coverage files
*.gcda
*.gcno
boot_package.cfg
dts
*.dtb
*.dtbo
*.fex
sys_config
tools/sunxi_proftool
*.dts
boot0_sdcard.fex-linux4.9
board/sunxi/sunxi_challenge.c

0
doc/device-tree-bindings/phy/no-op.txt → Documentation/devicetree/bindings/phy/no-op.txt
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0
doc/device-tree-bindings/rtc/brcm,brcmstb-waketimer.txt → Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt
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49
Kbuild
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@ -1,22 +1,54 @@
# SPDX-License-Identifier: GPL-2.0
#
# Kbuild for top-level directory of U-Boot
# This file takes care of the following:
# 1) Generate generic-asm-offsets.h
# 2) Generate asm-offsets.h
# Default sed regexp - multiline due to syntax constraints
define sed-y
"s:[[:space:]]*\.ascii[[:space:]]*\"\(.*\)\":\1:; \
/^->/{s:->#\(.*\):/* \1 */:; \
s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
s:->::; p;}"
endef
# Use filechk to avoid rebuilds when a header changes, but the resulting file
# does not
define filechk_offsets
(set -e; \
echo "#ifndef $2"; \
echo "#define $2"; \
echo "/*"; \
echo " * DO NOT MODIFY."; \
echo " *"; \
echo " * This file was generated by Kbuild"; \
echo " */"; \
echo ""; \
sed -ne $(sed-y); \
echo ""; \
echo "#endif" )
endef
#####
# Generate generic-asm-offsets.h
# 1) Generate generic-asm-offsets.h
generic-offsets-file := include/generated/generic-asm-offsets.h
always := $(generic-offsets-file)
targets := lib/asm-offsets.s
CFLAGS_REMOVE_asm-offsets.o := $(LTO_CFLAGS)
# We use internal kbuild rules to avoid the "is up to date" message from make
lib/asm-offsets.s: lib/asm-offsets.c FORCE
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cc_s_c)
$(obj)/$(generic-offsets-file): $(obj)/lib/asm-offsets.s FORCE
$(obj)/$(generic-offsets-file): lib/asm-offsets.s FORCE
$(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__)
#####
# Generate asm-offsets.h
# 2) Generate asm-offsets.h
#
ifneq ($(wildcard $(srctree)/arch/$(ARCH)/lib/asm-offsets.c),)
offsets-file := include/generated/asm-offsets.h
@ -27,5 +59,10 @@ targets += arch/$(ARCH)/lib/asm-offsets.s
CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY
$(obj)/$(offsets-file): $(obj)/arch/$(ARCH)/lib/asm-offsets.s FORCE
# We use internal kbuild rules to avoid the "is up to date" message from make
arch/$(ARCH)/lib/asm-offsets.s: arch/$(ARCH)/lib/asm-offsets.c FORCE
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cc_s_c)
$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s FORCE
$(call filechk,offsets,__ASM_OFFSETS_H__)

548
Kconfig
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@ -3,11 +3,11 @@
# see the file Documentation/kbuild/kconfig-language.txt in the
# Linux kernel source tree.
#
mainmenu "U-Boot $(UBOOTVERSION) Configuration"
mainmenu "U-Boot $UBOOTVERSION Configuration"
comment "Compiler: $(CC_VERSION_TEXT)"
source "scripts/Kconfig.include"
config UBOOTVERSION
string
option env="UBOOTVERSION"
# Allow defaults in arch-specific code to override any given here
source "arch/Kconfig"
@ -20,13 +20,6 @@ config BROKEN
This option cannot be enabled. It is used as dependency
for broken and incomplete features.
config DEPRECATED
bool
help
This option cannot be enabled. It it used as a dependency for
code that relies on deprecated features that will be removed and
the conversion deadline has passed.
config LOCALVERSION
string "Local version - append to U-Boot release"
help
@ -66,59 +59,6 @@ config CC_OPTIMIZE_FOR_SIZE
This option is enabled by default for U-Boot.
config OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in full U-Boot"
default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
do what it thinks is best, which is desirable in some cases for size
reasons.
config SPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in SPL"
depends on SPL
default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
do what it thinks is best, which is desirable in some cases for size
reasons.
config ARCH_SUPPORTS_LTO
bool
config LTO
bool "Enable Link Time Optimizations"
depends on ARCH_SUPPORTS_LTO
default n
help
This option enables Link Time Optimization (LTO), a mechanism which
allows the compiler to optimize between different compilation units.
This can optimize away dead code paths, resulting in smaller binary
size (if CC_OPTIMIZE_FOR_SIZE is enabled).
This option is not available for every architecture and may
introduce bugs.
Currently, when compiling with GCC, due to a weird bug regarding
jobserver, the final linking will not respect make's --jobs argument.
Instead all available processors will be used (as reported by the
nproc command).
If unsure, say n.
config TPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in TPL"
depends on TPL
default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
do what it thinks is best, which is desirable in some cases for size
reasons.
config CC_COVERAGE
bool "Enable code coverage analysis"
depends on SANDBOX
@ -126,50 +66,27 @@ config CC_COVERAGE
Enabling this option will pass "--coverage" to gcc to compile
and link code instrumented for coverage analysis.
config CC_HAS_ASM_INLINE
def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) -x c - -c -o /dev/null)
config XEN
bool "Select U-Boot be run as a bootloader for XEN Virtual Machine"
help
Enabling this option will make U-Boot be run as a bootloader
for XEN [1] Virtual Machine.
Xen is a virtual machine monitor (VMM) or a type-1 hypervisor with support
for para-virtualization. Xen can organize the safe execution of several
virtual machines on the same physical system with performance close to
native. It is used as the basis for a number of different commercial and
open source applications, such as: server virtualization, Infrastructure
as a Service (IaaS), desktop virtualization, security applications,
embedded and hardware appliances.
Xen has a special VM called Domain-0 that runs the Dom0 kernel and allows
Xen to use the device drivers for the Domain-0 kernel by default.
[1] - https://xenproject.org/
config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux distributions"
select AUTO_COMPLETE
select CMDLINE_EDITING
select CMD_BOOTI if ARM64
imply USE_BOOTCOMMAND
select CMD_BOOTZ if ARM && !ARM64
select CMD_BOOTI if ARM64
select CMD_DHCP if CMD_NET
select CMD_PING if CMD_NET
select CMD_PXE if NET
select CMD_ENV_EXISTS
select CMD_EXT2
select CMD_EXT4
select CMD_FAT
select CMD_FS_GENERIC
select CMD_PART if PARTITIONS
select CMD_PING if CMD_NET
select CMD_PXE if NET
select CMD_SYSBOOT
select ENV_VARS_UBOOT_CONFIG
select HUSH_PARSER
select SUPPORT_RAW_INITRD
select SYS_LONGHELP
imply CMD_MII if NET
imply USB_STORAGE
imply USE_BOOTCOMMAND
select CMD_PART if PARTITIONS
select HUSH_PARSER
select CMDLINE_EDITING
select AUTO_COMPLETE
select SYS_LONGHELP
select SUPPORT_RAW_INITRD
select ENV_VARS_UBOOT_CONFIG
help
Select this to enable various options and commands which are suitable
for building u-boot for booting general purpose Linux distributions.
@ -187,13 +104,6 @@ config ENV_VARS_UBOOT_CONFIG
- CONFIG_SYS_VENDOR
- CONFIG_SYS_SOC
config NR_DRAM_BANKS
int "Number of DRAM banks"
default 1 if ARCH_SUNXI || ARCH_OWL
default 4
help
This defines the number of DRAM banks.
config SYS_BOOT_GET_CMDLINE
bool "Enable kernel command line setup"
help
@ -209,7 +119,6 @@ config SYS_BOOT_GET_KBD
config SYS_MALLOC_F
bool "Enable malloc() pool before relocation"
default y if DM
help
Before relocation, memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
@ -220,11 +129,6 @@ config SYS_MALLOC_F_LEN
hex "Size of malloc() pool before relocation"
depends on SYS_MALLOC_F
default 0x1000 if AM33XX
default 0x4000 if SANDBOX
default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \
ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \
ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI || ARCH_OWL)
default 0x400
help
Before relocation, memory is very limited on many platforms. Still,
@ -232,37 +136,25 @@ config SYS_MALLOC_F_LEN
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP
default 0x2000000 if ARCH_ROCKCHIP
help
This defines memory to be allocated for Dynamic allocation
TODO: Use for other architectures
config SPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in SPL"
depends on SYS_MALLOC_F && SPL
default 0x2800 if RCAR_GEN3
default SYS_MALLOC_F_LEN
help
In SPL memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new
malloc() region in SDRAM once it is inited.
hex "Size of malloc() pool in SPL before relocation"
depends on SYS_MALLOC_F
default SYS_MALLOC_F_LEN
help
Before relocation, memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
config TPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in TPL"
depends on SYS_MALLOC_F && TPL
default SPL_SYS_MALLOC_F_LEN
help
In TPL memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
hex "Size of malloc() pool in TPL before relocation"
depends on SYS_MALLOC_F
default SYS_MALLOC_F_LEN
help
Before relocation, memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
@ -290,20 +182,6 @@ if EXPERT
When disabling this, please check if malloc calls, maybe
should be replaced by calloc - if one expects zeroed memory.
config SYS_MALLOC_DEFAULT_TO_INIT
bool "Default malloc to init while reserving the memory for it"
default n
help
It may happen that one needs to move the dynamic allocation
from one to another memory range, eg. when moving the malloc
from the limited static to a potentially large dynamic (DDR)
memory.
If so then on top of setting the updated memory aside one
needs to bring the malloc init.
If such a scenario is sought choose yes.
config TOOLS_DEBUG
bool "Enable debug information for tools"
help
@ -319,146 +197,246 @@ config PHYS_64BIT
help
Say Y here to support 64bit physical memory address.
This can be used not only for 64bit SoCs, but also for
large physical address extension on 32bit SoCs.
config HAS_ROM
bool
select BINMAN
help
Enables building of a u-boot.rom target. This collects U-Boot and
any necessary binary blobs.
config ROM_NEEDS_BLOBS
bool
depends on HAS_ROM
help
Enable this if building the u-boot.rom target needs binary blobs, and
so cannot be done normally. In this case, U-Boot will only build the
ROM if the required blobs exist. If not, you will see an warning like:
Image 'main-section' is missing external blobs and is non-functional:
intel-descriptor intel-me intel-refcode intel-vga intel-mrc
large physical address extention on 32bit SoCs.
config BUILD_ROM
bool "Build U-Boot as BIOS replacement"
depends on HAS_ROM
default y if !ROM_NEEDS_BLOBS
depends on X86
help
This option allows to build a ROM version of U-Boot.
The build process generally requires several binary blobs
which are not shipped in the U-Boot source tree.
Please, see doc/arch/x86.rst for details.
config SPL_IMAGE
string "SPL image used in the combined SPL+U-Boot image"
default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "spl/u-boot-spl.bin"
depends on SPL
help
Select the SPL build target that shall be generated by the SPL
build process (default spl/u-boot-spl.bin). This image will be
used to generate a combined image with SPL and main U-Boot
proper as one single image.
config BUILD_TARGET
string "Build target special images"
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
default "u-boot.kwb" if ARCH_KIRKWOOD
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
help
Some SoCs need special image types (e.g. U-Boot binary
with a special header) as build targets. By defining
CONFIG_BUILD_TARGET in the SoC / board header, this
special image will be automatically built upon calling
make / buildman.
config SYS_CUSTOM_LDSCRIPT
bool "Use a custom location for the U-Boot linker script"
help
Normally when linking U-Boot we will look in the board directory,
the CPU directory and finally the "cpu" directory of the architecture
for the ile "u-boot.lds" and use that as our linker. However, in
some cases we need to provide a different linker script. To do so,
enable this option and then provide the location under
CONFIG_SYS_LDSCRIPT.
config SYS_LDSCRIPT
depends on SYS_CUSTOM_LDSCRIPT
string "Custom ldscript location"
help
Path within the source tree to the linker script to use for the
main U-Boot binary.
config ERR_PTR_OFFSET
hex
default 0x0
help
Some U-Boot pointers have redundant information, so we can use a
scheme where we can return either an error code or a pointer with the
same return value. The default implementation just casts the pointer
to a number, however, this may fail on platforms where the end of the
address range is used for valid pointers (e.g. 0xffffff00 is a valid
heap pointer in socfpga SPL).
For such platforms, this value provides an upper range of those error
pointer values - up to 'MAX_ERRNO' bytes below this value must be
unused/invalid addresses.
config PLATFORM_ELFENTRY
string
default "__start" if MIPS
default "_start"
config STACK_SIZE
hex "Define max stack size that can be used by U-Boot"
default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
default 0x200000 if MICROBLAZE
default 0x1000000
help
Define Max stack size that can be used by U-Boot. This value is used
by the UEFI sub-system. On some boards initrd_high is calculated as
base stack pointer minus this stack size.
config SYS_HAS_SRAM
bool
default y if TARGET_PIC32MZDASK
default y if TARGET_DEVKIT8000
default y if TARGET_TRICORDER
default n
help
Enable this to allow support for the on board SRAM.
SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
SRAM size is controlled by CONFIG_SYS_SRAM_SIZE.
config SYS_SRAM_BASE
hex
default 0x80000000 if TARGET_PIC32MZDASK
default 0x40200000 if TARGET_DEVKIT8000
default 0x40200000 if TARGET_TRICORDER
default 0x0
config SYS_SRAM_SIZE
hex
default 0x00080000 if TARGET_PIC32MZDASK
default 0x10000 if TARGET_DEVKIT8000
default 0x10000 if TARGET_TRICORDER
default 0x0
config EXAMPLES
bool "Compile API examples"
depends on !SANDBOX
default y if ARCH_QEMU
help
U-Boot provides an API for standalone applications. Examples are
provided in directory examples/.
Please, see doc/README.x86 for details.
endmenu # General setup
menu "Boot images"
config ANDROID_BOOT_IMAGE
bool "Enable support for Android Boot Images"
default y if FASTBOOT
help
This enables support for booting images which use the Android
image format header.
config FIT
bool "Support Flattened Image Tree"
select MD5
select SHA1
help
This option allows you to boot the new uImage structure,
Flattened Image Tree. FIT is formally a FDT, which can include
images of various types (kernel, FDT blob, ramdisk, etc.)
in a single blob. To boot this new uImage structure,
pass the address of the blob to the "bootm" command.
FIT is very flexible, supporting compression, multiple images,
multiple configurations, verification through hashing and also
verified boot (secure boot using RSA).
if FIT
config FIT_ENABLE_SHA256_SUPPORT
bool "Support SHA256 checksum of FIT image contents"
select SHA256
default y
help
Enable this to support SHA256 checksum of FIT image contents. A
SHA256 checksum is a 256-bit (32-byte) hash value used to check that
the image contents have not been corrupted. SHA256 is recommended
for use in secure applications since (as at 2016) there is no known
feasible attack that could produce a 'collision' with differing
input data. Use this for the highest security. Note that only the
SHA256 variant is supported: SHA512 and others are not currently
supported in U-Boot.
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
depends on DM
select RSA
select HASH
help
This option enables signature verification of FIT uImages,
using a hash signed and verified using RSA. If
CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
hashing is available using hardware, then the RSA library will use
it. See doc/uImage.FIT/signature.txt for more details.
WARNING: When relying on signed FIT images with a required signature
check the legacy image format is disabled by default, so that
unsigned images cannot be loaded. If a board needs the legacy image
format support in this case, enable it using
CONFIG_IMAGE_FORMAT_LEGACY.
config FIT_VERBOSE
bool "Show verbose messages when FIT images fail"
help
Generally a system will have valid FIT images so debug messages
are a waste of code space. If you are debugging your images then
you can enable this option to get more verbose information about
failures.
config FIT_BEST_MATCH
bool "Select the best match for the kernel device tree"
help
When no configuration is explicitly selected, default to the
one whose fdt's compatibility field best matches that of
U-Boot itself. A match is considered "best" if it matches the
most specific compatibility entry of U-Boot's fdt's root node.
The order of entries in the configuration's fdt is ignored.
config FIT_IMAGE_POST_PROCESS
bool "Enable post-processing of FIT artifacts after loading by U-Boot"
depends on TI_SECURE_DEVICE
help
Allows doing any sort of manipulation to blobs after they got extracted
from FIT images like stripping off headers or modifying the size of the
blob, verification, authentication, decryption etc. in a platform or
board specific way. In order to use this feature a platform or board-
specific implementation of board_fit_image_post_process() must be
provided. Also, anything done during this post-processing step would
need to be comprehended in how the images were prepared before being
injected into the FIT creation (i.e. the blobs would have been pre-
processed before being added to the FIT image).
if SPL
config SPL_FIT
bool "Support Flattened Image Tree within SPL"
depends on SPL
select SPL_OF_LIBFDT
config SPL_FIT_SIGNATURE
bool "Enable signature verification of FIT firmware within SPL"
depends on SPL_DM
select SPL_FIT
select SPL_RSA
config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT"
select SPL_FIT
help
Normally with the SPL framework a legacy image is generated as part
of the build. This contains U-Boot along with information as to
where it should be loaded. This option instead enables generation
of a FIT (Flat Image Tree) which provides more flexibility. In
particular it can handle selecting from multiple device tree
and passing the correct one to U-Boot.
config SPL_FIT_IMAGE_POST_PROCESS
bool "Enable post-processing of FIT artifacts after loading by the SPL"
depends on SPL_LOAD_FIT
help
Allows doing any sort of manipulation to blobs after they got extracted
from the U-Boot FIT image like stripping off headers or modifying the
size of the blob, verification, authentication, decryption etc. in a
platform or board specific way. In order to use this feature a platform
or board-specific implementation of board_fit_image_post_process() must
be provided. Also, anything done during this post-processing step would
need to be comprehended in how the images were prepared before being
injected into the FIT creation (i.e. the blobs would have been pre-
processed before being added to the FIT image).
config SPL_FIT_SOURCE
string ".its source file for U-Boot FIT image"
depends on SPL_FIT
help
Specifies a (platform specific) FIT source file to generate the
U-Boot FIT image. This could specify further image to load and/or
execute.
config SPL_FIT_GENERATOR
string ".its file generator script for U-Boot FIT image"
depends on SPL_FIT
default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
help
Specifies a (platform specific) script file to generate the FIT
source file used to build the U-Boot FIT image file. This gets
passed a list of supported device tree file stub names to
include in the generated image.
endif # SPL
endif # FIT
config IMAGE_FORMAT_LEGACY
bool "Enable support for the legacy image format"
default y if !FIT_SIGNATURE
help
This option enables the legacy image format. It is enabled by
default for backward compatibility, unless FIT_SIGNATURE is
set where it is disabled so that unsigned images cannot be
loaded. If a board needs the legacy image format support in this
case, enable it here.
config OF_BOARD_SETUP
bool "Set up board-specific details in device tree before boot"
depends on OF_LIBFDT
help
This causes U-Boot to call ft_board_setup() before booting into
the Operating System. This function can set up various
board-specific information in the device tree for use by the OS.
The device tree is then passed to the OS.
config OF_SYSTEM_SETUP
bool "Set up system-specific details in device tree before boot"
depends on OF_LIBFDT
help
This causes U-Boot to call ft_system_setup() before booting into
the Operating System. This function can set up various
system-specific information in the device tree for use by the OS.
The device tree is then passed to the OS.
config OF_STDOUT_VIA_ALIAS
bool "Update the device-tree stdout alias from U-Boot"
depends on OF_LIBFDT
help
This uses U-Boot's serial alias from the aliases node to update
the device tree passed to the OS. The "linux,stdout-path" property
in the chosen node is set to point to the correct serial node.
This option currently references CONFIG_CONS_INDEX, which is
incorrect when used with device tree as this option does not
exist / should not be used.
config SYS_EXTRA_OPTIONS
string "Extra Options (DEPRECATED)"
help
The old configuration infrastructure (= mkconfig + boards.cfg)
provided the extra options field. If you have something like
"HAS_BAR,BAZ=64", the optional options
#define CONFIG_HAS
#define CONFIG_BAZ 64
will be defined in include/config.h.
This option was prepared for the smooth migration from the old
configuration to Kconfig. Since this option will be removed sometime,
new boards should not use this option.
config SYS_TEXT_BASE
depends on !NIOS2 && !XTENSA
depends on !EFI_APP
default 0x80800000 if ARCH_OMAP2PLUS
hex "Text Base"
help
The address in memory that U-Boot will be running from, initially.
config SYS_CLK_FREQ
depends on ARC || ARCH_SUNXI
int "CPU clock frequency"
help
TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
config ARCH_FIXUP_FDT_MEMORY
bool "Enable arch_fixup_memory_banks() call"
default y
help
Enable FDT memory map syncup before OS boot. This feature can be
used for booting OS with different memory setup where the part of
the memory location should be used for different purpose.
endmenu # Boot images
source "api/Kconfig"
source "common/Kconfig"
@ -481,4 +459,6 @@ source "lib/Kconfig"
source "test/Kconfig"
source "tools/Kconfig"
source "sprite/Kconfig"
source "rtos/Kconfig"

103
Licenses/README
View File

@ -1,5 +1,3 @@
SPDX-License-Identifier: GPL-2.0
U-Boot is Free Software. It is copyrighted by Wolfgang Denk and
many others who contributed code (see the actual source code and the
git commit messages for details). You can redistribute U-Boot and/or
@ -33,107 +31,27 @@ information, ...) which makes automatic processing a nightmare.
To make this easier, such license headers in the source files will be
replaced with a single line reference to Unique License Identifiers
as defined by the Linux Foundation's SPDX project [1].
as defined by the Linux Foundation's SPDX project [1]. For example,
in a source file the full "GPL v2.0 or later" header text will be
replaced by a single line:
SPDX-License-Identifier: GPL-2.0+
Ideally, the license terms of all files in the source tree should be
defined by such License Identifiers; in no case a file can contain
more than one such License Identifier list.
If a "SPDX-License-Identifier:" line references more than one Unique
License Identifier, then this means that the respective file can be
used under the terms of either of these licenses, i. e. with
SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
you can choose between GPL-2.0+ and BSD-3-Clause licensing.
We use the SPDX Unique License Identifiers here; these are available
at [2].
License identifier syntax
-------------------------
1. Placement:
The SPDX license identifier in U-Boot files shall be added at the first
possible line in a file which can contain a comment. For the majority
or files this is the first line, except for scripts which require the
'#!PATH_TO_INTERPRETER' in the first line. For those scripts the SPDX
identifier goes into the second line.
|
2. Style:
The SPDX license identifier is added in form of a comment. The comment
style depends on the file type::
C source: // SPDX-License-Identifier: <SPDX License Expression>
C header: /* SPDX-License-Identifier: <SPDX License Expression> */
ASM: /* SPDX-License-Identifier: <SPDX License Expression> */
scripts: # SPDX-License-Identifier: <SPDX License Expression>
.rst: .. SPDX-License-Identifier: <SPDX License Expression>
.dts{i}: // SPDX-License-Identifier: <SPDX License Expression>
If a specific tool cannot handle the standard comment style, then the
appropriate comment mechanism which the tool accepts shall be used. This
is the reason for having the "/\* \*/" style comment in C header
files. There was build breakage observed with generated .lds files where
'ld' failed to parse the C++ comment. This has been fixed by now, but
there are still older assembler tools which cannot handle C++ style
comments.
|
3. Syntax:
A <SPDX License Expression> is either an SPDX short form license
identifier found on the SPDX License List, or the combination of two
SPDX short form license identifiers separated by "WITH" when a license
exception applies. When multiple licenses apply, an expression consists
of keywords "AND", "OR" separating sub-expressions and surrounded by
"(", ")" .
License identifiers for licenses like [L]GPL with the 'or later' option
are constructed by using a "+" for indicating the 'or later' option.::
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: LGPL-2.1+
WITH should be used when there is a modifier to a license needed.
For example, the linux kernel UAPI files use the expression::
// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
// SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note
Other examples using WITH exceptions found in the linux kernel are::
// SPDX-License-Identifier: GPL-2.0 WITH mif-exception
// SPDX-License-Identifier: GPL-2.0+ WITH GCC-exception-2.0
Exceptions can only be used with particular License identifiers. The
valid License identifiers are listed in the tags of the exception text
file.
OR should be used if the file is dual licensed and only one license is
to be selected. For example, some dtsi files are available under dual
licenses::
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
Examples from U-Boot for license expressions in dual licensed files::
// SPDX-License-Identifier: GPL-2.0 OR MIT
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
AND should be used if the file has multiple licenses whose terms all
apply to use the file. For example, if code is inherited from another
project and permission has been given to put it in U-Boot, but the
original license terms need to remain in effect::
// SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) AND MIT
Another other example where both sets of license terms need to be
adhered to is::
// SPDX-License-Identifier: GPL-1.0+ AND LGPL-2.1+
[1] http://spdx.org/
[2] http://spdx.org/licenses/
@ -149,6 +67,5 @@ BSD 3-clause "New" or "Revised" License BSD-3-Clause Y bsd-3-clause.txt http:/
IBM PIBS (PowerPC Initialization and IBM-pibs ibm-pibs.txt
Boot Software) license
ISC License ISC Y isc.txt https://spdx.org/licenses/ISC
MIT License MIT Y mit.txt https://spdx.org/licenses/MIT.html
SIL OPEN FONT LICENSE (OFL-1.1) OFL-1.1 Y OFL.txt https://spdx.org/licenses/OFL-1.1.html
X11 License X11 x11.txt https://spdx.org/licenses/X11.html

20
Licenses/mit.txt
View File

@ -1,20 +0,0 @@
MIT License
Copyright (c) 2020 EPAM Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

845
MAINTAINERS
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File diff suppressed because it is too large Load Diff

1133
Makefile
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File diff suppressed because it is too large Load Diff

655
README
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File diff suppressed because it is too large Load Diff

76
api/api.c
View File

@ -8,13 +8,10 @@
#include <config.h>
#include <command.h>
#include <common.h>
#include <env.h>
#include <malloc.h>
#include <env_internal.h>
#include <linux/delay.h>
#include <environment.h>
#include <linux/types.h>
#include <api_public.h>
#include <u-boot/crc.h>
#include "api_private.h"
@ -57,7 +54,7 @@ static int API_getc(va_list ap)
if ((c = (int *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
*c = getchar();
*c = getc();
return 0;
}
@ -297,31 +294,27 @@ static int API_dev_close(va_list ap)
/*
* Notice: this is for sending network packets only, as U-Boot does not
* support writing to storage at the moment (12.2007)
*
* pseudo signature:
*
* int API_dev_write(
* struct device_info *di,
* void *buf,
* int *len,
* unsigned long *start
* int *len
* )
*
* buf: ptr to buffer from where to get the data to send
*
* len: ptr to length to be read
* - network: len of packet to be sent (in bytes)
* - storage: # of blocks to write (can vary in size depending on define)
* len: length of packet to be sent (in bytes)
*
* start: ptr to start block (only used for storage devices, ignored for
* network)
*/
static int API_dev_write(va_list ap)
{
struct device_info *di;
void *buf;
lbasize_t *len_stor, act_len_stor;
lbastart_t *start;
int *len_net;
int *len;
int err = 0;
/* 1. arg is ptr to the device_info struct */
@ -339,36 +332,23 @@ static int API_dev_write(va_list ap)
if (buf == NULL)
return API_EINVAL;
if (di->type & DEV_TYP_STOR) {
/* 3. arg - ptr to var with # of blocks to write */
len_stor = (lbasize_t *)va_arg(ap, uintptr_t);
if (!len_stor)
return API_EINVAL;
if (*len_stor <= 0)
return API_EINVAL;
/* 3. arg is length of buffer */
len = (int *)va_arg(ap, uintptr_t);
if (len == NULL)
return API_EINVAL;
if (*len <= 0)
return API_EINVAL;
/* 4. arg - ptr to var with start block */
start = (lbastart_t *)va_arg(ap, uintptr_t);
if (di->type & DEV_TYP_STOR)
/*
* write to storage is currently not supported by U-Boot:
* no storage device implements block_write() method
*/
return API_ENODEV;
act_len_stor = dev_write_stor(di->cookie, buf, *len_stor, *start);
if (act_len_stor != *len_stor) {
debugf("write @ %llu: done %llu out of %llu blocks",
(uint64_t)blk, (uint64_t)act_len_stor,
(uint64_t)len_stor);
return API_EIO;
}
} else if (di->type & DEV_TYP_NET) {
/* 3. arg points to the var with length of packet to write */
len_net = (int *)va_arg(ap, uintptr_t);
if (!len_net)
return API_EINVAL;
if (*len_net <= 0)
return API_EINVAL;
err = dev_write_net(di->cookie, buf, *len_net);
} else
else if (di->type & DEV_TYP_NET)
err = dev_write_net(di->cookie, buf, *len);
else
err = API_ENODEV;
return err;
@ -516,7 +496,7 @@ static int API_env_enum(va_list ap)
{
int i, buflen;
char *last, **next, *s;
struct env_entry *match, search;
ENTRY *match, search;
static char *var;
last = (char *)va_arg(ap, unsigned long);
@ -533,7 +513,7 @@ static int API_env_enum(va_list ap)
if (s != NULL)
*s = 0;
search.key = var;
i = hsearch_r(search, ENV_FIND, &match, &env_htab, 0);
i = hsearch_r(search, FIND, &match, &env_htab, 0);
if (i == 0) {
i = API_EINVAL;
goto done;
@ -642,7 +622,7 @@ int syscall(int call, int *retval, ...)
return 1;
}
int api_init(void)
void api_init(void)
{
struct api_signature *sig;
@ -679,7 +659,7 @@ int api_init(void)
sig = malloc(sizeof(struct api_signature));
if (sig == NULL) {
printf("API: could not allocate memory for the signature!\n");
return -ENOMEM;
return;
}
env_set_hex("api_address", (unsigned long)sig);
@ -691,8 +671,6 @@ int api_init(void)
sig->checksum = crc32(0, (unsigned char *)sig,
sizeof(struct api_signature));
debugf("syscall entry: 0x%lX\n", (unsigned long)sig->syscall);
return 0;
}
void platform_set_mr(struct sys_info *si, unsigned long start, unsigned long size,

1
api/api_display.c
View File

@ -6,7 +6,6 @@
#include <common.h>
#include <api_public.h>
#include <lcd.h>
#include <log.h>
#include <video_font.h> /* Get font width and height */
/* lcd.h needs BMP_LOGO_HEIGHT to calculate CONSOLE_ROWS */

3
api/api_platform-mips.c
View File

@ -24,7 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
int platform_sys_info(struct sys_info *si)
{
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_memstart,
gd->bd->bi_memsize, MR_ATTR_DRAM);
return 1;
}

2
api/api_platform-powerpc.c
View File

@ -42,7 +42,7 @@ int platform_sys_info(struct sys_info *si)
si->bar = 0;
#endif
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);

3
api/api_private.h
View File

@ -8,7 +8,7 @@
#ifndef _API_PRIVATE_H_
#define _API_PRIVATE_H_
int api_init(void);
void api_init(void);
void platform_set_mr(struct sys_info *, unsigned long, unsigned long, int);
int platform_sys_info(struct sys_info *);
@ -22,7 +22,6 @@ int dev_close_stor(void *);
int dev_close_net(void *);
lbasize_t dev_read_stor(void *, void *, lbasize_t, lbastart_t);
lbasize_t dev_write_stor(void *, void *, lbasize_t, lbastart_t);
int dev_read_net(void *, void *, int);
int dev_write_net(void *, void *, int);

30
api/api_storage.c
View File

@ -8,7 +8,6 @@
#include <config.h>
#include <common.h>
#include <api_public.h>
#include <part.h>
#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
#include <usb.h>
@ -100,7 +99,6 @@ static int dev_stor_get(int type, int *more, struct device_info *di)
{
struct blk_desc *dd;
int found = 0;
int found_last = 0;
int i = 0;
/* Wasn't configured for this type, return 0 directly */
@ -113,13 +111,9 @@ static int dev_stor_get(int type, int *more, struct device_info *di)
if (di->cookie ==
(void *)blk_get_dev(specs[type].name, i)) {
i += 1;
found_last = 1;
break;
}
}
if (!found_last)
i = 0;
}
for (; i < specs[type].max_dev; i++) {
@ -350,27 +344,3 @@ lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start
return dd->block_read(dd, start, len, buf);
#endif /* defined(CONFIG_BLK) */
}
lbasize_t dev_write_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start)
{
struct blk_desc *dd = (struct blk_desc *)cookie;
int type = dev_stor_type(dd);
if (type == ENUM_MAX)
return 0;
if (!dev_stor_is_valid(type, dd))
return 0;
#ifdef CONFIG_BLK
return blk_dwrite(dd, start, len, buf);
#else
if (dd->block_write == NULL) {
debugf("no block_write() for device 0x%08x\n", cookie);
return 0;
}
return dd->block_write(dd, start, len, buf);
#endif /* defined(CONFIG_BLK) */
}

206
arch/Kconfig
View File

@ -4,19 +4,9 @@ config CREATE_ARCH_SYMLINK
config HAVE_ARCH_IOREMAP
bool
config NEEDS_MANUAL_RELOC
bool
config LINKER_LIST_ALIGN
int
default 32 if SANDBOX
default 8 if ARM64 || X86
default 4
help
Force the each linker list to be aligned to this boundary. This
is required if ll_entry_get() is used, since otherwise the linker
may add padding into the table, thus breaking it.
See linker_lists.rst for full details.
config SUNXI_TEXT_SIZE
hex
default 0x100000
choice
prompt "Architecture select"
@ -24,16 +14,15 @@ choice
config ARC
bool "ARC architecture"
select ARC_TIMER
select CLK
select DM
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
select ARCH_EARLY_INIT_R
select CLK
select TIMER
select ARC_TIMER
config ARM
bool "ARM architecture"
select ARCH_SUPPORTS_LTO
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC if !ARM64
select SUPPORT_OF_CONTROL
@ -41,14 +30,11 @@ config ARM
config M68K
bool "M68000 architecture"
select HAVE_PRIVATE_LIBGCC
select NEEDS_MANUAL_RELOC
select SYS_BOOT_GET_CMDLINE
select SYS_BOOT_GET_KBD
select SUPPORT_OF_CONTROL
config MICROBLAZE
bool "MicroBlaze architecture"
select NEEDS_MANUAL_RELOC
select SUPPORT_OF_CONTROL
imply CMD_IRQ
@ -64,11 +50,10 @@ config NDS32
config NIOS2
bool "Nios II architecture"
select CPU
select DM
select OF_CONTROL
select SUPPORT_OF_CONTROL
imply CMD_DM
select OF_CONTROL
select DM
select CPU
config PPC
bool "PowerPC architecture"
@ -82,177 +67,74 @@ config RISCV
select CREATE_ARCH_SYMLINK
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
imply DM_SERIAL
imply DM_ETH
imply DM_MMC
imply DM_SPI
imply DM_SPI_FLASH
imply BLK
imply CLK
imply MTD
imply TIMER
imply CMD_DM
imply SPL_DM
imply SPL_OF_CONTROL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_SERIAL_SUPPORT
imply SPL_TIMER
config SANDBOX
bool "Sandbox"
select ARCH_SUPPORTS_LTO
select BOARD_LATE_INIT
select BZIP2
select CMD_POWEROFF
select DM
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
select DM_MMC
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select GZIP_COMPRESSED
select HAVE_BLOCK_DEVICE
select LZO
select OF_BOARD_SETUP
select PCI_ENDPOINT
select SPI
select SUPPORT_OF_CONTROL
select SYSRESET_CMD_POWEROFF
select IRQ
select SUPPORT_EXTENSION_SCAN
imply BITREVERSE
select BLOBLIST
imply LTO
imply CMD_DM
imply CMD_EXCEPTION
select DM
select DM_KEYBOARD
select DM_SPI_FLASH
select DM_SERIAL
select DM_I2C
select DM_SPI
select DM_GPIO
select DM_MMC
select HAVE_BLOCK_DEVICE
select SPI
select LZO
imply CMD_GETTIME
imply CMD_HASH
imply CMD_IO
imply CMD_IOTRACE
imply CMD_LZMADEC
imply CMD_SATA
imply CMD_SF
imply CMD_SF_TEST
imply CRC32_VERIFY
imply FAT_WRITE
imply FIRMWARE
imply HASH_VERIFY
imply LZMA
imply SCSI
imply TEE
imply AVB_VERIFY
imply LIBAVB
imply CMD_AVB
imply SCP03
imply CMD_SCP03
imply UDP_FUNCTION_FASTBOOT
imply VIRTIO_MMIO
imply VIRTIO_PCI
imply VIRTIO_SANDBOX
imply VIRTIO_BLK
imply VIRTIO_NET
imply DM_SOUND
imply PCI_SANDBOX_EP
imply PCH
imply PHYLIB
imply DM_MDIO
imply DM_MDIO_MUX
imply ACPI_PMC
imply ACPI_PMC_SANDBOX
imply CMD_PMC
imply CMD_CLONE
imply SILENT_CONSOLE
imply BOOTARGS_SUBST
imply PHY_FIXED
imply DM_DSA
imply CMD_EXTENSION
imply CMD_SATA
imply CMD_SF_TEST
config SH
bool "SuperH architecture"
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
config X86
bool "x86 architecture"
select SUPPORT_SPL
select SUPPORT_TPL
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC
select USE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
select DM_PCI
select HAVE_ARCH_IOMAP
select HAVE_PRIVATE_LIBGCC
select OF_CONTROL
select PCI
select SUPPORT_OF_CONTROL
select TIMER
select USE_PRIVATE_LIBGCC
select X86_TSC_TIMER
select IRQ
imply HAS_ROM if X86_RESET_VECTOR
imply BLK
imply CMD_DM
imply CMD_FPGA_LOADMK
imply CMD_GETTIME
imply CMD_IO
imply CMD_IRQ
imply CMD_PCI
imply CMD_SF
imply CMD_SF_TEST
imply CMD_ZBOOT
imply DM_ETH
imply DM_GPIO
imply DM_KEYBOARD
imply DM_MMC
imply DM_RTC
imply DM_SCSI
imply DM_SERIAL
imply DM_SCSI
imply DM_SPI
imply DM_SPI_FLASH
imply DM_USB
imply DM_VIDEO
imply SYSRESET
imply SPL_SYSRESET
imply SYSRESET_X86
imply CMD_FPGA_LOADMK
imply CMD_GETTIME
imply CMD_IO
imply CMD_IRQ
imply CMD_PCI
imply CMD_SF_TEST
imply CMD_ZBOOT
imply USB_HOST_ETHER
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX
imply USB_HOST_ETHER
imply PCH
imply RTC_MC146818
imply ACPIGEN if !QEMU
imply SYSINFO if GENERATE_SMBIOS_TABLE
imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
# Thing to enable for when SPL/TPL are enabled: SPL
imply SPL_DM
imply SPL_OF_LIBFDT
imply SPL_DRIVERS_MISC_SUPPORT
imply SPL_GPIO_SUPPORT
imply SPL_PINCTRL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_SERIAL_SUPPORT
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
imply SPL_OF_CONTROL
imply SPL_TIMER
imply SPL_REGMAP
imply SPL_SYSCON
# TPL
imply TPL_DM
imply TPL_DRIVERS_MISC_SUPPORT
imply TPL_GPIO_SUPPORT
imply TPL_PINCTRL
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_SERIAL_SUPPORT
imply TPL_OF_CONTROL
imply TPL_TIMER
imply TPL_REGMAP
imply TPL_SYSCON
config XTENSA
bool "Xtensa architecture"
@ -317,17 +199,16 @@ config SYS_CONFIG_NAME
The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
should be included from include/config.h.
config SYS_DISABLE_DCACHE_OPS
bool
help
This option disables dcache flush and dcache invalidation
operations. For example, on coherent systems where cache
operatios are not required, enable this option to avoid them.
Note that, its up to the individual architectures to implement
this functionality.
choice
prompt "Target select"
default ARCH_SUNXI
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
endchoice
source "arch/arc/Kconfig"
source "arch/arm/Kconfig"
source "arch/riscv/Kconfig"
source "arch/m68k/Kconfig"
source "arch/microblaze/Kconfig"
source "arch/mips/Kconfig"
@ -338,4 +219,3 @@ source "arch/sandbox/Kconfig"
source "arch/sh/Kconfig"
source "arch/x86/Kconfig"
source "arch/xtensa/Kconfig"
source "arch/riscv/Kconfig"

40
arch/arc/Kconfig
View File

@ -31,36 +31,36 @@ choice
config CPU_ARC750D
bool "ARC 750D"
depends on ISA_ARCOMPACT
select ARC_MMU_V2
depends on ISA_ARCOMPACT
help
Choose this option to build an U-Boot for ARC750D CPU.
config CPU_ARC770D
bool "ARC 770D"
depends on ISA_ARCOMPACT
select ARC_MMU_V3
depends on ISA_ARCOMPACT
help
Choose this option to build an U-Boot for ARC770D CPU.
config CPU_ARCEM6
bool "ARC EM6"
depends on ISA_ARCV2
select ARC_MMU_ABSENT
depends on ISA_ARCV2
help
Next Generation ARC Core based on ISA-v2 ISA without MMU.
config CPU_ARCHS36
bool "ARC HS36"
depends on ISA_ARCV2
select ARC_MMU_ABSENT
depends on ISA_ARCV2
help
Next Generation ARC Core based on ISA-v2 ISA without MMU.
config CPU_ARCHS38
bool "ARC HS38"
depends on ISA_ARCV2
select ARC_MMU_V4
depends on ISA_ARCV2
help
Next Generation ARC Core based on ISA-v2 ISA with MMU.
@ -114,26 +114,12 @@ config SYS_ICACHE_OFF
help
Do not enable instruction cache in U-Boot.
config SPL_SYS_ICACHE_OFF
bool "Do not enable icache in SPL"
depends on SPL
default SYS_ICACHE_OFF
help
Do not enable instruction cache in SPL.
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
config SPL_SYS_DCACHE_OFF
bool "Do not enable dcache in SPL"
depends on SPL
default SYS_DCACHE_OFF
help
Do not enable data cache in SPL.
menuconfig ARC_DBG
bool "ARC debugging"
default n
@ -160,7 +146,7 @@ config TARGET_TB100
bool "Support tb100"
config TARGET_NSIM
bool "Support ARC simulation & prototyping platforms"
bool "Support standalone nSIM & Free nSIM"
config TARGET_AXS101
bool "Support Synopsys Designware SDP board AXS101"
@ -168,24 +154,14 @@ config TARGET_AXS101
config TARGET_AXS103
bool "Support Synopsys Designware SDP board AXS103"
config TARGET_EMSDP
bool "Synopsys EM Software Development Platform"
select CPU_ARCEM6
config TARGET_HSDK
bool "Support Synopsys HSDK or HSDK-4xD board"
config TARGET_IOT_DEVKIT
bool "Synopsys Brite IoT Development kit"
select CPU_ARCEM6
bool "Support Synpsys HS DevelopmentKit board"
endchoice
source "board/abilis/tb100/Kconfig"
source "board/synopsys/Kconfig"
source "board/synopsys/axs10x/Kconfig"
source "board/synopsys/emsdp/Kconfig"
source "board/synopsys/hsdk/Kconfig"
source "board/synopsys/iot_devkit/Kconfig"
source "board/synopsys/nsim/Kconfig"
endmenu

32
arch/arc/config.mk
View File

@ -9,21 +9,47 @@ CONFIG_SYS_BIG_ENDIAN = 1
endif
ifdef CONFIG_SYS_LITTLE_ENDIAN
KBUILD_LDFLAGS += -EL
ARC_CROSS_COMPILE := arc-linux-
PLATFORM_LDFLAGS += -EL
PLATFORM_CPPFLAGS += -mlittle-endian
endif
ifdef CONFIG_SYS_BIG_ENDIAN
KBUILD_LDFLAGS += -EB
ARC_CROSS_COMPILE := arceb-linux-
PLATFORM_LDFLAGS += -EB
PLATFORM_CPPFLAGS += -mbig-endian
endif
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := $(ARC_CROSS_COMPILE)
endif
ifdef CONFIG_ARC_MMU_VER
CONFIG_MMU = 1
endif
ifdef CONFIG_CPU_ARC750D
PLATFORM_CPPFLAGS += -mcpu=arc700
endif
ifdef CONFIG_CPU_ARC770D
PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape
endif
ifdef CONFIG_CPU_ARCEM6
PLATFORM_CPPFLAGS += -mcpu=arcem
endif
ifdef CONFIG_CPU_ARCHS34
PLATFORM_CPPFLAGS += -mcpu=archs
endif
ifdef CONFIG_CPU_ARCHS38
PLATFORM_CPPFLAGS += -mcpu=archs
endif
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 -mno-sdata
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
# Needed for relocation
LDFLAGS_FINAL += -pie --gc-sections

19
arch/arc/cpu/u-boot.lds
View File

@ -5,22 +5,13 @@
#include <config.h>
OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc")
OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
OUTPUT_ARCH(arc)
ENTRY(_start)
SECTIONS
{
. = CONFIG_SYS_TEXT_BASE;
__image_copy_start = .;
. = ALIGN(1024);
__ivt_start = .;
.ivt :
{
KEEP(*(.ivt))
}
__ivt_end = .;
. = ALIGN(1024);
__text_start = .;
.text : {
arch/arc/lib/start.o (.text*)
@ -28,6 +19,14 @@ SECTIONS
}
__text_end = .;
. = ALIGN(1024);
__ivt_start = .;
.ivt :
{
*(.ivt)
}
__ivt_end = .;
. = ALIGN(4);
.rodata : {
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))

0
arch/powerpc/dts/.gitignore → arch/arc/dts/.gitignore vendored
View File

4
arch/arc/dts/Makefile
View File

@ -4,9 +4,7 @@ dtb-$(CONFIG_TARGET_AXS101) += axs101.dtb
dtb-$(CONFIG_TARGET_AXS103) += axs103.dtb
dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb
dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
dtb-$(CONFIG_TARGET_EMSDP) += emsdp.dtb
dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb hsdk-4xd.dtb
dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb
targets += $(dtb-y)

2
arch/arc/dts/abilis_tb100.dts
View File

@ -7,8 +7,6 @@
#include "skeleton.dtsi"
/ {
model = "abilis,tb100";
aliases {
console = &uart0;
};

2
arch/arc/dts/axs101.dts
View File

@ -9,8 +9,6 @@
/ {
model = "snps,axs101";
chosen {
stdout-path = &uart0;
};

2
arch/arc/dts/axs103.dts
View File

@ -9,8 +9,6 @@
/ {
model = "snps,axs103";
chosen {
stdout-path = &uart0;
};

69
arch/arc/dts/axs10x_mb.dtsi
View File

@ -4,10 +4,6 @@
*/
/ {
aliases {
spi0 = &spi0;
};
axs10x_mb@e0000000 {
compatible = "simple-bus";
#address-cells = <1>;
@ -31,29 +27,10 @@
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
mmcclk_ciu: mmcclk-ciu {
compatible = "fixed-clock";
/*
* DW sdio controller has external ciu clock divider
* controlled via register in SDIO IP. It divides
* sdio_ref_clk (which comes from CGU) by 16 for
* default. So default mmcclk clock (which comes
* to sdk_in) is 25000000 Hz.
*/
clock-frequency = <25000000>;
#clock-cells = <0>;
};
mmcclk_biu: mmcclk-biu {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
};
ethernet@18000 {
compatible = "snps,arc-dwmac-3.70a";
compatible = "altr,socfpga-stmmac";
reg = < 0x18000 0x2000 >;
phy-mode = "gmii";
snps,pbl = < 32 >;
@ -62,25 +39,16 @@
max-speed = <100>;
};
ehci@40000 {
ehci@0x40000 {
compatible = "generic-ehci";
reg = < 0x40000 0x100 >;
};
ohci@60000 {
ohci@0x60000 {
compatible = "generic-ohci";
reg = < 0x60000 0x100 >;
};
mmc: mmc@15000 {
compatible = "snps,dw-mshc";
reg = <0x15000 0x400>;
bus-width = <4>;
clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
clock-names = "biu", "ciu";
max-frequency = <25000000>;
};
uart0: serial0@22000 {
compatible = "snps,dw-apb-uart";
reg = <0x22000 0x100>;
@ -88,36 +56,5 @@
reg-shift = <2>;
reg-io-width = <4>;
};
spi0: spi@0 {
compatible = "snps,axs10x-spi", "snps,dw-apb-ssi";
reg = <0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <4000000>;
clocks = <&apbclk>;
clock-names = "spi_clk";
num-cs = <1>;
cs-gpios = <&cs_gpio 0>;
spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <4000000>;
};
};
cs_gpio: gpio@11218 {
compatible = "snps,creg-gpio";
reg = <0x11218 0x4>;
gpio-controller;
#gpio-cells = <1>;
gpio-bank-name = "axs-spi-cs";
gpio-count = <1>;
gpio-first-shift = <0>;
gpio-bit-per-line = <2>;
gpio-activate-val = <1>;
gpio-deactivate-val = <3>;
gpio-default-val = <1>;
};
};
};

58
arch/arc/dts/emsdp.dts
View File

@ -1,58 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
*/
/dts-v1/;
#include "skeleton.dtsi"
/ {
model = "snps,emsdp";
#address-cells = <1>;
#size-cells = <1>;
aliases {
console = &uart0;
};
cpu_card {
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <40000000>;
u-boot,dm-pre-reloc;
};
};
uart0: serial0@f0004000 {
compatible = "snps,dw-apb-uart";
clock-frequency = <100000000>;
reg = <0xf0004000 0x1000>;
reg-shift = <2>;
reg-io-width = <4>;
};
mmcclk_biu: mmcclk-biu {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
mmcclk_ciu: mmcclk-ciu {
compatible = "fixed-clock";
clock-frequency = <100000000>;
#clock-cells = <0>;
};
mmc: mmc0@f0010000 {
compatible = "snps,dw-mshc";
reg = <0xf0010000 0x400>;
bus-width = <4>;
fifo-depth = <256>;
clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
clock-names = "biu", "ciu";
max-frequency = <25000000>;
};
};

12
arch/arc/dts/hsdk-4xd.dts
View File

@ -1,12 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 Synopsys, Inc. All rights reserved.
* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
*/
/dts-v1/;
#include "hsdk-common.dtsi"
/ {
model = "snps,hsdk-4xd";
};

160
arch/arc/dts/hsdk-common.dtsi
View File

@ -1,160 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
*/
/dts-v1/;
#include "skeleton.dtsi"
#include "dt-bindings/clock/snps,hsdk-cgu.h"
#include "dt-bindings/reset/snps,hsdk-reset.h"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
console = &uart0;
spi0 = &spi0;
};
cpu_card {
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <500000000>;
u-boot,dm-pre-reloc;
};
};
clk-fmeas {
clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
<&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
<&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
<&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
<&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
<&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
<&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
<&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
<&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
<&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
<&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
<&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
<&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>,
<&cgu_clk CLK_TUN_TIMER>;
clock-names = "cpu-pll", "sys-pll",
"tun-pll", "ddr-clk",
"cpu-clk", "hdmi-pll",
"tun-clk", "hdmi-clk",
"apb-clk", "axi-clk",
"eth-clk", "usb-clk",
"sdio-clk", "hdmi-sys-clk",
"gfx-core-clk", "gfx-dma-clk",
"gfx-cfg-clk", "dmac-core-clk",
"dmac-cfg-clk", "sdio-ref-clk",
"spi-clk", "i2c-clk",
"uart-clk", "ebi-clk",
"rom-clk", "pwm-clk",
"timer-clk";
};
cgu_clk: cgu-clk@f0000000 {
compatible = "snps,hsdk-cgu-clock";
reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
#clock-cells = <1>;
};
cgu_rst: reset-controller@f00008a0 {
compatible = "snps,hsdk-reset";
#reset-cells = <1>;
reg = <0xf00008a0 0x4>, <0xf0000ff0 0x4>;
};
uart0: serial0@f0005000 {
compatible = "snps,dw-apb-uart";
reg = <0xf0005000 0x1000>;
reg-shift = <2>;
reg-io-width = <4>;
};
ethernet@f0008000 {
#interrupt-cells = <1>;
compatible = "snps,arc-dwmac-3.70a";
reg = <0xf0008000 0x2000>;
phy-mode = "gmii";
};
ehci@f0040000 {
compatible = "generic-ehci";
reg = <0xf0040000 0x100>;
/*
* OHCI and EHCI have reset line shared so we don't add
* reset property to OHCI node as it is probed later and
* it will reset sucessfuly probed and configured EHCI HW.
*/
resets = <&cgu_rst HSDK_USB_RESET>;
};
ohci@f0060000 {
compatible = "generic-ohci";
reg = <0xf0060000 0x100>;
};
mmcclk_ciu: mmcclk-ciu {
compatible = "fixed-clock";
/*
* DW sdio controller has external ciu clock divider
* controlled via register in SDIO IP. Due to its
* unexpected default value (it should divide by 1
* but it divides by 8) SDIO IP uses wrong clock and
* works unstable (see STAR 9001204800)
* We switched to the minimum possible value of the
* divisor (div-by-2) in HSDK platform code.
* So default mmcclk ciu clock is 50000000 Hz.
*/
clock-frequency = <50000000>;
#clock-cells = <0>;
};
mmc: mmc0@f000a000 {
compatible = "snps,dw-mshc";
reg = <0xf000a000 0x400>;
bus-width = <4>;
fifo-depth = <256>;
clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
clock-names = "biu", "ciu";
max-frequency = <25000000>;
};
spi0: spi@f0020000 {
compatible = "snps,hsdk-spi", "snps,dw-apb-ssi";
reg = <0xf0020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <4000000>;
clocks = <&cgu_clk CLK_SYS_SPI_REF>;
clock-names = "spi_clk";
num-cs = <1>;
cs-gpios = <&cs_gpio 0>;
spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <4000000>;
};
};
cs_gpio: gpio@f00014b0 {
compatible = "snps,creg-gpio";
reg = <0xf00014b0 0x4>;
gpio-controller;
#gpio-cells = <1>;
gpio-bank-name = "hsdk-spi-cs";
gpio-count = <1>;
gpio-first-shift = <0>;
gpio-bit-per-line = <2>;
gpio-activate-val = <2>;
gpio-deactivate-val = <3>;
gpio-default-val = <1>;
};
};

107
arch/arc/dts/hsdk.dts
View File

@ -1,12 +1,111 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
* Copyright (C) 2017 Synopsys, Inc. All rights reserved.
*/
/dts-v1/;
#include "hsdk-common.dtsi"
#include "skeleton.dtsi"
#include "dt-bindings/clock/snps,hsdk-cgu.h"
/ {
model = "snps,hsdk";
#address-cells = <1>;
#size-cells = <1>;
aliases {
console = &uart0;
spi0 = &spi0;
};
cpu_card {
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <1000000000>;
u-boot,dm-pre-reloc;
};
};
clk-fmeas {
clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
<&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
<&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
<&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
<&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
<&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
<&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
<&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
<&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
<&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
<&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
<&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
<&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
clock-names = "cpu-pll", "sys-pll",
"tun-pll", "ddr-clk",
"cpu-clk", "hdmi-pll",
"tun-clk", "hdmi-clk",
"apb-clk", "axi-clk",
"eth-clk", "usb-clk",
"sdio-clk", "hdmi-sys-clk",
"gfx-core-clk", "gfx-dma-clk",
"gfx-cfg-clk", "dmac-core-clk",
"dmac-cfg-clk", "sdio-ref-clk",
"spi-clk", "i2c-clk",
"uart-clk", "ebi-clk",
"rom-clk", "pwm-clk";
};
cgu_clk: cgu-clk@f0000000 {
compatible = "snps,hsdk-cgu-clock";
reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
#clock-cells = <1>;
};
uart0: serial0@f0005000 {
compatible = "snps,dw-apb-uart";
reg = <0xf0005000 0x1000>;
reg-shift = <2>;
reg-io-width = <4>;
};
ethernet@f0008000 {
#interrupt-cells = <1>;
compatible = "altr,socfpga-stmmac";
reg = <0xf0008000 0x2000>;
phy-mode = "gmii";
};
ehci@0xf0040000 {
compatible = "generic-ehci";
reg = <0xf0040000 0x100>;
};
ohci@0xf0060000 {
compatible = "generic-ohci";
reg = <0xf0060000 0x100>;
};
spi0: spi@f0020000 {
compatible = "snps,dw-apb-ssi";
reg = <0xf0020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <4000000>;
clocks = <&cgu_clk CLK_SYS_SPI_REF>;
clock-names = "spi_clk";
cs-gpio = <&cs_gpio 0>;
spi_flash@0 {
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <4000000>;
};
};
cs_gpio: gpio@f00014b0 {
compatible = "snps,hsdk-creg-gpio";
reg = <0xf00014b0 0x4>;
gpio-controller;
#gpio-cells = <1>;
gpio-bank-name = "hsdk-spi-cs";
gpio-count = <1>;
};
};

67
arch/arc/dts/iot_devkit.dts
View File

@ -1,67 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
*/
/dts-v1/;
#include "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
console = &uart0;
};
cpu_card {
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <144000000>;
u-boot,dm-pre-reloc;
};
};
uart0: serial0@80014000 {
compatible = "snps,dw-apb-uart";
clock-frequency = <16000000>;
reg = <0x80014000 0x1000>;
reg-shift = <2>;
reg-io-width = <4>;
};
usb: usb@f0040000 {
compatible = "snps,dwc2";
reg = <0xf0040000 0x10000>;
phys = <&usbphy>;
phy-names = "usb2-phy";
};
usbphy: phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
mmcclk_biu: mmcclk-biu {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
mmcclk_ciu: mmcclk-ciu {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
mmc: mmc0@f000b000 {
compatible = "snps,dw-mshc";
reg = <0xf000b000 0x400>;
bus-width = <4>;
fifo-depth = <128>;
clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
clock-names = "biu", "ciu";
max-frequency = <25000000>;
};
};

38
arch/arc/dts/nsim.dts
View File

@ -1,16 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015-2016, 2020 Synopsys, Inc. (www.synopsys.com)
* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
*/
/dts-v1/;
#include "skeleton.dtsi"
/ {
model = "snps,nsim";
aliases {
console = &uart0;
console = &arcuart0;
};
cpu_card {
@ -22,36 +20,10 @@
};
};
uart0: serial@f0000000 {
compatible = "snps,dw-apb-uart";
reg = <0xf0000000 0x1000>;
reg-shift = <2>;
reg-io-width = <4>;
arcuart0: serial@0xc0fc1000 {
compatible = "snps,arc-uart";
reg = <0xc0fc1000 0x100>;
clock-frequency = <70000000>;
};
virtio0: virtio@f0100000 {
compatible = "virtio,mmio";
reg = <0xf0100000 0x2000>;
};
virtio1: virtio@f0102000 {
compatible = "virtio,mmio";
reg = <0xf0102000 0x2000>;
};
virtio2: virtio@f0104000 {
compatible = "virtio,mmio";
reg = <0xf0104000 0x2000>;
};
virtio3: virtio@f0106000 {
compatible = "virtio,mmio";
reg = <0xf0106000 0x2000>;
};
virtio4: virtio@f0108000 {
compatible = "virtio,mmio";
reg = <0xf0108000 0x2000>;
};
};

34
arch/arc/include/asm/arcregs.h
View File

@ -16,26 +16,9 @@
* access: "lr"/"sr".
*/
/*
* Typically 8 least significant bits of Build Configuration Register (BCR)
* describe version of the HW block in question. Moreover if decoded version
* is 0 this means given HW block is absent - this is especially useful because
* we may safely read BRC regardless HW block existence while an attempt to
* access any other AUX regs associated with this HW block lead to imediate
* "instruction error" exception.
*
* I.e. before using any cofigurable HW block it's required to make sure it
* exists at all, and for that we introduce a special macro below.
*/
#define ARC_BCR_VERSION_MASK GENMASK(7, 0)
#define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK)
#define ARC_AUX_IDENTITY 0x04
#define ARC_AUX_STATUS32 0x0a
/* STATUS32 Bits Positions */
#define STATUS_AD_BIT 19 /* Enable unaligned access */
/* Instruction cache related auxiliary registers */
#define ARC_AUX_IC_IVIC 0x10
#define ARC_AUX_IC_CTRL 0x11
@ -51,9 +34,6 @@
#define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
/* CSM auxiliary registers */
#define ARC_AUX_CSM_ENABLE 0x9A0
/* Timer related auxiliary registers */
#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
#define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
@ -90,7 +70,7 @@
#define ARC_BCR_CLUSTER 0xcf
/* MMU Management regs */
#define ARC_AUX_MMU_BCR 0x6f
#define ARC_AUX_MMU_BCR 0x06f
/* IO coherency related auxiliary registers */
#define ARC_AUX_IO_COH_ENABLE 0x500
@ -98,19 +78,7 @@
#define ARC_AUX_IO_COH_AP0_BASE 0x508
#define ARC_AUX_IO_COH_AP0_SIZE 0x509
/* XY-memory related */
#define ARC_AUX_XY_BUILD 0x79
/* DSP-extensions related auxiliary registers */
#define ARC_AUX_DSP_BUILD 0x7A
#define ARC_AUX_DSP_CTRL 0x59F
/* ARC Subsystems related auxiliary registers */
#define ARC_AUX_SUBSYS_BUILD 0xF0
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
/* Accessors for auxiliary registers */
#define read_aux_reg(reg) __builtin_arc_lr(reg)

10
arch/arc/include/asm/cache.h
View File

@ -16,9 +16,6 @@
*/
#define ARCH_DMA_MINALIGN 128
/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
#if defined(ARC_MMU_ABSENT)
#define CONFIG_ARC_MMU_VER 0
#elif defined(CONFIG_ARC_MMU_V2)
@ -40,13 +37,6 @@ static const inline int is_ioc_enabled(void)
return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
}
/*
* We export SLC control functions to use them in platform configuration code.
* They maust not be used in any generic code!
*/
void slc_enable(void);
void slc_disable(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARC_CACHE_H */

2
arch/arc/include/asm/config.h
View File

@ -8,4 +8,6 @@
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#define CONFIG_LMB
#endif /*__ASM_ARC_CONFIG_H_ */

1
arch/arc/include/asm/dma-mapping.h
View File

@ -1 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */

2
arch/arc/include/asm/global_data.h
View File

@ -6,6 +6,8 @@
#ifndef __ASM_ARC_GLOBAL_DATA_H
#define __ASM_ARC_GLOBAL_DATA_H
#include <config.h>
#ifndef __ASSEMBLY__
/* Architecture-specific global data */
struct arch_global_data {

240
arch/arc/include/asm/io.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2014, 2020 Synopsys, Inc. All rights reserved.
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
#ifndef __ASM_ARC_IO_H
@ -9,12 +9,6 @@
#include <linux/types.h>
#include <asm/byteorder.h>
/*
* Compiler barrier. It prevents compiler from reordering instructions before
* and after it. It doesn't prevent HW (CPU) from any reordering though.
*/
#define __comp_b() asm volatile("" : : : "memory")
#ifdef __ARCHS__
/*
@ -51,8 +45,8 @@
#define __iormb() rmb()
#define __iowmb() wmb()
#else
#define __iormb() __comp_b()
#define __iowmb() __comp_b()
#define __iormb() asm volatile("" : : : "memory")
#define __iowmb() asm volatile("" : : : "memory")
#endif
static inline void sync(void)
@ -60,117 +54,134 @@ static inline void sync(void)
/* Not yet implemented */
}
/*
* We must use 'volatile' in C-version read/write IO accessors implementation
* to avoid merging several reads (writes) into one read (write), or optimizing
* them out by compiler.
* We must use compiler barriers before and after operation (read or write) so
* it won't be reordered by compiler.
*/
#define __arch_getb(a) ({ u8 __v; __comp_b(); __v = *(volatile u8 *)(a); __comp_b(); __v; })
#define __arch_getw(a) ({ u16 __v; __comp_b(); __v = *(volatile u16 *)(a); __comp_b(); __v; })
#define __arch_getl(a) ({ u32 __v; __comp_b(); __v = *(volatile u32 *)(a); __comp_b(); __v; })
#define __arch_getq(a) ({ u64 __v; __comp_b(); __v = *(volatile u64 *)(a); __comp_b(); __v; })
#define __arch_putb(v, a) ({ __comp_b(); *(volatile u8 *)(a) = (v); __comp_b(); })
#define __arch_putw(v, a) ({ __comp_b(); *(volatile u16 *)(a) = (v); __comp_b(); })
#define __arch_putl(v, a) ({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); })
#define __arch_putq(v, a) ({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); })
/*
* We add memory barriers for __raw_readX / __raw_writeX accessors same way as
* it is done for readX and writeX accessors as lots of U-boot driver uses
* __raw_readX / __raw_writeX instead of proper accessor with barrier.
*/
#define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); })
#define __raw_writew(v, c) ({ __iowmb(); __arch_putw(v, c); })
#define __raw_writel(v, c) ({ __iowmb(); __arch_putl(v, c); })
#define __raw_writeq(v, c) ({ __iowmb(); __arch_putq(v, c); })
#define __raw_readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
#define __raw_readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
#define __raw_readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
#define __raw_readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
static inline void __raw_writesb(unsigned long addr, const void *data,
int bytelen)
static inline u8 __raw_readb(const volatile void __iomem *addr)
{
u8 *buf = (uint8_t *)data;
u8 b;
__iowmb();
while (bytelen--)
__arch_putb(*buf++, addr);
__asm__ __volatile__("ldb%U1 %0, %1\n"
: "=r" (b)
: "m" (*(volatile u8 __force *)addr)
: "memory");
return b;
}
static inline void __raw_writesw(unsigned long addr, const void *data,
int wordlen)
static inline u16 __raw_readw(const volatile void __iomem *addr)
{
u16 *buf = (uint16_t *)data;
u16 s;
__iowmb();
while (wordlen--)
__arch_putw(*buf++, addr);
__asm__ __volatile__("ldw%U1 %0, %1\n"
: "=r" (s)
: "m" (*(volatile u16 __force *)addr)
: "memory");
return s;
}
static inline void __raw_writesl(unsigned long addr, const void *data,
int longlen)
static inline u32 __raw_readl(const volatile void __iomem *addr)
{
u32 *buf = (uint32_t *)data;
u32 w;
__iowmb();
while (longlen--)
__arch_putl(*buf++, addr);
__asm__ __volatile__("ld%U1 %0, %1\n"
: "=r" (w)
: "m" (*(volatile u32 __force *)addr)
: "memory");
return w;
}
static inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
{
u8 *buf = (uint8_t *)data;
while (bytelen--)
*buf++ = __arch_getb(addr);
__iormb();
__asm__ __volatile__("stb%U1 %0, %1\n"
:
: "r" (b), "m" (*(volatile u8 __force *)addr)
: "memory");
}
static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
static inline void __raw_writew(u16 s, volatile void __iomem *addr)
{
u16 *buf = (uint16_t *)data;
while (wordlen--)
*buf++ = __arch_getw(addr);
__iormb();
__asm__ __volatile__("stw%U1 %0, %1\n"
:
: "r" (s), "m" (*(volatile u16 __force *)addr)
: "memory");
}
static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
static inline void __raw_writel(u32 w, volatile void __iomem *addr)
{
u32 *buf = (uint32_t *)data;
while (longlen--)
*buf++ = __arch_getl(addr);
__iormb();
__asm__ __volatile__("st%U1 %0, %1\n"
:
: "r" (w), "m" (*(volatile u32 __force *)addr)
: "memory");
}
/*
* Relaxed I/O memory access primitives. These follow the Device memory
* ordering rules but do not guarantee any ordering relative to Normal memory
* accesses.
*/
#define readb_relaxed(c) ({ u8 __r = __arch_getb(c); __r; })
#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__arch_getw(c)); __r; })
#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__arch_getl(c)); __r; })
#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__arch_getq(c)); __r; })
static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
{
__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
"sub.f r2, r2, 1\n"
"bnz.d 1b\n"
"stb.ab r8, [r1, 1]\n"
:
: "r" (addr), "r" (data), "r" (bytelen)
: "r8");
return bytelen;
}
#define writeb_relaxed(v, c) ((void)__arch_putb((v), (c)))
#define writew_relaxed(v, c) ((void)__arch_putw((__force u16)cpu_to_le16(v), (c)))
#define writel_relaxed(v, c) ((void)__arch_putl((__force u32)cpu_to_le32(v), (c)))
#define writeq_relaxed(v, c) ((void)__arch_putq((__force u64)cpu_to_le64(v), (c)))
static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
{
__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
"sub.f r2, r2, 1\n"
"bnz.d 1b\n"
"stw.ab r8, [r1, 2]\n"
:
: "r" (addr), "r" (data), "r" (wordlen)
: "r8");
return wordlen;
}
static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
{
__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
"sub.f r2, r2, 1\n"
"bnz.d 1b\n"
"st.ab r8, [r1, 4]\n"
:
: "r" (addr), "r" (data), "r" (longlen)
: "r8");
return longlen;
}
static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
{
__asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n"
"sub.f r2, r2, 1\n"
"bnz.d 1b\n"
"st.di r8, [r0, 0]\n"
:
: "r" (addr), "r" (data), "r" (bytelen)
: "r8");
return bytelen;
}
static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
{
__asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n"
"sub.f r2, r2, 1\n"
"bnz.d 1b\n"
"st.ab.di r8, [r0, 0]\n"
:
: "r" (addr), "r" (data), "r" (wordlen)
: "r8");
return wordlen;
}
static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
{
__asm__ __volatile__ ("1:ld.ab r8, [r1, 4]\n"
"sub.f r2, r2, 1\n"
"bnz.d 1b\n"
"st.ab.di r8, [r0, 0]\n"
:
: "r" (addr), "r" (data), "r" (longlen)
: "r8");
return longlen;
}
/*
* MMIO can also get buffered/optimized in micro-arch, so barriers needed
@ -184,15 +195,32 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
*
* http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
*/
#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
#define writeb(v, c) ({ __iowmb(); writeb_relaxed(v, c); })
#define writew(v, c) ({ __iowmb(); writew_relaxed(v, c); })
#define writel(v, c) ({ __iowmb(); writel_relaxed(v, c); })
#define writeq(v, c) ({ __iowmb(); writeq_relaxed(v, c); })
#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
/*
* Relaxed API for drivers which can handle barrier ordering themselves
*
* Also these are defined to perform little endian accesses.
* To provide the typical device register semantics of fixed endian,
* swap the byte order for Big Endian
*
* http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
*/
#define readb_relaxed(c) __raw_readb(c)
#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
__raw_readw(c)); __r; })
#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
__raw_readl(c)); __r; })
#define writeb_relaxed(v,c) __raw_writeb(v,c)
#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))

36
arch/arc/include/asm/types.h
View File

@ -6,10 +6,42 @@
#ifndef __ASM_ARC_TYPES_H
#define __ASM_ARC_TYPES_H
#include <asm-generic/int-ll64.h>
typedef unsigned short umode_t;
/*
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
* header files exported to user space
*/
typedef __signed__ char __s8;
typedef unsigned char __u8;
typedef __signed__ short __s16;
typedef unsigned short __u16;
typedef __signed__ int __s32;
typedef unsigned int __u32;
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
typedef __signed__ long long __s64;
typedef unsigned long long __u64;
#endif
/*
* These aren't exported outside the kernel to avoid name space clashes
*/
typedef signed char s8;
typedef unsigned char u8;
typedef signed short s16;
typedef unsigned short u16;
typedef signed int s32;
typedef unsigned int u32;
typedef signed long long s64;
typedef unsigned long long u64;
#define BITS_PER_LONG 32
/* Dma addresses are 32-bits wide. */

9
arch/arc/lib/bootm.c
View File

@ -3,15 +3,8 @@
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
#include <common.h>
#include <bootstage.h>
#include <env.h>
#include <image.h>
#include <irq_func.h>
#include <lmb.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;

133
arch/arc/lib/cache.c
View File

@ -5,9 +5,6 @@
#include <config.h>
#include <common.h>
#include <cpu_func.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/log2.h>
@ -91,7 +88,8 @@
*
* [ NOTE 2 ]:
* As of today we only support the following cache configurations on ARC.
* Other configurations may exist in HW but we don't support it in SW.
* Other configurations may exist in HW (for example, since version 3.0 HS
* supports SL$ (L2 system level cache) disable) but we don't support it in SW.
* Configuration 1:
* ______________________
* | |
@ -121,8 +119,7 @@
* | |
* | L2 (SL$) |
* |______________________|
* always on (ARCv2, HS < 3.0)
* on/off (ARCv2, HS >= 3.0)
* always must be on
* ___|______________|____
* | |
* | main memory |
@ -180,8 +177,6 @@ DECLARE_GLOBAL_DATA_PTR;
static inlined_cachefunc void __ic_entire_invalidate(void);
static inlined_cachefunc void __dc_entire_op(const int cacheop);
static inlined_cachefunc void __slc_entire_op(const int op);
static inlined_cachefunc bool ioc_enabled(void);
static inline bool pae_exists(void)
{
@ -242,70 +237,6 @@ static inlined_cachefunc bool slc_exists(void)
return false;
}
enum slc_dis_status {
ST_SLC_MISSING = 0,
ST_SLC_NO_DISABLE_CTRL,
ST_SLC_DISABLE_CTRL
};
/*
* ARCv1 -> ST_SLC_MISSING
* ARCv2 && SLC absent -> ST_SLC_MISSING
* ARCv2 && SLC exists && SLC version <= 2 -> ST_SLC_NO_DISABLE_CTRL
* ARCv2 && SLC exists && SLC version > 2 -> ST_SLC_DISABLE_CTRL
*/
static inlined_cachefunc enum slc_dis_status slc_disable_supported(void)
{
if (is_isa_arcv2()) {
union bcr_generic sbcr;
sbcr.word = read_aux_reg(ARC_BCR_SLC);
if (sbcr.fields.ver == 0)
return ST_SLC_MISSING;
else if (sbcr.fields.ver <= 2)
return ST_SLC_NO_DISABLE_CTRL;
else
return ST_SLC_DISABLE_CTRL;
}
return ST_SLC_MISSING;
}
static inlined_cachefunc bool __slc_enabled(void)
{
return !(read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_DIS);
}
static inlined_cachefunc void __slc_enable(void)
{
unsigned int ctrl;
ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
ctrl &= ~SLC_CTRL_DIS;
write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
}
static inlined_cachefunc void __slc_disable(void)
{
unsigned int ctrl;
ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
ctrl |= SLC_CTRL_DIS;
write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
}
static inlined_cachefunc bool slc_enabled(void)
{
enum slc_dis_status slc_status = slc_disable_supported();
if (slc_status == ST_SLC_MISSING)
return false;
else if (slc_status == ST_SLC_NO_DISABLE_CTRL)
return true;
else
return __slc_enabled();
}
static inlined_cachefunc bool slc_data_bypass(void)
{
/*
@ -315,40 +246,7 @@ static inlined_cachefunc bool slc_data_bypass(void)
return !dcache_enabled();
}
void slc_enable(void)
{
if (slc_disable_supported() != ST_SLC_DISABLE_CTRL)
return;
if (__slc_enabled())
return;
__slc_enable();
}
/* TODO: warn if we are not able to disable SLC */
void slc_disable(void)
{
if (slc_disable_supported() != ST_SLC_DISABLE_CTRL)
return;
/* we don't support SLC disabling if we use IOC */
if (ioc_enabled())
return;
if (!__slc_enabled())
return;
/*
* We need to flush L1D$ to guarantee that we won't have any
* writeback operations during SLC disabling.
*/
__dc_entire_op(OP_FLUSH);
__slc_entire_op(OP_FLUSH_N_INV);
__slc_disable();
}
static inlined_cachefunc bool ioc_exists(void)
static inline bool ioc_exists(void)
{
if (is_isa_arcv2()) {
union bcr_clust_cfg cbcr;
@ -360,7 +258,7 @@ static inlined_cachefunc bool ioc_exists(void)
return false;
}
static inlined_cachefunc bool ioc_enabled(void)
static inline bool ioc_enabled(void)
{
/*
* We check only CONFIG option instead of IOC HW state check as IOC
@ -376,7 +274,7 @@ static inlined_cachefunc void __slc_entire_op(const int op)
{
unsigned int ctrl;
if (!slc_enabled())
if (!slc_exists())
return;
ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
@ -425,7 +323,7 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
unsigned int ctrl;
unsigned long end;
if (!slc_enabled())
if (!slc_exists())
return;
/*
@ -483,9 +381,6 @@ static void arc_ioc_setup(void)
if (!slc_exists())
panic("Try to enable IOC but SLC is not present");
if (!slc_enabled())
panic("Try to enable IOC but SLC is disabled");
/* Unsupported configuration. See [ NOTE 2 ] for more details. */
if (!dcache_enabled())
panic("Try to enable IOC but L1 D$ is disabled");
@ -537,16 +432,9 @@ void read_decode_cache_bcr(void)
int dc_line_sz = 0, ic_line_sz = 0;
union bcr_di_cache ibcr, dbcr;
/*
* We don't care much about I$ line length really as there're
* no per-line ops on I$ instead we only do full invalidation of it
* on occasion of relocation and right before jumping to the OS.
* Still we check insane config with zero-encoded line length in
* presense of version field in I$ BCR. Just in case.
*/
ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
if (ibcr.fields.ver) {
ic_line_sz = 8 << ibcr.fields.line_len;
gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
if (!ic_line_sz)
panic("Instruction exists but line length is 0\n");
}
@ -557,6 +445,9 @@ void read_decode_cache_bcr(void)
if (!dc_line_sz)
panic("Data cache exists but line length is 0\n");
}
if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz))
panic("Instruction and data cache line lengths differ\n");
}
void cache_init(void)
@ -621,6 +512,8 @@ void invalidate_icache_all(void)
/*
* If SL$ is bypassed for data it is used only for instructions,
* so we need to invalidate it too.
* TODO: HS 3.0 supports SLC disable so we need to check slc
* enable/disable status here.
*/
if (is_isa_arcv2() && slc_data_bypass())
__slc_entire_op(OP_INV);

206
arch/arc/lib/cpu.c
View File

@ -1,16 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved.
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*/
#include <common.h>
#include <init.h>
#include <malloc.h>
#include <vsprintf.h>
#include <asm/arcregs.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
@ -26,200 +21,15 @@ int arch_cpu_init(void)
return 0;
}
int arch_early_init_r(void)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
/* This is a dummy function on arc */
int dram_init(void)
{
return 0;
}
#ifdef CONFIG_DISPLAY_CPUINFO
const char *arc_700_version(int arcver, char *name, int name_len)
{
const char *arc_ver;
switch (arcver) {
case 0x32:
arc_ver = "v4.4-4.5";
break;
case 0x33:
arc_ver = "v4.6-v4.9";
break;
case 0x34:
arc_ver = "v4.10";
break;
case 0x35:
arc_ver = "v4.11";
break;
default:
arc_ver = "unknown version";
}
snprintf(name, name_len, "ARC 700 %s", arc_ver);
return name;
}
struct em_template_t {
const bool cache;
const bool dsp;
const bool xymem;
const char name[8];
};
static const struct em_template_t em_versions[] = {
{false, false, false, "EM4"},
{true, false, false, "EM6"},
{false, true, false, "EM5D"},
{true, true, false, "EM7D"},
{false, true, true, "EM9D"},
{true, true, true, "EM11D"},
};
const char *arc_em_version(int arcver, char *name, int name_len)
{
const char *arc_name = "EM";
const char *arc_ver;
bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD);
bool dsp = ARC_FEATURE_EXISTS(ARC_AUX_DSP_BUILD);
bool xymem = ARC_FEATURE_EXISTS(ARC_AUX_XY_BUILD);
int i;
for (i = 0; i < sizeof(em_versions) / sizeof(struct em_template_t); i++) {
if (em_versions[i].cache == cache &&
em_versions[i].dsp == dsp &&
em_versions[i].xymem == xymem) {
arc_name = em_versions[i].name;
break;
}
}
switch (arcver) {
case 0x41:
arc_ver = "v1.1a";
break;
case 0x42:
arc_ver = "v3.0";
break;
case 0x43:
arc_ver = "v4.0";
break;
case 0x44:
arc_ver = "v5.0";
break;
default:
arc_ver = "unknown version";
}
snprintf(name, name_len, "ARC %s %s", arc_name, arc_ver);
return name;
}
struct hs_template_t {
const bool cache;
const bool mmu;
const bool dual_issue;
const bool dsp;
const char name[8];
};
static const struct hs_template_t hs_versions[] = {
{false, false, false, false, "HS34"},
{true, false, false, false, "HS36"},
{true, true, false, false, "HS38"},
{false, false, true, false, "HS44"},
{true, false, true, false, "HS46"},
{true, true, true, false, "HS48"},
{false, false, true, true, "HS45D"},
{true, false, true, true, "HS47D"},
};
const char *arc_hs_version(int arcver, char *name, int name_len)
{
const char *arc_name = "HS";
const char *arc_ver;
bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD);
bool dsp = ARC_FEATURE_EXISTS(ARC_AUX_DSP_BUILD);
bool mmu = !!read_aux_reg(ARC_AUX_MMU_BCR);
bool dual_issue = arcver == 0x54 ? true : false;
int i;
for (i = 0; i < sizeof(hs_versions) / sizeof(struct hs_template_t); i++) {
if (hs_versions[i].cache == cache &&
hs_versions[i].mmu == mmu &&
hs_versions[i].dual_issue == dual_issue &&
hs_versions[i].dsp == dsp) {
arc_name = hs_versions[i].name;
break;
}
}
switch (arcver) {
case 0x50:
arc_ver = "v1.0";
break;
case 0x51:
arc_ver = "v2.0";
break;
case 0x52:
arc_ver = "v2.1c";
break;
case 0x53:
arc_ver = "v3.0";
break;
case 0x54:
arc_ver = "v4.0";
break;
default:
arc_ver = "unknown version";
}
snprintf(name, name_len, "ARC %s %s", arc_name, arc_ver);
return name;
}
const char *decode_identity(void)
{
#define MAX_CPU_NAME_LEN 64
int arcver = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
char *name = malloc(MAX_CPU_NAME_LEN);
if (arcver >= 0x50)
return arc_hs_version(arcver, name, MAX_CPU_NAME_LEN);
else if (arcver >= 0x40)
return arc_em_version(arcver, name, MAX_CPU_NAME_LEN);
else if (arcver >= 0x30)
return arc_700_version(arcver, name, MAX_CPU_NAME_LEN);
else
return "Unknown ARC core";
}
const char *decode_subsystem(void)
{
int subsys_type = read_aux_reg(ARC_AUX_SUBSYS_BUILD) & GENMASK(3, 0);
switch (subsys_type) {
case 0: return NULL;
case 2: return "ARC Sensor & Control IP Subsystem";
case 3: return "ARC Data Fusion IP Subsystem";
case 4: return "ARC Secure Subsystem";
default: return "Unknown subsystem";
};
}
__weak int print_cpuinfo(void)
{
const char *subsys_name = decode_subsystem();
char mhz[8];
printf("CPU: %s at %s MHz\n", decode_identity(),
strmhz(mhz, gd->cpu_clk));
if (subsys_name)
printf("Subsys:%s\n", subsys_name);
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */

1
arch/arc/lib/init_helpers.c
View File

@ -3,7 +3,6 @@
* Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
*/
#include <init.h>
#include <asm/cache.h>
#include <common.h>

1
arch/arc/lib/interrupts.c
View File

@ -4,7 +4,6 @@
*/
#include <common.h>
#include <irq_func.h>
#include <asm/arcregs.h>
#include <asm/ptrace.h>

75
arch/arc/lib/libgcc2.c
View File

@ -158,78 +158,3 @@ __umodsi3(long a, long b)
{
return udivmodsi4(a, b, 1);
}
UDWtype
__udivmoddi4(UDWtype n, UDWtype d, UDWtype *rp)
{
UDWtype q = 0, r = n, y = d;
UWtype lz1, lz2, i, k;
/*
* Implements align divisor shift dividend method. This algorithm
* aligns the divisor under the dividend and then perform number of
* test-subtract iterations which shift the dividend left. Number of
* iterations is k + 1 where k is the number of bit positions the
* divisor must be shifted left to align it under the dividend.
* quotient bits can be saved in the rightmost positions of the
* dividend as it shifts left on each test-subtract iteration.
*/
if (y <= r) {
lz1 = __builtin_clzll(d);
lz2 = __builtin_clzll(n);
k = lz1 - lz2;
y = (y << k);
/*
* Dividend can exceed 2 ^ (width - 1) - 1 but still be less
* than the aligned divisor. Normal iteration can drops the
* high order bit of the dividend. Therefore, first
* test-subtract iteration is a special case, saving its
* quotient bit in a separate location and not shifting
* the dividend.
*/
if (r >= y) {
r = r - y;
q = (1ULL << k);
}
if (k > 0) {
y = y >> 1;
/*
* k additional iterations where k regular test
* subtract shift dividend iterations are done.
*/
i = k;
do {
if (r >= y)
r = ((r - y) << 1) + 1;
else
r = (r << 1);
i = i - 1;
} while (i != 0);
/*
* First quotient bit is combined with the quotient
* bits resulting from the k regular iterations.
*/
q = q + r;
r = r >> k;
q = q - (r << k);
}
}
if (rp)
*rp = r;
return q;
}
UDWtype
__udivdi3(UDWtype n, UDWtype d)
{
return __udivmoddi4(n, d, (UDWtype *)0);
}

78
arch/arc/lib/relocate.c
View File

@ -5,14 +5,10 @@
#include <common.h>
#include <elf.h>
#include <log.h>
#include <asm-generic/sections.h>
#include <asm/global_data.h>
extern ulong __image_copy_start;
extern ulong __ivt_start;
extern ulong __ivt_end;
extern ulong __text_end;
DECLARE_GLOBAL_DATA_PTR;
@ -52,7 +48,7 @@ int do_elf_reloc_fixups(void)
debug("Section .rela.dyn is located at %08x-%08x\n",
(unsigned int)re_src, (unsigned int)re_end);
Elf32_Addr *offset_ptr_rom;
Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
Elf32_Addr *offset_ptr_ram;
do {
@ -61,28 +57,15 @@ int do_elf_reloc_fixups(void)
/* Check that the location of the relocation is in .text */
if (offset_ptr_rom >= (Elf32_Addr *)&__image_copy_start &&
offset_ptr_rom < (Elf32_Addr *)&__image_copy_end) {
unsigned int val, do_swap = 0;
offset_ptr_rom > last_offset) {
unsigned int val;
/* Switch to the in-RAM version */
offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
gd->reloc_off);
#ifdef __LITTLE_ENDIAN__
/* If location in ".text" section swap value */
if (((u32)offset_ptr_rom >= (u32)&__text_start &&
(u32)offset_ptr_rom <= (u32)&__text_end)
#if defined(__ARC700__) || defined(__ARC600__)
|| ((u32)offset_ptr_rom >= (u32)&__ivt_start &&
(u32)offset_ptr_rom <= (u32)&__ivt_end)
#endif
)
do_swap = 1;
#endif
debug("Patching value @ %08x (relocated to %08x)%s\n",
debug("Patching value @ %08x (relocated to %08x)\n",
(unsigned int)offset_ptr_rom,
(unsigned int)offset_ptr_ram,
do_swap ? ", middle-endian encoded" : "");
(unsigned int)offset_ptr_ram);
/*
* Use "memcpy" because target location might be
@ -92,45 +75,28 @@ int do_elf_reloc_fixups(void)
*/
memcpy(&val, offset_ptr_ram, sizeof(int));
if (do_swap)
#ifdef __LITTLE_ENDIAN__
/* If location in ".text" section swap value */
if ((unsigned int)offset_ptr_rom <
(unsigned int)&__ivt_end)
val = (val << 16) | (val >> 16);
#endif
/* Check that the target points into executable */
if (val < (unsigned int)&__image_copy_start ||
val > (unsigned int)&__image_copy_end) {
/* TODO: Use panic() instead of debug()
*
* For some reason GCC might generate
* fake relocation even for LD/SC of constant
* inderectly. See an example below:
* ----------------------->8--------------------
* static int setup_mon_len(void)
* {
* gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
* return 0;
* }
* ----------------------->8--------------------
*
* And that's what we get in the binary:
* ----------------------->8--------------------
* 10005cb4 <setup_mon_len>:
* 10005cb4: 193c 3f80 0003 2f80 st 0x32f80,[r25,60]
* 10005cb8: R_ARC_RELATIVE *ABS*-0x10000000
* 10005cbc: 7fe0 j_s.d [blink]
* 10005cbe: 700c mov_s r0,0
* ----------------------->8--------------------
*/
debug("Relocation target %08x points outside of image\n",
val);
if (val >= (unsigned int)&__image_copy_start && val <=
(unsigned int)&__image_copy_end) {
val += gd->reloc_off;
#ifdef __LITTLE_ENDIAN__
/* If location in ".text" section swap value */
if ((unsigned int)offset_ptr_rom <
(unsigned int)&__ivt_end)
val = (val << 16) | (val >> 16);
#endif
memcpy(offset_ptr_ram, &val, sizeof(int));
}
val += gd->reloc_off;
if (do_swap)
val = (val << 16) | (val >> 16);
memcpy(offset_ptr_ram, &val, sizeof(int));
}
last_offset = offset_ptr_rom;
} while (++re_src < re_end);
return 0;

17
arch/arc/lib/reset.c
View File

@ -5,19 +5,14 @@
#include <command.h>
#include <common.h>
#include <cpu_func.h>
__weak void reset_cpu(void)
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
printf("Put your restart handler here\n");
#ifdef DEBUG
/* Stop debug session here */
__builtin_arc_brk();
}
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
printf("Resetting the board...\n");
reset_cpu();
__asm__("brk");
#endif
return 0;
}

33
arch/arc/lib/start.S
View File

@ -16,7 +16,7 @@ ENTRY(_start)
lr r5, [ARC_BCR_IC_BUILD]
breq r5, 0, 1f ; I$ doesn't exist
lr r5, [ARC_AUX_IC_CTRL]
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifndef CONFIG_SYS_ICACHE_OFF
bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
#else
bset r5, r5, 0 ; I$ exists, but is not used
@ -37,7 +37,7 @@ ENTRY(_start)
breq r5, 0, 1f ; D$ doesn't exist
lr r5, [ARC_AUX_DC_CTRL]
bclr r5, r5, 6 ; Invalidate (discard w/o wback)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifndef CONFIG_SYS_DCACHE_OFF
bclr r5, r5, 0 ; Enable (+Inv)
#else
bset r5, r5, 0 ; Disable (+Inv)
@ -61,30 +61,6 @@ ENTRY(_start)
1:
#endif
#ifdef CONFIG_ISA_ARCV2
; In case of DSP extension presence in HW some instructions
; (related to integer multiply, multiply-accumulate, and divide
; operation) executes on this DSP execution unit. So their
; execution will depend on dsp configuration register (DSP_CTRL)
; As we want these instructions to execute the same way regardless
; of DSP presence we need to set DSP_CTRL properly.
lr r5, [ARC_AUX_DSP_BUILD]
bmsk r5, r5, 7
breq r5, 0, 1f
mov r5, 0
sr r5, [ARC_AUX_DSP_CTRL]
1:
#endif
#ifdef __ARC_UNALIGNED__
/*
* Enable handling of unaligned access in the CPU as by default
* this HW feature is disabled while GCC starting from 8.1.0
* unconditionally uses it for ARC HS cores.
*/
flag 1 << STATUS_AD_BIT
#endif
/* Establish C runtime stack and frame */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %fp, %sp
@ -99,11 +75,6 @@ ENTRY(_start)
/* Initialize reserved area - note: r0 already contains address */
bl board_init_f_init_reserve
#ifdef CONFIG_DEBUG_UART
/* Earliest point to set up early debug uart */
bl debug_uart_init
#endif
/* Zero the one and only argument of "board_init_f" */
mov_s %r0, 0
bl board_init_f

1258
arch/arm/Kconfig
View File

File diff suppressed because it is too large Load Diff

51
arch/arm/Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
CONFIG_CPU_V7A=
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
CONFIG_CPU_V7=
CONFIG_CPU_ARM720T=y
endif
@ -12,17 +12,15 @@ arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te
arch-$(CONFIG_CPU_ARM946ES) =-march=armv5te
arch-$(CONFIG_CPU_SA1100) =-march=armv4
arch-$(CONFIG_CPU_PXA) =
arch-$(CONFIG_CPU_ARM1136) =-march=armv5t
arch-$(CONFIG_CPU_ARM1136) =-march=armv5
arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \
$(call cc-option, -march=armv7))
arch-$(CONFIG_CPU_V7M) =-march=armv7-m
arch-$(CONFIG_CPU_V7R) =-march=armv7-r
arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, \
$(call cc-option, -march=armv7, -march=armv5))
arch-$(CONFIG_ARM64) =-march=armv8-a
# On Tegra systems we must build SPL for the armv4 core on the device
# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
arch-y += -D__LINUX_ARM_ARCH__=4
else
arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
@ -40,8 +38,7 @@ tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
tune-$(CONFIG_CPU_PXA) =-mcpu=xscale
tune-$(CONFIG_CPU_ARM1136) =
tune-$(CONFIG_CPU_ARM1176) =
tune-$(CONFIG_CPU_V7A) =-mtune=generic-armv7-a
tune-$(CONFIG_CPU_V7R) =
tune-$(CONFIG_CPU_V7) =
tune-$(CONFIG_ARM64) =
# Evaluate tune cc-option calls now
@ -54,39 +51,29 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_BCM283X) += bcm283x
machine-$(CONFIG_ARCH_BCMSTB) += bcmstb
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_EXYNOS) += exynos
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_IPQ40XX) += ipq40xx
machine-$(CONFIG_ARCH_K3) += k3
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
machine-$(CONFIG_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_NEXELL) += nexell
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x
machine-$(CONFIG_ARCH_OWL) += owl
machine-$(CONFIG_ARCH_RMOBILE) += rmobile
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STM32) += stm32
machine-$(CONFIG_ARCH_RMOBILE) += rmobile
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_STM32) += stm32
machine-$(CONFIG_ARCH_STM32MP) += stm32mp
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U8500) += u8500
machine-$(CONFIG_ARCH_OCTEONTX) += octeontx
machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSAL) += versal
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
@ -107,11 +94,11 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt))
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m))
libs-y += arch/arm/mach-imx/
endif
else
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imxrt vf610))
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m vf610))
libs-y += arch/arm/mach-imx/
endif
endif

31
arch/arm/config.mk
View File

@ -11,19 +11,12 @@ CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
endif
endif
CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
-fstack-protector-strong
CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections
CFLAGS_EFI := -fpic -fshort-wchar
ifneq ($(CONFIG_LTO)$(CONFIG_USE_PRIVATE_LIBGCC),yy)
LDFLAGS_FINAL += --gc-sections
endif
ifndef CONFIG_LTO
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
endif
PLATFORM_RELFLAGS += -fno-common -ffixed-r9
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
-fno-common -ffixed-r9
PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
@ -129,7 +122,7 @@ endif
ifneq ($(CONFIG_SPL_BUILD),y)
# Check that only R_ARM_RELATIVE relocations are generated.
INPUTS-y += checkarmreloc
ALL-y += checkarmreloc
# The movt / movw can hardcode 16 bit parts of the addresses in the
# instruction. Relocation is not supported for that case, so disable
# such usage by requiring word relocations.
@ -141,11 +134,15 @@ endif
ifdef CONFIG_ARM64
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
-j .binman_sym_table -j .text_rest
-j .binman_sym_table
else
ifeq ($(CONFIG_ARCH_SUNXI),y)
OBJCOPYFLAGS += -j .head
endif
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
-j .binman_sym_table -j .text_rest
-j .binman_sym_table
endif
# if a dtb section exists we always have to include it
@ -161,17 +158,17 @@ endif
ifneq ($(CONFIG_IMX_CONFIG),)
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
INPUTS-y += SPL
ALL-y += SPL
endif
else
ifeq ($(CONFIG_OF_SEPARATE),y)
INPUTS-y += u-boot-dtb.imx
ALL-y += u-boot-dtb.imx
else
INPUTS-y += u-boot.imx
ALL-y += u-boot.imx
endif
endif
ifneq ($(CONFIG_VF610),)
INPUTS-y += u-boot.vyb
ALL-y += u-boot.vyb
endif
endif

4
arch/arm/cpu/arm11/Makefile
View File

@ -4,7 +4,3 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y = cpu.o
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_EFI_LOADER) += sctlr.o
endif

5
arch/arm/cpu/arm11/cpu.c
View File

@ -16,9 +16,6 @@
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/cache.h>
#include <asm/system.h>
static void cache_flush(void);
@ -32,7 +29,7 @@ int cleanup_before_linux (void)
* we turn off caches etc ...
*/
disable_interrupts();
disable_interrupts ();
/* turn off I/D-cache */
icache_disable();

25
arch/arm/cpu/arm11/sctlr.S
View File

@ -1,25 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Routines to access the system control register
*
* Copyright (c) 2019 Heinrich Schuchardt
*/
#include <linux/linkage.h>
/*
* void allow_unaligned(void) - allow unaligned access
*
* This routine sets the enable unaligned data support flag and clears the
* aligned flag in the system control register.
* After calling this routine unaligned access does no longer leads to a
* data abort or undefined behavior but is handled by the CPU.
* For details see the "ARM Architecture Reference Manual" for ARMv6.
*/
ENTRY(allow_unaligned)
mrc p15, 0, r0, c1, c0, 0 @ load system control register
orr r0, r0, #1 << 22 @ set unaligned data support flag
bic r0, r0, #2 @ clear aligned flag
mcr p15, 0, r0, c1, c0, 0 @ write system control register
bx lr @ return
ENDPROC(allow_unaligned)

1
arch/arm/cpu/arm1136/mx31/generic.c
View File

@ -6,7 +6,6 @@
#include <common.h>
#include <div64.h>
#include <init.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/io.h>

1
arch/arm/cpu/arm1136/mx31/timer.c
View File

@ -5,7 +5,6 @@
*/
#include <common.h>
#include <init.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>

23
arch/arm/cpu/arm1136/mx35/generic.c
View File

@ -7,20 +7,15 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <command.h>
#include <div64.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_FSL_ESDHC_IMX
#include <fsl_esdhc_imx.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
#include <netdev.h>
#include <spl.h>
@ -32,7 +27,7 @@
#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
#ifdef CONFIG_FSL_ESDHC_IMX
#ifdef CONFIG_FSL_ESDHC
DECLARE_GLOBAL_DATA_PTR;
#endif
@ -381,8 +376,8 @@ u32 imx_get_fecclk(void)
}
#endif
int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
int do_mx35_showclocks(cmd_tbl_t *cmdtp,
int flag, int argc, char * const argv[])
{
u32 cpufreq = get_mcu_main_clk();
printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
@ -440,7 +435,7 @@ int print_cpuinfo(void)
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(struct bd_info *bis)
int cpu_eth_init(bd_t *bis)
{
int rc = -ENODEV;
@ -451,12 +446,12 @@ int cpu_eth_init(struct bd_info *bis)
return rc;
}
#ifdef CONFIG_FSL_ESDHC_IMX
#ifdef CONFIG_FSL_ESDHC
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
int cpu_mmc_init(bd_t *bis)
{
return fsl_esdhc_mmc_init(bis);
}
@ -464,7 +459,7 @@ int cpu_mmc_init(struct bd_info *bis)
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
#ifdef CONFIG_FSL_ESDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR

2
arch/arm/cpu/arm1136/mx35/timer.c
View File

@ -7,11 +7,9 @@
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/ptrace.h>
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */

4
arch/arm/cpu/arm1136/u-boot-spl.lds
View File

@ -8,8 +8,8 @@
* Aneesh V <aneesh@ti.com>
*/
MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = IMAGE_MAX_SIZE }
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }

2
arch/arm/cpu/arm720t/interrupts.c
View File

@ -11,7 +11,7 @@
#include <common.h>
#if defined(CONFIG_ARCH_TEGRA)
#if defined(CONFIG_TEGRA)
static ulong timestamp;
static ulong lastdec;

4
arch/arm/cpu/arm920t/cpu.c
View File

@ -14,8 +14,6 @@
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/system.h>
static void cache_flush(void);
@ -29,7 +27,7 @@ int cleanup_before_linux (void)
* we turn off caches etc ...
*/
disable_interrupts();
disable_interrupts ();
/* turn off I/D-cache */
icache_disable();

3
arch/arm/cpu/arm920t/ep93xx/cpu.c
View File

@ -9,12 +9,11 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
extern void reset_cpu(void)
extern void reset_cpu(ulong addr)
{
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
uint32_t value;

10
arch/arm/cpu/arm920t/ep93xx/timer.c
View File

@ -12,9 +12,6 @@
*/
#include <common.h>
#include <init.h>
#include <time.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
@ -69,9 +66,14 @@ unsigned long long get_ticks(void)
return sys_ticks;
}
unsigned long get_timer_masked(void)
{
return get_ticks();
}
unsigned long get_timer(unsigned long base)
{
return get_ticks() - base;
return get_timer_masked() - base;
}
void __udelay(unsigned long usec)

24
arch/arm/cpu/arm920t/imx/timer.c
View File

@ -13,12 +13,9 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <time.h>
#if defined (CONFIG_IMX)
#include <asm/arch/imx-regs.h>
#include <linux/delay.h>
int timer_init (void)
{
@ -39,17 +36,17 @@ int timer_init (void)
/*
* timer without interrupts
*/
static ulong get_timer_masked (void)
{
return TCN1;
}
ulong get_timer (ulong base)
{
return get_timer_masked() - base;
}
void __udelay(unsigned long usec)
ulong get_timer_masked (void)
{
return TCN1;
}
void udelay_masked (unsigned long usec)
{
ulong endtime = get_timer_masked() + usec;
signed long diff;
@ -60,6 +57,11 @@ void __udelay(unsigned long usec)
} while (diff >= 0);
}
void __udelay (unsigned long usec)
{
udelay_masked(usec);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
@ -73,7 +75,7 @@ unsigned long long get_ticks(void)
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
ulong get_tbclk (void)
{
return CONFIG_SYS_HZ;
}
@ -81,7 +83,7 @@ ulong get_tbclk(void)
/*
* Reset the cpu by setting up the watchdog timer and let him time out
*/
void reset_cpu(void)
void reset_cpu (ulong ignored)
{
/* Disable watchdog and set Time-Out field to 0 */
WCR = 0x00000000;

5
arch/arm/cpu/arm926ejs/Makefile
View File

@ -7,12 +7,13 @@ extra-y = start.o
obj-y = cpu.o cache.o
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_NO_CPU_SUPPORT
ifdef CONFIG_SPL_NO_CPU_SUPPORT_CODE
extra-y :=
endif
endif
obj-$(CONFIG_ARMADA100) += armada100/
obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
@ -25,8 +26,6 @@ ifndef CONFIG_HAS_THUMB2
CFLAGS_cpu.o := -marm
CFLAGS_cache.o := -marm
CFLAGS_REMOVE_cpu.o := $(LTO_CFLAGS)
CFLAGS_REMOVE_cache.o := $(LTO_CFLAGS)
endif
endif

2
arch/arm/cpu/arm926ejs/armada100/cpu.c
View File

@ -7,8 +7,6 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/arch/cpu.h>
#include <asm/arch/armada100.h>

2
arch/arm/cpu/arm926ejs/armada100/dram.c
View File

@ -7,8 +7,6 @@
*/
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/armada100.h>

11
arch/arm/cpu/arm926ejs/armada100/timer.c
View File

@ -7,13 +7,8 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <time.h>
#include <asm/arch/cpu.h>
#include <asm/arch/armada100.h>
#include <asm/global_data.h>
#include <linux/delay.h>
/*
* Timer registers
@ -66,7 +61,7 @@ ulong read_timer(void)
return(readl(&armd1timers->cvwr));
}
static ulong get_timer_masked(void)
ulong get_timer_masked(void)
{
ulong now = read_timer();
@ -142,7 +137,7 @@ int timer_init(void)
* 2. Write key value to TMP_WSAR reg.
* 3. Perform write operation.
*/
void reset_cpu(void)
void reset_cpu (unsigned long ignored)
{
struct armd1mpmu_registers *mpmu =
(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
@ -192,7 +187,7 @@ unsigned long long get_ticks(void)
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
ulong get_tbclk (void)
{
return (ulong)CONFIG_SYS_HZ;
}

2
arch/arm/cpu/arm926ejs/cache.c
View File

@ -3,8 +3,6 @@
* (C) Copyright 2011
* Ilya Yanok, EmCraft Systems
*/
#include <cpu_func.h>
#include <asm/cache.h>
#include <linux/types.h>
#include <common.h>

5
arch/arm/cpu/arm926ejs/cpu.c
View File

@ -14,9 +14,6 @@
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/cache.h>
#include <asm/system.h>
static void cache_flush(void);
@ -30,7 +27,7 @@ int cleanup_before_linux (void)
* we turn off caches etc ...
*/
disable_interrupts();
disable_interrupts ();
/* turn off I/D-cache */

0
arch/arm/mach-lpc32xx/Makefile → arch/arm/cpu/arm926ejs/lpc32xx/Makefile
View File

137
arch/arm/cpu/arm926ejs/lpc32xx/clk.c Normal file
View File

@ -0,0 +1,137 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
*/
#include <common.h>
#include <div64.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clk.h>
#include <asm/io.h>
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
unsigned int get_sys_clk_rate(void)
{
if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)
return RTC_CLK_FREQUENCY * 397;
else
return OSC_CLK_FREQUENCY;
}
unsigned int get_hclk_pll_rate(void)
{
unsigned long long fin, fref, fcco, fout;
u32 val, m_div, n_div, p_div;
/*
* Valid frequency ranges:
* 1 * 10^6 <= Fin <= 20 * 10^6
* 1 * 10^6 <= Fref <= 27 * 10^6
* 156 * 10^6 <= Fcco <= 320 * 10^6
*/
fref = fin = get_sys_clk_rate();
if (fin > 20000000ULL || fin < 1000000ULL)
return 0;
val = readl(&clk->hclkpll_ctrl);
m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
if (val & CLK_HCLK_PLL_DIRECT)
p_div = 0;
else
p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
p_div = 1 << p_div;
if (val & CLK_HCLK_PLL_BYPASS) {
do_div(fin, p_div);
return fin;
}
do_div(fref, n_div);
if (fref > 27000000ULL || fref < 1000000ULL)
return 0;
fcco = fref * m_div;
fout = fcco;
if (val & CLK_HCLK_PLL_FEEDBACK)
fcco *= p_div;
else
do_div(fout, p_div);
if (fcco > 320000000ULL || fcco < 156000000ULL)
return 0;
return fout;
}
unsigned int get_hclk_clk_div(void)
{
u32 val;
val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
return 1 << val;
}
unsigned int get_hclk_clk_rate(void)
{
return get_hclk_pll_rate() / get_hclk_clk_div();
}
unsigned int get_periph_clk_div(void)
{
u32 val;
val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
return (val >> 2) + 1;
}
unsigned int get_periph_clk_rate(void)
{
if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
return get_sys_clk_rate();
return get_hclk_pll_rate() / get_periph_clk_div();
}
unsigned int get_sdram_clk_rate(void)
{
unsigned int src_clk;
if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
return get_sys_clk_rate();
src_clk = get_hclk_pll_rate();
if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) {
/* using DDR */
switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) {
case CLK_HCLK_DDRAM_HALF:
return src_clk/2;
case CLK_HCLK_DDRAM_NOMINAL:
return src_clk;
default:
return 0;
}
} else {
/* using SDR */
switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) {
case CLK_HCLK_ARM_PLL_DIV_4:
return src_clk/4;
case CLK_HCLK_ARM_PLL_DIV_2:
return src_clk/2;
case CLK_HCLK_ARM_PLL_DIV_1:
return src_clk;
default:
return 0;
}
}
}
int get_serial_clock(void)
{
return get_periph_clk_rate();
}

77
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c Normal file
View File

@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clk.h>
#include <asm/arch/wdt.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
void reset_cpu(ulong addr)
{
/* Enable watchdog clock */
setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
/* To be compatible with the original U-Boot code:
* addr: - 0: perform hard reset.
* - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
if (addr == 0) {
/* Reset pulse length is 13005 peripheral clock frames */
writel(13000, &wdt->pulse);
/* Force WDOG_RESET2 and RESOUT_N signal active */
writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
| WDTIM_MCTRL_M_RES2, &wdt->mctrl);
} else {
/* Force match output active */
writel(0x01, &wdt->emr);
/* Internal reset on match output (no pulse on "RESOUT_N") */
writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
}
while (1)
/* NOP */;
}
#if defined(CONFIG_ARCH_CPU_INIT)
int arch_cpu_init(void)
{
/*
* It might be necessary to flush data cache, if U-Boot is loaded
* from kickstart bootloader, e.g. from S1L loader
*/
flush_dcache_all();
return 0;
}
#else
#error "You have to select CONFIG_ARCH_CPU_INIT"
#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
printf("CPU: NXP LPC32XX\n");
printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
return 0;
}
#endif
#ifdef CONFIG_LPC32XX_ETH
int cpu_eth_init(bd_t *bis)
{
lpc32xx_eth_initialize(bis);
return 0;
}
#endif

8
arch/arm/mach-lpc32xx/devices.c → arch/arm/cpu/arm926ejs/lpc32xx/devices.c
View File

@ -43,7 +43,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct ns16550_plat lpc32xx_uart[] = {
static const struct ns16550_platdata lpc32xx_uart[] = {
{ .base = UART3_BASE, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = UART4_BASE, .reg_shift = 2,
@ -55,14 +55,14 @@ static const struct ns16550_plat lpc32xx_uart[] = {
};
#if defined(CONFIG_LPC32XX_HSUART)
static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
{ HS_UART1_BASE, },
{ HS_UART2_BASE, },
{ HS_UART7_BASE, },
};
#endif
U_BOOT_DRVINFOS(lpc32xx_uarts) = {
U_BOOT_DEVICES(lpc32xx_uarts) = {
#if defined(CONFIG_LPC32XX_HSUART)
{ "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
{ "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
@ -124,7 +124,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
writel(ctrl, &clk->i2cclk_ctrl);
}
U_BOOT_DRVINFO(lpc32xx_gpios) = {
U_BOOT_DEVICE(lpc32xx_gpios) = {
.name = "gpio_lpc32xx"
};

76
arch/arm/cpu/arm926ejs/lpc32xx/dram.c Normal file
View File

@ -0,0 +1,76 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* LPC32xx dram init
*
* (C) Copyright 2014 DENX Software Engineering GmbH
* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
*
* This is called by SPL to gain access to the SDR DRAM.
*
* This code runs from SRAM.
*
* Actual CONFIG_LPC32XX_SDRAM_* parameters must be provided
* by the board configuration file.
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clk.h>
#include <asm/arch/wdt.h>
#include <asm/arch/emc.h>
#include <asm/io.h>
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
void ddr_init(struct emc_dram_settings *dram)
{
uint32_t ck;
/* Enable EMC interface and choose little endian mode */
writel(1, &emc->ctrl);
writel(0, &emc->config);
/* Select maximum EMC Dynamic Memory Refresh Time */
writel(0x7FF, &emc->refresh);
/* Determine CLK */
ck = get_sdram_clk_rate();
/* Configure SDRAM */
writel(dram->cmddelay, &clk->sdramclk_ctrl);
writel(dram->config0, &emc->config0);
writel(dram->rascas0, &emc->rascas0);
writel(dram->rdconfig, &emc->read_config);
/* Set timings */
writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);
writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);
writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);
writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);
writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);
writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);
writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);
writel(dram->trrd, &emc->t_rrd);
writel(dram->tmrd, &emc->t_mrd);
writel(dram->tcdlr, &emc->t_cdlr);
/* Dynamic refresh */
writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
udelay(10);
/* Force all clocks, enable inverted ck, issue NOP command */
writel(0x00000193, &emc->control);
udelay(100);
/* Keep all clocks enabled, issue a PRECHARGE ALL command */
writel(0x00000113, &emc->control);
/* Fast dynamic refresh for at least a few SDRAM ck cycles */
writel((((128) >> 4) & 0x7FF), &emc->refresh);
udelay(10);
/* set correct dynamic refresh timing */
writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
udelay(10);
/* set normal mode to CAS=3 */
writel(0x00000093, &emc->control);
readl(EMC_DYCS0_BASE | dram->mode);
/* set extended mode to all zeroes */
writel(0x00000093, &emc->control);
readl(EMC_DYCS0_BASE | dram->emode);
/* stop forcing clocks, keep inverted clock, issue normal mode */
writel(0x00000010, &emc->control);
}

0
arch/arm/mach-lpc32xx/lowlevel_init.S → arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
View File

81
arch/arm/cpu/arm926ejs/lpc32xx/timer.c Normal file
View File

@ -0,0 +1,81 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
*/
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clk.h>
#include <asm/arch/timer.h>
#include <asm/io.h>
static struct timer_regs *timer0 = (struct timer_regs *)TIMER0_BASE;
static struct timer_regs *timer1 = (struct timer_regs *)TIMER1_BASE;
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
static void lpc32xx_timer_clock(u32 bit, int enable)
{
if (enable)
setbits_le32(&clk->timclk_ctrl1, bit);
else
clrbits_le32(&clk->timclk_ctrl1, bit);
}
static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq)
{
writel(TIMER_TCR_COUNTER_RESET, &timer->tcr);
writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
writel(0, &timer->tc);
writel(0, &timer->pr);
/* Count mode is every rising PCLK edge */
writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr);
/* Set prescale counter value */
writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
}
static void lpc32xx_timer_count(struct timer_regs *timer, int enable)
{
if (enable)
writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr);
else
writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
}
int timer_init(void)
{
lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1);
lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ);
lpc32xx_timer_count(timer0, 1);
return 0;
}
ulong get_timer(ulong base)
{
return readl(&timer0->tc) - base;
}
void __udelay(unsigned long usec)
{
lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1);
lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000);
lpc32xx_timer_count(timer1, 1);
while (readl(&timer1->tc) < usec)
/* NOP */;
lpc32xx_timer_count(timer1, 0);
lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0);
}
unsigned long long get_ticks(void)
{
return get_timer(0);
}
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

25
arch/arm/cpu/arm926ejs/mx25/generic.c
View File

@ -9,20 +9,15 @@
*/
#include <common.h>
#include <clock_legacy.h>
#include <div64.h>
#include <init.h>
#include <net.h>
#include <netdev.h>
#include <vsprintf.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#ifdef CONFIG_FSL_ESDHC_IMX
#include <fsl_esdhc_imx.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
@ -219,12 +214,20 @@ int print_cpuinfo(void)
}
#endif
void enable_caches(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
#endif
}
#if defined(CONFIG_FEC_MXC)
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(struct bd_info *bis)
int cpu_eth_init(bd_t *bis)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong val;
@ -238,7 +241,7 @@ int cpu_eth_init(struct bd_info *bis)
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
#ifdef CONFIG_FSL_ESDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#else
@ -248,12 +251,12 @@ int get_clocks(void)
return 0;
}
#ifdef CONFIG_FSL_ESDHC_IMX
#ifdef CONFIG_FSL_ESDHC
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
int cpu_mmc_init(bd_t *bis)
{
return fsl_esdhc_mmc_init(bis);
}

3
arch/arm/cpu/arm926ejs/mx25/reset.c
View File

@ -16,14 +16,13 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu(void)
void reset_cpu(ulong ignored)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */

2
arch/arm/cpu/arm926ejs/mx25/timer.c
View File

@ -20,10 +20,8 @@
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/ptrace.h>
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32KHz 32-bit timer overruns in 134217 seconds */

14
arch/arm/cpu/arm926ejs/mx27/generic.c
View File

@ -6,9 +6,7 @@
#include <common.h>
#include <div64.h>
#include <net.h>
#include <netdev.h>
#include <vsprintf.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
@ -177,7 +175,7 @@ int print_cpuinfo (void)
}
#endif
int cpu_eth_init(struct bd_info *bis)
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_FEC_MXC)
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
@ -195,7 +193,7 @@ int cpu_eth_init(struct bd_info *bis)
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
int cpu_mmc_init(bd_t *bis)
{
#ifdef CONFIG_MMC_MXC
return mxc_mmc_init(bis);
@ -376,3 +374,11 @@ void mx27_sd2_init_pins(void)
}
#endif /* CONFIG_MMC_MXC */
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif /* CONFIG_SYS_DCACHE_OFF */

3
arch/arm/cpu/arm926ejs/mx27/reset.c
View File

@ -16,14 +16,13 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu(void)
void reset_cpu(ulong ignored)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */

7
arch/arm/cpu/arm926ejs/mx27/timer.c
View File

@ -17,13 +17,8 @@
#include <common.h>
#include <div64.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/ptrace.h>
#include <linux/delay.h>
/* General purpose timers bitfields */
#define GPTCR_SWR (1 << 15) /* Software reset */
@ -131,7 +126,7 @@ unsigned long long get_ticks(void)
return timestamp;
}
static ulong get_timer_masked(void)
ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in

1
arch/arm/cpu/arm926ejs/mxs/clock.c
View File

@ -10,7 +10,6 @@
*/
#include <common.h>
#include <log.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>

37
arch/arm/cpu/arm926ejs/mxs/mxs.c
View File

@ -10,13 +10,6 @@
*/
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
@ -25,7 +18,6 @@
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/sections.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
@ -33,9 +25,9 @@ DECLARE_GLOBAL_DATA_PTR;
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
__weak void lowlevel_init(void) {}
void reset_cpu(void) __attribute__((noreturn));
void reset_cpu(ulong ignored) __attribute__((noreturn));
void reset_cpu(void)
void reset_cpu(ulong ignored)
{
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
@ -57,6 +49,16 @@ void reset_cpu(void)
;
}
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable();
#endif
}
/*
* This function will craft a jumptable at 0x0 which will redirect interrupt
* vectoring to proper location of U-Boot in RAM.
@ -99,22 +101,20 @@ int arch_cpu_init(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
extern uint32_t _start;
mx28_fixup_vt((uint32_t)&_start);
/*
* Enable NAND clock
*/
/* Set bypass bit */
/* Clear bypass bit */
writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
&clkctrl_regs->hw_clkctrl_clkseq_set);
/* Set GPMI clock to ref_xtal / 1 */
clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE);
while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE)
;
/* Set GPMI clock to ref_gpmi / 12 */
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
CLKCTRL_GPMI_DIV_MASK, 1);
CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
udelay(1000);
@ -190,8 +190,7 @@ int print_cpuinfo(void)
}
#endif
int do_mx28_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
@ -204,7 +203,7 @@ int do_mx28_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
* Initializes on-chip ethernet controllers.
*/
#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
int cpu_eth_init(struct bd_info *bis)
int cpu_eth_init(bd_t *bis)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

17
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
View File

@ -8,15 +8,10 @@
#include <common.h>
#include <config.h>
#include <init.h>
#include <log.h>
#include <serial.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/sections.h>
#include <linux/compiler.h>
#include "mxs_init.h"
@ -24,12 +19,14 @@
DECLARE_GLOBAL_DATA_PTR;
static gd_t gdata __section(".data");
#ifdef CONFIG_SPL_SERIAL_SUPPORT
static struct bd_info bdata __section(".data");
static bd_t bdata __section(".data");
#endif
/*
* This delay function is intended to be used only in early stage of boot, where
* clock are not set up yet.
* clock are not set up yet. The timer used here is reset on every boot and
* takes a few seconds to roll. The boot doesn't take that long, so to keep the
* code simple, it doesn't take rolling into consideration.
*/
void early_delay(int delay)
{
@ -37,7 +34,8 @@ void early_delay(int delay)
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
uint32_t st = readl(&digctl_regs->hw_digctl_microseconds);
while (readl(&digctl_regs->hw_digctl_microseconds) - st <= delay)
st += delay;
while (st > readl(&digctl_regs->hw_digctl_microseconds))
;
}
@ -101,6 +99,7 @@ static void mxs_spl_fixup_vectors(void)
* thus this fixup. Our vectoring table is PIC, so copying is
* fine.
*/
extern uint32_t _start;
/* cppcheck-suppress nullPointer */
memcpy(0x0, &_start, 0x60);
@ -122,7 +121,7 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
{
struct mxs_spl_data *data = MXS_SPL_DATA;
uint8_t bootmode = mxs_get_bootmode_index();
set_gd(&gdata);
gd = &gdata;
mxs_spl_fixup_vectors();

1
arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
View File

@ -8,7 +8,6 @@
#include <common.h>
#include <config.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>

16
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
View File

@ -8,8 +8,6 @@
#include <common.h>
#include <config.h>
#include <init.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
@ -17,7 +15,7 @@
#include "mxs_init.h"
__weak uint32_t mxs_dram_vals[] = {
static uint32_t dram_vals[] = {
/*
* i.MX28 DDR2 at 200MHz
*/
@ -102,11 +100,11 @@ static void initialize_dram_values(void)
int i;
debug("SPL: Setting mx28 board specific SDRAM parameters\n");
mxs_adjust_memory_params(mxs_dram_vals);
mxs_adjust_memory_params(dram_vals);
debug("SPL: Applying SDRAM parameters\n");
for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++)
writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
#else
static void initialize_dram_values(void)
@ -114,7 +112,7 @@ static void initialize_dram_values(void)
int i;
debug("SPL: Setting mx23 board specific SDRAM parameters\n");
mxs_adjust_memory_params(mxs_dram_vals);
mxs_adjust_memory_params(dram_vals);
/*
* HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
@ -126,10 +124,10 @@ static void initialize_dram_values(void)
* So skip the initialization of these HW_DRAM_CTL registers.
*/
debug("SPL: Applying SDRAM parameters\n");
for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) {
for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
if (i == 8 || i == 27 || i == 28 || i == 35)
continue;
writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
/*

6
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
View File

@ -8,8 +8,6 @@
#include <common.h>
#include <config.h>
#include <hang.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
@ -1256,8 +1254,8 @@ void mxs_power_init(void)
debug("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n");
mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
debug("SPL: Setting VDDD to 1V55 (brownout @ 1v400)\n");
mxs_power_set_vddx(&mxs_vddd_cfg, 1550, 1400);
debug("SPL: Setting VDDD to 1V5 (brownout @ 1v315)\n");
mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1315);
#ifdef CONFIG_MX23
debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);

11
arch/arm/cpu/arm926ejs/mxs/timer.c
View File

@ -10,13 +10,9 @@
*/
#include <common.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <linux/delay.h>
/* Maximum fixed count */
#if defined(CONFIG_MX23)
@ -114,9 +110,14 @@ unsigned long long get_ticks(void)
return timestamp;
}
ulong get_timer_masked(void)
{
return tick_to_time(get_ticks());
}
ulong get_timer(ulong base)
{
return tick_to_time(get_ticks()) - base;
return get_timer_masked() - base;
}
/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */

2
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
View File

@ -15,7 +15,7 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = IMAGE_TEXT_BASE;
. = CONFIG_SPL_TEXT_BASE;
. = ALIGN(4);
.text :

4
arch/arm/mach-orion5x/u-boot-spl.lds → arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds
View File

@ -16,8 +16,8 @@
* Texas Instruments, <www.ti.com>
* Aneesh V <aneesh@ti.com>
*/
MEMORY { .nor : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = IMAGE_MAX_SIZE }
MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }

20
arch/arm/cpu/arm926ejs/spear/cpu.c
View File

@ -5,8 +5,6 @@
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_misc.h>
@ -51,18 +49,22 @@ int arch_cpu_init(void)
#if defined(CONFIG_USB_EHCI_SPEAR)
periph1_clken |= PERIPH_USBH1 | PERIPH_USBH2;
#endif
#if defined(CONFIG_SPEAR_GPIO)
periph1_clken |= MISC_GPIO3ENB | MISC_GPIO4ENB;
#endif
#if defined(CONFIG_PL022_SPI)
periph1_clken |= MISC_SSP1ENB | MISC_SSP2ENB | MISC_SSP3ENB;
#endif
writel(periph1_clken, &misc_p->periph1_clken);
return 0;
}
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
icache_enable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable();
#endif
}
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
@ -82,7 +84,7 @@ int print_cpuinfo(void)
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
static int do_switch_ecc(struct cmd_tbl *cmdtp, int flag, int argc,
static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
if (argc != 2)

4
arch/arm/cpu/arm926ejs/spear/reset.c
View File

@ -5,13 +5,11 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_syscntl.h>
#include <linux/delay.h>
void reset_cpu(void)
void reset_cpu(ulong ignored)
{
struct syscntl_regs *syscntl_regs_p =
(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;

52
arch/arm/cpu/arm926ejs/spear/spl.c
View File

@ -7,23 +7,15 @@
*/
#include <common.h>
#include <init.h>
#include <spl.h>
#include <version.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_defs.h>
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_syscntl.h>
#include <linux/mtd/st_smi.h>
/* Reserve some space to store the BootROM's stack pointer during SPL operation.
* The BSS cannot be used for this purpose because it will be zeroed after
* having stored the pointer, so force the location to the data section.
*/
u32 bootrom_stash_sp __section(".data");
static void ddr_clock_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
@ -231,9 +223,8 @@ u32 spl_boot_device(void)
{
u32 mode = 0;
if (usb_boot_selected()) {
mode = BOOT_DEVICE_BOOTROM;
} else if (snor_boot_selected()) {
/* Currently only SNOR is supported as the only */
if (snor_boot_selected()) {
/* SNOR-SMI initialization */
snor_init();
@ -243,18 +234,6 @@ u32 spl_boot_device(void)
return mode;
}
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = spl_boot_device();
/*
* If the main boot device (eg. NOR) is empty, try to jump back into the
* BootROM for USB boot process.
*/
if (USB_BOOT_SUPPORTED)
spl_boot_list[1] = BOOT_DEVICE_BOOTROM;
}
void board_init_f(ulong dummy)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
@ -272,31 +251,6 @@ void board_init_f(ulong dummy)
puts("Configure DDR\n");
mpmc_init();
spear_late_init();
}
/*
* In a few cases (Ethernet, UART or USB boot, we might want to go back into the
* BootROM code right after having initialized a few components like the DRAM).
* The following function is called from SPL common code (board_init_r).
*/
int board_return_to_bootrom(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
/*
* Retrieve the BootROM's stack pointer and jump back to the start of
* the SPL, where we can easily branch back into the BootROM. Don't do
* it right here because SPL might be compiled in Thumb mode while the
* BootROM expects ARM mode.
*/
asm volatile ("ldr r0, =bootrom_stash_sp;"
"ldr r0, [r0];"
"mov sp, r0;"
#if defined(CONFIG_SPL_SYS_THUMB_BUILD)
"blx back_to_bootrom;"
#else
"bl back_to_bootrom;"
#endif
);
return 0;
board_init_r(NULL, 0);
}

8
arch/arm/cpu/arm926ejs/spear/spr_misc.c
View File

@ -6,12 +6,9 @@
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <env.h>
#include <environment.h>
#include <i2c.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <linux/mtd/st_smi.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
@ -183,8 +180,7 @@ static int write_mac(uchar *mac)
}
#endif
int do_chip_config(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
void (*sram_setfreq) (unsigned int, unsigned int);
unsigned int frequency;

56
arch/arm/cpu/arm926ejs/spear/start.S
View File

@ -21,35 +21,51 @@
*
* Startup Code (reset vector)
*
* The BootROM already initialized its own stack in the [0-0xb00] reserved
* range of the SRAM. The SPL (in _main) will update the stack pointer to
* its own SRAM area (right before the gd section).
* Below are the critical initializations already taken place in BootROM.
* So, these are not taken care in Xloader
* 1. Relocation to RAM
* 2. Initializing stacks
*
*************************************************************************
*/
.globl reset
.globl back_to_bootrom
reset:
/*
* SPL has to return back to BootROM in a few cases (eg. Ethernet boot,
* UART boot, USB boot): save registers in BootROM's stack and then the
* BootROM's stack pointer in the SPL's data section.
*/
push {r0-r12,lr}
ldr r0, =bootrom_stash_sp
str sp, [r0]
/*
* Xloader has to return back to BootROM in a few cases.
* eg. Ethernet boot, UART boot, USB boot
* Saving registers for returning back
*/
stmdb sp!, {r0-r12,r14}
bl cpu_init_crit
/*
* Clearing bss area is not done in Xloader.
* BSS area lies in the DDR location which is not yet initialized
* bss is assumed to be uninitialized.
*/
ldmia sp!, {r0-r12,pc}
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
cpu_init_crit:
/*
* Flush v4 I/D caches
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* Flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* Flush v4 TLB */
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* Enable instruction cache
* enable instruction cache
*/
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
@ -57,9 +73,7 @@ reset:
/*
* Go setup Memory and board specific bits prior to relocation.
* This call is not supposed to return.
*/
b _main /* _main will call board_init_f */
back_to_bootrom:
pop {r0-r12,pc}
stmdb sp!, {lr}
bl _main /* _main will call board_init_f */
ldmia sp!, {pc}

14
arch/arm/cpu/arm926ejs/spear/timer.c
View File

@ -5,15 +5,10 @@
*/
#include <common.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_gpt.h>
#include <asm/arch/spr_misc.h>
#include <asm/ptrace.h>
#include <linux/delay.h>
#define GPT_RESOLUTION (CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
#define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
@ -26,8 +21,6 @@ static struct misc_regs *const misc_regs_p =
DECLARE_GLOBAL_DATA_PTR;
static ulong get_timer_masked(void);
#define timestamp gd->arch.tbl
#define lastdec gd->arch.lastinc
@ -89,7 +82,7 @@ void __udelay(unsigned long usec)
;
}
static ulong get_timer_masked(void)
ulong get_timer_masked(void)
{
ulong now = READ_TIMER();
@ -105,6 +98,11 @@ static ulong get_timer_masked(void)
return timestamp;
}
void udelay_masked(unsigned long usec)
{
return udelay(usec);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.

4
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
View File

@ -12,8 +12,8 @@
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*/
MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = IMAGE_MAX_SIZE }
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)

6
arch/arm/cpu/arm946es/cpu.c
View File

@ -14,8 +14,6 @@
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/system.h>
#include <asm/io.h>
@ -30,7 +28,7 @@ int cleanup_before_linux (void)
* we turn off caches etc ...
*/
disable_interrupts();
disable_interrupts ();
/* ARM926E-S needs the protection unit enabled for the icache to have
* been enabled - left for possible later use
@ -56,7 +54,7 @@ static void cache_flush (void)
#ifndef CONFIG_ARCH_INTEGRATOR
__attribute__((noreturn)) void reset_cpu(void)
__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
{
writew(0x0, 0xfffece10);
writew(0x8, 0xfffece10);

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