104 lines
3.1 KiB
Diff
104 lines
3.1 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Marvin Wewer <mwewer37@proton.me>
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Date: Thu, 23 Oct 2025 13:30:29 +0000
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Subject: spi: sunxi: Add support for Allwinner A523 SPI controllers
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Signed-off-by: Marvin Wewer <mwewer37@proton.me>
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---
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drivers/spi/spi-sunxi.c | 44 ++++++++++
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1 file changed, 44 insertions(+)
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diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
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index 111111111111..222222222222 100644
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--- a/drivers/spi/spi-sunxi.c
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+++ b/drivers/spi/spi-sunxi.c
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@@ -84,6 +84,8 @@ DECLARE_GLOBAL_DATA_PTR;
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#define SUN4I_SPI_DEFAULT_RATE 1000000
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#define SUN4I_SPI_TIMEOUT_MS 1000
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+#define SUN55I_BUF_STA_REG 0x400
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+
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#define SPI_REG(priv, reg) ((priv)->base + \
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(priv)->variant->regs[reg])
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#define SPI_BIT(priv, bit) ((priv)->variant->bits[bit])
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@@ -130,6 +132,7 @@ struct sun4i_spi_variant {
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bool has_soft_reset;
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bool has_burst_ctl;
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bool has_clk_ctl;
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+ bool has_bsr;
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};
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struct sun4i_spi_plat {
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@@ -366,6 +369,21 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
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setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) |
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SPI_BIT(priv, SPI_FCR_TF_RST));
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+ if (priv->variant->has_bsr) {
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+ u32 reg;
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+ int ret;
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+
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+ ret = readl_poll_timeout(SPI_REG(priv, SPI_FCR), reg,
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+ !(reg & (SPI_BIT(priv, SPI_FCR_RF_RST) |
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+ SPI_BIT(priv, SPI_FCR_TF_RST))),
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+ SUN4I_SPI_TIMEOUT_MS * 1000);
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+ if (ret) {
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+ printf("ERROR: sun4i_spi: FIFO reset timeout\n");
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+ sun4i_spi_set_cs(bus, slave_plat->cs[0], false);
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+ return ret;
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+ }
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+ }
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+
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while (len) {
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/* Setup the transfer now... */
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nbytes = min(len, (priv->variant->fifo_depth - 1));
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@@ -519,6 +537,19 @@ static const unsigned long sun6i_spi_regs[] = {
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[SPI_RXD] = SUN6I_RXDATA_REG,
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};
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+static const unsigned long sun55i_spi_regs[] = {
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+ [SPI_GCR] = SUN6I_GBL_CTL_REG,
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+ [SPI_TCR] = SUN6I_TFR_CTL_REG,
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+ [SPI_FCR] = SUN6I_FIFO_CTL_REG,
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+ [SPI_FSR] = SUN55I_BUF_STA_REG,
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+ [SPI_CCR] = SUN6I_CLK_CTL_REG,
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+ [SPI_BC] = SUN6I_BURST_CNT_REG,
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+ [SPI_TC] = SUN6I_XMIT_CNT_REG,
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+ [SPI_BCTL] = SUN6I_BURST_CTL_REG,
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+ [SPI_TXD] = SUN6I_TXDATA_REG,
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+ [SPI_RXD] = SUN6I_RXDATA_REG,
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+};
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+
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static const u32 sun6i_spi_bits[] = {
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[SPI_GCR_TP] = BIT(7),
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[SPI_GCR_SRST] = BIT(31),
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@@ -570,6 +601,15 @@ static const struct sun4i_spi_variant sun50i_r329_spi_variant = {
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.has_burst_ctl = true,
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};
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+static const struct sun4i_spi_variant sun55i_a523_spi_variant = {
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+ .regs = sun55i_spi_regs,
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+ .bits = sun6i_spi_bits,
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+ .fifo_depth = 64,
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+ .has_soft_reset = true,
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+ .has_burst_ctl = true,
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+ .has_bsr = true,
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+};
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+
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static const struct udevice_id sun4i_spi_ids[] = {
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{
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.compatible = "allwinner,sun4i-a10-spi",
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@@ -587,6 +627,10 @@ static const struct udevice_id sun4i_spi_ids[] = {
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.compatible = "allwinner,sun50i-r329-spi",
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.data = (ulong)&sun50i_r329_spi_variant,
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},
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+ {
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+ .compatible = "allwinner,sun55i-a523-spi",
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+ .data = (ulong)&sun55i_a523_spi_variant,
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+ },
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{ /* sentinel */ }
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};
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--
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Armbian
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