Update source to Armbian-dev-202610.A311Y3
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@@ -175,6 +175,10 @@ unsigned long ulSynchTrap(unsigned long mcause, unsigned long sp, unsigned long
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printf("Dump Stack: \n");
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vTaskDumpStack(NULL);
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//_exit(mcause);
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/*
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* The while loop is necessary for risc-v trap handler.
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*/
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/* coverity[no_escape] */
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do {}while(1);
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}
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@@ -204,6 +208,10 @@ void vPortExitCritical( void );
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void vPortExitCritical( void )
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{
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configASSERT( uxCriticalNesting );
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/*
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* INTEGER_OVERFLOW is protected by configASSERT.
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*/
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/* coverity[INTEGER_OVERFLOW] */
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uxCriticalNesting--;
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if ( uxCriticalNesting == 0 )
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{
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@@ -294,6 +302,10 @@ void prvTaskExitError( void )
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configASSERT( uxCriticalNesting == ~0UL );
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portDISABLE_INTERRUPTS();
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printf("prvTaskExitError\n");
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/*
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* The for loop is necessary for matching freertos OS task exit error.
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*/
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/* coverity[no_escape] */
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for ( ;; );
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}
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/*-----------------------------------------------------------*/
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@@ -420,6 +432,10 @@ void vBusRespERRHandler(void)
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#else
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printf("bl30 bus resp err: access limitation, stop!\n");
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printf("mepc: 0x%lx, mbadaddr: 0x%lx\n", read_csr(mepc), read_csr(mbadaddr));
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/*
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* The while loop is necessary for handling the bus error.
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*/
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/* coverity[no_escape] */
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do {} while (1);
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#endif
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}
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@@ -476,4 +492,16 @@ void vPortSetup(void) {
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vPortSetupSoftIRQ();
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uxCriticalNesting = 0;
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}
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void vAssertCalled(const char *pcFileName, uint32_t ulLine)
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{
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taskDISABLE_INTERRUPTS();
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printf("ASSERT: %s %ld\n", pcFileName, ulLine);
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/*
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* The for loop is necessary for matching Freertos OS assert logic.
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*/
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/* coverity[no_escape] */
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for (;;)
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;
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}
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/*-----------------------------------------------------------*/
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@@ -432,9 +432,6 @@ irq_entry: // -------------> This label will be set to MTVT2 register
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int_loop: // 3 instructions in pending-interrupt service loop.
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csrrw ra, CSR_JALMNXTI, ra
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csrrsi a0, CSR_MNXTI, MSTATUS_MIE // Claim any pending interrupt at level > mcause.pil
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bnez a0, int_loop // Loop to service any interrupt.
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/*have a chance to switch task*/
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// li a2,40
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// ecall
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@@ -432,9 +432,6 @@ irq_entry: // -------------> This label will be set to MTVT2 register
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int_loop: // 3 instructions in pending-interrupt service loop.
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csrrw ra, CSR_JALMNXTI, ra
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csrrsi a0, CSR_MNXTI, MSTATUS_MIE // Claim any pending interrupt at level > mcause.pil
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bnez a0, int_loop // Loop to service any interrupt.
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/*have a chance to switch task*/
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// li a2,40
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// ecall
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