From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Hans Zhang <18255117159@163.com> Date: Fri, 28 Nov 2025 01:09:07 +0800 Subject: PCI: Configure Root Port MPS during host probing Current PCIe initialization logic may leave Root Ports operating with non-optimal Maximum Payload Size (MPS) settings. The existing code in pci_configure_mps() returns early for devices without an upstream bridge which includes Root Ports, so their MPS values remain at firmware defaults. This fails to utilize the controller's full capabilities, leading to suboptimal data transfer efficiency across the PCIe hierarchy. With this patch, during the host controller probing phase: - When PCIe bus tuning is enabled (not PCIE_BUS_TUNE_OFF) and not PCIE_BUS_PEER2PEER (which requires the default 128 bytes for optimal peer-to-peer operation), and - The device is a Root Port, the Root Port's MPS is set to its maximum supported value. Note that this initial maximum MPS setting may be reduced later, during downstream device enumeration, if any downstream device does not support the Root Port's maximum MPS. This change ensures Root Ports are initialized to their maximum MPS before downstream devices negotiate MPS, while maintaining backward compatibility via the PCIE_BUS_TUNE_OFF check and not interfering with the PCIE_BUS_PEER2PEER strategy. Suggested-by: Niklas Cassel Suggested-by: Manivannan Sadhasivam Signed-off-by: Hans Zhang <18255117159@163.com> Tested-by: Mahesh Vaidya Tested-by: Shawn Lin --- drivers/pci/probe.c | 12 ++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 111111111111..222222222222 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2229,6 +2229,18 @@ static void pci_configure_mps(struct pci_dev *dev) return; } + /* + * Unless MPS strategy is PCIE_BUS_TUNE_OFF (don't touch MPS at all) or + * PCIE_BUS_PEER2PEER (use minimum MPS for peer-to-peer), set Root Ports' + * MPS to their maximum supported value. Depending on the MPS strategy + * and MPSS of downstream devices, a Root Port's MPS may be reduced + * later during device enumeration. + */ + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT && + pcie_bus_config != PCIE_BUS_TUNE_OFF && + pcie_bus_config != PCIE_BUS_PEER2PEER) + pcie_set_mps(dev, 128 << dev->pcie_mpss); + if (!bridge || !pci_is_pcie(bridge)) return; -- Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Hans Zhang <18255117159@163.com> Date: Fri, 28 Nov 2025 01:09:08 +0800 Subject: PCI: dwc: Remove redundant MPS configuration The Meson PCIe controller driver manually configures maximum payload size (MPS) through meson_set_max_payload, duplicating functionality now centralized in the PCI core. Deprecating redundant code simplifies the driver and aligns it with the consolidated MPS management strategy, improving long-term maintainability. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pci-meson.c | 17 ---------- 1 file changed, 17 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c index 111111111111..222222222222 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -272,22 +272,6 @@ static int meson_size_to_payload(struct meson_pcie *mp, int size) return fls(size) - 8; } -static void meson_set_max_payload(struct meson_pcie *mp, int size) -{ - struct dw_pcie *pci = &mp->pci; - u32 val; - u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - int max_payload_size = meson_size_to_payload(mp, size); - - val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val &= ~PCI_EXP_DEVCTL_PAYLOAD; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); - - val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); -} - static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size) { struct dw_pcie *pci = &mp->pci; @@ -362,7 +346,6 @@ static int meson_pcie_host_init(struct dw_pcie_rp *pp) pp->bridge->ops = &meson_pci_ops; - meson_set_max_payload(mp, MAX_PAYLOAD_SIZE); meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); return 0; -- Armbian