From bea4b2ca743e63edb9b926f54d040a185399e0dc Mon Sep 17 00:00:00 2001 From: Patrick Yavitz Date: Sun, 15 Jun 2025 09:36:33 -0400 Subject: [PATCH] Add board NanoPi R3S LTS Signed-off-by: Patrick Yavitz --- configs/nanopi-r3s-lts-rk3566_defconfig | 74 +++++++++++++++++++ .../arm64/rockchip/rk3566-nanopi-r3s-lts.dts | 59 +++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 configs/nanopi-r3s-lts-rk3566_defconfig create mode 100644 dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s-lts.dts diff --git a/configs/nanopi-r3s-lts-rk3566_defconfig b/configs/nanopi-r3s-lts-rk3566_defconfig new file mode 100644 index 00000000000..af983228048 --- /dev/null +++ b/configs/nanopi-r3s-lts-rk3566_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-nanopi-r3s-lts" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_SERIAL=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s-lts.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s-lts.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s-lts.dts new file mode 100644 index 00000000000..e3305f4044d --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s-lts.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; + +#include "rk3566-nanopi-r3s.dts" + +/ { + compatible = "friendlyarm,nanopi-r3s-lts", "rockchip,rk3566"; + model = "FriendlyElec NanoPi R3S LTS"; + + hdmi-con { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; -- 2.43.0