56 lines
2.3 KiB
C
56 lines
2.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __C3_AUDIO_CLK_H__
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#define __C3_AUDIO_CLK_H__
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/*
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* CLKID audio index values
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*/
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/* Audio CLK Gate En0 */
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#define CLKID_AUDIO_GATE_DDR_ARB 0
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#define CLKID_AUDIO_GATE_PDM 1
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#define CLKID_AUDIO_GATE_TDMINA 2
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#define CLKID_AUDIO_GATE_TDMINLB 3
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#define CLKID_AUDIO_GATE_TDMOUTA 4
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#define CLKID_AUDIO_GATE_TDMOUTB 5
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#define CLKID_AUDIO_GATE_FRDDRA 6
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#define CLKID_AUDIO_GATE_FRDDRB 7
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#define CLKID_AUDIO_GATE_FRDDRC 8
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#define CLKID_AUDIO_GATE_TODDRA 9
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#define CLKID_AUDIO_GATE_TODDRB 10
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#define CLKID_AUDIO_GATE_LOOPBACKA 11
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#define CLKID_AUDIO_GATE_RESAMPLEA 12
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#define CLKID_AUDIO_GATE_EQDRC 13
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#define CLKID_AUDIO_GATE_TOVAD 14
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#define CLKID_AUDIO_GATE_AUDIOLOCKER 15
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#define CLKID_AUDIO_GATE_MAX 16
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#define MCLK_BASE CLKID_AUDIO_GATE_MAX
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#define CLKID_AUDIO_MCLK_A (MCLK_BASE + 0)
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#define CLKID_AUDIO_MCLK_B (MCLK_BASE + 1)
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#define CLKID_AUDIO_MCLK_C (MCLK_BASE + 2)
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#define CLKID_AUDIO_MCLK_D (MCLK_BASE + 3)
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#define CLKID_AUDIO_MCLK_E (MCLK_BASE + 4)
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#define CLKID_AUDIO_MCLK_F (MCLK_BASE + 5)
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#define CLKID_AUDIO_RESAMPLE_A (MCLK_BASE + 6)
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#define CLKID_AUDIO_LOCKER_OUT (MCLK_BASE + 7)
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#define CLKID_AUDIO_LOCKER_IN (MCLK_BASE + 8)
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#define CLKID_AUDIO_PDMIN0 (MCLK_BASE + 9)
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#define CLKID_AUDIO_PDMIN1 (MCLK_BASE + 10)
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#define CLKID_AUDIO_EQDRC (MCLK_BASE + 11)
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#define CLKID_AUDIO_VAD (MCLK_BASE + 12)
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#define CLKID_AUDIO_MCLK_PAD0 (MCLK_BASE + 13)
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#define CLKID_AUDIO_MCLK_PAD1 (MCLK_BASE + 14)
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#define CLKID_AUDIO_MCLK_PAD2 (MCLK_BASE + 15)
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#define CLKID_AUDIO_MCLK_PAD3 (MCLK_BASE + 16)
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#define NUM_AUDIO_CLKS (MCLK_BASE + 17)
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#endif /* __C3_AUDIO_CLK_H__ */
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