92 lines
2.1 KiB
C
92 lines
2.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_T5_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_T5_RESET_H
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/* RESET0 */
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/* 0-3 */
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#define RESET_USBCTRL 4
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/* 5-7 */
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#define RESET_USBPHY20 8
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/* 9 */
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#define RESET_USB2DRD 10
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/* 11-31 */
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/* RESET1 */
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#define RESET_AUDIO 32
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#define RESET_AUDIO_VAD 33
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/* 34 */
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#define RESET_DDRAPB 35
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#define RESET_DDR 36
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/* 37-40 */
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#define RESET_DSPA_DEBUG 41
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/* 42 */
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#define RESET_DSPA 43
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/* 44-46 */
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#define RESET_NNA 47
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#define RESET_ETHERNET 48
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/* 49-63 */
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/* RESET2 */
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#define RESET_ABUS_ARB 64
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#define RESET_IRCTRL 65
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/* 66 */
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#define RESET_TEMP_PII 67
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/* 68-72 */
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#define RESET_SPICC_0 73
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#define RESET_SPICC_1 74
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#define RESET_RSA 75
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/* 76-79 */
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#define RESET_MSR_CLK 80
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#define RESET_SPIFC 81
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#define RESET_SAR_ADC 82
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/* 83-90 */
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#define RESET_WATCHDOG 91
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/* 92-95 */
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/* RESET4 */
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#define RESET_RTC 96
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/* 97-99 */
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#define RESET_PWM_AB 100
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#define RESET_PWM_CD 101
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#define RESET_PWM_EF 102
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#define RESET_PWM_GH 103
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/* 104-105 */
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#define RESET_UART_A 106
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#define RESET_UART_B 107
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#define RESET_UART_C 108
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#define RESET_UART_D 109
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#define RESET_UART_E 110
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/* 111*/
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#define RESET_I2C_S_A 112
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#define RESET_I2C_M_A 113
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#define RESET_I2C_M_B 114
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#define RESET_I2C_M_C 115
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#define RESET_I2C_M_D 116
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/* 117-119 */
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#define RESET_SDEMMC_A 120
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/* 121 */
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#define RESET_SDEMMC_C 122
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/* RESET5 */
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/* 128-143 */
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#define RESET_BRG_AO_NIC_SYS 144
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#define RESET_BRG_AO_NIC_DSPA 145
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#define RESET_BRG_AO_NIC_MAIN 146
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#define RESET_BRG_AO_NIC_AUDIO 147
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/* 148-151 */
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#define RESET_BRG_AO_NIC_ALL 152
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#define RESET_BRG_NIC_NNA 153
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#define RESET_BRG_NIC_SDIO 154
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#define RESET_BRG_NIC_EMMC 155
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#define RESET_BRG_NIC_DSU 156
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#define RESET_BRG_NIC_SYSCLK 157
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#define RESET_BRG_NIC_MAIN 158
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#define RESET_BRG_NIC_ALL 159
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#endif
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