247 lines
6.7 KiB
C
247 lines
6.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_A9_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_A9_RESET_H
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/* AO RESET0 */
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#define AO_RESET_APB 0
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#define AO_RESET_RTC 1
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#define AO_RESET_BRG_NIC_RTC 2
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#define AO_RESET_AO2EE 3
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#define AO_RESET_BRG_NIC_EE 4
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#define AO_RESET_WATCHDOG 5
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#define AO_RESET_I3C 6
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#define AO_RESET_PWRCTRL 7
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#define AO_RESET_PWM_A 8
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#define AO_RESET_PWM_B 9
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#define AO_RESET_PWM_C 10
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#define AO_RESET_PWM_D 11
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#define AO_RESET_PWM_E 12
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#define AO_RESET_PWM_F 13
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#define AO_RESET_PWM_G 14
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#define AO_RESET_I2C_M_A 15
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#define AO_RESET_I2C_M_B 16
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#define AO_RESET_I2C_M_C 17
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#define AO_RESET_I2C_M_D 18
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#define AO_RESET_IR_CTRL 19
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#define AO_RESET_UART_B 20
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#define AO_RESET_UART_C 21
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#define AO_RESET_UART_D 22
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#define AO_RESET_SPISG_0 23
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#define AO_RESET_SED 24
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#define AO_RESET_CEC 25
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#define AO_RESET_AOCPU 26
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#define AO_RESET_AOCPU_POR 27
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#define AO_RESET_AOCPU_CORE 28
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#define AO_RESET_AO_SRAM 29
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#define AO_RESET_CAPU 30
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#define AO_RESET_UART_E 31
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/* RESET0 */
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#define RESET_ETH_1G 0
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#define RESET_ISP 1
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#define RESET_U3DRD_USB3PHY_APB 2
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#define RESET_U3DRD_USB3PHY 3
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#define RESET_U3DRD_USB2PHY 4
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#define RESET_U3DRD 5
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#define RESET_U3DRD_COMB 6
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#define RESET_U3DRD_USB2PHY_APB 7
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#define RESET_DP_PHY_APB 8
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#define RESET_DP_PHY 9
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#define RESET_DPTX_1P4 10
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#define RESET_DPTX_1P4_APB 11
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#define RESET_EDPTX_1P4 12
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#define RESET_USB2DRD_PHY_APB 13
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#define RESET_U2DRD 14
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#define RESET_U2DRD_COMB 15
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#define RESET_HDMI20_AES 16
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#define RESET_HDMITX_CAPB3 17
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#define RESET_BRG_VCBUS_DEC 18
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#define RESET_VCBUS 19
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#define RESET_VID_PLL_DIV 20
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#define RESET_VDI6 21
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#define RESET_HDMITXPHY 22
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#define RESET_VID_LOCK 23
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#define RESET_VENC2 24
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#define RESET_VDAC 25
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#define RESET_VENC1 26
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#define RESET_VENC0 27
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#define RESET_RDMA 28
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#define RESET_HDMITX 29
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#define RESET_VIU 30
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#define RESET_VENC 31
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/* RESET1 */
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#define RESET_AUDIO 32
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#define RESET_MALI_CAPB3 33
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#define RESET_MALI 34
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#define RESET_PCIEB_PHY 35
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#define RESET_PCIE_B_POR 36
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#define RESET_DOS_CAPB3 37
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#define RESET_DOS 38
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#define RESET_MALI_SYS 39
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#define RESET_CC 40
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#define RESET_I_DEBUGA 41
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#define RESET_PCIEA_PHY_APB 42
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#define RESET_PCIEA_PIPE 43
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#define RESET_PCIE_A_POR 44
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#define RESET_PCIEA_PHY 45
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#define RESET_PCIEA_MAC_APB 46
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#define RESET_AMFC_APB 47
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#define RESET_ETH 48
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/* 49*/
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#define RESET_MALI_MBIST 50
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#define RESET_ETH_1G_AXI 51
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#define RESET_VICP 52
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#define RESET_DEWARP 53
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#define RESET_GE2D 54
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#define RESET_VGE 55
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#define RESET_PCIEA_0 56
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#define RESET_PCIEA_1 57
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#define RESET_PCIEA_2 58
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#define RESET_PCIEA_3 59
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#define RESET_PCIEA_4 60
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#define RESET_PCIEA_5 61
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#define RESET_PCIEA_6 62
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#define RESET_PCIEA_7 63
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/* RESET2 */
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#define RESET_AM2AXI 64
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#define RESET_DSPA 65
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#define RESET_MIPI_DSI_PHY 66
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#define RESET_TS_PLL 67
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#define RESET_TS_A55 68
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#define RESET_ETH_AXI 69
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#define RESET_TS_CORE 70
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#define RESET_MIPI_DSI1_PHY 71
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#define RESET_SMART_CARD 72
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#define RESET_SPISG_0 73
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#define RESET_TS_DOS 74
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#define RESET_U2DRD_USB2PHY 75
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#define RESET_PIO 76
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#define RESET_U2H 77
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#define RESET_U2H_COMB 78
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/* RESET_USB2H_PHY_APB is not used by U2H. */
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#define RESET_USB2H_PHY_APB 79
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#define RESET_MSR_CLK 80
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/* 81*/
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#define RESET_AUX_DIG 82
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/* 83*/
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#define RESET_U2H_USB2PHY 84
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#define RESET_U3HSG_PCIE_PIPE 85
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#define RESET_AMFC 86
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#define RESET_U3HSG_PCIE2_PHY_APB 87
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#define RESET_U3HSG_PCIE2_PHY 88
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#define RESET_PP_DMA 89
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#define RESET_I3C 90
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#define RESET_WATCHDOG 91
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#define RESET_PP_WRAPPER 92
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#define RESET_MIPI_DSI_HOST 93
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#define RESET_DSI_PLL_DIV 94
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#define RESET_MIPI_DSI_B_HOST 95
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/* RESET3 */
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/* 96*/
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#define RESET_HDMIRX_WRAP_APB 97
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#define RESET_HDMIRX 98
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#define RESET_PCIEB_0 99
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#define RESET_PCIEB_1 100
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#define RESET_PCIEB_2 101
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#define RESET_PCIEB_3 102
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#define RESET_PCIEB_4 103
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#define RESET_PCIEB_5 104
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#define RESET_PCIEB_6 105
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#define RESET_PCIEB_7 106
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#define RESET_PCIEB_PIPE 107
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#define RESET_PCIEB_MAC_APB 108
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#define RESET_NNA_TO_VGA_PIPEL 109
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#define RESET_CVE 110
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#define RESET_GLOBAL_TIMER 111
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#define RESET_COMBO_DPHY_PCLK 112
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#define RESET_COMBO_DPHY 113
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/* 114 - 118*/
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#define RESET_U3PHY30_APB 119
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#define RESET_U3PHY30 120
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#define RESET_HSG 121
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#define RESET_U3HSG_HSG 122
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#define RESET_U3DRDB 123
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#define RESET_U3DRDB_APB 124
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#define RESET_U3PHY20_APB 125
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#define RESET_U3PHY20 126
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#define RESET_A55_ACE 127
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/* RESET4 */
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#define RESET_CAN0 128
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#define RESET_CAN1 129
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#define RESET_TAHOE_CORE 130
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#define RESET_TAHOE 131
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#define RESET_TAHOE_APB 132
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#define RESET_TAHOE_SYS 133
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/* 134 - 135*/
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#define RESET_PWM_I 136
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#define RESET_PWM_J 137
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#define RESET_UART_A 138
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/* 139 - 143*/
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#define RESET_MALI_AVBCD 144
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#define RESET_MALI_AVBCD_APB 145
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#define RESET_MALI_MCR_TOP 146
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#define RESET_I2C_M_E 147
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#define RESET_I2C_M_F 148
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#define RESET_I2C_M_G 149
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#define RESET_I2C_M_H 150
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#define RESET_I2C_M_I 151
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#define RESET_SD_EMMC_A 152
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#define RESET_SD_EMMC_B 153
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#define RESET_SD_EMMC_C 154
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#define RESET_UART_F 155
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#define RESET_PWM_N 156
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#define RESET_PWM_M 157
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#define RESET_PWM_L 158
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#define RESET_PWM_K 159
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/* RESET5 */
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#define RESET_BRG_ISP_PIPEL1 160
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#define RESET_BRG_HEVCF_DMC_PIPEL 161
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#define RESET_BRG_HEVCB_PIPEL1 162
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#define RESET_BRG_EMMC_PIPEL1 163
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#define RESET_BRG_VGE_PIPEL1 164
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#define RESET_BRG_DMC_VPU1_PIPEL 165
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#define RESET_BRG_DMC_VPU0_PIPEL 166
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#define RESET_BRG_NNA_PIPEL1 167
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#define RESET_BRG_NNA_SRAM_PIPEL1 168
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#define RESET_BRG_U2DRDA_PIPEL1 169
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#define RESET_BRG_U3DRDA_PIPEL1 170
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/* 171 - 173*/
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#define RESET_BRG_NIC_AOSYS 174
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#define RESET_BRG_NIC_AMFC 175
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#define RESET_BRG_NIC_GIC 176
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#define RESET_BRG_SRAM_NIC_NNA 177
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#define RESET_BRG_SRAM_NIC_MAIN 178
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#define RESET_BRG_SRAM_NIC_ALL 179
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#define RESET_BRG_NIC_SOCBRG 180
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#define RESET_BRG_NIC_GPV 181
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#define RESET_BRG_NIC_AO 182
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#define RESET_BRG_NIC_EMMC 183
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#define RESET_BRG_NIC_DSPA 184
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#define RESET_BRG_NIC_SDIOB 185
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#define RESET_BRG_NIC_SDIOA 186
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#define RESET_BRG_NIC_VAPB 187
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#define RESET_BRG_NIC_DSU 188
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#define RESET_BRG_NIC_CLK81 189
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#define RESET_BRG_NIC_MAIN 190
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#define RESET_BRG_NIC_ALL 191
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/* RESET6 */
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/* 192 - 216*/
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#define RESET_BRG_PP_CLK 217
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#define RESET_BRG_PP_NIC_CLK81 218
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/* 219 - 220*/
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#define RESET_BRG_PERIPH_APB_SYNC 221
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#define RESET_BRG_VPU_APB_SYNC 222
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#define RESET_BRG_DSPA_PIPEL1 223
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#endif
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