64 lines
2.0 KiB
C
64 lines
2.0 KiB
C
/*
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* Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef __SOC_H
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#define __SOC_H
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#ifndef __ASM
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#include "FreeRTOSConfig.h"
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#include "riscv_const.h"
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#include "irq.h"
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#include "register.h"
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#endif
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#define SOC_ECLIC_NUM_INTERRUPTS 32
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#define SOC_TIMER_FREQ configCPU_CLOCK_HZ
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#define SOC_ECLIC_CTRL_ADDR 0x0C000000UL
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#define SOC_TIMER_CTRL_ADDR 0x02000000UL
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#define SOC_PMP_BASE 0xff100000UL
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#define SOC_LOCAL_SRAM_BASE 0x10000000UL
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#define SRAM_BEGIN SOC_LOCAL_SRAM_BASE
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#define SRAM_SIZE (0x20000)//(96*1024)
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#define SRAM_END (SRAM_BEGIN + SRAM_SIZE)
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#define IO_BASE 0xff000000UL
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#define IO_SIZE 0x00100000
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#define IO_BEGIN (IO_BASE)
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#define IO_END (IO_BASE + IO_SIZE)
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/* There're more than 255 interrupts in this chip, each interrupt
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* mapping need at least 9 bits, so each register has only two
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* regions to map the interrupt.
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*/
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#define AOCPU_IRQ_NUMS_ABOVE_255
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/*SoC/Shadow register mapping*/
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#define VRTC_PARA_REG SYSCTRL_STATUS_REG2
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#define VRTC_STICKY_REG SYSCTRL_STICKY_REG2
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#define VRTC_TIMER_CTRL SYSCTRL_TIMERD_CTRL
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#define VRTC_TIMER SYSCTRL_TIMERD
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#define TIMERE_LOW_REG SYSCTRL_TIMERE
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#define TIMERE_HIG_REG SYSCTRL_TIMERE_HI
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#define WAKEUP_REASON_STICK_REG SYSCTRL_STICKY_REG7
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#define FSM_TRIGER_CTRL SYSCTRL_TIMERB_CTRL
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#define FSM_TRIGER_SRC SYSCTRL_TIMERB
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#define TIMER_CLK_SEL_SYS_CLK 0
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#define TIMER_CLK_SEL_1US 1
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#define TIMER_CLK_SEL_10US 2
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#define TIMER_CLK_SEL_100US 3
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#define TIMER_MODE_IRQ_PERIO (1 << 6)
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#define TIMER_EN (1 << 7)
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#define UART_PORT_CONS UART_B_WFIFO
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#define SYSCTRL_TIMER SYSCTRL_TIMERJ
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#define SYSTICK_TIMER_CTRL SYSCTRL_TIMERJ_CTRL
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#define SYSTICK_TIMER_CTRL_PARM (TIMER_MODE_IRQ_PERIO | TIMER_EN | TIMER_CLK_SEL_1US)
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#define AOCPU_ALIVE_REG_VAL_WR (*(volatile uint32_t *)MAILBOX_BUF_MBOX04)
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#define AOCPU_ALIVE_REG_VAL_RD (*(volatile uint32_t *)MAILBOX_BUF_MBOX04)
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#endif
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