131 lines
4.7 KiB
Diff
131 lines
4.7 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Date: Sun, 14 Mar 2021 04:52:34 +0300
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Subject: drm/msm/dpu1: improve support for active CTLs
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- Support setting master interface if several INTFs are to be handled by
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a single CTL
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- Support setting handling several MERGE_3D instances using a single
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CTL.
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Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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[Marijn: Rebase patch on -next, fix conflicting implementation with
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recent MERGE_3D patch, implement proper active support for DSC]
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Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
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---
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drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 38 ++++++++--
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drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 +
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2 files changed, 32 insertions(+), 8 deletions(-)
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diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
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index 111111111111..222222222222 100644
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--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
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+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
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@@ -544,10 +544,12 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
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struct dpu_hw_intf_cfg *cfg)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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- u32 intf_active = 0;
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- u32 dsc_active = 0;
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- u32 wb_active = 0;
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u32 mode_sel = 0;
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+ u32 cdm_active;
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+ u32 intf_active;
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+ u32 wb_active;
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+ u32 dsc_active;
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+ u32 merge_3d_active;
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/* CTL_TOP[31:28] carries group_id to collate CTL paths
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* per VM. Explicitly disable it until VM support is
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@@ -559,9 +561,14 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
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if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
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mode_sel |= BIT(17);
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+ cdm_active = DPU_REG_READ(c, CTL_CDM_ACTIVE);
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intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
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wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE);
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dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE);
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+ merge_3d_active = DPU_REG_READ(c, CTL_MERGE_3D_ACTIVE);
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+
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+ if (cfg->cdm)
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+ cdm_active |= cfg->cdm;
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if (cfg->intf)
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intf_active |= BIT(cfg->intf - INTF_0);
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@@ -572,17 +579,23 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
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if (cfg->dsc)
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dsc_active |= cfg->dsc;
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+ if (cfg->merge_3d)
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+ merge_3d_active |= BIT(cfg->merge_3d - MERGE_3D_0);
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+
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DPU_REG_WRITE(c, CTL_TOP, mode_sel);
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+ DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cdm_active);
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DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
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DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
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DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
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+ DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
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- if (cfg->merge_3d)
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- DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
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- BIT(cfg->merge_3d - MERGE_3D_0));
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+ if (cfg->intf_master)
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+ DPU_REG_WRITE(c, CTL_INTF_MASTER, BIT(cfg->intf_master - INTF_0));
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- if (cfg->cdm)
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- DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm);
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+ if (cfg->intf_master)
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+ DPU_DEBUG_DRIVER("ACTIVE: intf:%#x merge_3d:%#x dsc:%#x master_intf:%d\n", intf_active, merge_3d_active, dsc_active, cfg->intf_master - INTF_0);
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+ else
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+ DPU_DEBUG_DRIVER("ACTIVE: intf:%#x merge_3d:%#x dsc:%#x\n", intf_active, merge_3d_active, dsc_active);
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}
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static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
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@@ -623,6 +636,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx,
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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u32 intf_active = 0;
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+ u32 intf_master = 0;
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u32 wb_active = 0;
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u32 merge3d_active = 0;
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u32 dsc_active;
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@@ -649,6 +663,14 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx,
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intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
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intf_active &= ~BIT(cfg->intf - INTF_0);
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DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
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+
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+ /* Unset this intf as master, if it is the current master */
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+ /* TODO: Marijn: does this make any sense? */
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+ intf_master = DPU_REG_READ(c, CTL_INTF_MASTER);
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+ if (intf_master == BIT(cfg->intf - INTF_0)) {
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+ DPU_DEBUG_DRIVER("Unsetting intf:%d master\n", cfg->intf - INTF_0);
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+ DPU_REG_WRITE(c, CTL_INTF_MASTER, 0);
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+ }
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}
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if (cfg->wb) {
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diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
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index 111111111111..222222222222 100644
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--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
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+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
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@@ -36,6 +36,7 @@ struct dpu_hw_stage_cfg {
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/**
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* struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
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* @intf : Interface id
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+ * @intf_master: Master interface id in the dual pipe topology
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* @mode_3d: 3d mux configuration
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* @merge_3d: 3d merge block used
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* @intf_mode_sel: Interface mode, cmd / vid
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@@ -45,6 +46,7 @@ struct dpu_hw_stage_cfg {
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*/
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struct dpu_hw_intf_cfg {
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enum dpu_intf intf;
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+ enum dpu_intf intf_master;
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enum dpu_wb wb;
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enum dpu_3d_blend_mode mode_3d;
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enum dpu_merge_3d merge_3d;
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--
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Armbian
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