210 lines
5.4 KiB
Diff
210 lines
5.4 KiB
Diff
From be6c079fabc8012e1c89bc34d046031675da3be5 Mon Sep 17 00:00:00 2001
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From: map220v <map220v300@gmail.com>
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Date: Wed, 15 Jan 2025 15:20:29 +0000
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Subject: [PATCH] SM8550: Fix L2 cache for CPU2 and add cache sizes
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---
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arch/arm64/boot/dts/qcom/sm8550.dtsi | 80 +++++++++++++++++++++++++---
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1 file changed, 73 insertions(+), 7 deletions(-)
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diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
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index eac8de4005d8..f49f9ca2235a 100644
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--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
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+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
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@@ -71,6 +71,12 @@
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reg = <0 0>;
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clocks = <&cpufreq_hw 0>;
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enable-method = "psci";
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <128>;
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <128>;
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next-level-cache = <&l2_0>;
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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@@ -82,11 +88,17 @@
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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+ cache-size = <0x20000>;
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+ cache-line-size = <64>;
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+ cache-sets = <256>;
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next-level-cache = <&l3_0>;
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l3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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+ cache-size = <0x800000>;
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+ cache-line-size = <64>;
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+ cache-sets = <8192>;
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};
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};
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};
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@@ -97,6 +109,12 @@
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reg = <0 0x100>;
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clocks = <&cpufreq_hw 0>;
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enable-method = "psci";
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <128>;
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <128>;
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next-level-cache = <&l2_100>;
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power-domains = <&cpu_pd1>;
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power-domain-names = "psci";
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@@ -108,6 +126,9 @@
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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+ cache-size = <0x40000>;
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+ cache-line-size = <64>;
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+ cache-sets = <512>;
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next-level-cache = <&l3_0>;
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};
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};
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@@ -118,19 +139,19 @@
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reg = <0 0x200>;
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clocks = <&cpufreq_hw 0>;
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enable-method = "psci";
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- next-level-cache = <&l2_200>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <128>;
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <128>;
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+ next-level-cache = <&l2_100>;
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power-domains = <&cpu_pd2>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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#cooling-cells = <2>;
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- l2_200: l2-cache {
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- compatible = "cache";
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- cache-level = <2>;
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- cache-unified;
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- next-level-cache = <&l3_0>;
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- };
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};
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cpu3: cpu@300 {
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@@ -139,6 +160,12 @@
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reg = <0 0x300>;
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clocks = <&cpufreq_hw 1>;
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enable-method = "psci";
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <128>;
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <128>;
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next-level-cache = <&l2_300>;
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power-domains = <&cpu_pd3>;
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power-domain-names = "psci";
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@@ -150,6 +177,9 @@
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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+ cache-size = <0x80000>;
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+ cache-line-size = <64>;
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+ cache-sets = <1024>;
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next-level-cache = <&l3_0>;
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};
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};
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@@ -160,6 +190,12 @@
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reg = <0 0x400>;
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clocks = <&cpufreq_hw 1>;
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enable-method = "psci";
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <128>;
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <128>;
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next-level-cache = <&l2_400>;
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power-domains = <&cpu_pd4>;
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power-domain-names = "psci";
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@@ -171,6 +207,9 @@
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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+ cache-size = <0x80000>;
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+ cache-line-size = <64>;
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+ cache-sets = <1024>;
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next-level-cache = <&l3_0>;
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};
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};
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@@ -181,6 +220,12 @@
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reg = <0 0x500>;
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clocks = <&cpufreq_hw 1>;
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enable-method = "psci";
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <128>;
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <128>;
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next-level-cache = <&l2_500>;
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power-domains = <&cpu_pd5>;
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power-domain-names = "psci";
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@@ -192,6 +237,9 @@
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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+ cache-size = <0x80000>;
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+ cache-line-size = <64>;
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+ cache-sets = <1024>;
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next-level-cache = <&l3_0>;
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};
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};
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@@ -202,6 +250,12 @@
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reg = <0 0x600>;
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clocks = <&cpufreq_hw 1>;
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enable-method = "psci";
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <128>;
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <128>;
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next-level-cache = <&l2_600>;
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power-domains = <&cpu_pd6>;
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power-domain-names = "psci";
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@@ -213,6 +267,9 @@
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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+ cache-size = <0x80000>;
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+ cache-line-size = <64>;
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+ cache-sets = <1024>;
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next-level-cache = <&l3_0>;
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};
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};
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@@ -223,6 +280,12 @@
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reg = <0 0x700>;
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clocks = <&cpufreq_hw 2>;
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enable-method = "psci";
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+ d-cache-size = <0x10000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ i-cache-size = <0x10000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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next-level-cache = <&l2_700>;
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power-domains = <&cpu_pd7>;
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power-domain-names = "psci";
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@@ -234,6 +297,9 @@
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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+ cache-size = <0x100000>;
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+ cache-line-size = <64>;
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+ cache-sets = <2048>;
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next-level-cache = <&l3_0>;
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};
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};
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