119 lines
3.1 KiB
Diff
119 lines
3.1 KiB
Diff
From 8d65c3d60bb0fa951d782e67f58a0dbd69e00f2f Mon Sep 17 00:00:00 2001
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From: Paolo Sabatino <paolo.sabatino@gmail.com>
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Date: Fri, 19 Sep 2025 14:41:26 +0200
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Subject: [PATCH 1/2] Dusun DSOM-010R defconfig
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---
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configs/dusun-dsom-010r-rk3328_defconfig | 99 ++++++++++++++++++++++++
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1 file changed, 99 insertions(+)
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create mode 100644 configs/dusun-dsom-010r-rk3328_defconfig
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diff --git a/configs/dusun-dsom-010r-rk3328_defconfig b/configs/dusun-dsom-010r-rk3328_defconfig
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new file mode 100644
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index 0000000000..87f5c97eae
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--- /dev/null
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+++ b/configs/dusun-dsom-010r-rk3328_defconfig
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@@ -0,0 +1,99 @@
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+CONFIG_ARM=y
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+CONFIG_SKIP_LOWLEVEL_INIT=y
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+CONFIG_COUNTER_FREQUENCY=24000000
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+CONFIG_ARCH_ROCKCHIP=y
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+CONFIG_SPL_GPIO=y
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+CONFIG_NR_DRAM_BANKS=1
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+CONFIG_SF_DEFAULT_SPEED=20000000
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+CONFIG_ENV_OFFSET=0x3F8000
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+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-dusun-dsom-010r"
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+CONFIG_DM_RESET=y
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+CONFIG_ROCKCHIP_RK3328=y
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+CONFIG_ROCKCHIP_EXTERNAL_TPL=y
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+CONFIG_SYS_LOAD_ADDR=0x800800
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+CONFIG_DEBUG_UART_BASE=0xFF130000
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+CONFIG_DEBUG_UART_CLOCK=24000000
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+CONFIG_DEBUG_UART=y
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+CONFIG_FIT=y
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+CONFIG_FIT_VERBOSE=y
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+CONFIG_SPL_FIT_SIGNATURE=y
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+CONFIG_SPL_LOAD_FIT=y
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+CONFIG_LEGACY_IMAGE_FORMAT=y
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+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"
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+# CONFIG_DISPLAY_CPUINFO is not set
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+CONFIG_DISPLAY_BOARDINFO_LATE=y
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+CONFIG_SPL_MAX_SIZE=0x40000
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+CONFIG_SPL_PAD_TO=0x7f8000
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+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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+CONFIG_SPL_POWER=y
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+CONFIG_SPL_ATF=y
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+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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+CONFIG_CMD_BOOTZ=y
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+CONFIG_CMD_GPIO=y
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+CONFIG_CMD_GPT=y
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+CONFIG_CMD_MMC=y
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+CONFIG_CMD_USB=y
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+CONFIG_CMD_TIME=y
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+CONFIG_CMD_REGULATOR=y
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+CONFIG_SPL_OF_CONTROL=y
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+CONFIG_TPL_OF_CONTROL=y
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+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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+CONFIG_TPL_OF_PLATDATA=y
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+CONFIG_ENV_IS_IN_MMC=y
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+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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+CONFIG_SYS_MMC_ENV_DEV=1
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+CONFIG_TPL_DM=y
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+CONFIG_SPL_DM_SEQ_ALIAS=y
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+CONFIG_REGMAP=y
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+CONFIG_SPL_REGMAP=y
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+CONFIG_TPL_REGMAP=y
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+CONFIG_SYSCON=y
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+CONFIG_SPL_SYSCON=y
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+CONFIG_TPL_SYSCON=y
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+CONFIG_CLK=y
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+CONFIG_SPL_CLK=y
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+CONFIG_ROCKCHIP_GPIO=y
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+CONFIG_SYS_I2C_ROCKCHIP=y
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+CONFIG_LED=y
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+CONFIG_LED_GPIO=y
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+CONFIG_MMC_DW=y
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+CONFIG_MMC_DW_ROCKCHIP=y
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+CONFIG_PHY_REALTEK=y
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+CONFIG_DM_MDIO=y
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+CONFIG_DM_ETH_PHY=y
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+CONFIG_PHY_GIGE=y
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+CONFIG_ETH_DESIGNWARE=y
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+CONFIG_GMAC_ROCKCHIP=y
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+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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+CONFIG_PINCTRL=y
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+CONFIG_SPL_PINCTRL=y
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+CONFIG_DM_PMIC=y
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+CONFIG_PMIC_RK8XX=y
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+CONFIG_SPL_DM_REGULATOR=y
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+CONFIG_DM_REGULATOR_FIXED=y
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+CONFIG_SPL_DM_REGULATOR_FIXED=y
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+CONFIG_REGULATOR_RK8XX=y
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+CONFIG_PWM_ROCKCHIP=y
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+CONFIG_RAM=y
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+CONFIG_SPL_RAM=y
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+CONFIG_TPL_RAM=y
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+CONFIG_DM_RNG=y
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+CONFIG_RNG_ROCKCHIP=y
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+CONFIG_BAUDRATE=1500000
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+CONFIG_DEBUG_UART_SHIFT=2
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+CONFIG_SYS_NS16550_MEM32=y
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+CONFIG_SYSINFO=y
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+CONFIG_SYSINFO_SMBIOS=y
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+CONFIG_SYSRESET=y
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+# CONFIG_TPL_SYSRESET is not set
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+CONFIG_USB=y
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+CONFIG_USB_XHCI_HCD=y
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+CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB_EHCI_GENERIC=y
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+CONFIG_USB_OHCI_HCD=y
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+CONFIG_USB_OHCI_GENERIC=y
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+CONFIG_USB_DWC3=y
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+CONFIG_USB_DWC3_GENERIC=y
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+CONFIG_SPL_TINY_MEMSET=y
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+CONFIG_TPL_TINY_MEMSET=y
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+CONFIG_ERRNO_STR=y
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--
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2.43.0
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