290 lines
15 KiB
C
290 lines
15 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H
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#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H
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#define CLKID_GP0_PLL 0
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#define CLKID_HIFI_PLL 1
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#define CLKID_HDMI_PLL_DCO 2
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#define CLKID_MPLL_PREDIV 3
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#define CLKID_MPLL0 4
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#define CLKID_MPLL0_DIV 5
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#define CLKID_MPLL1 6
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#define CLKID_MPLL1_DIV 7
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#define CLKID_MPLL2 8
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#define CLKID_MPLL2_DIV 9
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#define CLKID_MPLL3 10
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#define CLKID_MPLL3_DIV 11
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#define CLKID_HDMI_PLL_OD 12
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#define CLKID_HDMI_PLL 13
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#define CLKID_FCLK_DIV2_DIV 14
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#define CLKID_FCLK_DIV2 15
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#define CLKID_FCLK_DIV2P5_DIV 16
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#define CLKID_FCLK_DIV2P5 17
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#define CLKID_FCLK_DIV3_DIV 18
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#define CLKID_FCLK_DIV3 19
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#define CLKID_FCLK_DIV4_DIV 20
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#define CLKID_FCLK_DIV4 21
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#define CLKID_FCLK_DIV5_DIV 22
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#define CLKID_FCLK_DIV5 23
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#define CLKID_FCLK_DIV7_DIV 24
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#define CLKID_FCLK_DIV7 25
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#define CLKID_RTC_DUAL_CLKIN 26
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#define CLKID_RTC_DUAL_DIV 27
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#define CLKID_RTC_DUAL_MUX 28
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#define CLKID_RTC_DUAL 29
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#define CLKID_RTC_CLK 30
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#define CLKID_CECA_DUAL_CLKIN 31
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#define CLKID_CECA_DUAL_DIV 32
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#define CLKID_CECA_DUAL_MUX 33
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#define CLKID_CECA_DUAL 34
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#define CLKID_CECA_CLK 35
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#define CLKID_CECB_DUAL_CLKIN 36
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#define CLKID_CECB_DUAL_DIV 37
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#define CLKID_CECB_DUAL_MUX 38
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#define CLKID_CECB_DUAL 39
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#define CLKID_CECB_CLK 40
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#define CLKID_RAMA_0_MUX 41
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#define CLKID_RAMA_0_DIV 42
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#define CLKID_RAMA_0 43
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#define CLKID_RAMA_1_MUX 44
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#define CLKID_RAMA_1_DIV 45
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#define CLKID_RAMA_1 46
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#define CLKID_RAMA 47
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#define CLKID_SAR_ADC_MUX 48
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#define CLKID_SAR_ADC_DIV 49
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#define CLKID_SAR_ADC 50
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#define CLKID_SC_MUX 51
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#define CLKID_SC_DIV 52
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#define CLKID_SC 53
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#define CLKID_CDAC_MUX 54
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#define CLKID_CDAC_DIV 55
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#define CLKID_CDAC 56
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#define CLKID_VID_PLL_DIV 57
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#define CLKID_VID_PLL_SEL 58
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#define CLKID_VID_PLL 59
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#define CLKID_VIDEO_SRC0_IN_MUX 60
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#define CLKID_VIDEO_SRC0_IN 61
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#define CLKID_VIDEO_SRC0_DIV 62
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#define CLKID_VIDEO_SRC0 63
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#define CLKID_VIDEO_SRC1_IN_MUX 64
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#define CLKID_VIDEO_SRC1_IN 65
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#define CLKID_VIDEO_SRC1_DIV 66
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#define CLKID_VIDEO_SRC1 67
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#define CLKID_VIDEO0_DIV1 68
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#define CLKID_VIDEO0_DIV2_GATE 69
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#define CLKID_VIDEO0_DIV2 70
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#define CLKID_VIDEO0_DIV4_GATE 71
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#define CLKID_VIDEO0_DIV4 72
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#define CLKID_VIDEO0_DIV6_GATE 73
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#define CLKID_VIDEO0_DIV6 74
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#define CLKID_VIDEO0_DIV12_GATE 75
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#define CLKID_VIDEO0_DIV12 76
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#define CLKID_VIDEO2_DIV1 77
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#define CLKID_VIDEO2_DIV2_GATE 78
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#define CLKID_VIDEO2_DIV2 79
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#define CLKID_VIDEO2_DIV4_GATE 80
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#define CLKID_VIDEO2_DIV4 81
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#define CLKID_VIDEO2_DIV6_GATE 82
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#define CLKID_VIDEO2_DIV6 83
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#define CLKID_VIDEO2_DIV12_GATE 84
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#define CLKID_VIDEO2_DIV12 85
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#define CLKID_LCD_AN_MUX 86
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#define CLKID_LCD_AN 87
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#define CLKID_LCD_AN_PH2 88
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#define CLKID_LCD_AN_PH3 89
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#define CLKID_HDMITX_PIXEL_MUX 90
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#define CLKID_HDMITX_PIXEL 91
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#define CLKID_ENCI_MUX 92
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#define CLKID_ENCI 93
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#define CLKID_ENCP_MUX 94
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#define CLKID_ENCP 95
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#define CLKID_ENCT_MUX 96
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#define CLKID_ENCT 97
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#define CLKID_ENCL_MUX 98
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#define CLKID_ENCL 99
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#define CLKID_VDAC_MUX 100
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#define CLKID_VDAC 101
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#define CLKID_VID_LOCK_MUX 102
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#define CLKID_VID_LOCK_DIV 103
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#define CLKID_VID_LOCK 104
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#define CLKID_MALI_0_MUX 105
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#define CLKID_MALI_0_DIV 106
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#define CLKID_MALI_0 107
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#define CLKID_MALI_1_MUX 108
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#define CLKID_MALI_1_DIV 109
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#define CLKID_MALI_1 110
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#define CLKID_MALI 111
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#define CLKID_VDEC_0_MUX 112
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#define CLKID_VDEC_0_DIV 113
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#define CLKID_VDEC_0 114
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#define CLKID_VDEC_1_MUX 115
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#define CLKID_VDEC_1_DIV 116
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#define CLKID_VDEC_1 117
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#define CLKID_VDEC 118
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#define CLKID_HEVCF_0_MUX 119
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#define CLKID_HEVCF_0_DIV 120
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#define CLKID_HEVCF_0 121
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#define CLKID_HEVCF_1_MUX 122
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#define CLKID_HEVCF_1_DIV 123
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#define CLKID_HEVCF_1 124
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#define CLKID_HEVCF 125
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#define CLKID_VPU_0_MUX 126
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#define CLKID_VPU_0_DIV 127
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#define CLKID_VPU_0 128
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#define CLKID_VPU_1_MUX 129
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#define CLKID_VPU_1_DIV 130
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#define CLKID_VPU_1 131
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#define CLKID_VPU 132
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#define CLKID_VPU_CLKB_TMP_MUX 133
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#define CLKID_VPU_CLKB_TMP_DIV 134
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#define CLKID_VPU_CLKB_TMP 135
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#define CLKID_VPU_CLKB_DIV 136
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#define CLKID_VPU_CLKB 137
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#define CLKID_VPU_CLKC_0_MUX 138
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#define CLKID_VPU_CLKC_0_DIV 139
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#define CLKID_VPU_CLKC_0 140
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#define CLKID_VPU_CLKC_1_MUX 141
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#define CLKID_VPU_CLKC_1_DIV 142
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#define CLKID_VPU_CLKC_1 143
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#define CLKID_VPU_CLKC 144
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#define CLKID_VAPB_0_MUX 145
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#define CLKID_VAPB_0_DIV 146
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#define CLKID_VAPB_0 147
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#define CLKID_VAPB_1_MUX 148
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#define CLKID_VAPB_1_DIV 149
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#define CLKID_VAPB_1 150
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#define CLKID_VAPB 151
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#define CLKID_GE2D 152
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#define CLKID_VDIN_MEAS_MUX 153
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#define CLKID_VDIN_MEAS_DIV 154
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#define CLKID_VDIN_MEAS 155
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#define CLKID_SD_EMMC_A_MUX 156
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#define CLKID_SD_EMMC_A_DIV 157
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#define CLKID_SD_EMMC_A 158
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#define CLKID_SD_EMMC_B_MUX 159
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#define CLKID_SD_EMMC_B_DIV 160
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#define CLKID_SD_EMMC_B 161
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#define CLKID_SD_EMMC_C_MUX 162
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#define CLKID_SD_EMMC_C_DIV 163
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#define CLKID_SD_EMMC_C 164
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#define CLKID_SPICC0_MUX 165
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#define CLKID_SPICC0_DIV 166
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#define CLKID_SPICC0 167
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#define CLKID_PWM_A_MUX 168
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#define CLKID_PWM_A_DIV 169
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#define CLKID_PWM_A 170
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#define CLKID_PWM_B_MUX 171
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#define CLKID_PWM_B_DIV 172
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#define CLKID_PWM_B 173
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#define CLKID_PWM_C_MUX 174
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#define CLKID_PWM_C_DIV 175
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#define CLKID_PWM_C 176
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#define CLKID_PWM_D_MUX 177
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#define CLKID_PWM_D_DIV 178
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#define CLKID_PWM_D 179
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#define CLKID_PWM_E_MUX 180
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#define CLKID_PWM_E_DIV 181
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#define CLKID_PWM_E 182
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#define CLKID_PWM_F_MUX 183
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#define CLKID_PWM_F_DIV 184
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#define CLKID_PWM_F 185
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#define CLKID_PWM_G_MUX 186
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#define CLKID_PWM_G_DIV 187
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#define CLKID_PWM_G 188
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#define CLKID_PWM_H_MUX 189
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#define CLKID_PWM_H_DIV 190
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#define CLKID_PWM_H 191
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#define CLKID_PWM_I_MUX 192
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#define CLKID_PWM_I_DIV 193
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#define CLKID_PWM_I 194
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#define CLKID_PWM_J_MUX 195
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#define CLKID_PWM_J_DIV 196
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#define CLKID_PWM_J 197
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#define CLKID_HDMITX_SYS_MUX 198
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#define CLKID_HDMITX_SYS_DIV 199
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#define CLKID_HDMITX_SYS 200
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#define CLKID_HDCP22_ESM_MUX 201
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#define CLKID_HDCP22_ESM_DIV 202
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#define CLKID_HDCP22_ESM 203
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#define CLKID_HDCP22_SKP_MUX 204
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#define CLKID_HDCP22_SKP_DIV 205
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#define CLKID_HDCP22_SKP 206
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#define CLKID_DEMOD_CORE_MUX 207
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#define CLKID_DEMOD_CORE_DIV 208
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#define CLKID_DEMOD_CORE 209
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#define CLKID_DEMOD_CORE_T2_MUX 210
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#define CLKID_DEMOD_CORE_T2_DIV 211
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#define CLKID_DEMOD_CORE_T2 212
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#define CLKID_DEMOD_32K_CLKIN 213
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#define CLKID_DEMOD_32K_DIV 214
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#define CLKID_DEMOD_32K_MUX 215
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#define CLKID_DEMOD_32K 216
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#define CLKID_ADC_EXTCLK_IN_MUX 217
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#define CLKID_ADC_EXTCLK_IN_DIV 218
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#define CLKID_ADC_EXTCLK_IN 219
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#define CLKID_ETH_CLK_RMII_DIV 220
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#define CLKID_ETH_CLK_RMII 221
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#define CLKID_ETH_CLK125M_DIV 222
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#define CLKID_ETH_CLK125M 223
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#define CLKID_TS_DIV 224
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#define CLKID_TS 225
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#define CLKID_GEN_MUX 226
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#define CLKID_GEN_DIV 227
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#define CLKID_GEN 228
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#define CLKID_SYS_DDR 229
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#define CLKID_SYS_DOS 230
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#define CLKID_SYS_ETH_PHY 231
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#define CLKID_SYS_MALI 232
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#define CLKID_SYS_AOCPU 233
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#define CLKID_SYS_AUCPU 234
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#define CLKID_SYS_CEC 235
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#define CLKID_SYS_SD_EMMC_A 236
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#define CLKID_SYS_SD_EMMC_B 237
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#define CLKID_SYS_SD_EMMC_C 238
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#define CLKID_SYS_SMARTCARD 239
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#define CLKID_SYS_ACODEC 240
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#define CLKID_SYS_SPIFC 241
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#define CLKID_SYS_MSR_CLK 242
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#define CLKID_SYS_IR_CTRL 243
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#define CLKID_SYS_AUDIO 244
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#define CLKID_SYS_ETH 245
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#define CLKID_SYS_UART_A 246
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#define CLKID_SYS_UART_B 247
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#define CLKID_SYS_UART_C 248
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#define CLKID_SYS_UART_D 249
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#define CLKID_SYS_UART_E 250
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#define CLKID_SYS_AIFIFO 251
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#define CLKID_SYS_TS_DDR 252
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#define CLKID_SYS_TS_PLL 253
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#define CLKID_SYS_GE2D 254
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#define CLKID_SYS_SPICC0 255
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#define CLKID_SYS_USB 256
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#define CLKID_SYS_I2C_M_A 257
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#define CLKID_SYS_I2C_M_B 258
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#define CLKID_SYS_I2C_M_C 259
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#define CLKID_SYS_I2C_M_D 260
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#define CLKID_SYS_I2C_M_E 261
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#define CLKID_SYS_I2C_M_F 262
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#define CLKID_SYS_HDMITX_APB 263
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#define CLKID_SYS_I2C_S_A 264
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#define CLKID_SYS_USB1_TO_DDR 265
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#define CLKID_SYS_HDCP22 266
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#define CLKID_SYS_MMC_APB 267
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#define CLKID_SYS_RSA 268
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#define CLKID_SYS_CPU_DEBUG 269
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#define CLKID_SYS_VPU_INTR 270
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#define CLKID_SYS_DEMOD 271
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#define CLKID_SYS_SAR_ADC 272
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#define CLKID_SYS_GIC 273
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#define CLKID_SYS_PWM_AB 274
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#define CLKID_SYS_PWM_CD 275
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#define CLKID_SYS_PWM_EF 276
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#define CLKID_SYS_PWM_GH 277
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#define CLKID_SYS_PWM_IJ 278
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#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H */
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