269 lines
7.7 KiB
C
269 lines
7.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __DEBUG_IOTM_HW_H_
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#define __DEBUG_IOTM_HW_H_
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#include <linux/list.h>
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#define AML_IOTM_SMC_CMD 0x8200007A
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#define AML_IOTM_INIT_SMC_ARG 0x1
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#define AML_IOTM_RANGE_SMC_ARG 0x2
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#define AML_IOTM_JTAG_SMC_ARG 0x3
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#define AML_IOTM_SHUTDOWN_SMC_ARG 0x4
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#define AML_IOTM_JTAG_DISABLE_SMC_ARG 0x0
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#define AML_IOTM_JTAG_ENABLE_SMC_ARG 0x1
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#define AML_IOTM_INIT_CLK_SMC_ARG 0x0
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#define AML_IOTM_INIT_HW_SMC_ARG 0x1
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#define CONTINUOUS_PULSE_TIME 10
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#define CONTINUOUS_PULSE 20
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#define REPLICAPTER_LOCKACCESS 0x1fb0
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#define TPIU_ITATBCTR2 0x2ef0
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#define TPIU_ITCTRL 0x2f00
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#define TPIU_LOCKACCESS 0x2fb0
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#define ETB_DEPTH 0x3004
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#define ETB_STATUS 0x300c
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#define ETB_RRD 0x3010
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#define ETB_RRP 0x3014
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#define ETB_RWP 0x3018
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#define ETB_CTL 0x3020
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#define ETB_FFCR 0x3304
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#define ETB_LOCKACCESS 0x3fb0
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#define FUNNEL_CTRL_REG 0x4000
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#define FUNNUL_LOCKACCESS 0x4fb0
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#define ADDR_RANGE0_BEGIN (0x7000 + (0x00 << 2))
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#define ADDR_RANGE0_END (0x7000 + (0x01 << 2))
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#define ADDR_RANGE1_BEGIN (0x7000 + (0x02 << 2))
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#define ADDR_RANGE1_END (0x7000 + (0x03 << 2))
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#define ADDR_RANGE2_BEGIN (0x7000 + (0x04 << 2))
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#define ADDR_RANGE2_END (0x7000 + (0x05 << 2))
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#define ADDR_RANGE3_BEGIN (0x7000 + (0x06 << 2))
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#define ADDR_RANGE3_END (0x7000 + (0x07 << 2))
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#define ADDR_RANGE4_BEGIN (0x7000 + (0x08 << 2))
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#define ADDR_RANGE4_END (0x7000 + (0x09 << 2))
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#define ADDR_RANGE5_BEGIN (0x7000 + (0x0a << 2))
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#define ADDR_RANGE5_END (0x7000 + (0x0b << 2))
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#define ADDR_RANGE6_BEGIN (0x7000 + (0x0c << 2))
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#define ADDR_RANGE6_END (0x7000 + (0x0d << 2))
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#define ADDR_RANGE7_BEGIN (0x7000 + (0x0e << 2))
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#define ADDR_RANGE7_END (0x7000 + (0x0f << 2))
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#define MONITOR_RANGE_INCLUDE (0x7000 + (0x10 << 2))
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#define SW_DATA_STREAM0 (0x7000 + (0x11 << 2))
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#define SW_DATA_STREAM1 (0x7000 + (0x12 << 2))
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#define VAPB4_WAIT_TIME (0x7000 + (0X13 << 2))
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#define MONITOR_CTRL (0x7000 + (0x14 << 2))
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#define MONITOR_BUF_BASEADDR_LOW (0x7000 + (0x15 << 2))
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#define MONITOR_BUF_SIZE_LOW (0x7000 + (0x16 << 2))
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#define MONITOR_STATUS (0x7000 + (0x17 << 2))
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#define IOTM_PACK_FEED_DATA (0x7000 + (0x18 << 2))
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#define IOTM_IRQ_CTRL (0x7000 + (0x19 << 2))
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#define CAPU_WAIT_TIME (0x7000 + (0x1a << 2))
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#define CAPU_MONITOR_ADDR (0x7000 + (0x1b << 2))
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#define CAPU_MONITOR_DATA (0x7000 + (0x1c << 2))
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#define VAPB4_MONITOR_ADDR (0x7000 + (0x1d << 2))
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#define VAPB4_MONITOR_DATA (0x7000 + (0x1e << 2))
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#define IOTM_ARB_QOS_WEIGHT (0x7000 + (0x1f << 2))
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#define IOTM_CTRL_MODE (0x7000 + (0x20 << 2))
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#define IOTM_AXI_ADDR (0x7000 + (0x21 << 2))
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#define IOTM_AXI_SIZE (0x7000 + (0x22 << 2))
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#define IOTM_FAIL_READ_DATA (0x7000 + (0x23 << 2))
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#define IOTM_WTDRST_MAGIC_DATA (0x7000 + (0x24 << 2))
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#define IOTM_SW_DEBUG0 (0x7000 + (0x25 << 2))
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#define IOTM_SW_DEBUG1 (0x7000 + (0x26 << 2))
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#define IOTM_SW_DEBUG2 (0x7000 + (0x27 << 2))
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#define IOTM_SW_DEBUG3 (0x7000 + (0x28 << 2))
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#define NUM_OF_IOTM_REGISTERS (((IOTM_SW_DEBUG3 - ADDR_RANGE0_BEGIN) >> 2) + 1)
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#define IOTM_CTRL_MODE_ACCURATE GENMASK(21, 18)
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#define IOTM_CTRL_MODE_ACCURATE_16 (0x4 << 18)
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#define IOTM_CTRL_MODE_TS GENMASK(17, 13)
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#define IOTM_CTRL_MODE_TS_27 (0x4 << 13)
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#define IOTM_CTRL_MODE_TRACE_ENABLE BIT(2)
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#define IOTM_CTRL_MODE_CAPU_ENABLE BIT(3)
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#define IOTM_CTRL_MODE_VAPB4_ENABLE BIT(4)
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#define IOTM_CTRL_MODE_TRACE_DISABLE BIT(5)
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#define ETB_LOCK_ACCESS_ALL 0xc5acce55
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#define FUNNEL_CTRL_REG_VAL_V1 (BIT(9) | BIT(8) | BIT(4))
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#define FUNNEL_CTRL_REG_VAL_V2 (BIT(9) | BIT(8) | BIT(5))
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#define TPIU_ITCTRL_DISABLE BIT(0)
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#define TPIU_ITATBCTR2_ATREADY BIT(0)
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#define ETB_FFCR_DISABLE_FORMATTING 0U
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#define ETB_CTL_ENABLE_CAPTURE BIT(0)
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#define MONITOR_RANGE_INCLUDE_RST_MASK BIT(15)
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#define MONITOR_STATUS_SEC_WDT_RESET BIT(31)
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#define MONITOR_STATUS_WDT_RESET BIT(30)
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#define IOTM_IRQ_CTRL_WDT_IRQ BIT(20)
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#define IOTM_IRQ_CTRL_SEC_WDT_IRQ BIT(17)
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#define IOTM_IRQ_CTRL_PACK_IRQ BIT(14)
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#define IOTM_IRQ_CTRL_PACK_IRQ_CLEAR BIT(13)
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#define IOTM_IRQ_CTRL_PACK_IRQ_MASK BIT(12)
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#define IOTM_IRQ_CTRL_VAPB4_TIMEOUT BIT(11)
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#define IOTM_IRQ_CTRL_VAPB4_FULL BIT(10)
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#define IOTM_IRQ_CTRL_VAPB4_TIMEOUT_CLEAR BIT(9)
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#define IOTM_IRQ_CTRL_VAPB4_FULL_CLEAR BIT(8)
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#define IOTM_IRQ_CTRL_VAPB4_FULL_MASK BIT(6)
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#define IOTM_IRQ_CTRL_CAPU_TIMEOUT BIT(5)
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#define IOTM_IRQ_CTRL_CAPU_FULL BIT(4)
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#define IOTM_IRQ_CTRL_CAPU_TIMEOUT_CLEAR BIT(3)
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#define IOTM_IRQ_CTRL_CAPU_FULL_CLEAR BIT(2)
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#define IOTM_IRQ_CTRL_CAPU_FULL_MASK BIT(0)
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#define SW_DATA_STREAM1_WRITE BIT(31)
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#define ADDR_OFFSET 0xE0000000
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#define AOCPU_TRACE 1
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#define SW_TRACE 2
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#define MAX_MONITOR_RANGE 8
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#define MAX_TS 0x7ffffff
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//NSEC_PER_IOTM_TS:TS1 * NSEC_PER_IOTM_TS = NS
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#define NSEC_PER_IOTM_TS 666
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#define THOUSAND_NSEC_PER_IOTM_TS 666666
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#define iotm_smccc_smc(cmd, arg0, arg1, arg2, arg3, res) \
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__arm_smccc_smc(cmd, arg0, arg1, arg2, arg3, 0, 0, 0, &(res), NULL)
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/* Combine two words into double_word */
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#define PACK_U32_TO_U64(high, low) \
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((((u64)(high)) << 32) | ((u64)(low)))
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enum iotm_en_mode {
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IOTM_DISABLE,
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IOTM_ENABLE,
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IOTM_ENABLE_NO_TRACE,
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};
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enum iotm_mode {
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AXI_MODE,
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TPIU_MODE,
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ETB_MODE,
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};
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enum iotm_type {
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IOTM_TYPE_T6D,
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IOTM_TYPE_T6W,
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IOTM_TYPE_T6X,
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};
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enum iotm_dump {
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IOTM_DUMP_NONE,
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IOTM_DUMP_WATCHDOG,
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IOTM_DUMP_ALL,
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};
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struct iotm_record_v1 {
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struct {
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u32 rw:1;
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u32 idx:4;
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u32 ts:27;
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} stream0;
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union {
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struct {
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u32 cpu:3;
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u32 sw_type:3;
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u32 reserved:23;
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u32 mid:2;
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u32 fail:1;
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} sw_stream1;
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struct {
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u32 addr:29;
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u32 mid:2;
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u32 fail:1;
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} io_stream1;
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u32 stream1;
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};
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u32 stream2;
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};
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struct iotm_record_v2 {
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u32 stream0;
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struct {
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u32 mid:1;
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u32 idx:4;
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u32 ts:27;
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} stream1;
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union {
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struct {
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u32 cpu:3;
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u32 sw_type:3;
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u32 reserved:25;
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u32 mid:1;
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} sw_stream2;
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struct {
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u32 addr:29;
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u32 fail:1;
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u32 rw:1;
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u32 mid:1;
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} io_stream2;
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u32 stream2;
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};
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u32 stream3;
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};
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extern const char *sw_record_name[];
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struct monitor_range {
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phys_addr_t start;
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phys_addr_t end;
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};
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struct reg_entry {
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phys_addr_t reg_start;
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phys_addr_t reg_end;
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const char *reg_name;
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};
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struct iotm {
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int cpu_type;
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int supported;
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int en_saved;
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int dump_cnt;
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int bytes_per_trace;
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unsigned int dump_mode;
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void __iomem *cssys_base;
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unsigned int monitor_mode;
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unsigned int version;
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struct monitor_range range[MAX_MONITOR_RANGE];
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unsigned int buf_start;
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unsigned int buf_end;
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void *saved_trace;
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u32 *etb_buf;
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int etb_buf_words_cnt;
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/* Protects access to the IOTM trace records */
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spinlock_t record_lock;
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struct timer_list ts_to_kernel_timer;
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int timeout_irq_handled;
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struct iotm_ops *ops;
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struct reg_entry *reg_table;
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int reg_table_size;
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int saved_trace_show;
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};
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struct iotm_ops {
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void (*ddr_range_set)(u32 trace_buf_start);
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void (*ddr_range_get)(u32 *reg_base, void *buf, int *offset);
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void (*etb_coresight_clk)(void);
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void (*coresight_clk_enable)(void);
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void (*boot_time_record)(u64 pct, u64 ns_time);
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void (*boot_timer_setup)(void);
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bool (*is_watchdog)(void);
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bool (*is_trace_loop)(void);
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void (*print_single_trace)(void *ptr, char *buf);
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void (*sw_record_write)(u32 sw_type, u32 val1, u32 val2);
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void (*trace_time_loop_check)(void *trace_start, void *trace_end, u64 *prev_time);
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void (*clean_buf)(void);
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int (*axi_mode_enable)(struct iotm *iotm, int iotm_en);
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void (*update_monitor_mode)(struct iotm *iotm);
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};
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extern struct iotm iotm;
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extern struct iotm_ops iotm_v1_ops;
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extern struct iotm_ops iotm_v2_ops;
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const char *find_register_node(phys_addr_t addr);
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void get_boot_time(struct timer_list *t);
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#endif /* __DEBUG_IOTM_HW_H_ */
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