259 lines
6.8 KiB
C
259 lines
6.8 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include <linux/delay.h>
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#include <linux/highmem.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/scatterlist.h>
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#include <linux/platform_device.h>
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#include <linux/ktime.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/card.h>
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#include <linux/amlogic/aml_sd.h>
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#include "meson-cqhci.h"
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bool aml_cqe_irq(struct meson_host *host, u32 intmask, int *cmd_error,
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int *data_error)
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{
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if (!host->mmc->cqe_on)
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return false;
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if (intmask & (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR))
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*data_error = -EILSEQ;
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else if (intmask & IRQ_DESC_TIMEOUT)
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*data_error = -ETIMEDOUT;
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else if (intmask & IRQ_DESC_ERR)
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*data_error = -EIO; /* indicate all ddr issue */
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else
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*data_error = 0;
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if (intmask & (IRQ_RESP_ERR))
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*cmd_error = -EILSEQ;
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else if (intmask & IRQ_RESP_TIMEOUT)
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*cmd_error = -ETIMEDOUT;
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else
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*cmd_error = 0;
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writel(0x7fff, host->regs + SD_EMMC_STATUS);
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if (*data_error || *cmd_error) {
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dev_err(host->dev, "cmd_err[0x%x], data_err[0x%x],status[0x%x]\n",
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*cmd_error, *data_error, intmask);
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if (host->debug_flag) {
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dev_notice(host->dev, "clktree : 0x%x,host_clock: 0x%x\n",
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readl(host->clk_tree_base),
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readl(host->regs));
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dev_notice(host->dev, "adjust: 0x%x,cfg: 0x%x,intf3: 0x%x\n",
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readl(host->regs + SD_EMMC_V3_ADJUST),
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readl(host->regs + SD_EMMC_CFG),
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readl(host->regs + SD_EMMC_INTF3));
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dev_notice(host->dev, "irq_en: 0x%x\n",
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readl(host->regs + 0x4c));
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dev_notice(host->dev, "delay1: 0x%x,delay2: 0x%x\n",
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readl(host->regs + SD_EMMC_DELAY1),
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readl(host->regs + SD_EMMC_DELAY2));
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dev_notice(host->dev, "pinmux: 0x%x\n",
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readl(host->pin_mux_base));
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}
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}
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return true;
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}
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u32 aml_cqhci_irq(struct meson_host *host)
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{
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int cmd_error = 0;
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int data_error = 0;
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u32 irq_en, raw_status, intmask;
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irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
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raw_status = readl(host->regs + SD_EMMC_STATUS);
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intmask = raw_status & irq_en;
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if (!aml_cqe_irq(host, intmask, &cmd_error, &data_error))
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return intmask;
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cqhci_irq(host->mmc, intmask, cmd_error, data_error);
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return 0;
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}
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void aml_cqhci_writel(struct cqhci_host *host, u32 val, int reg)
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{
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writel(val, host->mmio + reg);
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}
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u32 aml_cqhci_readl(struct cqhci_host *host, int reg)
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{
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return readl(host->mmio + reg);
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}
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void aml_cqe_enable(struct mmc_host *mmc)
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{
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struct cqhci_host *cq_host = mmc->cqe_private;
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u32 val;
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/*
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* CQHCI/SDMMC design prevents write access to sdhci block size
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* register when CQE is enabled and unhalted.
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* CQHCI driver enables CQE prior to activation, so disable CQE before
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* programming block size in sdhci controller and enable it back.
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*/
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if (!cq_host->activated) {
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val = cqhci_readl(cq_host, CQHCI_CFG);
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if (val & CQHCI_ENABLE)
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cqhci_writel(cq_host, (val & ~CQHCI_ENABLE), CQHCI_CFG);
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//aml_set_max_blocks(mmc);
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if (val & CQHCI_ENABLE)
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cqhci_writel(cq_host, val, CQHCI_CFG);
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}
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/*
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* CMD CRC errors are seen sometimes with some eMMC devices when status
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* command is sent during transfer of last data block which is the
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* default case as send status command block counter (CBC) is 1.
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* Recommended fix to set CBC to 0 allowing send status command only
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* when data lines are idle.
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* amlogic cheng recommend 1 & 1;
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*/
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//val = cqhci_readl(cq_host, CQHCI_SSC1);
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val = CQHCI_SSC1_CBC(1) | CQHCI_SSC1_CIT(0x7D);
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cqhci_writel(cq_host, val, CQHCI_SSC1);
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mmc->cqe_on = true;
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}
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void aml_cqe_disable(struct mmc_host *mmc, bool recovery)
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{
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//struct cqhci_host *cq_host = mmc->cqe_private;
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struct meson_host *host = mmc_priv(mmc);
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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mmc->cqe_on = false;
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pr_debug("%s: CQE off, IRQ mask %#x, IRQ status %#x\n",
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mmc_hostname(mmc), readl(host->regs + SD_EMMC_IRQ_EN),
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readl(host->regs + SD_EMMC_STATUS));
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spin_unlock_irqrestore(&host->lock, flags);
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}
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struct cqhci_host_ops amlogic_cqhci_ops = {
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// .write_l = aml_cqhci_writel,
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// .read_l = aml_cqhci_readl,
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.enable = aml_cqe_enable,
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.disable = aml_cqe_disable,
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// .dumpregs = aml_dumpregs,
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// .update_dcmd_desc = aml_update_dcmd_desc,
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};
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void meson_crypto_init(struct cqhci_host *cq_host)
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{
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/* set 256Byte key in cap0 */
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cqhci_writel(cq_host, CRYPTO_KS(CFG_256_BIT), CQHCI_CRCAP0);
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/* set 256Byte key in cap1 */
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cqhci_writel(cq_host, CRYPTO_KS(CFG_256_BIT), CQHCI_CRCAP1);
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}
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int meson_crypto_prepare_req(struct mmc_host *mmc, struct mmc_request *mrq)
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{
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struct cqhci_host *cq_host = NULL;
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unsigned int slot = 0;
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if (!mrq->data || !mrq->crypto_ctx)
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return 1;
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cq_host = mmc->cqe_private;
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slot = mrq->crypto_key_slot;
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/* enable Crypt Engine */
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cqhci_writel(cq_host, CRYPTO_ENGINE, CQHCI_CFG);
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/* enable Crypt Engine for Non-Qeueu */
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cqhci_writel(cq_host, CRYPTO_NON_QUEUE | slot, CQHCI_CRNQP);
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/* We set max_dun_bytes_supported=4, so all DUNs should be 32-bit. */
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WARN_ON_ONCE(mrq->crypto_ctx->bc_dun[0] > U32_MAX);
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//cqhci_readl(cq_host, CQHCI_CRCFG(slot) + 17 * sizeof(__le32)));
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/* Write dword 16, which includes the new value of CFGE */
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//cqhci_readl(cq_host, CQHCI_CRCFG(slot) + 16 * sizeof(__le32)));
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cqhci_writel(cq_host, mrq->crypto_ctx->bc_dun[0], CQHCI_CRNQDUN);
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return 0;
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}
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int meson_crypto_post_req(struct mmc_host *mmc, struct mmc_request *mrq)
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{
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struct cqhci_host *cq_host = NULL;
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unsigned int slot = 0, val = 0;
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if (!mrq->data || !mrq->crypto_ctx)
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return 1;
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cq_host = mmc->cqe_private;
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slot = mrq->crypto_key_slot;
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/* disable Crypt Engine */
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val = cqhci_readl(cq_host, CQHCI_CFG);
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cqhci_writel(cq_host, val & ~CRYPTO_ENGINE, CQHCI_CFG);
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/* disable Crypt Engine for Non-Qeueu */
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val = cqhci_readl(cq_host, CQHCI_CRNQP);
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cqhci_writel(cq_host, val & ~CRYPTO_NON_QUEUE, CQHCI_CRNQP);
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cqhci_writel(cq_host, 0, CQHCI_CRNQDUN);
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return 0;
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}
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int amlogic_add_host(struct meson_host *host)
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{
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struct mmc_host *mmc = host->mmc;
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struct cqhci_host *cq_host;
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bool dma64 = false;
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int ret;
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if (!aml_card_type_mmc(host) ||
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(!host->enable_hwcq && !host->enable_inline_crypto))
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return mmc_add_host(mmc);
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if (host->enable_hwcq) {
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mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
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mmc->max_seg_size = SD_EMMC_MAX_SEG_SIZE;
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}
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cq_host = devm_kzalloc(host->dev,
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sizeof(*cq_host), GFP_KERNEL);
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if (!cq_host) {
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ret = -ENOMEM;
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return ret;
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}
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cq_host->mmio = host->regs + SD_EMMC_CQE_REG;
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cq_host->ops = &amlogic_cqhci_ops;
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if (host->enable_inline_crypto) {
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mmc->caps2 |= MMC_CAP2_CRYPTO;
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meson_crypto_init(cq_host);
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}
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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dma64 = host->flags & AML_MMC_64BIT_DMA;
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if (dma64)
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cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
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#endif
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ret = cqhci_init(cq_host, host->mmc, dma64);
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if (ret)
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return ret;
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ret = mmc_add_host(mmc);
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if (ret)
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goto cleanup;
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return 0;
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cleanup:
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devm_kfree(host->dev, cq_host);
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return ret;
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}
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