200 lines
7.7 KiB
C
200 lines
7.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __A1_CLKC_H
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#define __A1_CLKC_H
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#define CLKID_EE_CORE 0
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#define CLKID_FIXED_PLL_DCO 1
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#define CLKID_FIXED_PLL 2
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#define CLKID_FCLK_DIV2 3
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#define CLKID_FCLK_DIV3 4
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#define CLKID_FCLK_DIV5 5
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#define CLKID_FCLK_DIV7 6
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#define CLKID_FCLK_DIV2_DIV 7
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#define CLKID_FCLK_DIV3_DIV 8
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#define CLKID_FCLK_DIV5_DIV 9
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#define CLKID_FCLK_DIV7_DIV 10
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#define CLKID_SYS_A_SEL 11
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#define CLKID_SYS_A_DIV 12
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#define CLKID_SYS_A 13
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#define CLKID_SYS_B_SEL 14
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#define CLKID_SYS_B_DIV 15
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#define CLKID_SYS_B 16
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#define CLKID_SYS_CLK 17
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#define CLKID_HIFI_PLL 18
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#define CLKID_SYS_PLL 19
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#define CLKID_AUD_DDS 20
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#define CLKID_CPU_BASE 21
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#define CLKID_CPU_DYN_CLK (CLKID_CPU_BASE + 0)
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#define CLKID_CPU_CLK (CLKID_CPU_BASE + 1)
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/* CLKTREE_SYS_OSCIN_CTRL gates*/
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#define XTAL_BASE (CLKID_CPU_BASE + 2)
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#define CLKID_XTAL_CLKTREE (XTAL_BASE + 0)
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#define CLKID_XTAL_FIXPLL (XTAL_BASE + 1)
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#define CLKID_XTAL_USB_PHY (XTAL_BASE + 2)
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#define CLKID_XTAL_USB_CTRL (XTAL_BASE + 3)
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#define CLKID_XTAL_HIFIPLL (XTAL_BASE + 4)
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#define CLKID_XTAL_SYSPLL (XTAL_BASE + 5)
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#define CLKID_XTAL_DDS (XTAL_BASE + 6)
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/* CLKTREE_SYS_CLK_EN0 gates*/
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#define GATE_BASE0 (XTAL_BASE + 7)
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#define CLKID_CLKTREE (GATE_BASE0 + 0)
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#define CLKID_RESET_CTRL (GATE_BASE0 + 1)
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#define CLKID_ANALOG_CTRL (GATE_BASE0 + 2)
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#define CLKID_PWR_CTRL (GATE_BASE0 + 3)
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#define CLKID_PAD_CTRL (GATE_BASE0 + 4)
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#define CLKID_SYS_CTRL (GATE_BASE0 + 5)
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#define CLKID_TEMP_SENSOR (GATE_BASE0 + 6)
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#define CLKID_AM2AXI_DIV (GATE_BASE0 + 7)
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#define CLKID_SPICC_B (GATE_BASE0 + 8)
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#define CLKID_SPICC_A (GATE_BASE0 + 9)
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#define CLKID_CLK_MSR (GATE_BASE0 + 10)
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#define CLKID_AUDIO (GATE_BASE0 + 11)
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#define CLKID_JTAG_CTRL (GATE_BASE0 + 12)
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#define CLKID_SARADC (GATE_BASE0 + 13)
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#define CLKID_PWM_EF (GATE_BASE0 + 14)
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#define CLKID_PWM_CD (GATE_BASE0 + 15)
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#define CLKID_PWM_AB (GATE_BASE0 + 16)
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#define CLKID_CEC (GATE_BASE0 + 17)
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#define CLKID_I2C_S (GATE_BASE0 + 18)
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#define CLKID_IR_CTRL (GATE_BASE0 + 19)
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#define CLKID_I2C_M_D (GATE_BASE0 + 20)
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#define CLKID_I2C_M_C (GATE_BASE0 + 21)
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#define CLKID_I2C_M_B (GATE_BASE0 + 22)
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#define CLKID_I2C_M_A (GATE_BASE0 + 23)
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#define CLKID_ACODEC (GATE_BASE0 + 24)
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#define CLKID_OTP (GATE_BASE0 + 25)
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#define CLKID_SD_EMMC_A (GATE_BASE0 + 26)
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#define CLKID_USB_PHY (GATE_BASE0 + 27)
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#define CLKID_USB_CTRL (GATE_BASE0 + 28)
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#define CLKID_SYS_DSPB (GATE_BASE0 + 29)
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#define CLKID_SYS_DSPA (GATE_BASE0 + 30)
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#define CLKID_DMA (GATE_BASE0 + 31)
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/* CLKTREE_SYS_CLK_EN1 gates*/
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#define GATE_BASE1 (GATE_BASE0 + 32)
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#define CLKID_IRQ_CTRL (GATE_BASE1 + 0)
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#define CLKID_NIC (GATE_BASE1 + 1)
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#define CLKID_GIC (GATE_BASE1 + 2)
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#define CLKID_UART_C (GATE_BASE1 + 3)
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#define CLKID_UART_B (GATE_BASE1 + 4)
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#define CLKID_UART_A (GATE_BASE1 + 5)
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#define CLKID_SYS_PSRAM (GATE_BASE1 + 6)
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#define CLKID_RSA (GATE_BASE1 + 7)
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#define CLKID_CORESIGHT (GATE_BASE1 + 8)
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/* CLKTREE_AXI_CLK_EN gates */
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#define GATE_BASE2 (GATE_BASE1 + 9)
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#define CLKID_AM2AXI_VAD (GATE_BASE2 + 0)
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#define CLKID_AUDIO_VAD (GATE_BASE2 + 1)
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#define CLKID_AXI_DMC (GATE_BASE2 + 2)
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#define CLKID_AXI_PSRAM (GATE_BASE2 + 3)
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#define CLKID_RAMB (GATE_BASE2 + 4)
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#define CLKID_RAMA (GATE_BASE2 + 5)
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#define CLKID_AXI_SPIFC (GATE_BASE2 + 6)
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#define CLKID_AXI_NIC (GATE_BASE2 + 7)
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#define CLKID_AXI_DMA (GATE_BASE2 + 8)
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#define CLKID_CPU_CTRL (GATE_BASE2 + 9)
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#define CLKID_ROM (GATE_BASE2 + 10)
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#define CLKID_PROC_I2C (GATE_BASE2 + 11)
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/* dsp clks */
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#define DSP_BASE (GATE_BASE2 + 12)
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#define CLKID_DSPA_A_SEL (DSP_BASE + 0)
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#define CLKID_DSPA_A_DIV (DSP_BASE + 1)
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#define CLKID_DSPA_A (DSP_BASE + 2)
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#define CLKID_DSPA_B_SEL (DSP_BASE + 3)
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#define CLKID_DSPA_B_DIV (DSP_BASE + 4)
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#define CLKID_DSPA_B (DSP_BASE + 5)
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#define CLKID_DSPA_SEL (DSP_BASE + 6)
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#define CLKID_DSPB_A_SEL (DSP_BASE + 7)
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#define CLKID_DSPB_A_DIV (DSP_BASE + 8)
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#define CLKID_DSPB_A (DSP_BASE + 9)
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#define CLKID_DSPB_B_SEL (DSP_BASE + 10)
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#define CLKID_DSPB_B_DIV (DSP_BASE + 11)
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#define CLKID_DSPB_B (DSP_BASE + 12)
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#define CLKID_DSPB_SEL (DSP_BASE + 13)
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#define CLKID_DSPA_EN_DSPA (DSP_BASE + 14)
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#define CLKID_DSPA_EN_NIC (DSP_BASE + 15)
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#define CLKID_DSPB_EN_DSPB (DSP_BASE + 16)
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#define CLKID_DSPB_EN_NIC (DSP_BASE + 17)
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/* 32k: rtc and ceca clock */
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#define RTC_32K_BASE (DSP_BASE + 18)
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#define CLKID_RTC_32K_CLKIN (RTC_32K_BASE + 0)
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#define CLKID_RTC_32K_DIV (RTC_32K_BASE + 1)
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#define CLKID_RTC_32K_XTAL (RTC_32K_BASE + 2)
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#define CLKID_RTC_32K_SEL (RTC_32K_BASE + 3)
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#define CLKID_RTC_CLK (RTC_32K_BASE + 4)
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#define CLKID_CECA_32K_CLKIN (RTC_32K_BASE + 5)
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#define CLKID_CECA_32K_DIV (RTC_32K_BASE + 6)
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#define CLKID_CECA_32K_SEL_PRE (RTC_32K_BASE + 7)
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#define CLKID_CECA_32K_SEL (RTC_32K_BASE + 8)
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#define CLKID_CECA_32K (RTC_32K_BASE + 9)
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#define CLKID_CECB_32K_CLKIN (RTC_32K_BASE + 10)
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#define CLKID_CECB_32K_DIV (RTC_32K_BASE + 11)
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#define CLKID_CECB_32K_SEL_PRE (RTC_32K_BASE + 12)
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#define CLKID_CECB_32K_SEL (RTC_32K_BASE + 13)
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#define CLKID_CECB_32K (RTC_32K_BASE + 14)
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/* 12m/24m/gen clks */
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#define BASIC_BASE (RTC_32K_BASE + 15)
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#define CLKID_24M (BASIC_BASE + 0)
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#define CLKID_12M (BASIC_BASE + 1)
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#define CLKID_DIV2_PRE (BASIC_BASE + 2)
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#define CLKID_FCLK_DIV2_DIVN (BASIC_BASE + 3)
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#define CLKID_24M_DIV2 (BASIC_BASE + 4)
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#define CLKID_GEN_SEL (BASIC_BASE + 5)
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#define CLKID_GEN_DIV (BASIC_BASE + 6)
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#define CLKID_GEN (BASIC_BASE + 7)
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#define CLKID_SARADC_SEL (BASIC_BASE + 8)
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#define CLKID_SARADC_DIV (BASIC_BASE + 9)
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#define CLKID_SARADC_GATE (BASIC_BASE + 10)
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#define CLKID_PWM_A_SEL (BASIC_BASE + 11)
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#define CLKID_PWM_A_DIV (BASIC_BASE + 12)
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#define CLKID_PWM_A (BASIC_BASE + 13)
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#define CLKID_PWM_B_SEL (BASIC_BASE + 14)
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#define CLKID_PWM_B_DIV (BASIC_BASE + 15)
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#define CLKID_PWM_B (BASIC_BASE + 16)
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#define CLKID_PWM_C_SEL (BASIC_BASE + 17)
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#define CLKID_PWM_C_DIV (BASIC_BASE + 18)
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#define CLKID_PWM_C (BASIC_BASE + 19)
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#define CLKID_PWM_D_SEL (BASIC_BASE + 20)
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#define CLKID_PWM_D_DIV (BASIC_BASE + 21)
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#define CLKID_PWM_D (BASIC_BASE + 22)
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#define CLKID_PWM_E_SEL (BASIC_BASE + 23)
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#define CLKID_PWM_E_DIV (BASIC_BASE + 24)
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#define CLKID_PWM_E (BASIC_BASE + 25)
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#define CLKID_PWM_F_SEL (BASIC_BASE + 26)
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#define CLKID_PWM_F_DIV (BASIC_BASE + 27)
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#define CLKID_PWM_F (BASIC_BASE + 28)
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#define CLKID_SPICC_SEL (BASIC_BASE + 29)
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#define CLKID_SPICC_DIV (BASIC_BASE + 30)
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#define CLKID_SPICC_GATE (BASIC_BASE + 31)
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#define CLKID_SPICC (BASIC_BASE + 32)
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#define CLKID_TS_DIV (BASIC_BASE + 33)
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#define CLKID_TS (BASIC_BASE + 34)
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#define BASIC_BASE2 (BASIC_BASE + 35)
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#define CLKID_SPIFC_SEL (BASIC_BASE2 + 0)
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#define CLKID_SPIFC_DIV (BASIC_BASE2 + 1)
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#define CLKID_SPIFC_GATE (BASIC_BASE2 + 2)
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#define CLKID_SPIFC (BASIC_BASE2 + 3)
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#define CLKID_USB_BUS_SEL (BASIC_BASE2 + 4)
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#define CLKID_USB_BUS_DIV (BASIC_BASE2 + 5)
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#define CLKID_USB_BUS (BASIC_BASE2 + 6)
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#define CLKID_SD_EMMC_SEL (BASIC_BASE2 + 7)
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#define CLKID_SD_EMMC_DIV (BASIC_BASE2 + 8)
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#define CLKID_SD_EMMC_GATE (BASIC_BASE2 + 9)
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#define CLKID_SD_EMMC (BASIC_BASE2 + 10)
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#define CLKID_PSRAM_SEL (BASIC_BASE2 + 11)
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#define CLKID_PSRAM_DIV (BASIC_BASE2 + 12)
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#define CLKID_PSRAM_GATE (BASIC_BASE2 + 13)
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#define CLKID_PSRAM (BASIC_BASE2 + 14)
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#define CLKID_DMC_SEL (BASIC_BASE2 + 15)
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#define CLKID_DMC_DIV (BASIC_BASE2 + 16)
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#define CLKID_DMC_GATE (BASIC_BASE2 + 17)
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#define CLKID_DMC (BASIC_BASE2 + 18)
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#define CLKID_FIXED_PLL_DIV2 (BASIC_BASE2 + 19)
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#endif /* __A1_CLKC_H */
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