169 lines
8.5 KiB
C
169 lines
8.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
|
/*
|
|
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_CLKC_H
|
|
#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_CLKC_H
|
|
|
|
#define CLKID_GP0_PLL 0
|
|
#define CLKID_HIFI_PLL 1
|
|
#define CLKID_MPLL_PREDIV 2
|
|
#define CLKID_MPLL0 3
|
|
#define CLKID_MPLL0_DIV 4
|
|
#define CLKID_MPLL1 5
|
|
#define CLKID_MPLL1_DIV 6
|
|
#define CLKID_MPLL2 7
|
|
#define CLKID_MPLL2_DIV 8
|
|
#define CLKID_MPLL3 9
|
|
#define CLKID_MPLL3_DIV 10
|
|
#define CLKID_FCLK_DIV2_DIV 11
|
|
#define CLKID_FCLK_DIV2 12
|
|
#define CLKID_FCLK_DIV2P5_DIV 13
|
|
#define CLKID_FCLK_DIV2P5 14
|
|
#define CLKID_FCLK_DIV3_DIV 15
|
|
#define CLKID_FCLK_DIV3 16
|
|
#define CLKID_FCLK_DIV4_DIV 17
|
|
#define CLKID_FCLK_DIV4 18
|
|
#define CLKID_FCLK_DIV5_DIV 19
|
|
#define CLKID_FCLK_DIV5 20
|
|
#define CLKID_FCLK_DIV7_DIV 21
|
|
#define CLKID_FCLK_DIV7 22
|
|
#define CLKID_CLK_24M_IN 23
|
|
#define CLKID_CLK_12M_DIV 24
|
|
#define CLKID_CLK_12M 25
|
|
#define CLKID_CLK_25M_DIV 26
|
|
#define CLKID_CLK_25M 27
|
|
#define CLKID_RTC_DUAL_CLKIN 28
|
|
#define CLKID_RTC_DUAL_DIV 29
|
|
#define CLKID_RTC_DUAL_MUX 30
|
|
#define CLKID_RTC_DUAL 31
|
|
#define CLKID_RTC_CLK 32
|
|
#define CLKID_SAR_ADC_MUX 33
|
|
#define CLKID_SAR_ADC_DIV 34
|
|
#define CLKID_SAR_ADC 35
|
|
#define CLKID_DSPA_0_MUX 36
|
|
#define CLKID_DSPA_0_DIV 37
|
|
#define CLKID_DSPA_0 38
|
|
#define CLKID_DSPA_1_MUX 39
|
|
#define CLKID_DSPA_1_DIV 40
|
|
#define CLKID_DSPA_1 41
|
|
#define CLKID_DSPA 42
|
|
#define CLKID_NNA_CORE_MUX 43
|
|
#define CLKID_NNA_CORE_DIV 44
|
|
#define CLKID_NNA_CORE 45
|
|
#define CLKID_NNA_AXI_MUX 46
|
|
#define CLKID_NNA_AXI_DIV 47
|
|
#define CLKID_NNA_AXI 48
|
|
#define CLKID_PWM_A_MUX 49
|
|
#define CLKID_PWM_A_DIV 50
|
|
#define CLKID_PWM_A 51
|
|
#define CLKID_PWM_B_MUX 52
|
|
#define CLKID_PWM_B_DIV 53
|
|
#define CLKID_PWM_B 54
|
|
#define CLKID_PWM_C_MUX 55
|
|
#define CLKID_PWM_C_DIV 56
|
|
#define CLKID_PWM_C 57
|
|
#define CLKID_PWM_D_MUX 58
|
|
#define CLKID_PWM_D_DIV 59
|
|
#define CLKID_PWM_D 60
|
|
#define CLKID_PWM_E_MUX 61
|
|
#define CLKID_PWM_E_DIV 62
|
|
#define CLKID_PWM_E 63
|
|
#define CLKID_PWM_F_MUX 64
|
|
#define CLKID_PWM_F_DIV 65
|
|
#define CLKID_PWM_F 66
|
|
#define CLKID_PWM_G_MUX 67
|
|
#define CLKID_PWM_G_DIV 68
|
|
#define CLKID_PWM_G 69
|
|
#define CLKID_PWM_H_MUX 70
|
|
#define CLKID_PWM_H_DIV 71
|
|
#define CLKID_PWM_H 72
|
|
#define CLKID_SPICC0_MUX 73
|
|
#define CLKID_SPICC0_DIV 74
|
|
#define CLKID_SPICC0 75
|
|
#define CLKID_SPICC1_MUX 76
|
|
#define CLKID_SPICC1_DIV 77
|
|
#define CLKID_SPICC1 78
|
|
#define CLKID_SD_EMMC_A_MUX 79
|
|
#define CLKID_SD_EMMC_A_DIV 80
|
|
#define CLKID_SD_EMMC_A 81
|
|
#define CLKID_SD_EMMC_C_MUX 82
|
|
#define CLKID_SD_EMMC_C_DIV 83
|
|
#define CLKID_SD_EMMC_C 84
|
|
#define CLKID_ETH_CLK_RMII_MUX 85
|
|
#define CLKID_ETH_CLK_RMII_DIV 86
|
|
#define CLKID_ETH_CLK_RMII 87
|
|
#define CLKID_ETH_CLK125M_DIV 88
|
|
#define CLKID_ETH_CLK125M 89
|
|
#define CLKID_TS_DIV 90
|
|
#define CLKID_TS 91
|
|
#define CLKID_GEN_MUX 92
|
|
#define CLKID_GEN_DIV 93
|
|
#define CLKID_GEN 94
|
|
#define CLKID_SYS_CLK_CTRL 95
|
|
#define CLKID_SYS_RESET_CTRL 96
|
|
#define CLKID_SYS_ANALOG_CTRL 97
|
|
#define CLKID_SYS_PWR_CTRL 98
|
|
#define CLKID_SYS_PAD_CTRL 99
|
|
#define CLKID_SYS_SYS_CTRL 100
|
|
#define CLKID_SYS_TS_PLL 101
|
|
#define CLKID_SYS_DEV_ARB 102
|
|
#define CLKID_SYS_MMC_PCLK 103
|
|
#define CLKID_SYS_CAPU 104
|
|
#define CLKID_SYS_MAILBOX 105
|
|
#define CLKID_SYS_CPU_CTRL 106
|
|
#define CLKID_SYS_JTAG_CTRL 107
|
|
#define CLKID_SYS_IR_CTRL 108
|
|
#define CLKID_SYS_IRQ_CTRL 109
|
|
#define CLKID_SYS_MSR_CLK 110
|
|
#define CLKID_SYS_ROM 111
|
|
#define CLKID_SYS_AOCPU 112
|
|
#define CLKID_SYS_CPU_APB 113
|
|
#define CLKID_SYS_RSA 114
|
|
#define CLKID_SYS_SAR_ADC 115
|
|
#define CLKID_SYS_STARTUP 116
|
|
#define CLKID_SYS_SECURE 117
|
|
#define CLKID_SYS_SPIFC 118
|
|
#define CLKID_SYS_LED_CTRL 119
|
|
#define CLKID_SYS_ETH_PHY 120
|
|
#define CLKID_SYS_ETH_MAC 121
|
|
#define CLKID_SYS_GIC 122
|
|
#define CLKID_SYS_RAMA 123
|
|
#define CLKID_SYS_BIG_NIC 124
|
|
#define CLKID_SYS_RAMB 125
|
|
#define CLKID_SYS_AUDIO_TOP 126
|
|
#define CLKID_SYS_AUDIO_VAD 127
|
|
#define CLKID_SYS_USB 128
|
|
#define CLKID_SYS_SD_EMMC_A 129
|
|
#define CLKID_SYS_SD_EMMC_C 130
|
|
#define CLKID_SYS_PWM_AB 131
|
|
#define CLKID_SYS_PWM_CD 132
|
|
#define CLKID_SYS_PWM_EF 133
|
|
#define CLKID_SYS_PWM_GH 134
|
|
#define CLKID_SYS_SPICC_1 135
|
|
#define CLKID_SYS_SPICC_0 136
|
|
#define CLKID_SYS_UART_A 137
|
|
#define CLKID_SYS_UART_B 138
|
|
#define CLKID_SYS_UART_C 139
|
|
#define CLKID_SYS_UART_D 140
|
|
#define CLKID_SYS_UART_E 141
|
|
#define CLKID_SYS_I2C_M_A 142
|
|
#define CLKID_SYS_I2C_M_B 143
|
|
#define CLKID_SYS_I2C_M_C 144
|
|
#define CLKID_SYS_I2C_M_D 145
|
|
#define CLKID_SYS_RTC 146
|
|
#define CLKID_SYS_VOUT 147
|
|
#define CLKID_SYS_USB_CTRL 148
|
|
#define CLKID_SYS_ACODEC 149
|
|
#define CLKID_AXI_AUDIO_VAD 150
|
|
#define CLKID_AXI_AUDIO_TOP 151
|
|
#define CLKID_AXI_SYS_NIC 152
|
|
#define CLKID_AXI_RAMA 153
|
|
#define CLKID_AXI_CPU_DMC 154
|
|
#define CLKID_AXI_DEV1_DMC 155
|
|
#define CLKID_AXI_DEV0_DMC 156
|
|
#define CLKID_AXI_DSP_DMC 157
|
|
|
|
#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_CLKC_H */
|