445 lines
23 KiB
C
445 lines
23 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A9_CLKC_H
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#define _DT_BINDINGS_CLOCK_AMLOGIC_A9_CLKC_H
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#define CLKID_GP0_PLL 0
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#define CLKID_HIFI_PLL 1
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#define CLKID_HIFI1_PLL 2
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#define CLKID_MCLK_PLL 3
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#define CLKID_MCLK1_PLL 4
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#define CLKID_MCLK_0_PRE_DIV 5
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#define CLKID_MCLK_0_PRE 6
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#define CLKID_MCLK_0_MUX 7
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#define CLKID_MCLK_0_DIV 8
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#define CLKID_MCLK_0 9
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#define CLKID_MCLK_1_PRE_DIV 10
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#define CLKID_MCLK_1_PRE 11
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#define CLKID_MCLK_1_MUX 12
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#define CLKID_MCLK_1_DIV 13
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#define CLKID_MCLK_1 14
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#define CLKID_MCLK1_0_PRE_DIV 15
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#define CLKID_MCLK1_0_PRE 16
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#define CLKID_MCLK1_0_MUX 17
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#define CLKID_MCLK1_0_DIV 18
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#define CLKID_MCLK1_0 19
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#define CLKID_MCLK1_1_PRE_DIV 20
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#define CLKID_MCLK1_1_PRE 21
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#define CLKID_MCLK1_1_MUX 22
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#define CLKID_MCLK1_1_DIV 23
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#define CLKID_MCLK1_1 24
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#define CLKID_SAR_ADC_MUX 25
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#define CLKID_SAR_ADC_DIV 26
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#define CLKID_SAR_ADC 27
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#define CLKID_SC_PRE_MUX 28
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#define CLKID_SC_PRE_DIV 29
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#define CLKID_SC_PRE 30
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#define CLKID_SC 31
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#define CLKID_VIDEO_SRC0_IN_MUX 32
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#define CLKID_VIDEO_SRC0_IN 33
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#define CLKID_VIDEO_SRC0_DIV 34
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#define CLKID_VIDEO_SRC0 35
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#define CLKID_VIDEO_SRC1_IN_MUX 36
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#define CLKID_VIDEO_SRC1_IN 37
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#define CLKID_VIDEO_SRC1_DIV 38
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#define CLKID_VIDEO_SRC1 39
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#define CLKID_VIDEO0_DIV1 40
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#define CLKID_VIDEO0_DIV2_EN 41
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#define CLKID_VIDEO0_DIV2 42
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#define CLKID_VIDEO0_DIV4_EN 43
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#define CLKID_VIDEO0_DIV4 44
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#define CLKID_VIDEO0_DIV6_EN 45
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#define CLKID_VIDEO0_DIV6 46
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#define CLKID_VIDEO0_DIV12_EN 47
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#define CLKID_VIDEO0_DIV12 48
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#define CLKID_VIDEO1_DIV1 49
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#define CLKID_VIDEO1_DIV2_EN 50
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#define CLKID_VIDEO1_DIV2 51
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#define CLKID_VIDEO1_DIV4_EN 52
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#define CLKID_VIDEO1_DIV4 53
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#define CLKID_VIDEO1_DIV6_EN 54
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#define CLKID_VIDEO1_DIV6 55
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#define CLKID_VIDEO1_DIV12_EN 56
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#define CLKID_VIDEO1_DIV12 57
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#define CLKID_LCD_AN_MUX 58
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#define CLKID_LCD_AN 59
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#define CLKID_LCD_AN_PH2 60
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#define CLKID_LCD_AN_PH3 61
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#define CLKID_ENC0_MUX 62
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#define CLKID_ENC0 63
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#define CLKID_ENC1_MUX 64
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#define CLKID_ENC1 65
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#define CLKID_VDAC_MUX 66
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#define CLKID_VDAC 67
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#define CLKID_HDMITX_PIXEL_MUX 68
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#define CLKID_HDMITX_PIXEL 69
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#define CLKID_HDMITX_FE_MUX 70
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#define CLKID_HDMITX_FE 71
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#define CLKID_HDMITX1_PIXEL_MUX 72
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#define CLKID_HDMITX1_PIXEL 73
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#define CLKID_HDMITX1_FE_MUX 74
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#define CLKID_HDMITX1_FE 75
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#define CLKID_MALI_0_MUX 76
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#define CLKID_MALI_0_DIV 77
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#define CLKID_MALI_0 78
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#define CLKID_MALI_1_MUX 79
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#define CLKID_MALI_1_DIV 80
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#define CLKID_MALI_1 81
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#define CLKID_MALI 82
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#define CLKID_MALI_STACK_0_MUX 83
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#define CLKID_MALI_STACK_0_DIV 84
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#define CLKID_MALI_STACK_0 85
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#define CLKID_MALI_STACK_1_MUX 86
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#define CLKID_MALI_STACK_1_DIV 87
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#define CLKID_MALI_STACK_1 88
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#define CLKID_MALI_STACK 89
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#define CLKID_HEVCF_0_MUX 90
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#define CLKID_HEVCF_0_DIV 91
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#define CLKID_HEVCF_0 92
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#define CLKID_HEVCF_1_MUX 93
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#define CLKID_HEVCF_1_DIV 94
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#define CLKID_HEVCF_1 95
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#define CLKID_HEVCF 96
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#define CLKID_HCODEC_0_MUX 97
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#define CLKID_HCODEC_0_DIV 98
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#define CLKID_HCODEC_0 99
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#define CLKID_HCODEC_1_MUX 100
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#define CLKID_HCODEC_1_DIV 101
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#define CLKID_HCODEC_1 102
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#define CLKID_HCODEC 103
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#define CLKID_VPU_0_MUX 104
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#define CLKID_VPU_0_DIV 105
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#define CLKID_VPU_0 106
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#define CLKID_VPU_1_MUX 107
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#define CLKID_VPU_1_DIV 108
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#define CLKID_VPU_1 109
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#define CLKID_VPU 110
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#define CLKID_VPU_CLKB_TMP_MUX 111
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#define CLKID_VPU_CLKB_TMP_DIV 112
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#define CLKID_VPU_CLKB_TMP 113
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#define CLKID_VPU_CLKB_DIV 114
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#define CLKID_VPU_CLKB 115
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#define CLKID_VAPB_0_MUX 116
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#define CLKID_VAPB_0_DIV 117
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#define CLKID_VAPB_0 118
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#define CLKID_VAPB_1_MUX 119
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#define CLKID_VAPB_1_DIV 120
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#define CLKID_VAPB_1 121
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#define CLKID_VAPB 122
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#define CLKID_GE2D 123
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#define CLKID_HDMITX_SYS_MUX 124
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#define CLKID_HDMITX_SYS_DIV 125
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#define CLKID_HDMITX_SYS 126
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#define CLKID_HDMITX_PRIF_MUX 127
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#define CLKID_HDMITX_PRIF_DIV 128
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#define CLKID_HDMITX_PRIF 129
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#define CLKID_HDMITX_200M_MUX 130
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#define CLKID_HDMITX_200M_DIV 131
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#define CLKID_HDMITX_200M 132
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#define CLKID_HDMITX_AUD_MUX 133
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#define CLKID_HDMITX_AUD_DIV 134
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#define CLKID_HDMITX_AUD 135
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#define CLKID_PWM_H_MUX 136
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#define CLKID_PWM_H_DIV 137
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#define CLKID_PWM_H 138
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#define CLKID_PWM_I_MUX 139
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#define CLKID_PWM_I_DIV 140
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#define CLKID_PWM_I 141
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#define CLKID_PWM_J_MUX 142
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#define CLKID_PWM_J_DIV 143
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#define CLKID_PWM_J 144
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#define CLKID_PWM_K_MUX 145
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#define CLKID_PWM_K_DIV 146
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#define CLKID_PWM_K 147
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#define CLKID_PWM_L_MUX 148
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#define CLKID_PWM_L_DIV 149
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#define CLKID_PWM_L 150
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#define CLKID_PWM_M_MUX 151
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#define CLKID_PWM_M_DIV 152
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#define CLKID_PWM_M 153
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#define CLKID_PWM_N_MUX 154
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#define CLKID_PWM_N_DIV 155
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#define CLKID_PWM_N 156
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#define CLKID_SPISG0_MUX 157
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#define CLKID_SPISG0_DIV 158
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#define CLKID_SPISG0 159
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#define CLKID_SPISG1_MUX 160
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#define CLKID_SPISG1_DIV 161
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#define CLKID_SPISG1 162
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#define CLKID_SPISG2_MUX 163
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#define CLKID_SPISG2_DIV 164
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#define CLKID_SPISG2 165
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#define CLKID_SD_EMMC_A_MUX 166
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#define CLKID_SD_EMMC_A_DIV 167
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#define CLKID_SD_EMMC_A 168
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#define CLKID_SD_EMMC_B_MUX 169
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#define CLKID_SD_EMMC_B_DIV 170
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#define CLKID_SD_EMMC_B 171
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#define CLKID_SD_EMMC_C_MUX 172
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#define CLKID_SD_EMMC_C_DIV 173
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#define CLKID_SD_EMMC_C 174
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#define CLKID_VDIN_MEAS_MUX 175
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#define CLKID_VDIN_MEAS_DIV 176
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#define CLKID_VDIN_MEAS 177
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#define CLKID_VID_LOCK_MUX 178
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#define CLKID_VID_LOCK_DIV 179
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#define CLKID_VID_LOCK 180
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#define CLKID_ETH_RMII_MUX 181
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#define CLKID_ETH_RMII_DIV 182
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#define CLKID_ETH_RMII 183
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#define CLKID_ETH_125M_DIV 184
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#define CLKID_ETH_125M 185
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#define CLKID_TS_DIV 186
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#define CLKID_TS 187
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#define CLKID_AMFC_MUX 188
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#define CLKID_AMFC_DIV 189
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#define CLKID_AMFC 190
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#define CLKID_PCIE0_TL_MUX 191
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#define CLKID_PCIE0_TL_DIV 192
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#define CLKID_PCIE0_TL 193
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#define CLKID_PCIE1_TL_MUX 194
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#define CLKID_PCIE1_TL_DIV 195
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#define CLKID_PCIE1_TL 196
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#define CLKID_PP_MUX 197
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#define CLKID_PP_DIV 198
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#define CLKID_PP 199
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#define CLKID_ISP_MUX 200
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#define CLKID_ISP_DIV 201
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#define CLKID_ISP 202
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#define CLKID_DSPA_0_MUX 203
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#define CLKID_DSPA_0_DIV 204
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#define CLKID_DSPA_0 205
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#define CLKID_DSPA_1_MUX 206
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#define CLKID_DSPA_1_DIV 207
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#define CLKID_DSPA_1 208
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#define CLKID_DSPA 209
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#define CLKID_GLB_MUX 210
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#define CLKID_GLB_DIV 211
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#define CLKID_GLB 212
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#define CLKID_CAN0_PE_MUX 213
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#define CLKID_CAN0_PE_DIV 214
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#define CLKID_CAN0_PE 215
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#define CLKID_CAN1_PE_MUX 216
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#define CLKID_CAN1_PE_DIV 217
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#define CLKID_CAN1_PE 218
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#define CLKID_CAN0_FILTER_MUX 219
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#define CLKID_CAN0_FILTER_DIV 220
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#define CLKID_CAN0_FILTER 221
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#define CLKID_CAN1_FILTER_MUX 222
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#define CLKID_CAN1_FILTER_DIV 223
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#define CLKID_CAN1_FILTER 224
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#define CLKID_I3C_MUX 225
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#define CLKID_I3C_DIV 226
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#define CLKID_I3C 227
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#define CLKID_CMPR_MUX 228
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#define CLKID_CMPR_DIV 229
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#define CLKID_CMPR 230
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#define CLKID_VGE_MUX 231
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#define CLKID_VGE_DIV 232
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#define CLKID_VGE 233
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#define CLKID_CVE_MUX 234
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#define CLKID_CVE_DIV 235
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#define CLKID_CVE 236
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#define CLKID_DEWARPA_MUX 237
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#define CLKID_DEWARPA_DIV 238
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#define CLKID_DEWARPA 239
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#define CLKID_DPTX_APB2_MUX 240
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#define CLKID_DPTX_APB2_DIV 241
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#define CLKID_DPTX_APB2 242
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#define CLKID_DPTX_AUD_MUX 243
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#define CLKID_DPTX_AUD_DIV 244
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#define CLKID_DPTX_AUD 245
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#define CLKID_DSI_MEAS_MUX 246
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#define CLKID_DSI_MEAS_DIV 247
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#define CLKID_DSI_MEAS 248
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#define CLKID_DSI_B_MEAS_MUX 249
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#define CLKID_DSI_B_MEAS_DIV 250
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#define CLKID_DSI_B_MEAS 251
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#define CLKID_HDMIRX_2M_MUX 252
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#define CLKID_HDMIRX_2M_DIV 253
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#define CLKID_HDMIRX_2M 254
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#define CLKID_HDMIRX_5M_MUX 255
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#define CLKID_HDMIRX_5M_DIV 256
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#define CLKID_HDMIRX_5M 257
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#define CLKID_HDMIRX_CFG_MUX 258
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#define CLKID_HDMIRX_CFG_DIV 259
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#define CLKID_HDMIRX_CFG 260
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#define CLKID_HDMIRX_HDCP2X_MUX 261
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#define CLKID_HDMIRX_HDCP2X_DIV 262
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#define CLKID_HDMIRX_HDCP2X 263
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#define CLKID_HDMIRX_ACR_REF_MUX 264
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#define CLKID_HDMIRX_ACR_REF_DIV 265
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#define CLKID_HDMIRX_ACR_REF 266
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#define CLKID_HDMIRX_METER_MUX 267
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#define CLKID_HDMIRX_METER_DIV 268
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#define CLKID_HDMIRX_METER 269
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#define CLKID_USB_250M_MUX 270
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#define CLKID_USB_250M_DIV 271
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#define CLKID_USB_250M 272
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#define CLKID_NNA_CORE_MUX 273
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#define CLKID_NNA_CORE_DIV 274
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#define CLKID_NNA_CORE 275
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#define CLKID_CSI_PHY_MUX 276
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#define CLKID_CSI_PHY_DIV 277
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#define CLKID_CSI_PHY 278
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#define CLKID_USB_48M_PRE_MUX 279
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#define CLKID_USB_48M_PRE_DIV 280
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#define CLKID_USB_48M_PRE 281
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#define CLKID_USB_48M_DUAL_CLKIN 282
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#define CLKID_USB_48M_DUAL_DIV 283
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#define CLKID_USB_48M_DUAL_MUX 284
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#define CLKID_USB_48M_DUAL 285
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#define CLKID_USB_48M 286
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#define CLKID_GEN_MUX 287
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#define CLKID_GEN_DIV 288
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#define CLKID_GEN 289
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#define CLKID_SYS_AM_AXI 290
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#define CLKID_SYS_DOS 291
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#define CLKID_SYS_MIPI_DSI 292
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#define CLKID_SYS_ETH_PHY 293
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#define CLKID_SYS_AMFC 294
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#define CLKID_SYS_MALI 295
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#define CLKID_SYS_NNA 296
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#define CLKID_SYS_ETH_AXI 297
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#define CLKID_SYS_DP_APB 298
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#define CLKID_SYS_EDPTX_APB 299
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#define CLKID_SYS_U3HSG 300
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#define CLKID_SYS_AUCPU 301
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#define CLKID_SYS_GLB 302
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#define CLKID_SYS_COMBO_DPHY_APB 303
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#define CLKID_SYS_HDMIRX_APB 304
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#define CLKID_SYS_HDMIRX_PCLK 305
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#define CLKID_SYS_MIPI_DSI_PHY 306
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#define CLKID_SYS_CAN1 307
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#define CLKID_SYS_CAN0 308
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#define CLKID_SYS_SD_EMMC_A 309
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#define CLKID_SYS_SD_EMMC_B 310
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#define CLKID_SYS_SD_EMMC_C 311
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#define CLKID_SYS_SC 312
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#define CLKID_SYS_ACODEC 313
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#define CLKID_SYS_MIPI_ISP 314
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#define CLKID_SYS_MSR_CLK 315
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#define CLKID_SYS_AUDIO 316
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#define CLKID_SYS_MIPI_DSI_B 317
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#define CLKID_SYS_MIPI_DSI1_PHY 318
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#define CLKID_SYS_ETH 319
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#define CLKID_SYS_ETH_1G_MAC 320
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#define CLKID_SYS_UART_A 321
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#define CLKID_SYS_UART_F 322
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#define CLKID_SYS_TS_A55 323
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#define CLKID_SYS_ETH_1G_AXI 324
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#define CLKID_SYS_TS_DOS 325
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#define CLKID_SYS_USB3DRD_B 326
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#define CLKID_SYS_TS_CORE 327
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#define CLKID_SYS_TS_PLL 328
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#define CLKID_SYS_CSI_DIG_CLKIN 329
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#define CLKID_SYS_CVE 330
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#define CLKID_SYS_GE2D 331
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#define CLKID_SYS_SPISG0 332
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#define CLKID_SYS_U3DRD_1 333
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#define CLKID_SYS_U2H 334
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#define CLKID_SYS_PCIEMAC_A 335
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#define CLKID_SYS_USB3DRD_A 336
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#define CLKID_SYS_USB2DRD 337
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#define CLKID_SYS_PCIEPHY 338
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#define CLKID_SYS_PCIEMAC_B 339
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#define CLKID_SYS_PERIPH 340
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#define CLKID_SYS_PIO 341
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#define CLKID_SYS_I3C 342
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#define CLKID_SYS_I2C_M_E 343
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#define CLKID_SYS_I2C_M_F 344
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#define CLKID_SYS_HDMITX_APB 345
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#define CLKID_SYS_I2C_M_I 346
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#define CLKID_SYS_I2C_M_G 347
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#define CLKID_SYS_I2C_M_H 348
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#define CLKID_SYS_HDMI20_AES 349
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#define CLKID_SYS_CSI2_HOST 350
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#define CLKID_SYS_CSI2_ADAPT 351
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#define CLKID_SYS_DSPA 352
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#define CLKID_SYS_PP_DMA 353
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#define CLKID_SYS_PP_WRAPPER 354
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#define CLKID_SYS_VPU_INTR 355
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#define CLKID_SYS_CSI2_PHY0 356
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#define CLKID_SYS_SAR_ADC 357
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#define CLKID_SYS_PWM_J 358
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#define CLKID_SYS_PWM_I 359
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#define CLKID_SYS_PWM_H 360
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#define CLKID_SYS_PWM_N 361
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#define CLKID_SYS_PWM_M 362
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#define CLKID_SYS_PWM_L 363
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#define CLKID_SYS_PWM_K 364
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/**
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* ao clk ids
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*/
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#define CLKID_AO_OSCIN_CLK 0
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#define CLKID_AO_SYS_CLK 1
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#define CLKID_AO_RTC_DUAL_CLKIN 2
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#define CLKID_AO_RTC_DUAL_DIV 3
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#define CLKID_AO_RTC_DUAL_MUX 4
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#define CLKID_AO_RTC_DUAL 5
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#define CLKID_AO_RTC_CLK 6
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#define CLKID_AO_CECB_DUAL_CLKIN 7
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#define CLKID_AO_CECB_DUAL_DIV 8
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#define CLKID_AO_CECB_DUAL_MUX 9
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#define CLKID_AO_CECB_DUAL 10
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#define CLKID_AO_CECB_CLK 11
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#define CLKID_AO_PWM_A_MUX 12
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#define CLKID_AO_PWM_A_DIV 13
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#define CLKID_AO_PWM_A 14
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#define CLKID_AO_PWM_B_MUX 15
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#define CLKID_AO_PWM_B_DIV 16
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#define CLKID_AO_PWM_B 17
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#define CLKID_AO_PWM_C_MUX 18
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#define CLKID_AO_PWM_C_DIV 19
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#define CLKID_AO_PWM_C 20
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#define CLKID_AO_PWM_D_MUX 21
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#define CLKID_AO_PWM_D_DIV 22
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#define CLKID_AO_PWM_D 23
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#define CLKID_AO_PWM_E_MUX 24
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#define CLKID_AO_PWM_E_DIV 25
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#define CLKID_AO_PWM_E 26
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#define CLKID_AO_PWM_F_MUX 27
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#define CLKID_AO_PWM_F_DIV 28
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#define CLKID_AO_PWM_F 29
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#define CLKID_AO_PWM_G_MUX 30
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#define CLKID_AO_PWM_G_DIV 31
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#define CLKID_AO_PWM_G 32
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#define CLKID_AO_SYS_I3C 33
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#define CLKID_AO_SYS_RTC_REG 34
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#define CLKID_AO_SYS_CLKTREE 35
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#define CLKID_AO_SYS_RST_CTRL 36
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#define CLKID_AO_SYS_PAD 37
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#define CLKID_AO_SYS_RTC_DIG 38
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#define CLKID_AO_SYS_IRQ 39
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#define CLKID_AO_SYS_PWRCTRL 40
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#define CLKID_AO_SYS_PWM_A 41
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#define CLKID_AO_SYS_PWM_B 42
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#define CLKID_AO_SYS_PWM_C 43
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#define CLKID_AO_SYS_PWM_D 44
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#define CLKID_AO_SYS_PWM_E 45
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#define CLKID_AO_SYS_PWM_F 46
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#define CLKID_AO_SYS_PWM_G 47
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#define CLKID_AO_SYS_I2C_M_A 48
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#define CLKID_AO_SYS_I2C_M_B 49
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#define CLKID_AO_SYS_I2C_M_C 50
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#define CLKID_AO_SYS_I2C_M_D 51
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#define CLKID_AO_SYS_SED 52
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#define CLKID_AO_SYS_IR_CTRL 53
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#define CLKID_AO_SYS_UART_B 54
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#define CLKID_AO_SYS_UART_C 55
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#define CLKID_AO_SYS_UART_D 56
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#define CLKID_AO_SYS_UART_E 57
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#define CLKID_AO_SYS_SPISG_0 58
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#define CLKID_AO_SYS_RTC_SEC 59
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#define CLKID_AO_SYS_CEC 60
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#define CLKID_AO_SYS_AOCPU 61
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#define CLKID_AO_SYS_SRAM 62
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#define CLKID_AO_SYS_SPISG_1 63
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#define CLKID_AO_SYS_SPISG_2 64
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#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A9_CLKC_H */
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