235 lines
12 KiB
C
235 lines
12 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C4_CLKC_H
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#define _DT_BINDINGS_CLOCK_AMLOGIC_C4_CLKC_H
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#define CLKID_GP0_PLL 0
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#define CLKID_HIFI_PLL 1
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#define CLKID_MCLK_PLL 2
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#define CLKID_FCLK_50M_DIV 3
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#define CLKID_FCLK_50M 4
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#define CLKID_FCLK_DIV2_DIV 5
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#define CLKID_FCLK_DIV2 6
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#define CLKID_FCLK_DIV2P5_DIV 7
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#define CLKID_FCLK_DIV2P5 8
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#define CLKID_FCLK_DIV3_DIV 9
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#define CLKID_FCLK_DIV3 10
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#define CLKID_FCLK_DIV4_DIV 11
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#define CLKID_FCLK_DIV4 12
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#define CLKID_FCLK_DIV5_DIV 13
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#define CLKID_FCLK_DIV5 14
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#define CLKID_FCLK_DIV7_DIV 15
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#define CLKID_FCLK_DIV7 16
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#define CLKID_MCLK_PLL_CLK 17
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#define CLKID_MCLK0_MUX 18
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#define CLKID_MCLK0_DIV 19
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#define CLKID_MCLK0 20
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#define CLKID_MCLK1_MUX 21
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#define CLKID_MCLK1_DIV 22
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#define CLKID_MCLK1 23
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#define CLKID_RTC_DUAL_CLKIN 24
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#define CLKID_RTC_DUAL_DIV 25
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#define CLKID_RTC_DUAL_MUX 26
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#define CLKID_RTC_DUAL 27
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#define CLKID_RTC_CLK 28
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#define CLKID_SAR_ADC_MUX 29
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#define CLKID_SAR_ADC_DIV 30
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#define CLKID_SAR_ADC 31
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#define CLKID_NNA_MUX 32
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#define CLKID_NNA_DIV 33
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#define CLKID_NNA 34
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#define CLKID_PWM_C_MUX 35
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#define CLKID_PWM_C_DIV 36
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#define CLKID_PWM_C 37
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#define CLKID_PWM_D_MUX 38
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#define CLKID_PWM_D_DIV 39
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#define CLKID_PWM_D 40
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#define CLKID_PWM_E_MUX 41
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#define CLKID_PWM_E_DIV 42
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#define CLKID_PWM_E 43
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#define CLKID_PWM_F_MUX 44
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#define CLKID_PWM_F_DIV 45
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#define CLKID_PWM_F 46
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#define CLKID_PWM_G_MUX 47
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#define CLKID_PWM_G_DIV 48
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#define CLKID_PWM_G 49
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#define CLKID_PWM_H_MUX 50
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#define CLKID_PWM_H_DIV 51
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#define CLKID_PWM_H 52
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#define CLKID_PWM_I_MUX 53
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#define CLKID_PWM_I_DIV 54
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#define CLKID_PWM_I 55
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#define CLKID_PWM_J_MUX 56
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#define CLKID_PWM_J_DIV 57
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#define CLKID_PWM_J 58
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#define CLKID_PWM_K_MUX 59
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#define CLKID_PWM_K_DIV 60
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#define CLKID_PWM_K 61
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#define CLKID_PWM_L_MUX 62
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#define CLKID_PWM_L_DIV 63
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#define CLKID_PWM_L 64
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#define CLKID_PWM_M_MUX 65
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#define CLKID_PWM_M_DIV 66
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#define CLKID_PWM_M 67
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#define CLKID_PWM_N_MUX 68
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#define CLKID_PWM_N_DIV 69
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#define CLKID_PWM_N 70
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#define CLKID_SPICC0_MUX 71
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#define CLKID_SPICC0_DIV 72
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#define CLKID_SPICC0 73
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#define CLKID_SPICC1_MUX 74
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#define CLKID_SPICC1_DIV 75
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#define CLKID_SPICC1 76
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#define CLKID_SD_EMMC_A_MUX 77
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#define CLKID_SD_EMMC_A_DIV 78
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#define CLKID_SD_EMMC_A 79
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#define CLKID_SD_EMMC_B_MUX 80
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#define CLKID_SD_EMMC_B_DIV 81
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#define CLKID_SD_EMMC_B 82
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#define CLKID_SD_EMMC_C_MUX 83
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#define CLKID_SD_EMMC_C_DIV 84
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#define CLKID_SD_EMMC_C 85
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#define CLKID_ETH_RMII_MUX 86
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#define CLKID_ETH_RMII_DIV 87
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#define CLKID_ETH_RMII 88
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#define CLKID_ETH_125M_DIV 89
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#define CLKID_ETH_125M 90
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#define CLKID_TS_DIV 91
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#define CLKID_TS 92
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#define CLKID_HCODEC_0_MUX 93
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#define CLKID_HCODEC_0_DIV 94
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#define CLKID_HCODEC_0 95
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#define CLKID_HCODEC_1_MUX 96
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#define CLKID_HCODEC_1_DIV 97
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#define CLKID_HCODEC_1 98
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#define CLKID_HCODEC 99
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#define CLKID_TAHOE_MUX 100
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#define CLKID_TAHOE_DIV 101
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#define CLKID_TAHOE 102
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#define CLKID_CVE_MUX 103
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#define CLKID_CVE_DIV 104
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#define CLKID_CVE 105
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#define CLKID_CVE_ARB_MUX 106
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#define CLKID_CVE_ARB_DIV 107
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#define CLKID_CVE_ARB 108
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#define CLKID_GE2D_MUX 109
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#define CLKID_GE2D_DIV 110
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#define CLKID_GE2D 111
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#define CLKID_DEWARP_MUX 112
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#define CLKID_DEWARP_DIV 113
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#define CLKID_DEWARP 114
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#define CLKID_ISP_MUX 115
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#define CLKID_ISP_DIV 116
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#define CLKID_ISP 117
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#define CLKID_CSI_PHY_MUX 118
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#define CLKID_CSI_PHY_DIV 119
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#define CLKID_CSI_PHY 120
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#define CLKID_AMFC_MUX 121
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#define CLKID_AMFC_DIV 122
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#define CLKID_AMFC 123
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#define CLKID_CLK_24M_IN 124
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#define CLKID_CLK_12M_DIV 125
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#define CLKID_CLK_12M 126
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#define CLKID_GEN_MUX 127
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#define CLKID_GEN_DIV 128
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#define CLKID_GEN 129
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#define CLKID_SYS_CLK_CTRL 130
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#define CLKID_SYS_RESET_CTRL 131
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#define CLKID_SYS_ANALOG_CTRL 132
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#define CLKID_SYS_PWR_CTRL 133
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#define CLKID_SYS_PAD_CTRL 134
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#define CLKID_SYS_SYS_CTRL 135
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#define CLKID_SYS_TS_PLL 136
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#define CLKID_SYS_MMC_PCLK 137
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#define CLKID_SYS_CAPU 138
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#define CLKID_SYS_CPU_CTRL 139
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#define CLKID_SYS_JTAG_CTRL 140
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#define CLKID_SYS_IRQ_CTRL 141
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#define CLKID_SYS_MSR_CLK 142
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#define CLKID_SYS_ROM 143
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#define CLKID_SYS_UART_F 144
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#define CLKID_SYS_CPU_APB 145
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#define CLKID_SYS_SAR_ADC 146
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#define CLKID_SYS_STARTUP 147
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#define CLKID_SYS_SECURE 148
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#define CLKID_SYS_AMFC 149
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#define CLKID_SYS_NNA 150
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#define CLKID_SYS_ETH_MAC 151
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#define CLKID_SYS_GIC 152
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#define CLKID_SYS_RAMA 153
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#define CLKID_SYS_BIG_NIC 154
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#define CLKID_SYS_AUDIO_VAD 155
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#define CLKID_SYS_AUDIO 156
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#define CLKID_SYS_PWM_A 157
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#define CLKID_SYS_PWM_B 158
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#define CLKID_SYS_USB 159
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#define CLKID_SYS_SD_EMMC_A 160
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#define CLKID_SYS_SD_EMMC_C 161
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#define CLKID_SYS_PWM_C 162
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#define CLKID_SYS_PWM_D 163
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#define CLKID_SYS_PWM_E 164
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#define CLKID_SYS_PWM_F 165
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#define CLKID_SYS_PIO_CORE 166
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#define CLKID_SYS_SPICC 167
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#define CLKID_SYS_UART_A 168
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#define CLKID_SYS_UART_B 169
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#define CLKID_SYS_UART_C 170
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#define CLKID_SYS_UART_D 171
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#define CLKID_SYS_UART_E 172
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#define CLKID_SYS_I2C_M_A 173
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#define CLKID_SYS_I2C_M_B 174
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#define CLKID_SYS_I2C_M_C 175
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#define CLKID_SYS_I2C_M_D 176
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#define CLKID_SYS_I2C_S_A 177
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#define CLKID_SYS_ETH_PHY 178
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#define CLKID_SYS_ACODEC 179
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#define CLKID_SYS_PWM_N 180
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#define CLKID_SYS_DOS 181
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#define CLKID_SYS_CVE 182
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#define CLKID_SYS_ISP_CAPU 183
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#define CLKID_SYS_TAHOE 184
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#define CLKID_SYS_CVE_INTR 185
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#define CLKID_SYS_SD_EMMC_B 186
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#define CLKID_SYS_PWM_G 187
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#define CLKID_SYS_PWM_H 188
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#define CLKID_SYS_PWM_I 189
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#define CLKID_SYS_PWM_J 190
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#define CLKID_SYS_PWM_K 191
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#define CLKID_SYS_PWM_L 192
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#define CLKID_SYS_PWM_M 193
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#define CLKID_AXI_SYS_NIC 194
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#define CLKID_AXI_RAMA 195
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#define CLKID_AXI_MUX_NIC 196
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#define CLKID_AXI_DEV_DMC 197
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/**
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* ao clk ids
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*/
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#define CLKID_AO_ROUGH_32K_CLK_DIV 0
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#define CLKID_AO_ROUGH_32K_CLK 1
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#define CLKID_AO_OSCIN32K_CLK 2
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#define CLKID_AO_OSCIN_CLK 3
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#define CLKID_AO_SYS_CLK 4
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#define CLKID_AO_PWM_J_MUX 5
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#define CLKID_AO_PWM_J_DIV 6
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#define CLKID_AO_PWM_J 7
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#define CLKID_AO_PWM_K_MUX 8
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#define CLKID_AO_PWM_K_DIV 9
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#define CLKID_AO_PWM_K 10
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#define CLKID_AO_SYS_APB_CLK 11
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#define CLKID_AO_SYS_RTC_REG 12
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#define CLKID_AO_SYS_RTC_CLK 13
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#define CLKID_AO_SYS_RESET_CTRL 14
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#define CLKID_AO_SYS_PAD_CTRL 15
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#define CLKID_AO_SYS_RTC_DIG 16
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#define CLKID_AO_SYS_IRQ_CTRL 17
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#define CLKID_AO_SYS_PWR_CTRL 18
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#define CLKID_AO_SYS_PWM_J 19
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#define CLKID_AO_SYS_PWM_K 20
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#define CLKID_AO_SYS_SED 21
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#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C4_CLKC_H */
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