265 lines
14 KiB
C
265 lines
14 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
|
/*
|
|
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S7D_CLKC_H
|
|
#define _DT_BINDINGS_CLOCK_AMLOGIC_S7D_CLKC_H
|
|
|
|
#define CLKID_GP0_PLL 0
|
|
#define CLKID_HIFI_PLL 1
|
|
#define CLKID_HIFI1_PLL 2
|
|
#define CLKID_FCLK_50M_DIV 3
|
|
#define CLKID_FCLK_50M 4
|
|
#define CLKID_FCLK_DIV2_DIV 5
|
|
#define CLKID_FCLK_DIV2 6
|
|
#define CLKID_FCLK_DIV2P5_DIV 7
|
|
#define CLKID_FCLK_DIV2P5 8
|
|
#define CLKID_FCLK_DIV3_DIV 9
|
|
#define CLKID_FCLK_DIV3 10
|
|
#define CLKID_FCLK_DIV4_DIV 11
|
|
#define CLKID_FCLK_DIV4 12
|
|
#define CLKID_FCLK_DIV5_DIV 13
|
|
#define CLKID_FCLK_DIV5 14
|
|
#define CLKID_FCLK_DIV7_DIV 15
|
|
#define CLKID_FCLK_DIV7 16
|
|
#define CLKID_RTC_DUAL_CLKIN 17
|
|
#define CLKID_RTC_DUAL_DIV 18
|
|
#define CLKID_RTC_DUAL_MUX 19
|
|
#define CLKID_RTC_DUAL 20
|
|
#define CLKID_RTC_CLK 21
|
|
#define CLKID_SAR_ADC_MUX 22
|
|
#define CLKID_SAR_ADC_DIV 23
|
|
#define CLKID_SAR_ADC 24
|
|
#define CLKID_CECB_DUAL_CLKIN 25
|
|
#define CLKID_CECB_DUAL_DIV 26
|
|
#define CLKID_CECB_DUAL_MUX 27
|
|
#define CLKID_CECB_DUAL 28
|
|
#define CLKID_CECB_CLK 29
|
|
#define CLKID_SC_MUX 30
|
|
#define CLKID_SC_DIV 31
|
|
#define CLKID_SC 32
|
|
#define CLKID_CDAC_MUX 33
|
|
#define CLKID_CDAC_DIV 34
|
|
#define CLKID_CDAC 35
|
|
#define CLKID_VIDEO_SRC0_IN_MUX 36
|
|
#define CLKID_VIDEO_SRC0_IN 37
|
|
#define CLKID_VIDEO_SRC0_DIV 38
|
|
#define CLKID_VIDEO_SRC0 39
|
|
#define CLKID_VIDEO_SRC1_IN_MUX 40
|
|
#define CLKID_VIDEO_SRC1_IN 41
|
|
#define CLKID_VIDEO_SRC1_DIV 42
|
|
#define CLKID_VIDEO_SRC1 43
|
|
#define CLKID_VIDEO0_DIV1 44
|
|
#define CLKID_VIDEO0_DIV2_GATE 45
|
|
#define CLKID_VIDEO0_DIV2 46
|
|
#define CLKID_VIDEO0_DIV4_GATE 47
|
|
#define CLKID_VIDEO0_DIV4 48
|
|
#define CLKID_VIDEO0_DIV6_GATE 49
|
|
#define CLKID_VIDEO0_DIV6 50
|
|
#define CLKID_VIDEO0_DIV12_GATE 51
|
|
#define CLKID_VIDEO0_DIV12 52
|
|
#define CLKID_VIDEO2_DIV1 53
|
|
#define CLKID_VIDEO2_DIV2_GATE 54
|
|
#define CLKID_VIDEO2_DIV2 55
|
|
#define CLKID_VIDEO2_DIV4_GATE 56
|
|
#define CLKID_VIDEO2_DIV4 57
|
|
#define CLKID_VIDEO2_DIV6_GATE 58
|
|
#define CLKID_VIDEO2_DIV6 59
|
|
#define CLKID_VIDEO2_DIV12_GATE 60
|
|
#define CLKID_VIDEO2_DIV12 61
|
|
#define CLKID_LCD_AN_MUX 62
|
|
#define CLKID_LCD_AN 63
|
|
#define CLKID_LCD_AN_PH2 64
|
|
#define CLKID_LCD_AN_PH3 65
|
|
#define CLKID_ENCI_MUX 66
|
|
#define CLKID_ENCI 67
|
|
#define CLKID_ENCP_MUX 68
|
|
#define CLKID_ENCP 69
|
|
#define CLKID_ENCL_MUX 70
|
|
#define CLKID_ENCL 71
|
|
#define CLKID_VDAC_MUX 72
|
|
#define CLKID_VDAC 73
|
|
#define CLKID_HDMITX_PIXEL_MUX 74
|
|
#define CLKID_HDMITX_PIXEL 75
|
|
#define CLKID_HDMITX_FE_MUX 76
|
|
#define CLKID_HDMITX_FE 77
|
|
#define CLKID_MALI_0_MUX 78
|
|
#define CLKID_MALI_0_DIV 79
|
|
#define CLKID_MALI_0 80
|
|
#define CLKID_MALI_1_MUX 81
|
|
#define CLKID_MALI_1_DIV 82
|
|
#define CLKID_MALI_1 83
|
|
#define CLKID_MALI 84
|
|
#define CLKID_MALI_STACK_0_MUX 85
|
|
#define CLKID_MALI_STACK_0_DIV 86
|
|
#define CLKID_MALI_STACK_0 87
|
|
#define CLKID_MALI_STACK_1_MUX 88
|
|
#define CLKID_MALI_STACK_1_DIV 89
|
|
#define CLKID_MALI_STACK_1 90
|
|
#define CLKID_MALI_STACK 91
|
|
#define CLKID_VDEC_0_MUX 92
|
|
#define CLKID_VDEC_0_DIV 93
|
|
#define CLKID_VDEC_0 94
|
|
#define CLKID_VDEC_1_MUX 95
|
|
#define CLKID_VDEC_1_DIV 96
|
|
#define CLKID_VDEC_1 97
|
|
#define CLKID_VDEC 98
|
|
#define CLKID_HEVCF_0_MUX 99
|
|
#define CLKID_HEVCF_0_DIV 100
|
|
#define CLKID_HEVCF_0 101
|
|
#define CLKID_HEVCF_1_MUX 102
|
|
#define CLKID_HEVCF_1_DIV 103
|
|
#define CLKID_HEVCF_1 104
|
|
#define CLKID_HEVCF 105
|
|
#define CLKID_HCODEC_0_MUX 106
|
|
#define CLKID_HCODEC_0_DIV 107
|
|
#define CLKID_HCODEC_0 108
|
|
#define CLKID_HCODEC_1_MUX 109
|
|
#define CLKID_HCODEC_1_DIV 110
|
|
#define CLKID_HCODEC_1 111
|
|
#define CLKID_HCODEC 112
|
|
#define CLKID_VPU_0_MUX 113
|
|
#define CLKID_VPU_0_DIV 114
|
|
#define CLKID_VPU_0 115
|
|
#define CLKID_VPU_1_MUX 116
|
|
#define CLKID_VPU_1_DIV 117
|
|
#define CLKID_VPU_1 118
|
|
#define CLKID_VPU 119
|
|
#define CLKID_VPU_CLKB_TMP_MUX 120
|
|
#define CLKID_VPU_CLKB_TMP_DIV 121
|
|
#define CLKID_VPU_CLKB_TMP 122
|
|
#define CLKID_VPU_CLKB_DIV 123
|
|
#define CLKID_VPU_CLKB 124
|
|
#define CLKID_VPU_CLKC_0_MUX 125
|
|
#define CLKID_VPU_CLKC_0_DIV 126
|
|
#define CLKID_VPU_CLKC_0 127
|
|
#define CLKID_VPU_CLKC_1_MUX 128
|
|
#define CLKID_VPU_CLKC_1_DIV 129
|
|
#define CLKID_VPU_CLKC_1 130
|
|
#define CLKID_VPU_CLKC 131
|
|
#define CLKID_VAPB_0_MUX 132
|
|
#define CLKID_VAPB_0_DIV 133
|
|
#define CLKID_VAPB_0 134
|
|
#define CLKID_VAPB_1_MUX 135
|
|
#define CLKID_VAPB_1_DIV 136
|
|
#define CLKID_VAPB_1 137
|
|
#define CLKID_VAPB 138
|
|
#define CLKID_GE2D 139
|
|
#define CLKID_HDMITX_SYS_MUX 140
|
|
#define CLKID_HDMITX_SYS_DIV 141
|
|
#define CLKID_HDMITX_SYS 142
|
|
#define CLKID_HDMITX_PRIF_MUX 143
|
|
#define CLKID_HDMITX_PRIF_DIV 144
|
|
#define CLKID_HDMITX_PRIF 145
|
|
#define CLKID_HDMITX_200M_MUX 146
|
|
#define CLKID_HDMITX_200M_DIV 147
|
|
#define CLKID_HDMITX_200M 148
|
|
#define CLKID_HDMITX_AUD_MUX 149
|
|
#define CLKID_HDMITX_AUD_DIV 150
|
|
#define CLKID_HDMITX_AUD 151
|
|
#define CLKID_PWM_A_MUX 152
|
|
#define CLKID_PWM_A_DIV 153
|
|
#define CLKID_PWM_A 154
|
|
#define CLKID_PWM_B_MUX 155
|
|
#define CLKID_PWM_B_DIV 156
|
|
#define CLKID_PWM_B 157
|
|
#define CLKID_PWM_C_MUX 158
|
|
#define CLKID_PWM_C_DIV 159
|
|
#define CLKID_PWM_C 160
|
|
#define CLKID_PWM_D_MUX 161
|
|
#define CLKID_PWM_D_DIV 162
|
|
#define CLKID_PWM_D 163
|
|
#define CLKID_PWM_E_MUX 164
|
|
#define CLKID_PWM_E_DIV 165
|
|
#define CLKID_PWM_E 166
|
|
#define CLKID_PWM_F_MUX 167
|
|
#define CLKID_PWM_F_DIV 168
|
|
#define CLKID_PWM_F 169
|
|
#define CLKID_SPICC0_MUX 170
|
|
#define CLKID_SPICC0_DIV 171
|
|
#define CLKID_SPICC0 172
|
|
#define CLKID_SD_EMMC_A_MUX 173
|
|
#define CLKID_SD_EMMC_A_DIV 174
|
|
#define CLKID_SD_EMMC_A 175
|
|
#define CLKID_SD_EMMC_B_MUX 176
|
|
#define CLKID_SD_EMMC_B_DIV 177
|
|
#define CLKID_SD_EMMC_B 178
|
|
#define CLKID_SD_EMMC_C_MUX 179
|
|
#define CLKID_SD_EMMC_C_DIV 180
|
|
#define CLKID_SD_EMMC_C 181
|
|
#define CLKID_VDIN_MEAS_MUX 182
|
|
#define CLKID_VDIN_MEAS_DIV 183
|
|
#define CLKID_VDIN_MEAS 184
|
|
#define CLKID_VID_LOCK_MUX 185
|
|
#define CLKID_VID_LOCK_DIV 186
|
|
#define CLKID_VID_LOCK 187
|
|
#define CLKID_ETH_RMII_DIV 188
|
|
#define CLKID_ETH_RMII 189
|
|
#define CLKID_ETH_125M_DIV 190
|
|
#define CLKID_ETH_125M 191
|
|
#define CLKID_TS_DIV 192
|
|
#define CLKID_TS 193
|
|
#define CLKID_AMFC_MUX 194
|
|
#define CLKID_AMFC_DIV 195
|
|
#define CLKID_AMFC 196
|
|
#define CLKID_CLK_24M_IN 197
|
|
#define CLKID_CLK_12M_DIV 198
|
|
#define CLKID_CLK_12M 199
|
|
#define CLKID_GEN_MUX 200
|
|
#define CLKID_GEN_DIV 201
|
|
#define CLKID_GEN 202
|
|
#define CLKID_SYS_AM_AXI 203
|
|
#define CLKID_SYS_DOS 204
|
|
#define CLKID_SYS_ETHPHY 205
|
|
#define CLKID_SYS_MALI 206
|
|
#define CLKID_SYS_AOCPU 207
|
|
#define CLKID_SYS_AUCPU 208
|
|
#define CLKID_SYS_CEC 209
|
|
#define CLKID_SYS_SD_EMMC_A 210
|
|
#define CLKID_SYS_SD_EMMC_B 211
|
|
#define CLKID_SYS_SD_EMMC_C 212
|
|
#define CLKID_SYS_SMARTCARD 213
|
|
#define CLKID_SYS_ACODEC 214
|
|
#define CLKID_SYS_MSR_CLK 215
|
|
#define CLKID_SYS_IR_CTRL 216
|
|
#define CLKID_SYS_AUDIO 217
|
|
#define CLKID_SYS_ETH 218
|
|
#define CLKID_SYS_UART_A 219
|
|
#define CLKID_SYS_UART_B 220
|
|
#define CLKID_SYS_UART_C 221
|
|
#define CLKID_SYS_UART_D 222
|
|
#define CLKID_SYS_UART_E 223
|
|
#define CLKID_SYS_TS_PLL 224
|
|
#define CLKID_SYS_GE2D 225
|
|
#define CLKID_SYS_SPICC0 226
|
|
#define CLKID_SYS_USB 227
|
|
#define CLKID_SYS_I2C_M_A 228
|
|
#define CLKID_SYS_I2C_M_B 229
|
|
#define CLKID_SYS_I2C_M_C 230
|
|
#define CLKID_SYS_I2C_M_D 231
|
|
#define CLKID_SYS_I2C_M_E 232
|
|
#define CLKID_SYS_HDMITX_APB 233
|
|
#define CLKID_SYS_I2C_S_A 234
|
|
#define CLKID_SYS_HDMI20_AES 235
|
|
#define CLKID_SYS_MMC_APB 236
|
|
#define CLKID_SYS_CPU_APB 237
|
|
#define CLKID_SYS_VPU_INTR 238
|
|
#define CLKID_SYS_SAR_ADC 239
|
|
#define CLKID_SYS_PWM_J 240
|
|
#define CLKID_SYS_GIC 241
|
|
#define CLKID_SYS_PWM_I 242
|
|
#define CLKID_SYS_PWM_H 243
|
|
#define CLKID_SYS_PWM_G 244
|
|
#define CLKID_SYS_PWM_F 245
|
|
#define CLKID_SYS_PWM_E 246
|
|
#define CLKID_SYS_PWM_D 247
|
|
#define CLKID_SYS_PWM_C 248
|
|
#define CLKID_SYS_PWM_B 249
|
|
#define CLKID_SYS_PWM_A 250
|
|
#define CLKID_AXI_SYS_NIC 251
|
|
#define CLKID_AXI_RAMA 252
|
|
#define CLKID_AXI_DEV0_MMC 253
|
|
|
|
#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S7D_CLKC_H */
|