48 lines
1.4 KiB
C
48 lines
1.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_T7_SCMI_CLK_H
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#define _DT_BINDINGS_CLOCK_T7_SCMI_CLK_H
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#define CLKID_DDR_PLL_OSC 0
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#define CLKID_AUD_PLL_OSC 1
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#define CLKID_TOP_PLL_OSC 2
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#define CLKID_TCON_PLL_OSC 3
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#define CLKID_USB_PLL0_OSC 4
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#define CLKID_USB_PLL1_OSC 5
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#define CLKID_MCLK_PLL_OSC 6
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#define CLKID_PCIE_OSC 7
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#define CLKID_ETH_PLL_OSC 8
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#define CLKID_PCIE_REFCLK_PLL_OSC 9
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#define CLKID_EARC_OSC 10
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#define CLKID_SYS1_PLL_OSC 11
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#define CLKID_HDMI_PLL_OSC 12
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#define CLKID_SYS_CLK 13
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#define CLKID_AXI_CLK 14
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#define CLKID_FIXED_PLL_DCO 15
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#define CLKID_FIXED_PLL 16
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#define CLKID_FCLK_DIV2_DIV 17
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#define CLKID_FCLK_DIV2 18
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#define CLKID_FCLK_DIV2P5_DIV 19
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#define CLKID_FCLK_DIV2P5 20
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#define CLKID_FCLK_DIV3_DIV 21
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#define CLKID_FCLK_DIV3 22
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#define CLKID_FCLK_DIV4_DIV 23
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#define CLKID_FCLK_DIV4 24
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#define CLKID_FCLK_DIV5_DIV 25
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#define CLKID_FCLK_DIV5 26
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#define CLKID_FCLK_DIV7_DIV 27
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#define CLKID_FCLK_DIV7 28
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#define CLKID_FCLK_50M_DIV 29
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#define CLKID_FCLK_50M 30
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#define CLKID_CPU_CLK 31
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#define CLKID_A73_CLK 32
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#define CLKID_CPU_CLK_DIV16_DIV 33
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#define CLKID_CPU_CLK_DIV16 34
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#define CLKID_A73_CLK_DIV16_DIV 35
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#define CLKID_A73_CLK_DIV16 36
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#endif /* _DT_BINDINGS_CLOCK_T7_SCMI_CLK_H */
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