337 lines
17 KiB
C
337 lines
17 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __S6_CLKC_H
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#define __S6_CLKC_H
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#define CLKID_GP0_PLL 0
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#define CLKID_HIFI_PLL 1
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#define CLKID_HIFI1_PLL 2
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#define CLKID_MCLK_PLL 3
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#define CLKID_MCLK_PLL_CLK 4
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#define CLKID_MCLK0_DIV 5
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#define CLKID_MCLK0_DIV2 6
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#define CLKID_MCLK0 7
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#define CLKID_FCLK50M_DIV 8
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#define CLKID_FCLK50M 9
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#define CLKID_FCLK_DIV2_DIV 10
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#define CLKID_FCLK_DIV2 11
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#define CLKID_FCLK_DIV2P5_DIV 12
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#define CLKID_FCLK_DIV2P5 13
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#define CLKID_FCLK_DIV3_DIV 14
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#define CLKID_FCLK_DIV3 15
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#define CLKID_FCLK_DIV4_DIV 16
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#define CLKID_FCLK_DIV4 17
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#define CLKID_FCLK_DIV5_DIV 18
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#define CLKID_FCLK_DIV5 19
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#define CLKID_FCLK_DIV7_DIV 20
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#define CLKID_FCLK_DIV7 21
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#define CLKID_RTC_DUAL_CLKIN 22
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#define CLKID_RTC_DUAL_DIV 23
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#define CLKID_RTC_DUAL_MUX 24
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#define CLKID_RTC_DUAL 25
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#define CLKID_RTC_CLK 26
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#define CLKID_CLK_24M_IN 27
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#define CLKID_CLK_12M_DIV 28
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#define CLKID_CLK_12M 29
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#define CLKID_SAR_ADC_MUX 30
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#define CLKID_SAR_ADC_DIV 31
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#define CLKID_SAR_ADC 32
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#define CLKID_CECB_DUAL_CLKIN 33
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#define CLKID_CECB_DUAL_DIV 34
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#define CLKID_CECB_DUAL_MUX 35
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#define CLKID_CECB_DUAL 36
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#define CLKID_CECB_CLK 37
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#define CLKID_SC_PRE_MUX 38
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#define CLKID_SC_PRE_DIV 39
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#define CLKID_SC_PRE 40
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#define CLKID_SC 41
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#define CLKID_CDAC_MUX 42
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#define CLKID_CDAC_DIV 43
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#define CLKID_CDAC 44
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#define CLKID_VIDEO_SRC0_IN_MUX 45
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#define CLKID_VIDEO_SRC0_IN 46
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#define CLKID_VIDEO_SRC0_DIV 47
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#define CLKID_VIDEO_SRC0 48
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#define CLKID_VIDEO_SRC1_IN_MUX 49
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#define CLKID_VIDEO_SRC1_IN 50
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#define CLKID_VIDEO_SRC1_DIV 51
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#define CLKID_VIDEO_SRC1 52
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#define CLKID_VIDEO0_DIV1 53
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#define CLKID_VIDEO0_DIV2_GATE 54
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#define CLKID_VIDEO0_DIV2 55
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#define CLKID_VIDEO0_DIV4_GATE 56
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#define CLKID_VIDEO0_DIV4 57
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#define CLKID_VIDEO0_DIV6_GATE 58
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#define CLKID_VIDEO0_DIV6 59
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#define CLKID_VIDEO0_DIV12_GATE 60
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#define CLKID_VIDEO0_DIV12 61
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#define CLKID_VIDEO2_DIV1 62
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#define CLKID_VIDEO2_DIV2_GATE 63
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#define CLKID_VIDEO2_DIV2 64
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#define CLKID_VIDEO2_DIV4_GATE 65
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#define CLKID_VIDEO2_DIV4 66
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#define CLKID_VIDEO2_DIV6_GATE 67
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#define CLKID_VIDEO2_DIV6 68
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#define CLKID_VIDEO2_DIV12_GATE 69
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#define CLKID_VIDEO2_DIV12 70
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#define CLKID_LCD_AN_MUX 71
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#define CLKID_LCD_AN 72
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#define CLKID_LCD_AN_PH2 73
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#define CLKID_LCD_AN_PH3 74
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#define CLKID_ENCI_MUX 75
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#define CLKID_ENCI 76
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#define CLKID_ENCP_MUX 77
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#define CLKID_ENCP 78
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#define CLKID_ENCL_MUX 79
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#define CLKID_ENCL 80
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#define CLKID_VDAC_MUX 81
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#define CLKID_VDAC 82
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#define CLKID_HDMITX_PIXEL_MUX 83
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#define CLKID_HDMITX_PIXEL 84
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#define CLKID_HDMITX_FE_MUX 85
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#define CLKID_HDMITX_FE 86
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#define CLKID_MALI_0_MUX 87
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#define CLKID_MALI_0_DIV 88
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#define CLKID_MALI_0 89
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#define CLKID_MALI_1_MUX 90
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#define CLKID_MALI_1_DIV 91
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#define CLKID_MALI_1 92
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#define CLKID_MALI 93
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#define CLKID_MALI_STACK_0_MUX 94
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#define CLKID_MALI_STACK_0_DIV 95
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#define CLKID_MALI_STACK_0 96
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#define CLKID_MALI_STACK_1_MUX 97
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#define CLKID_MALI_STACK_1_DIV 98
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#define CLKID_MALI_STACK_1 99
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#define CLKID_MALI_STACK 100
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#define CLKID_VDEC_0_MUX 101
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#define CLKID_VDEC_0_DIV 102
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#define CLKID_VDEC_0 103
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#define CLKID_VDEC_1_MUX 104
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#define CLKID_VDEC_1_DIV 105
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#define CLKID_VDEC_1 106
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#define CLKID_VDEC 107
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#define CLKID_HEVCF_0_MUX 108
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#define CLKID_HEVCF_0_DIV 109
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#define CLKID_HEVCF_0 110
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#define CLKID_HEVCF_1_MUX 111
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#define CLKID_HEVCF_1_DIV 112
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#define CLKID_HEVCF_1 113
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#define CLKID_HEVCF 114
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#define CLKID_VPU_0_MUX 115
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#define CLKID_VPU_0_DIV 116
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#define CLKID_VPU_0 117
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#define CLKID_VPU_1_MUX 118
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#define CLKID_VPU_1_DIV 119
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#define CLKID_VPU_1 120
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#define CLKID_VPU 121
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#define CLKID_VPU_CLKB_TMP_MUX 122
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#define CLKID_VPU_CLKB_TMP_DIV 123
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#define CLKID_VPU_CLKB_TMP 124
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#define CLKID_VPU_CLKB_DIV 125
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#define CLKID_VPU_CLKB 126
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#define CLKID_VPU_CLKC_0_MUX 127
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#define CLKID_VPU_CLKC_0_DIV 128
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#define CLKID_VPU_CLKC_0 129
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#define CLKID_VPU_CLKC_1_MUX 130
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#define CLKID_VPU_CLKC_1_DIV 131
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#define CLKID_VPU_CLKC_1 132
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#define CLKID_VPU_CLKC 133
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#define CLKID_VAPB_0_MUX 134
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#define CLKID_VAPB_0_DIV 135
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#define CLKID_VAPB_0 136
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#define CLKID_VAPB_1_MUX 137
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#define CLKID_VAPB_1_DIV 138
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#define CLKID_VAPB_1 139
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#define CLKID_VAPB 140
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#define CLKID_GE2D 141
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#define CLKID_DEWARPA_MUX 142
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#define CLKID_DEWARPA_DIV 143
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#define CLKID_DEWARPA 144
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#define CLKID_CMPR_MUX 145
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#define CLKID_CMPR_DIV 146
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#define CLKID_CMPR 147
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#define CLKID_HDMITX_SYS_MUX 148
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#define CLKID_HDMITX_SYS_DIV 149
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#define CLKID_HDMITX_SYS 150
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#define CLKID_HDMITX_PRIF_MUX 151
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#define CLKID_HDMITX_PRIF_DIV 152
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#define CLKID_HDMITX_PRIF 153
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#define CLKID_HDMITX_200M_MUX 154
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#define CLKID_HDMITX_200M_DIV 155
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#define CLKID_HDMITX_200M 156
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#define CLKID_HDMITX_AUD_MUX 157
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#define CLKID_HDMITX_AUD_DIV 158
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#define CLKID_HDMITX_AUD 159
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#define CLKID_PWM_A_MUX 160
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#define CLKID_PWM_A_DIV 161
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#define CLKID_PWM_A 162
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#define CLKID_PWM_B_MUX 163
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#define CLKID_PWM_B_DIV 164
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#define CLKID_PWM_B 165
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#define CLKID_PWM_C_MUX 166
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#define CLKID_PWM_C_DIV 167
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#define CLKID_PWM_C 168
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#define CLKID_PWM_D_MUX 169
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#define CLKID_PWM_D_DIV 170
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#define CLKID_PWM_D 171
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#define CLKID_PWM_E_MUX 172
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#define CLKID_PWM_E_DIV 173
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#define CLKID_PWM_E 174
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#define CLKID_PWM_F_MUX 175
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#define CLKID_PWM_F_DIV 176
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#define CLKID_PWM_F 177
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#define CLKID_PWM_G_MUX 178
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#define CLKID_PWM_G_DIV 179
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#define CLKID_PWM_G 180
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#define CLKID_PWM_H_MUX 181
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#define CLKID_PWM_H_DIV 182
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#define CLKID_PWM_H 183
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#define CLKID_PWM_I_MUX 184
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#define CLKID_PWM_I_DIV 185
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#define CLKID_PWM_I 186
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#define CLKID_PWM_J_MUX 187
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#define CLKID_PWM_J_DIV 188
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#define CLKID_PWM_J 189
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#define CLKID_SPICC0_MUX 190
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#define CLKID_SPICC0_DIV 191
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#define CLKID_SPICC0 192
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#define CLKID_SD_EMMC_A_MUX 193
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#define CLKID_SD_EMMC_A_DIV 194
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#define CLKID_SD_EMMC_A 195
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#define CLKID_SD_EMMC_B_MUX 196
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#define CLKID_SD_EMMC_B_DIV 197
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#define CLKID_SD_EMMC_B 198
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#define CLKID_SD_EMMC_C_MUX 199
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#define CLKID_SD_EMMC_C_DIV 200
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#define CLKID_SD_EMMC_C 201
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#define CLKID_VDIN_MEAS_MUX 202
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#define CLKID_VDIN_MEAS_DIV 203
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#define CLKID_VDIN_MEAS 204
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#define CLKID_VID_LOCK_MUX 205
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#define CLKID_VID_LOCK_DIV 206
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#define CLKID_VID_LOCK 207
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#define CLKID_ETH_CLK_RMII_MUX 208
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#define CLKID_ETH_CLK_RMII_DIV 209
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#define CLKID_ETH_CLK_RMII 210
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#define CLKID_ETH_CLK125M_DIV 211
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#define CLKID_ETH_CLK125M 212
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#define CLKID_TS_DIV 213
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#define CLKID_TS 214
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#define CLKID_AMFC_MUX 215
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#define CLKID_AMFC_DIV 216
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#define CLKID_AMFC 217
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#define CLKID_CSI2_ADAPT_MUX 218
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#define CLKID_CSI2_ADAPT_DIV 219
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#define CLKID_CSI2_ADAPT 220
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#define CLKID_MIPI_CSI_PHY_0_MUX 221
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#define CLKID_MIPI_CSI_PHY_0_DIV 222
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#define CLKID_MIPI_CSI_PHY_0 223
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#define CLKID_MIPI_CSI_PHY_1_MUX 224
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#define CLKID_MIPI_CSI_PHY_1_DIV 225
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#define CLKID_MIPI_CSI_PHY_1 226
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#define CLKID_MIPI_CSI_PHY 227
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#define CLKID_MIPI_DSI_MEAS_MUX 228
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#define CLKID_MIPI_DSI_MEAS_DIV 229
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#define CLKID_MIPI_DSI_MEAS 230
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#define CLKID_NNA_MUX 231
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#define CLKID_NNA_DIV 232
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#define CLKID_NNA 233
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#define CLKID_VC9000E_AXI_MUX 234
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#define CLKID_VC9000E_AXI_DIV 235
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#define CLKID_VC9000E_AXI 236
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#define CLKID_VC9000E_CORE_MUX 237
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#define CLKID_VC9000E_CORE_DIV 238
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#define CLKID_VC9000E_CORE 239
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#define CLKID_DSPA_0_MUX 240
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#define CLKID_DSPA_0_DIV 241
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#define CLKID_DSPA_0 242
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#define CLKID_DSPA_1_MUX 243
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#define CLKID_DSPA_1_DIV 244
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#define CLKID_DSPA_1 245
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#define CLKID_DSPA 246
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#define CLKID_PCIE_TL_MUX 247
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#define CLKID_PCIE_TL_DIV 248
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#define CLKID_PCIE_TL 249
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#define CLKID_USB_250M_MUX 250
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#define CLKID_USB_250M_DIV 251
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#define CLKID_USB_250M 252
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#define CLKID_GEN_MUX 253
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#define CLKID_GEN_DIV 254
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#define CLKID_GEN 255
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#define CLKID_SYS_AM_AXI 256
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#define CLKID_SYS_DOS 257
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#define CLKID_SYS_VC9000E 258
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#define CLKID_SYS_MIPI_DSI 259
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#define CLKID_SYS_ETH_PHY 260
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#define CLKID_SYS_AMFC 261
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#define CLKID_SYS_MALI 262
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#define CLKID_SYS_NNA 263
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#define CLKID_SYS_ETH_MAC 264
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#define CLKID_SYS_AOCPU 265
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#define CLKID_SYS_AUCPU 266
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#define CLKID_SYS_CEC 267
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#define CLKID_SYS_MIPI_DSI_PHY 268
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#define CLKID_SYS_SD_EMMC_A 269
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#define CLKID_SYS_SD_EMMC_B 270
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#define CLKID_SYS_SD_EMMC_C 271
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#define CLKID_SYS_SMARTCARD 272
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#define CLKID_SYS_ACODEC 273
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#define CLKID_SYS_MSR_CLK 274
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#define CLKID_SYS_IR_CTRL 275
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#define CLKID_SYS_AUDIO 276
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#define CLKID_SYS_ETH 277
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#define CLKID_SYS_UART_A 278
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#define CLKID_SYS_UART_B 279
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#define CLKID_SYS_UART_C 280
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#define CLKID_SYS_UART_D 281
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#define CLKID_SYS_UART_E 282
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#define CLKID_SYS_TS_CORE 283
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#define CLKID_SYS_TS_PLL 284
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#define CLKID_SYS_CSI_DIG_CLKIN 285
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#define CLKID_SYS_GE2D 286
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#define CLKID_SYS_SPICC0 287
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#define CLKID_SYS_USB3DRD 288
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#define CLKID_SYS_USB2DRD 289
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#define CLKID_SYS_PCIE_PHY 290
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#define CLKID_SYS_PCIE_MAC 291
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#define CLKID_SYS_I2C_M_A 292
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#define CLKID_SYS_I2C_M_B 293
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#define CLKID_SYS_I2C_M_C 294
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#define CLKID_SYS_I2C_M_D 295
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#define CLKID_SYS_I2C_M_E 296
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#define CLKID_SYS_I2C_M_F 297
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#define CLKID_SYS_HDMITX_APB 298
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#define CLKID_SYS_I2C_S_A 299
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#define CLKID_SYS_HDMI20_AES 300
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#define CLKID_SYS_MMC_APB 301
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#define CLKID_SYS_CSI2_HOST 302
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#define CLKID_SYS_CSI2_ADAPT 303
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#define CLKID_SYS_CPU_APB 304
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#define CLKID_SYS_DSPA 305
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#define CLKID_SYS_VPU_INTR 306
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#define CLKID_SYS_CSI2_PHY0 307
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#define CLKID_SYS_SAR_ADC 308
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#define CLKID_SYS_PWM_J 309
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#define CLKID_SYS_GIC 310
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#define CLKID_SYS_PWM_I 311
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#define CLKID_SYS_PWM_H 312
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#define CLKID_SYS_PWM_G 313
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#define CLKID_SYS_PWM_F 314
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#define CLKID_SYS_PWM_E 315
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#define CLKID_SYS_PWM_D 316
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#define CLKID_SYS_PWM_C 317
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#define CLKID_SYS_PWM_B 318
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#define CLKID_SYS_PWM_A 319
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#define CLKID_AXI_AO_NIC 320
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#define CLKID_AXI_SRAM 321
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#define CLKID_AXI_DEV0_MMC 322
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#define CLKID_AXI_CPU_SRAM 323
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#define NR_CLKS 324
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#endif /* __S6_CLKC_H */
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