59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#define PDID_T7_DSPA 0
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#define PDID_T7_DSPB 1
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#define PDID_T7_DOS_HCODEC 2
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#define PDID_T7_DOS_HEVC 3
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#define PDID_T7_DOS_VDEC 4
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#define PDID_T7_DOS_WAVE 5
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#define PDID_T7_VPU_HDMI 6
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#define PDID_T7_USB_COMB 7
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#define PDID_T7_PCIE 8
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#define PDID_T7_GE2D 9
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#define PDID_T7_SRAMA 10
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#define PDID_T7_SRAMB 11
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#define PDID_T7_HDMIRX 12
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#define PDID_T7_VI_CLK1 13
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#define PDID_T7_VI_CLK2 14
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#define PDID_T7_ETH 15
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#define PDID_T7_ISP 16
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#define PDID_T7_MIPI_ISP 17
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#define PDID_T7_GDC 18
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#define PDID_T7_CVE 18
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#define PDID_T7_DEWARP 19
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#define PDID_T7_SDIO_A 20
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#define PDID_T7_SDIO_B 21
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#define PDID_T7_EMMC 22
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#define PDID_T7_MALI_SC0 23
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#define PDID_T7_MALI_SC1 24
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#define PDID_T7_MALI_SC2 25
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#define PDID_T7_MALI_SC3 26
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#define PDID_T7_MALI_TOP 27
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#define PDID_T7_NNA_CORE0 28
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#define PDID_T7_NNA_CORE1 29
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#define PDID_T7_NNA_CORE2 30
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#define PDID_T7_NNA_CORE3 31
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#define PDID_T7_NNA_TOP 32
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#define PDID_T7_DDR0 33
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#define PDID_T7_DDR1 34
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#define PDID_T7_DMC0 35
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#define PDID_T7_DMC1 36
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#define PDID_T7_NOC 37
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#define PDID_T7_NIC2 38
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#define PDID_T7_NIC3 39
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#define PDID_T7_CCI 40
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#define PDID_T7_MIPI_DSI0 41
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#define PDID_T7_SPICC0 42
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#define PDID_T7_SPICC1 43
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#define PDID_T7_SPICC2 44
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#define PDID_T7_SPICC3 45
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#define PDID_T7_SPICC4 46
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#define PDID_T7_SPICC5 47
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#define PDID_T7_EDP0 48
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#define PDID_T7_EDP1 49
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#define PDID_T7_MIPI_DSI1 50
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#define PDID_T7_AUDIO 51
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