150 lines
4.3 KiB
C
150 lines
4.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_DOS_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_DOS_RESET_H
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/*
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* DOS_SW_RESET0 base is 0x3f00
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* [0] reserved
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* [1] Reset Dos top level registers, except sw_reset0/1/2
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* which is only reset by external reset_n.
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* [2] VDEC1 Reset assist, mdec's CBUS
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* [3] VDEC1 Reset mdec's VLD
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* [4] VDEC1 Reset mdec's VLD
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* [5] VDEC1 Reset mdec's VLD
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* [6] VDEC1 Reset mdec's IQIDCT
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* [7] VDEC1 Reset mdec's MC
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* [8] VDEC1 Reset mdec's DBLK
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* [9] VDEC1 Reset mdec's PIC_DC
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* [10] VDEC1 Reset mdec's Pscale
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* [11] VDEC1 Reset vcpu's MCPU
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* [12] VDEC1 Reset vcpu's CCPU
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* [13] VDEC1 Reset mmc_pre_arb
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* [31-14] RESERVED
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*/
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#define RESET0_VDEC1_RESERVED0 (0)
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#define RESET0_VDEC1_TOP_LEVEL (1)
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#define RESET0_VDEC1_MDEC_CBUS (2)
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#define RESET0_VDEC1_MDEC_VLD0 (3)
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#define RESET0_VDEC1_MDEC_VLD1 (4)
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#define RESET0_VDEC1_MDEC_VLD2 (5)
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#define RESET0_VDEC1_MDEC_IQIDCT (6)
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#define RESET0_VDEC1_MDEC_MC (7)
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#define RESET0_VDEC1_MDEC_DBLK (8)
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#define RESET0_VDEC1_MDEC_PIC_DC (9)
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#define RESET0_VDEC1_MDEC_PSCALE (10)
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#define RESET0_VDEC1_VCPU_MCPU (11)
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#define RESET0_VDEC1_VCPU_CCPU (12)
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#define RESET0_VDEC1_MMC_PRE_ARB (13)
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/*
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* DOS_SW_RESET1 base is 0x3f07
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* [0] Reserved
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* [1] Reserved
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* [2] HCODEC Reset assist, hdec's CBUS
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* [3] HCODEC Reset hdec's VLD
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* [4] HCODEC Reset hdec's VLD
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* [5] HCODEC Reset hdec's VLD
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* [6] HCODEC Reset hdec's IQIDCT
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* [7] HCODEC Reset hdec's MC
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* [8] HCODEC Reset hdec's DBLK
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* [9] HCODEC Reset hdec's PIC_DC
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* [10] HCODEC Reset hdec's Pscale
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* [11] HCODEC Reset vcpu's MCPU
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* [12] HCODEC Reset vcpu's CCPU
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* [13] HCODEC Reset mmc_pre_arb
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* [14] HCODEC Reserved
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* [15] HCODEC Reserved
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* [16] HCODEC Reset henc's VLC
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* [31-17] RESERVED
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*/
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#define RESET1_HCODEC_RESERVED0 (32)
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#define RESET1_HCODEC_RESERVED1 (33)
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#define RESET1_HCODEC_HDEC_CBUS (34)
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#define RESET1_HCODEC_HDEC_VLD0 (35)
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#define RESET1_HCODEC_HDEC_VLD1 (36)
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#define RESET1_HCODEC_HDEC_VLD2 (37)
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#define RESET1_HCODEC_HDEC_IQIDCT (38)
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#define RESET1_HCODEC_HDEC_MC (39)
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#define RESET1_HCODEC_HDEC_DBLK (40)
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#define RESET1_HCODEC_HDEC_PIC_DC (41)
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#define RESET1_HCODEC_HDEC_PSCALE (42)
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#define RESET1_HCODEC_VCPU_MCPU (43)
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#define RESET1_HCODEC_VCPU_CCPU (44)
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#define RESET1_HCODEC_MMC_PRE_ARB (45)
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#define RESET1_HCODEC_RESERVED2 (46)
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#define RESET1_HCODEC_RESERVED3 (47)
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#define RESET1_HCODEC_HENC_VLC (48)
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/*
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* DOS_SW_RESET2 base is 0x3f07
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* [0] Reserved
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* [1] Reserved
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* [2] VDEC2 Reset assist, mdec's CBUS
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* [3] VDEC2 Reset mdec's VLD
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* [4] VDEC2 Reset mdec's VLD
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* [5] VDEC2 Reset mdec's VLD
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* [6] VDEC2 Reset mdec's IQIDCT
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* [7] VDEC2 Reset mdec's MC
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* [8] VDEC2 Reset mdec's DBLK
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* [9] VDEC2 Reset mdec's PIC_DC
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* [10] VDEC2 Reset mdec's Pscale
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* [11] VDEC2 Reset vcpu's MCPU
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* [12] VDEC2 Reset vcpu's CCPU
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* [13] VDEC2 Reset mmc_pre_arb
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* [31-14]
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*/
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#define RESET2_VDEC2_RESERVED0 (64)
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#define RESET2_VDEC2_RESERVED1 (65)
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#define RESET2_VDEC2_MDEC_CBUS (66)
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#define RESET2_VDEC2_MDEC_VLD0 (67)
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#define RESET2_VDEC2_MDEC_VLD1 (68)
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#define RESET2_VDEC2_MDEC_VLD2 (69)
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#define RESET2_VDEC2_MDEC_IQIDCT (70)
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#define RESET2_VDEC2_MDEC_MC (71)
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#define RESET2_VDEC2_MDEC_DBLK (72)
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#define RESET2_VDEC2_MDEC_PIC_DC (73)
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#define RESET2_VDEC2_MDEC_PSCALE (74)
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#define RESET2_VDEC2_VCPU_MCPU (75)
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#define RESET2_VDEC2_VCPU_CCPU (76)
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#define RESET2_VDEC2_MMC_PRE_ARB (77)
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/* DOS_SW_RESET3 base is 0x3f34 */
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#define RESET3_RESERVED0 (96)
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/**97**/
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#define RESET3_BIT2 (98)
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#define RESET3_BIT3 (99)
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#define RESET3_BIT4 (100)
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#define RESET3_BIT5 (101)
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#define RESET3_BIT6 (102)
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#define RESET3_BIT7 (103)
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#define RESET3_BIT8 (104)
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#define RESET3_BIT9 (105)
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#define RESET3_BIT10 (106)
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#define RESET3_BIT11 (107)
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#define RESET3_BIT12 (108)
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#define RESET3_BIT13 (109)
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#define RESET3_BIT14 (110)
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#define RESET3_BIT15 (111)
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#define RESET3_BIT16 (112)
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#define RESET3_BIT17 (113)
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#define RESET3_BIT18 (114)
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#define RESET3_BIT19 (115)
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/**116~119**/
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#define RESET3_BIT24 (120)
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/* DOS_SW_RESET4 base is 0x3f37 */
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#define RESET4_RESERVED0 (128)
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/**127~135**/
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#define RESET4_BIT8 (136)
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#define RESET4_BIT9 (137)
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#define RESET4_BIT10 (138)
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#define RESET4_BIT11 (139)
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#define RESET4_RESERVED31 (159)
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#endif //_DT_BINDINGS_AMLOGIC_MESON_DOS_RESET_H
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