97 lines
2.1 KiB
C
97 lines
2.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_S1A_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_S1A_RESET_H
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/* RESET0 */
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/* 0-3 */
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#define RESET_USBCTRL 4
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#define RESET_U2DRDX0 5
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/* 6-7 */
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#define RESET_USBPHY20 8
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/* 9-14 */
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#define RESET_HDMI20_AES 15
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#define RESET_HDMITX_APB 16
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#define RESET_BRG_VCBUS_DEC 17
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#define RESET_VCBUS 18
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#define RESET_VID_PLL_DIV 19
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#define RESET_VIDEO6 20
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#define RESET_GE2D 21
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#define RESET_HDMITXPHY 22
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#define RESET_VID_LOCK 23
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#define RESET_VENCL 24
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#define RESET_VDAC 25
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#define RESET_VENCP 26
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#define RESET_VENCI 27
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#define RESET_RDMA 28
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#define RESET_HDMI_TX 29
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#define RESET_VIU 30
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#define RESET_VENC 31
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/* RESET1 */
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#define RESET_AUDIO 32
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/* 33-36 */
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#define RESET_DOS_APB 37
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#define RESET_DOS 38
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/* 39-47 */
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#define RESET_ETH 48
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/* 49-51 */
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#define RESET_DEMOD 52
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/* 53-63 */
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/* RESET2 */
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#define RESET_AM2AXI 64
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#define RESET_IR_CTRL 65
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/* 66 */
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#define RESET_TEMPSENSOR_PLL 67
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/* 68-71 */
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#define RESET_SMART_CARD 72
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/* 73-79 */
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#define RESET_MSR_CLK 80
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/* 81 */
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#define RESET_SARADC 82
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/* 83-87 */
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#define RESET_ACODEC 88
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#define RESET_CEC 89
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/* 90 */
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#define RESET_WATCHDOG 91
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/* 92-95 */
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/* RESET3 */
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/* 96 ~ 127 */
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/* RESET4 */
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/* 128-131 */
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#define RESET_PWM_AB 132
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#define RESET_PWM_CD 133
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/* 134-137 */
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#define RESET_UART_A 138
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#define RESET_UART_B 139
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/* 140-143 */
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#define RESET_I2C_M_A 145
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#define RESET_I2C_M_B 146
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#define RESET_I2C_M_C 147
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/* 148-153 */
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#define RESET_SDEMMC 154
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/* 155-159 */
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/* RESET5 */
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#define RESET_VDEC_PIPEL 160
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#define RESET_HEVCF_DMC_PIPEL 161
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#define RESET_GE2D_DMC_PIPEL 162
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#define RESET_VPU_DMC_PIPEL 163
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#define RESET_A53_DMC_PIPEL 164
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#define RESET_BRG_HEVCF_PIPEL 165
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/* 166-185 */
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#define RESET_BRG_NIC_EMMC 186
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#define RESET_BRG_NIC_VAPB 187
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#define RESET_BRG_NIC_DSU 188
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#define RESET_BRG_NIC_SYSCLK 189
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#define RESET_BRG_NIC_MAIN 190
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#define RESET_BRG_NIC_ALL 191
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#endif
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