125 lines
2.8 KiB
C
125 lines
2.8 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_T5W_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_T5W_RESET_H
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/* RESET0 */
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#define RESET_HIU 0
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/* 1 */
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#define RESET_DOS 2
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/* 3 */
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#define RESET_PL301_ADB400_PWRDNREQN 4
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#define RESET_VIU 5
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#define RESET_AFIFO 6
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#define RESET_VID_PLL_DIV 7
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#define RESET_DEMOD 8
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#define RESET_HDMIRX 9
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#define RESET_VENC 10
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#define RESET_ASSIST 11
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/* 12 */
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#define RESET_VCBUS 13
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/* 14-15 */
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#define RESET_GIC 16
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#define RESET_CAPB3_DECODE 17
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#define RESET_HDMIRX_APB 18
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/* 19 */
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#define RESET_MALI_CAPB3 20
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#define RESET_DOS_CAPB3 21
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#define RESET_CLK_RST 22
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#define RESET_CBUS_CAPB3 23
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#define RESET_AHB_CNTL 24
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#define RESET_AHB_DATA 25
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#define RESET_VCBUS_CLK81 26
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#define RESET_NIC_AXI 27
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/* 28-31 */
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/* RESET1 */
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/* 32-33 */
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#define RESET_USB 34
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#define RESET_DDR 35
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#define RESET_AML_TCON 36
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/* 37 */
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#define RESET_AHB_SRAM 38
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#define RESET_TVFE_TOP 39
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/* 40 */
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#define RESET_AVT_DMD 41
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#define RESET_ISA 42
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#define RESET_ETHERNET 43
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/* 44 */
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#define RESET_PWR_CTRL 45
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#define RESET_SD_EMMC_C 46
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#define RESET_SD_EMMC_B 47
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#define RESET_USB_PHY20 48
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#define RESET_USB_PHY21 49
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#define RESET_USB_PHY22 50
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/* 51-53 */
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#define RESET_HDMIRX20_AES 54
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#define RESET_HRX_EMP_AXI 55
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/* 56-60 */
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#define RESET_AUDIO_CODEC 61
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/* 62-63 */
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/* RESET2 */
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#define RESET_A55_ACE 64
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#define RESET_AUDIO 65
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/* 66 */
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#define RESET_ADEC_TOP_WRAP 67
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/* 68-69 */
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#define RESET_GE2D 70
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/* 71-57 */
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#define RESET_MALI 78
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/* 79-95 */
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/* RESET3 */
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/* 96-127 */
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/* RESET4 */
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/* 128-132 */
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#define RESET_RDMA 133
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#define RESET_VENC2 134
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#define RESET_VENC1 135
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/* 136 */
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#define RESET_VDAC 137
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/* 138-139 */
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#define RESET_VDI6 140
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#define RESET_VENC0 141
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#define RESET_I2C_M1 142
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#define RESET_I2C_M2 143
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/* 144-159 */
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/* RESET5 */
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/* 160-191 */
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/* RESET6 */
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#define RESET_GEN 192
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#define RESET_SPICC0 193
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#define RESET_SC 194
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/* 195 */
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#define RESET_I2C_M0 196
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#define RESET_TS_PLL 197
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#define RESET_SPICC1 198
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#define RESET_STREAM 199
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#define RESET_CIPLUS 200
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#define RESET_UART0 201
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#define RESET_UART1_2 202
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#define RESET_ASYNC0 203
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#define RESET_ASYNC1 204
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#define RESET_SPIFC0 205
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#define RESET_I2C_M3 206
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#define RESET_ASYNC3 207
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/* 208-223 */
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/* RESET7 */
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/* 224 */
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#define RESET_USB_DDR_1 225
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/* 226-227 */
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#define RESET_SPICC2 228
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#define RESET_DEVICE_MMC_ARB 229
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#define RESET_MALI_DMC_PIPL 230
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#define RESET_VPU_VID_LOCK 231
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/* 232 */
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#define RESET_DMC_VPU_PIPL 233
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/* 234-235 */
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#define RESET_VPU_BUS 236
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#define RESET_HEVCF_DM_PIPL 237
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#define RESET_DEVICE_MMC_ARB1 238
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/* 239-255 */
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#endif
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