159 lines
3.6 KiB
C
159 lines
3.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_T6D_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_T6D_RESET_H
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/* RESET0 */
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#define RESET_USB0_COMB 0
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#define RESET_USB0 1
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#define RESET_USB1_COMB 2
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#define RESET_USB1 3
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#define RESET_USB2_COMB 4
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#define RESET_USB2 5
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#define RESET_U2PHY20 6
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#define RESET_U2PHY21 7
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#define RESET_U2PHY22 8
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/* 9*/
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#define RESET_I2C_MON 10
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#define RESET_HDMI20_AES 11
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#define RESET_HDMIRX 12
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#define RESET_HDMIRX_APB 13
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#define RESET_I2C_MON_APB 14
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#define RESET_VPU_HDMI_AXI 15
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/* 16*/
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#define RESET_BRG_VCBUS_DEC 17
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#define RESET_VCBUS 18
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#define RESET_VID_PLL_DIV 19
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#define RESET_VDI6 20
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#define RESET_GE2D 21
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/* 22*/
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#define RESET_VID_LOCK 23
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#define RESET_VENC0 24
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#define RESET_VDAC 25
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#define RESET_VENC2 26
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#define RESET_VENC1 27
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#define RESET_RDMA 28
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/* 29*/
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#define RESET_VIU 30
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#define RESET_VENC 31
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/* RESET1 */
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#define RESET_AUDIO 32
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#define RESET_MALI_CAPB3 33
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#define RESET_MALI 34
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#define RESET_DDRPLL 35
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#define RESET_DMC 36
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#define RESET_DOS_CAPB3 37
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#define RESET_DOS 38
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/* 39-44*/
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#define RESET_AMFC_APB 45
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#define RESET_AMFC 46
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/* 47*/
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#define RESET_ETH 48
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/* 49-50*/
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#define RESET_COMBO_DPHY_CHAN0 51
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/* 52-56*/
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#define RESET_DEMOD 57
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/* 58-61*/
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#define RESET_DDRPHY0 62
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/* 63*/
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/* RESET2 */
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#define RESET_IOTM 64
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#define RESET_IR_CTRL 65
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/* 66-67*/
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#define RESET_ETH_AXI 68
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#define RESET_TCON 69
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/* 70-71*/
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#define RESET_SMART_CARD 72
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#define RESET_SPICC_0 73
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/* 74*/
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#define RESET_LED_CTRL 75
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/* 76-79*/
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#define RESET_MSR_CLK 80
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/* 81*/
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#define RESET_SAR_ADC 82
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/* 83-87*/
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#define RESET_ACODEC 88
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#define RESET_CEC 89
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/* 90*/
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#define RESET_WATCHDOG 91
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/* 92*/
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#define RESET_TVFE 93
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#define RESET_ATV_DMD 94
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#define RESET_ADEC 95
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/* RESET3 */
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/* 96-127*/
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/* RESET4 */
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#define RESET_PWM_A 128
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#define RESET_PWM_B 129
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#define RESET_PWM_C 130
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#define RESET_PWM_D 131
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#define RESET_PWM_E 132
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#define RESET_PWM_F 133
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#define RESET_PWM_G 134
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#define RESET_PWM_H 135
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/* 136-137*/
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#define RESET_UART_A 138
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#define RESET_UART_B 139
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#define RESET_UART_C 140
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/* 141-142*/
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#define RESET_CIPLUS 143
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#define RESET_I2C_S_A 144
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#define RESET_I2C_M_A 145
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#define RESET_I2C_M_B 146
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#define RESET_I2C_M_C 147
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#define RESET_I2C_M_D 148
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/* 149-153*/
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#define RESET_SD_EMMC_C 154
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/* 155*/
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#define RESET_TS_CPU 156
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#define RESET_BRG_PERIPH_SYNC 157
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#define RESET_TS_TOP 158
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/* 159*/
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/* RESET5 */
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/* 160-166*/
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#define RESET_BRG_SYS_APB_DEC 167
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/* 168-182*/
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#define RESET_BRG_NICSYS_HDMI 183
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#define RESET_BRG_NICSYS_IOTM 184
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#define RESET_BRG_NICSYS_AMFC 185
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#define RESET_BRG_NICSYS_EMMCC 186
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#define RESET_BRG_NICSYS_MAIN 187
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#define RESET_BRG_NICSYS_VAPB 188
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#define RESET_BRG_NICSYS_SYS 189
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#define RESET_BRG_NICSYS_CPU 190
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#define RESET_BRG_NICSYS_ALL 191
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/* RESET6 */
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/* 192*/
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#define RESET_BRG_HEVCF_DMC_PIPEL 193
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#define RESET_BRG_VPU_TOP_APB_PIPEL 194
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/* 195-198*/
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#define RESET_BRG_HDMIRXTONICSYS_PIPEL 199
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#define RESET_BRG_VPU1TODDR0_PIPEL 200
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#define RESET_BRG_VPU0TODDR0_PIPEL 201
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/* 202*/
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#define RESET_BRG_GE2DTODDR0_PIPEL 203
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/* 204*/
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#define RESET_BRG_MALITONICGPU_PIPEL 205
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/* 206-207*/
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#define RESET_BRG_ETH_HDMIRX_APB_PIPEL 208
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#define RESET_BRG_DOS_APB_PIPEL 209
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#define RESET_BRG_GE2D_APB_PIPEL 210
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#define RESET_BRG_ACODEC_APB_PIPEL 211
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/* 212-216*/
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#define RESET_BRG_USB_WRAPPER_APB_SYNC 217
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/* 218-221*/
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#define RESET_BRG_AM2AXI1 222
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/* 223*/
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#endif
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