227 lines
6.3 KiB
C
227 lines
6.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __AML_MMC_H__
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#define __AML_MMC_H__
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#include <mmc.h>
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#include "emmc_partitions.h"
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/*mmc.h*/
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#define NO_CARD_ERR -16
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#define UNUSABLE_ERR -17
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#define COMM_ERR -18
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#define TIMEOUT -19
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#define IN_PROGRESS -20
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#define SWITCH_ERR -21
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#define MESON_SD_EMMC_CALOUT 0x10
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#define MESON_SD_EMMC_ADJ_IDX_LOG 0x20
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#define MESON_SD_EMMC_CLKTEST_LOG 0x24
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#define CLKTEST_TIMES_MASK GENMASK(30, 0)
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#define CLKTEST_DONE BIT(31)
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#define MESON_SD_EMMC_CLKTEST_OUT 0x28
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#define MESON_SD_EMMC_EYETEST_LOG 0x2c
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#define EYETEST_TIMES_MASK GENMASK(30, 0)
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#define EYETEST_DONE BIT(31)
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#define MESON_SD_EMMC_EYETEST_OUT0 0x30
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#define MESON_SD_EMMC_EYETEST_OUT1 0x34
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#define MESON_SD_EMMC_INTF3 0x38
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#define CLKTEST_EXP_MASK GENMASK(4, 0)
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#define CLKTEST_ON_M BIT(5)
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#define EYETEST_EXP_MASK GENMASK(10, 6)
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#define EYETEST_ON BIT(11)
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#define DS_SHT_M_MASK GENMASK(17, 12)
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#define DS_SHT_EXP_MASK GENMASK(21, 18)
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#define SD_INTF3 BIT(22)
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#define EYETEST_SEL BIT(26)
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#define RESP_SEL BIT(27)
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#define CFG_RX_SEL BIT(26)
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#define CFG_RX_PN BIT(27)
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#define RESP_OLD BIT(28)
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#define RESP_PN BIT(29)
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#define RESP_DS BIT(30)
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#define MMC_CMD23
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#define MMC_CMD_SET_WRITE_PROTECT 28
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#define MMC_CMD_CLR_WRITE_PROT 29
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#define MMC_CMD_SEND_WRITE_PROT 30
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#define MMC_CMD_SEND_WRITE_PROT_TYPE 31
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#define MMC_SD_HS_TUNING 70
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#define EXT_CSD_CLASS_6_CTRL 59 /*R/W/E_P*/
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#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
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#define EXT_CSD_DEV_LIFETIME_EST_TYP_A 268 /* RO */
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#define EXT_CSD_DEV_LIFETIME_EST_TYP_B 269 /* RO */
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#define EXT_CSD_SUPPORTED_MODES 493 /* RO */
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#define EXT_CSD_FW_VERSION 254 /* RO, 261:254 */
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#define EXT_CSD_FW_CFG 169 /* R/W */
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#define EXT_CSD_MODE_CFG 30 /* R/W */
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#define EXT_CSD_FFU_STATUS 26 /* RO */
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#define US_PWR_WP_DIS_BIT 1<<3
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#define US_PERM_WP_DIS_BIT 1<<4
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#define WP_CLEAR_TYPE 0
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#define WP_POWER_ON_TYPE (1<<1)
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#define WP_TEMPORARY_TYPE 1
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#define WP_PERMANENT_TYPE ((1<<0)|(1<<1))
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#define WP_TYPE_MASK 3
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#define WP_ENABLE_MASK 7
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#define WP_TEMPORARY_EN_BIT 0
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#define WP_POWER_ON_EN_BIT (1<<0)
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#define WP_PERM_EN_BIT (1<<2)
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#define WP_GRP_SIZE_MASK 31
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#define MAX_TUNING_RETRY (4)
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#define CALI_BLK_CNT (1024)
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#define REFIX_BLK_CNT (100)
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#define TUNING_NUM_PER_POINT 40
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#define MMC_MAX_DESC_NUM 512
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#define MAX_RESPONSE_BYTES 4
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#define SD_EMMC_DESC_MAX_BLKS 511
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#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT (MMC_MAX_DESC_NUM * SD_EMMC_DESC_MAX_BLKS)
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#endif
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/*mmc.h*/
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/* bootloader operation */
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#define AML_BL_USER (0x1 << 0)
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#define AML_BL_BOOT0 (0x1 << 1)
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#define AML_BL_BOOT1 (0x1 << 2)
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#define AML_BL_BOOT (0x6)
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#define AML_BL_ALL (0x7)
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/* delay_cell=70ps, 1ns/delay_cell */
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#define DELAY_CELL_COUNTS 14
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/** For actually partitions with mask 8 store into bootinfo
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* name: partition name.
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* addr: sector addr of the partition
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* size: sector cont of the partition
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*/
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struct part_property
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{
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char name[8];
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uint32_t addr;
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uint32_t size;
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};
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#define PART_PROPERTY_SIZE sizeof(struct part_property)
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#define BOOTINFO_MAX_PARTITIONS (4)
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#define BOOTINFO_PARTITIONS_SIZE (PART_PROPERTY_SIZE * BOOTINFO_MAX_PARTITIONS)
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#define VPART_PROPERTY_SIZE sizeof(struct vpart_property)
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struct vpart_property {
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u32 addr;
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u32 size;
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};
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/*
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* sizeof(struct storage_emmc_boot_info) is strictly
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* smaller than or equal to one sector. we will bind
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* it in one sector with u-boot.bin together and
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* write into boot loader area.
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* @rsv_base_addr : the sector address of reserved area
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* @dtb : the sector address and size of dtb property
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* @ddr : the sector address and size of ddr property
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*/
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#define EMMC_BOOT_INFO_SIZE 512
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struct storage_emmc_boot_info {
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u32 version;
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u32 rsv_base_addr;
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struct vpart_property dtb;
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struct vpart_property ddr;
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struct part_property parts[BOOTINFO_MAX_PARTITIONS];
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uint8_t reserved[512 - 2 * VPART_PROPERTY_SIZE - BOOTINFO_PARTITIONS_SIZE - 12];
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u32 checksum;
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};
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struct boot_info_emmc {
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struct {
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/*
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* we provide a array of fixed clock providers in
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* ROM, such as GP0, FCLK_DIV2 source clock.
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*/
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unsigned char src_index;
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/* clock divider */
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unsigned char clk_div;
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unsigned char co_phase;
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/* rx adjust index, to adjust the sampling point */
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unsigned char rx_adj;
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unsigned char reserved0[4];
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} ehost_cfg;
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struct {
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/* emmc work mode */
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unsigned char speed_mode;
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unsigned char width_mode;
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/* reserved */
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unsigned char reserved1[2];
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} dev_cfg;
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};
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struct boot_info {
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#define BOOTINFO_MAGIC "BOOTINFO"
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#define BOOTINFO_INFO_VER 1
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char magic[8];
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unsigned char version; /* need to greater than or equal to 2 */
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unsigned char reserved[3]; /* reserve zero */
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/* 8 Bytes for only nand/spinand, eMMC skip */
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struct {
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/* from SPI NAND datasheet */
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unsigned int page_size;
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/* bit0~3: planes_per_lun bit4~7: plane_shift */
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unsigned char planes_per_lun;
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/* bit0~3: bus_width bit4~7: cache_plane_shift */
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/* 0, 1, 2, 3 buswidth, 2: 4 wires; 3: 8 wires */
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unsigned char bus_width;
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} dev_cfg0;
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/* the checksum of the whole boot_info struct */
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unsigned int checksum;
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struct boot_info_emmc emmc;
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};
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#define stamp_after(a,b) ((int)(b) - (int)(a) < 0)
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int amlmmc_write_bootloader(int dev, int map,
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unsigned int size, const void *src);
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int amlmmc_erase_bootloader(int dev, int map);
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/* interface on reserved area. */
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void mmc_write_cali_mattern(void *addr, struct aml_pattern *table);
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/* dtb operation */
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int dtb_write(void *addr);
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/* emmc key operation */
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int mmc_key_read(unsigned char *buf,
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unsigned int size, uint32_t *actual_length);
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int mmc_key_write(unsigned char *buf,
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unsigned int size, uint32_t *actual_length);
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int mmc_key_erase(void);
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/* partition operation */
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int renew_partition_tbl(unsigned char *buffer);
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int find_dev_num_by_partition_name (char const *name);
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#ifdef CONFIG_AML_PARTITION
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int emmc_update_mbr(unsigned char *buffer);
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#endif
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/*mmc ext_csd register operation*/
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int mmc_get_ext_csd(struct mmc *mmc, u8 *ext_csd);
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int mmc_set_ext_csd(struct mmc *mmc, u8 index, u8 value);
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/* flash write rsv */
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extern int store_ddr_save_fastboot_para(size_t size, void *buf);
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/* mmc caps quirks */
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int emmc_quirks(void);
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#endif /* __AML_MMC_H__ */
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