43 lines
2.0 KiB
Diff
43 lines
2.0 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Andy Yan <andy.yan@rock-chips.com>
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Date: Fri, 18 Jul 2025 14:41:13 +0800
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Subject: drm/rockchip: vop2: Add delay between poll registers
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According to the implementation of read_poll_timeout_atomic, if the
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delay time is 0, it will only use a simple loop based on timeout_us to
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decrement the count. Therefore, the final timeout time will differ
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significantly from the setted timteout time. So, here we set a specific
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delay time to ensure that the calculation of the timeout duration is accurate.
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Fixes: 3e89a8c68354 ("drm/rockchip: vop2: Fix the update of LAYER/PORT select registers when there are multi display output on rk3588/rk3568")
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Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
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---
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drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
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index 111111111111..222222222222 100644
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--- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
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+++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
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@@ -2104,7 +2104,7 @@ static void rk3568_vop2_wait_for_port_mux_done(struct vop2 *vop2)
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* Spin until the previous port_mux figuration is done.
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*/
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ret = readx_poll_timeout_atomic(rk3568_vop2_read_port_mux, vop2, port_mux_sel,
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- port_mux_sel == vop2->old_port_sel, 0, 50 * 1000);
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+ port_mux_sel == vop2->old_port_sel, 10, 50 * 1000);
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if (ret)
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DRM_DEV_ERROR(vop2->dev, "wait port_mux done timeout: 0x%x--0x%x\n",
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port_mux_sel, vop2->old_port_sel);
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@@ -2124,7 +2124,7 @@ static void rk3568_vop2_wait_for_layer_cfg_done(struct vop2 *vop2, u32 cfg)
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* Spin until the previous layer configuration is done.
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*/
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ret = readx_poll_timeout_atomic(rk3568_vop2_read_layer_cfg, vop2, atv_layer_cfg,
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- atv_layer_cfg == cfg, 0, 50 * 1000);
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+ atv_layer_cfg == cfg, 10, 50 * 1000);
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if (ret)
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DRM_DEV_ERROR(vop2->dev, "wait layer cfg done timeout: 0x%x--0x%x\n",
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atv_layer_cfg, cfg);
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--
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Armbian
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