Spreadtrum PCIe controller DT description

Spreadtrum PCIe host controller is based on Designware PCI core.
It shares common functions with PCIe Designware core driver and inherits
common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt.

Additional properties are described here:

Required properties:
 - compatible: Should be "sprd,pcie" for RC
	       Should be "sprd,pcie-ep" for EP
 - num-lanes as specified in ../designware-pcie.txt

HOST MODE
=========
 - reg: Should contain dbi, config registers location and length.
 - reg-names: Must include the following entries:
	      "dbi": controller configuration registers;
	      "config": PCIe configuration space registers.
 - #address-cells,
 - #size-cells,
 - #interrupt-cells,
 - device_type,
 - ranges,
 - interrupt-map-mask,
 - interrupt-map: as specified in ../designware-pcie.txt

 - sprd,pcie-startup-syscons:
	The global registers of pcie are used when pcie startup.
	Each group syscon has 6 cells as follows:
	- phandle of pcie syscon for used for pcie host controller
	- the type of syscon:
          0： set/clear, use regmap_update_bits() to operate these registers
          1: not set/clear, use regmap_read() and regmap_write() to operate
             these registers
	- the delay value: the delay time (unit: us) after the syscon is set
	- register: the register to be operated by the syscon
	- mask: the mask of the syscon register
	- value: the value to be set to the syscon register mask
 - sprd,pcie-shutdown-syscons:
	The global registers of pcie are used when pcie shutdown.
	This property is the same as sprd,pcie-startup-syscons.
 - sprd,pcie-resume-syscons:
	The global registers of pcie are used when pcie resume.
	This property is the same as sprd,pcie-startup-syscons.
 - sprd,pcie-suspend-syscons:
	The global registers of pcie are used when pcie suspend.
	This property is the same as sprd,pcie-startup-syscons.
 - sprd,pcie-perst-assert:
	The global registers of pcie are used when pcie assert PERST#.
	This property is the same as sprd,pcie-startup-syscons.
 - sprd,pcie-perst-deassert:
	The global registers of pcie are used when pcie deassert PERST#.
	This property is the same as sprd,pcie-startup-syscons.
 - sprd,pcie-aspml1p2-syscons:
	The global registers of pcie are used when pcie enter ASPM L1.2.
	This property is the same as sprd,pcie-startup-syscons.

- interrupts: as specified about #interrupt-cells.
- interrupt-names: must include "msi" entries.

DEVICE MODE
===========
 - reg : Three register ranges as listed in the reg-names property
 - reg-names: "dbi" for simple register. Single register accessed directly by
	      its address. Most of registers (including configuration space,
	      iATU and DMA) are of this type.
	      "dbi2" for shadow register. Another register exists at the same
	      address as a Simple register. For example the BAR Mask registers
	      have the same address as the BAR registers.
 - num-ib-windows: number of inbound address translation windows
 - num-ob-windows: number of outbound address translation windows

Example:
pcie0@2b100000 {
	compatible = "sprd,pcie", "snps,dw-pcie";
	reg = <0x0 0x2b100000 0x0 0x2000>,
	      <0x2 0x00000000 0x0 0x2000>;
	reg-names = "dbi", "config";
	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";
	ranges = <0x01000000 0x0 0x00000000 0x2 0x00002000 0x0 0x00010000
		  0x03000000 0x0 0x10000000 0x2 0x10000000 0x1 0xefffffff>;
	bus-range = <0  15>;
	num-lanes = <1>;
	num-vectors = <256>;
	num-viewport = <8>;
	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	sprd,pcie-startup-syscons =
		<&aon_apb_regs 0 0
			REG_AON_APB_RF_PCIE_SLV_ADDR_OFFSET
			MASK_AON_APB_RF_PCIE_SLV_ADDR_OFFSET
			0x1>,
		<&aon_apb_regs 0 0
			REG_AON_APB_RF_PCIE_SLV_ADDR_OFFSET
			MASK_AON_APB_RF_PCIE_MOD_SEL
			0x10000>,
		<&aon_apb_regs 0 0
			REG_AON_APB_RF_PHY_REF_CLK_EN
			MASK_AON_APB_RF_PCIE_PHY_REF_CLK_EN
			0x200>,
		<&pmu_apb_regs 0 0
			REG_PMU_APB_RF_PCIEPLL_H_REL_CFG
			MASK_PMU_APB_RF_PCIEPLL_H_FRC_OFF
			0x0>,
		<&ap_ipa_ahb_regs 0 0
			REG_AP_IPA_AHB_RF_AHB_EB
			MASK_AP_IPA_AHB_RF_PCIE_SEL
			0x0>,
		<&ap_ipa_ahb_regs 0 0
			REG_AP_IPA_AHB_RF_AHB_EB
			MASK_AP_IPA_AHB_RF_PCIE_AUX_EB
			0x40>,
		<&ap_ipa_ahb_regs 0 0
			REG_AP_IPA_AHB_RF_AHB_EB
			MASK_AP_IPA_AHB_RF_PCIE_EB
			0x20>,
		<&pmu_apb_regs 0 0
			REG_PMU_APB_RF_PCIE_SLP_CFG
			MASK_PMU_APB_RF_PCIE_CLKREQ_PLL_GATE_MASK
			0x0>;

	sprd,pcie-shutdown-syscons =
		<&ap_ipa_ahb_regs 0 0
			REG_AP_IPA_AHB_RF_AHB_EB
			MASK_AP_IPA_AHB_RF_PCIE_EB
			0x0>;

	sprd,pcie-resume-syscons =
		<&ap_ipa_ahb_regs 0 0
			REG_AP_IPA_AHB_RF_AHB_EB
			MASK_AP_IPA_AHB_RF_PCIE_EB
			0x20>;

	sprd,pcie-suspend-syscons =
		<&ap_ipa_ahb_regs 0 0
			REG_AP_IPA_AHB_RF_AHB_EB
			MASK_AP_IPA_AHB_RF_PCIE_EB
			0x0>;

	sprd,pcie-aspml1p2-syscons =
		<&anlg_pcie20_phy_regs 1 0
			REG_PIPE_CFGA_ANA_CFG13
			MASK_PIPE_CFGA_ANA_CFG13_CFG_FORCE_REFCLK_EN
			(0x1 << 23)>;

	sprd,pcie-perst-deassert =
		<&pmu_apb_regs 0 200
			REG_PMU_APB_RF_PCIE_SLP_CFG
			MASK_PMU_APB_RF_REG_PERST_N_ASSERT
			0x0>;

	sprd,pcie-perst-assert =
		<&pmu_apb_regs 0 200
			REG_PMU_APB_RF_PCIE_SLP_CFG
			MASK_PMU_APB_RF_REG_PERST_N_ASSERT
			0x10>;
};

pcie1@2b100000 {
	compatible = "sprd,pcie-ep", "snps,dw-pcie";
	reg = <0x0 0x2b100000 0x0 0x2000>,
	      <0x0 0x2b108000 0x0 0x2000>,
	      <0x2 0x00000000 0x2 0x00000000>;
	reg-names = "dbi", "dbi2","addr_space";
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	num-lanes = <1>;
	num-ib-windows = <6>;
	num-ob-windows = <8>;
};
