71 lines
2.0 KiB
C
71 lines
2.0 KiB
C
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/* * Copyright (C) 2012 Spreadtrum Communications Inc.
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*/
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#ifndef __ADI_H__
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#define __ADI_H__
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#include <sci_types.h>
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#if defined(CONFIG_FPGA)
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static inline void sci_adi_init(void) {}
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static inline int sci_adi_read(u32 reg) { return 0; }
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static inline int sci_adi_write_fast(u32 reg, u16 val) { return 0; }
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static inline int sci_adi_write(u32 reg, u16 or_val, u16 clear_msk) { return 0; }
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static inline int sci_adi_raw_write(u32 reg, u16 val) { return 0; }
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static inline int sci_adi_set(u32 reg, u16 bits) { return 0; }
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static inline int sci_adi_clr(u32 reg, u16 bits) { return 0; }
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#else
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void sci_adi_init(void);
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int sci_adi_read(u32 reg);
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/*
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* WARN: the arguments (reg, value) is different from
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* the general __raw_writel(value, reg)
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* For sci_adi_write_fast: if set sync 1, then this function will
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* return until the val have reached hardware.otherwise, just
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* async write(is maybe in software buffer)
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*/
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int sci_adi_write_fast(u32 reg, u16 val);
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int sci_adi_write(u32 reg, u16 or_val, u16 clear_msk);
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static inline int sci_adi_raw_write(u32 reg, u16 val)
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{
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return sci_adi_write_fast(reg, val);
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}
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static inline int sci_adi_set(u32 reg, u16 bits)
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{
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return sci_adi_write(reg, bits, 0);
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}
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static inline int sci_adi_clr(u32 reg, u16 bits)
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{
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return sci_adi_write(reg, 0, bits);
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}
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#endif
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///for analog die register operation
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#define ANA_REG_OR(reg_addr, value) \
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do{\
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sci_adi_write(reg_addr, (unsigned short)(value), 0); \
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}while(0)
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#define ANA_REG_MSK_OR(reg_addr, value, msk) \
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do{\
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sci_adi_write(reg_addr, (unsigned short)((value)&(msk)), msk); \
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}while(0)
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#define ANA_REG_AND(reg_addr, value) \
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do{\
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sci_adi_write(reg_addr, 0, (unsigned short)(~(value))); \
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}while(0)
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#define ANA_REG_BIC(reg_addr, value) \
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do{\
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sci_adi_write(reg_addr, 0, (unsigned short)(value)); \
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}while(0)
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#define ANA_REG_SET(reg_addr, value) sci_adi_raw_write(reg_addr, (unsigned short)(value))
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#define ANA_REG_GET(reg_addr) sci_adi_read(reg_addr)
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#endif
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