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This commit is contained in:
jf
2026-11-04 06:31:20 +00:00
parent 5bffc3c666
commit 3b2d5c3a0a
95 changed files with 0 additions and 32077 deletions
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HDMI/LT8912B-HDMI-extra.patch
-301
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@@ -1,301 +0,0 @@
diff --git a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi
--- a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi
+++ b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi
@@ -42,9 +42,9 @@
hfront-porch = <88>;
hsync-len = <44>;
hback-porch = <148>;
- vfront-porch = <56>;
- vsync-len = <6>;
- vback-porch = <60>;
+ vfront-porch = <4>;
+ vsync-len = <5>;
+ vback-porch = <36>;
};
};
};
diff --git a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi
--- a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi
+++ b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi
@@ -42,9 +42,9 @@
hfront-porch = <88>;
hsync-len = <44>;
hback-porch = <148>;
- vfront-porch = <56>;
- vsync-len = <6>;
- vback-porch = <60>;
+ vfront-porch = <4>;
+ vsync-len = <5>;
+ vback-porch = <36>;
};
};
};
diff --git a/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi
--- a/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi
+++ b/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi
@@ -47,9 +47,9 @@
hfront-porch = <88>;
hsync-len = <44>;
hback-porch = <148>;
- vfront-porch = <56>;
+ vfront-porch = <38>;
vsync-len = <6>;
- vback-porch = <60>;
+ vback-porch = <40>;
};
};
};
diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c
--- a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c
+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c
@@ -9,6 +9,7 @@
u8 Hsync_L, Hsync_H, Vsync_L, Vsync_H;
u8 mipi_det_fail_count = 0;
u8 mipi_relock_count = 0;
+bool mipi_video_ready = 0;
bool suspend_on = 0;
@@ -24,11 +25,13 @@
struct video_timing video_1280x720_60Hz = {110, 40, 220, 1280, 1650, 5, 5, 20, 720, 750, 1,1, 4, AR_16_9, 74250};
struct video_timing video_1280x800_60Hz = {28, 32, 100, 1280, 1440, 2, 6, 15, 800, 823, 0,0, 0, AR_16_9, 71000};
//struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 4, 5, 36, 1080, 1125, 1,1,16, AR_16_9, 148500};
-struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 56, 6, 60, 1080, 1202, 1,1, 0, AR_16_9, 153600};
+struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 4, 5, 36, 1080, 1125, 1,1,16, AR_16_9, 153600};
struct video_timing *video;
-void DDSConfig(void);
+void DDSConfig(struct video_timing *video_format);
+void HdmiOutput(bool on);
+u8 LT8912_Get_HPD(void);
void DigitalClockEn(void)
{
@@ -72,25 +75,66 @@
{
u8 VIC = video_format->vic;
u8 AR = video_format->aspact_ratio;
- u8 pb0,pb2,pb4,Sync_Polarity;
+ u8 pb0,pb1,pb2,pb4,Sync_Polarity;
+ u8 pb6, pb7, pb8, pb9, pb10, pb11, pb12, pb13;
+ u8 checksum;
I2CADR = 0x94;
HDMI_WriteI2C_Byte(0x3c,0x41); //enable null package
Sync_Polarity = (video_format->h_polarity*0x02) + (video_format->v_polarity*0x01);
- pb2 = (AR<<4) + 0x08;
- pb4 = VIC;
- pb0 = (((pb2 + pb4) <= 0x5f)?(0x5f - pb2 - pb4):(0x15f - pb2 - pb4));
+ if (video_format->hact == 1920 && video_format->vact == 1080) {
+ Sync_Polarity = 0x03;
+ pb1 = 0x1c;
+ pb2 = 0xa8;
+ pb4 = 0x10;
+ pb6 = 0x29;
+ pb7 = 0x00;
+ pb8 = 0x61;
+ pb9 = 0x04;
+ pb10 = 0xc0;
+ pb11 = 0x00;
+ pb12 = 0x40;
+ pb13 = 0x08;
+ } else {
+ pb1 = 0x10;
+ pb2 = (AR<<4) + 0x08;
+ pb4 = VIC;
+ pb6 = 0x00;
+ pb7 = 0x00;
+ pb8 = 0x00;
+ pb9 = 0x00;
+ pb10 = 0x00;
+ pb11 = 0x00;
+ pb12 = 0x00;
+ pb13 = 0x00;
+ }
+
+ checksum = 0x82 + 0x02 + 0x0d + pb1 + pb2 + pb4;
+ checksum += pb6 + pb7 + pb8 + pb9;
+ checksum += pb10 + pb11 + pb12 + pb13;
+ pb0 = 0x100 - checksum;
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0xab,Sync_Polarity); //sync polarity
I2CADR = 0x94;
HDMI_WriteI2C_Byte(0x43,pb0); //PB0:check sum
- HDMI_WriteI2C_Byte(0x44,0x10); //PB1:RGB888
+ HDMI_WriteI2C_Byte(0x44,pb1); //PB1
HDMI_WriteI2C_Byte(0x45,pb2); //PB2
HDMI_WriteI2C_Byte(0x46,0x00); //PB3
HDMI_WriteI2C_Byte(0x47,pb4); //PB4:vic
+ HDMI_WriteI2C_Byte(0x49,pb6);
+ HDMI_WriteI2C_Byte(0x4a,pb7);
+ HDMI_WriteI2C_Byte(0x4b,pb8);
+ HDMI_WriteI2C_Byte(0x4c,pb9);
+ HDMI_WriteI2C_Byte(0x4d,pb10);
+ HDMI_WriteI2C_Byte(0x4e,pb11);
+ HDMI_WriteI2C_Byte(0x4f,pb12);
+ HDMI_WriteI2C_Byte(0x50,pb13);
+ printk("%s AviInfoframe %ux%u pb0=0x%02x pb1=0x%02x pb2=0x%02x vic=%u sync=0x%02x\n",
+ LOG_FLAG, video_format->hact, video_format->vact,
+ pb0, pb1, pb2, pb4, Sync_Polarity);
}
void MipiAnalog(void)
@@ -128,7 +172,13 @@
void MIPI_Video_Setup(struct video_timing *video_format)
{
+ u8 settle = 0x10;
+
+ if (video_format->vact == 1080)
+ settle = 0x0a;
+
I2CADR = 0x92;
+ HDMI_WriteI2C_Byte(0x11, settle); // settle
HDMI_WriteI2C_Byte(0x18,(u8)(video_format->hs%256)); // hwidth
HDMI_WriteI2C_Byte(0x19,(u8)(video_format->vs%256)); // vwidth
HDMI_WriteI2C_Byte(0x1c,(u8)(video_format->hact%256)); // H_active[7:0]
@@ -146,6 +196,10 @@
HDMI_WriteI2C_Byte(0x3d,(u8)(video_format->hbp/256)); // HBP[15:8]
HDMI_WriteI2C_Byte(0x3e,(u8)(video_format->hfp%256)); // HFP[7:0]
HDMI_WriteI2C_Byte(0x3f,(u8)(video_format->hfp/256)); // HFP[15:8]
+ printk("%s MIPI_Video_Setup %ux%u total=%ux%u pclk=%u settle=0x%02x vic=%u\n",
+ LOG_FLAG, video_format->hact, video_format->vact,
+ video_format->htotal, video_format->vtotal,
+ video_format->pclk_khz, settle, video_format->vic);
video = video_format;
}
@@ -168,19 +222,26 @@
MipiAnalog();
MipiBasicSet();
- DDSConfig();
+ DDSConfig(&video_1920x1080_60Hz);
MIPI_Video_Setup(&video_1920x1080_60Hz);
AviInfoframe(&video_1920x1080_60Hz);
MIPIRxLogicRes();
}
-void DDSConfig(void)
+void DDSConfig(struct video_timing *video_format)
{
+ u32 dds_word;
+
+ dds_word = (video_format->pclk_khz / 1000) * 0x16C16;
+ dds_word += ((video_format->pclk_khz % 1000) * 0x16C16 + 500) / 1000;
+
I2CADR = 0x92;
- HDMI_WriteI2C_Byte(0x4e,0x93);//strm_sw_freq_word[ 7: 0]
- HDMI_WriteI2C_Byte(0x4f,0x3E);//strm_sw_freq_word[15: 8]
- HDMI_WriteI2C_Byte(0x50,0x29);//strm_sw_freq_word[23:16]
+ HDMI_WriteI2C_Byte(0x4e,(u8)(dds_word & 0xff));//strm_sw_freq_word[ 7: 0]
+ HDMI_WriteI2C_Byte(0x4f,(u8)((dds_word >> 8) & 0xff));//strm_sw_freq_word[15: 8]
+ HDMI_WriteI2C_Byte(0x50,(u8)((dds_word >> 16) & 0xff));//strm_sw_freq_word[23:16]
HDMI_WriteI2C_Byte(0x51,0x80);//[0]=strm_sw_freq_word[24]
+ printk("%s DDSConfig pclk=%u kHz word=0x%06x\n",
+ LOG_FLAG, video_format->pclk_khz, dds_word);
HDMI_WriteI2C_Byte(0x1e,0x4f);
HDMI_WriteI2C_Byte(0x1f,0x5e);//full_value 464
HDMI_WriteI2C_Byte(0x20,0x01);
@@ -231,8 +292,15 @@
I2CADR = 0x94;
HDMI_WriteI2C_Byte(0x06,0x08);
HDMI_WriteI2C_Byte(0x07,0xF0);
- HDMI_WriteI2C_Byte(0x34,0xD2);//0xE2:32FS; 0xD2:64FS
+ HDMI_WriteI2C_Byte(0x09,0x00);
+ HDMI_WriteI2C_Byte(0x34,0xE2);//0xE2:32FS; 0xD2:64FS
+ HDMI_WriteI2C_Byte(0x35,0x00);//N = 6144(0x1800)
+ HDMI_WriteI2C_Byte(0x36,0x18);
+ HDMI_WriteI2C_Byte(0x37,0x00);
+ HDMI_WriteI2C_Byte(0x3c,0x41);
+ HDMI_WriteI2C_Byte(0x3e,0x0a);
HDMI_WriteI2C_Byte(0x0F,0x2B);
+ printk("%s HDMI audio packet setup: 48k N=0x1800\n", LOG_FLAG);
}
void AudioSpdifEn(void)
@@ -500,11 +568,8 @@
if (mipi_det_fail_count < 0xff)
mipi_det_fail_count++;
- if (mipi_det_fail_count >= 10 && mipi_relock_count < 5) {
- mipi_relock_count++;
- mipi_det_fail_count = 0;
- LT8912B_MIPI_Relock();
- }
+ if (mipi_det_fail_count == 10)
+ printk("%s MIPI input invalid, skip auto relock\n", LOG_FLAG);
} else {
mipi_det_fail_count = 0;
}
@@ -525,7 +590,7 @@
video_valid = true;
printk("%s videoformat = VESA_1280x800_60\n",LOG_FLAG);
}
- else if(Vsync_H == 0x04 && Vsync_L <= 0xb6&&Vsync_L >= 0x63)//0x4b2
+ else if(Vsync_H == 0x04 && Vsync_L <= 0x67&&Vsync_L >= 0x63)//0x465
{
video = &video_1920x1080_60Hz;
video_valid = true;
@@ -544,9 +609,21 @@
if (video_valid) {
mipi_det_fail_count = 0;
mipi_relock_count = 0;
+ mipi_video_ready = 1;
+ DDSConfig(video);
MIPI_Video_Setup(video);
AviInfoframe(video);
MIPIRxLogicRes();
+
+ #ifdef _hdmi_output
+ if (LT8912_Get_HPD() && !Tx_HPD) {
+ msleep(50);
+ HdmiOutput(1);
+ Tx_HPD = 1;
+ printk("%s HDMI output enabled after valid MIPI video\n",
+ LOG_FLAG);
+ }
+ #endif
}
}
@@ -716,7 +793,7 @@
HDMIPllAnalog();
MipiAnalog();
MipiBasicSet();
- DDSConfig();
+ DDSConfig(&video_1920x1080_60Hz);
MIPI_Video_Setup(&video_1920x1080_60Hz);
MIPI_Input_det();
AudioIIsEn();
@@ -726,7 +803,7 @@
lt8912_check_dds(); // can be removed when debug stage.
#endif
- #ifdef _lvds_bypass
+ #ifdef _lvds_output
lvds_output_cfg();
LvdsOutput(1);
#endif
@@ -737,7 +814,7 @@
/////////////////////////////////////////////////////////////
#ifdef _hdmi_output
- if(LT8912_Get_HPD())
+ if(LT8912_Get_HPD() && mipi_video_ready)
{
if(!Tx_HPD)
{
@@ -769,7 +846,7 @@
#ifdef _hdmi_output
if(LT8912_Get_HPD())
{
- if(!Tx_HPD)
+ if(mipi_video_ready && !Tx_HPD)
{
LT8912B_Suspend(0);
HdmiOutput(1);
HDMI/LT8912B-HDMI.patch
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HDMI/LT8912B/LT8912B Ap note.pdf
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HDMI/LT8912B/LT8912B PCB layout 建议.txt
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@@ -1,5 +0,0 @@
LT8912B PCB layout建议:
1、差分（MIPI、HDMI、LVDS）周围40mil的范围不要有地或信号线、敷铜，控制好100欧姆阻抗匹配
2、差分信号对（MIPI、HDMI、LVDS）之间控制三倍线宽间距，伴随GND离差分3倍线宽间距，并且在GND线上多打些孔，若空间不够可以不加伴随
3、晶振布线尽量短，可以将反馈电阻放在晶振与IC之间
HDMI/LT8912B/LT8912B 差分走线参考.png
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HDMI/LT8912B/LT8912B 输入MIPI 信号的要求.pdf
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HDMI/LT8912B/LT8912B_Datasheet_R1.2(1).pdf
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HDMI/LT8912B/LT8912B_Linux_Driver_v1.0.zip
LFS
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HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/Kconfig
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@@ -1,9 +0,0 @@
config LT8912B
tristate "LT8912B Driver"
default m
help
Control LT8912B Chip
Select m:build as a separate module;
Select y:Build into the kernel
Select n:Not build
HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/Makefile
-5
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@@ -1,5 +0,0 @@
lt8912b-y := src/LontiumDrv.o src/LT8912B_Main.o src/LT8912B.o src/OcmI2cMaster.o \
obj-$(CONFIG_LT8912B) += lt8912b.o
HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/doc/LT8912B Linux Driver Introduction document (English).docx
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HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/doc/Makefile
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@@ -1,27 +0,0 @@
# 1. Be sure to change KERN_DIR when using a different board kernel
# 2. The kernel in KERN_DIR must be configured and compiled in advance, and the following environment variables must be set in order to compile the kernel:
# 2.1 ARCH, For example: export ARCH=arm64
# 2.2 CROSS_COMPILE, For example: export CROSS_COMPILE=aarch64-linux-gnu-
# 2.3 PATH, For example: export PATH=$PATH:/home/book/100ask_roc-rk3399-pc/ToolChain-6.3.1/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin
# Note: The above three environment variables may not be the same for different development boards and different compilers.
# For details, see the Advanced user manual of each development board
KERN_DIR = /home/ysy/workspace/imx6ull_pro/Imx6ull_source_code/Linux-4.9.88
all:
make -C $(KERN_DIR) M=`pwd` modules
clean:
make -C $(KERN_DIR) M=`pwd` modules clean
rm -rf modules.order
lt8912b-y := src/LontiumDrv.o src/LT8912B_Main.o src/LT8912B.o src/OcmI2cMaster.o \
obj-m += lt8912b.o
HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/LT8912B.h
-72
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@@ -1,72 +0,0 @@
#ifndef _LT8912B_H
#define _LT8912B_H
#define _1080P_60Hz
/* output mode */
#define _hdmi_output
#define _lvds_bypass
//#define _pattern_test_
#define _lane_swap_ //mipi input 3210
//#define _pn_swap_ //mipi input lane pn swap
#define dds_debug
/* lanes */
#define lane_cnt 0 /*0: 4lane; 1: 1lane; 2: 2lane; 3: 3lane;*/
typedef struct video_timing{
u16 hfp;
u16 hs;
u16 hbp;
u16 hact;
u16 htotal;
u16 vfp;
u16 vs;
u16 vbp;
u16 vact;
u16 vtotal;
bool h_polarity;
bool v_polarity;
u16 vic;
u8 aspact_ratio; // 0=no data, 1=4:3, 2=16:9, 3=no data.
u32 pclk_khz;
}_video_timing;
typedef enum
{
I2S_2CH,
I2S_8CH,
SPDIF
}_Audio_Input_Mode;
#define Audio_Input_Mode I2S_2CH
#define AR_ND 0x00
#define AR_4_3 0x01
#define AR_16_9 0x02
typedef struct panel_parameter
{
u16 hfp;
u16 hs;
u16 hbp;
u16 hact;
u16 htotal;
u16 vfp;
u16 vs;
u16 vbp;
u16 vact;
u16 vtotal;
u32 pclk_khz;
}_panel_parameter;
extern void LT8912B_Config(void);
extern u8 Tx_HPD;
#endif
HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/LT8912B_Main.h
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@@ -1,5 +0,0 @@
#ifndef _LT8912B_MAIN_H_
#define _LT8912B_MAIN_H_
extern int LT8912B_Main(void *data);
#endif
HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/LontiumDrv.h
-39
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@@ -1,39 +0,0 @@
#ifndef _LONTIUMDRV_H_
#define _LONTIUMDRV_H_
struct _lt8912b{
struct device *dev;
struct mutex ocm_lock;
struct gpio_desc *reset_gpio;
struct gpio_desc *power_gpio;
struct i2c_client *i2c_stu;
struct regmap *chip_regmap;
struct addr_1{
struct i2c_client *i2c_stu;
struct regmap *regmap;
}*addr_1;
struct addr_2{
struct i2c_client *i2c_stu;
struct regmap *regmap;
}*addr_2;
};
typedef struct
{
u8 address;
u8 value;
} Chip_Control_Args;
extern struct _lt8912b *lt8912b;
extern volatile bool Main_Loop;
extern const char *LOG_FLAG;
extern u8 addr_1;
extern u8 addr_2;
#endif
HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/OcmI2cMaster.h
-10
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@@ -1,10 +0,0 @@
#ifndef _OCMI2CMASTER_H_
#define _OCMI2CMASTER_H_
extern int HDMI_WriteI2C_Byte(u8 addr,u8 data);
extern int HDMI_ReadI2C_Byte(u8 addr);
extern u8 I2CADR;
#endif
HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/include.h
-41
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@@ -1,41 +0,0 @@
#ifndef _INCLUDE_H_
#define _INCLUDE_H_
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/gpio.h>
#include <linux/kobject.h>
#include <linux/sysfs.h>
#include <linux/printk.h>
#include <linux/miscdevice.h>
#include <linux/kernel.h>
#include <linux/major.h>
#include <linux/mutex.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/stat.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/tty.h>
#include <linux/kmod.h>
#include <linux/gfp.h>
#include <linux/module.h>
#include <linux/kthread.h>
#include <linux/atomic.h>
#include "LontiumDrv.h"
#include "LT8912B_Main.h"
#include "LT8912B.h"
#include "OcmI2cMaster.h"
#endif
HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/LT8912B.c
-749
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@@ -1,749 +0,0 @@
#include "../include/include.h"
u8 Hsync_H_last = 0x00;
u8 Hsync_L_last = 0x00;
u8 Vsync_H_last = 0x00;
u8 Vsync_L_last = 0x00;
u8 Hsync_L, Hsync_H, Vsync_L, Vsync_H;
bool suspend_on = 0;
u8 Tx_HPD=0;
// hfp, hs, hbp, hact, htotal, vfp, vs, vbp, vact, vtotal, hfp, hs, hbp, hact, htotal, vfp, vs, vbp, vact, vtotal, h_polary, v_polary, vic, aspact_ratio, pclk_khz
struct video_timing video_640x480_60Hz = {16, 96, 48, 640, 800, 10, 2, 33, 480, 525, 0,0, 1, AR_4_3, 25000};
struct video_timing video_720x480_60Hz = {16, 62, 60, 720, 858, 9, 6, 30, 480, 525, 0,0, 2, AR_4_3, 27000};
struct video_timing video_720x576_50Hz = {12, 64, 68, 720, 864, 5, 5, 39, 576, 625, 0,0,17, AR_4_3, 27000};
struct video_timing video_800x600_60Hz = {48, 128, 88, 800, 1056, 1, 4, 23, 600, 628, 1,1, 0, AR_16_9, 40000};
struct video_timing video_1024x768_60Hz = {24, 136, 160, 1024, 1344, 3, 6, 29, 768, 806, 0,0, 0, AR_16_9, 65000};
struct video_timing video_1280x720_60Hz = {110, 40, 220, 1280, 1650, 5, 5, 20, 720, 750, 1,1, 4, AR_16_9, 74250};
struct video_timing video_1280x800_60Hz = {28, 32, 100, 1280, 1440, 2, 6, 15, 800, 823, 0,0, 0, AR_16_9, 71000};
struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 4, 5, 36, 1080, 1125, 1,1,16, AR_16_9, 148500};
struct video_timing *video;
void DigitalClockEn(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x02,0xf7);
HDMI_WriteI2C_Byte(0x08,0xff);
HDMI_WriteI2C_Byte(0x09,0xff);
HDMI_WriteI2C_Byte(0x0a,0xff);
HDMI_WriteI2C_Byte(0x0b,0x7c);
HDMI_WriteI2C_Byte(0x0c,0xff);
}
void TxAnalog(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x31,0xE1);
HDMI_WriteI2C_Byte(0x32,0xE1);
HDMI_WriteI2C_Byte(0x33,0x0c); //en/disable hdmid output
HDMI_WriteI2C_Byte(0x37,0x00);
HDMI_WriteI2C_Byte(0x38,0x22);
HDMI_WriteI2C_Byte(0x60,0x82);
}
void CbusAnalog(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x39,0x45);
HDMI_WriteI2C_Byte(0x3a,0x00); //20180719
HDMI_WriteI2C_Byte(0x3b,0x00);
}
void HDMIPllAnalog(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x44,0x31);
HDMI_WriteI2C_Byte(0x55,0x44);
HDMI_WriteI2C_Byte(0x57,0x01);
HDMI_WriteI2C_Byte(0x5a,0x02);
}
void AviInfoframe(struct video_timing *video_format)
{
u8 VIC = video_format->vic;
u8 AR = video_format->aspact_ratio;
u8 pb0,pb2,pb4,Sync_Polarity;
I2CADR = 0x94;
HDMI_WriteI2C_Byte(0x3c,0x41); //enable null package
Sync_Polarity = (video_format->h_polarity*0x02) + (video_format->v_polarity*0x01);
pb2 = (AR<<4) + 0x08;
pb4 = VIC;
pb0 = (((pb2 + pb4) <= 0x5f)?(0x5f - pb2 - pb4):(0x15f - pb2 - pb4));
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0xab,Sync_Polarity); //sync polarity
I2CADR = 0x94;
HDMI_WriteI2C_Byte(0x43,pb0); //PB0:check sum
HDMI_WriteI2C_Byte(0x44,0x10); //PB1:RGB888
HDMI_WriteI2C_Byte(0x45,pb2); //PB2
HDMI_WriteI2C_Byte(0x46,0x00); //PB3
HDMI_WriteI2C_Byte(0x47,pb4); //PB4:vic
}
void MipiAnalog(void)
{
I2CADR = 0x90;
#ifdef _pn_swap_
HDMI_WriteI2C_Byte(0x3e,0xf6); //P/N swap
#else
HDMI_WriteI2C_Byte(0x3e,0xd6); //if mipi pin map follow reference design, no need swap P/N.
#endif
HDMI_WriteI2C_Byte(0x3f,0xd4);//EQ
HDMI_WriteI2C_Byte(0x41,0x3c);//EQ
}
void MipiBasicSet(void)
{
I2CADR = 0x92;
HDMI_WriteI2C_Byte(0x10,0x01); // term en
HDMI_WriteI2C_Byte(0x11,0x10); // settle
//HDMI_WriteI2C_Byte(0x12,0x08); // trail
HDMI_WriteI2C_Byte(0x13,lane_cnt); //00 4 lane //01 1 lane //02 2 lane //03 3lane
HDMI_WriteI2C_Byte(0x14,0x00); //debug mux
#ifdef _lane_swap_ //for EVB only, if mipi pin map follow reference design, no need swap lane.
HDMI_WriteI2C_Byte(0x15,0xa8); //lane swap:3210
printk("%s nmipi basic set: lane swap 3210, %d\n",LOG_FLAG,lane_cnt);
#else
HDMI_WriteI2C_Byte(0x15,0x00); //lane swap:0123
#endif
HDMI_WriteI2C_Byte(0x1a,0x03); // hshift 3
HDMI_WriteI2C_Byte(0x1b,0x03); // vshift 3
}
void MIPI_Video_Setup(struct video_timing *video_format)
{
I2CADR = 0x92;
HDMI_WriteI2C_Byte(0x18,(u8)(video_format->hs%256)); // hwidth
HDMI_WriteI2C_Byte(0x19,(u8)(video_format->vs%256)); // vwidth
HDMI_WriteI2C_Byte(0x1c,(u8)(video_format->hact%256)); // H_active[7:0]
HDMI_WriteI2C_Byte(0x1d,(u8)(video_format->hact/256)); // H_active[15:8]
HDMI_WriteI2C_Byte(0x2f,0x0c); // fifo_buff_length 12
HDMI_WriteI2C_Byte(0x34,(u8)(video_format->htotal%256)); // H_total[7:0]
HDMI_WriteI2C_Byte(0x35,(u8)(video_format->htotal/256)); // H_total[15:8]
HDMI_WriteI2C_Byte(0x36,(u8)(video_format->vtotal%256)); // V_total[7:0]
HDMI_WriteI2C_Byte(0x37,(u8)(video_format->vtotal/256)); // V_total[15:8]
HDMI_WriteI2C_Byte(0x38,(u8)(video_format->vbp%256)); // VBP[7:0]
HDMI_WriteI2C_Byte(0x39,(u8)(video_format->vbp/256)); // VBP[15:8]
HDMI_WriteI2C_Byte(0x3a,(u8)(video_format->vfp%256)); // VFP[7:0]
HDMI_WriteI2C_Byte(0x3b,(u8)(video_format->vfp/256)); // VFP[15:8]
HDMI_WriteI2C_Byte(0x3c,(u8)(video_format->hbp%256)); // HBP[7:0]
HDMI_WriteI2C_Byte(0x3d,(u8)(video_format->hbp/256)); // HBP[15:8]
HDMI_WriteI2C_Byte(0x3e,(u8)(video_format->hfp%256)); // HFP[7:0]
HDMI_WriteI2C_Byte(0x3f,(u8)(video_format->hfp/256)); // HFP[15:8]
video = video_format;
}
void MIPIRxLogicRes(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x03,0x7f); //mipi rx reset
msleep(10);
HDMI_WriteI2C_Byte(0x03,0xff);
HDMI_WriteI2C_Byte(0x05,0xfb); //dds reset
msleep(10);
HDMI_WriteI2C_Byte(0x05,0xff);
}
void DDSConfig(void)
{
I2CADR = 0x92;
HDMI_WriteI2C_Byte(0x4e,0x93);//strm_sw_freq_word[ 7: 0]
HDMI_WriteI2C_Byte(0x4f,0x3E);//strm_sw_freq_word[15: 8]
HDMI_WriteI2C_Byte(0x50,0x29);//strm_sw_freq_word[23:16]
HDMI_WriteI2C_Byte(0x51,0x80);//[0]=strm_sw_freq_word[24]
HDMI_WriteI2C_Byte(0x1e,0x4f);
HDMI_WriteI2C_Byte(0x1f,0x5e);//full_value 464
HDMI_WriteI2C_Byte(0x20,0x01);
HDMI_WriteI2C_Byte(0x21,0x2c);//full_value1 416
HDMI_WriteI2C_Byte(0x22,0x01);
HDMI_WriteI2C_Byte(0x23,0xfa);//full_value2 400
HDMI_WriteI2C_Byte(0x24,0x00);
HDMI_WriteI2C_Byte(0x25,0xc8);//full_value3 384
HDMI_WriteI2C_Byte(0x26,0x00);
HDMI_WriteI2C_Byte(0x27,0x5e);//empty_value 464
HDMI_WriteI2C_Byte(0x28,0x01);
HDMI_WriteI2C_Byte(0x29,0x2c);//empty_value1 416
HDMI_WriteI2C_Byte(0x2a,0x01);
HDMI_WriteI2C_Byte(0x2b,0xfa);//empty_value2 400
HDMI_WriteI2C_Byte(0x2c,0x00);
HDMI_WriteI2C_Byte(0x2d,0xc8);//empty_value3 384
HDMI_WriteI2C_Byte(0x2e,0x00);
HDMI_WriteI2C_Byte(0x42,0x64);//tmr_set[ 7:0]:100us
HDMI_WriteI2C_Byte(0x43,0x00);//tmr_set[15:8]:100us
HDMI_WriteI2C_Byte(0x44,0x04);//timer step
HDMI_WriteI2C_Byte(0x45,0x00);
HDMI_WriteI2C_Byte(0x46,0x59);
HDMI_WriteI2C_Byte(0x47,0x00);
HDMI_WriteI2C_Byte(0x48,0xf2);
HDMI_WriteI2C_Byte(0x49,0x06);
HDMI_WriteI2C_Byte(0x4a,0x00);
HDMI_WriteI2C_Byte(0x4b,0x72);
HDMI_WriteI2C_Byte(0x4c,0x45);
HDMI_WriteI2C_Byte(0x4d,0x00);
HDMI_WriteI2C_Byte(0x52,0x08);// trend step
HDMI_WriteI2C_Byte(0x53,0x00);
HDMI_WriteI2C_Byte(0x54,0xb2);
HDMI_WriteI2C_Byte(0x55,0x00);
HDMI_WriteI2C_Byte(0x56,0xe4);
HDMI_WriteI2C_Byte(0x57,0x0d);
HDMI_WriteI2C_Byte(0x58,0x00);
HDMI_WriteI2C_Byte(0x59,0xe4);
HDMI_WriteI2C_Byte(0x5a,0x8a);
HDMI_WriteI2C_Byte(0x5b,0x00);
HDMI_WriteI2C_Byte(0x5c,0x34);
HDMI_WriteI2C_Byte(0x51,0x00);
}
void AudioIIsEn(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0xB2,0x01);//DVI mode:0x00; HDMI mode:0x01;
I2CADR = 0x94;
HDMI_WriteI2C_Byte(0x06,0x08);
HDMI_WriteI2C_Byte(0x07,0xF0);
HDMI_WriteI2C_Byte(0x34,0xD2);//0xE2:32FS; 0xD2:64FS
HDMI_WriteI2C_Byte(0x0F,0x2B);
}
void AudioSpdifEn(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0xB2,0x01);
I2CADR = 0x94;
HDMI_WriteI2C_Byte(0x06,0x0e);
HDMI_WriteI2C_Byte(0x07,0x00);
HDMI_WriteI2C_Byte(0x34,0xD2);//0xE2:32FS; 0xD2:64FS
}
void Core_Pll_setup(struct panel_parameter *panel)
{
u8 cpll_m, cpll_k1,cpll_k2; //cpll_k3;
u32 temp;
temp=(panel->pclk_khz*7)/25;
cpll_m=temp/1000;
temp=(panel->pclk_khz*7)/25;
temp=temp%1000;
//temp=temp*16.384;
temp=temp*16384/1000;
cpll_k1=temp%256;
cpll_k2=temp/256;
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x50,0x24);//cp=50uA
HDMI_WriteI2C_Byte(0x51,0x05);//xtal_clk as reference,second order passive LPF PLL
HDMI_WriteI2C_Byte(0x52,0x14);//use second-order PLL
HDMI_WriteI2C_Byte(0x69,cpll_m);//CP_PRESET_DIV_RATIO
HDMI_WriteI2C_Byte(0x69,(cpll_m|0x80));
HDMI_WriteI2C_Byte(0x6c,(cpll_k2|0x80));//RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8]
HDMI_WriteI2C_Byte(0x6b,cpll_k1);
HDMI_WriteI2C_Byte(0x04,0xfb);//core pll reset
HDMI_WriteI2C_Byte(0x04,0xff);
}
void Core_Pll_bypass(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x50,0x24); //cp=50uA
HDMI_WriteI2C_Byte(0x51,0x2d); //Pix_clk as reference,second order passive LPF PLL
HDMI_WriteI2C_Byte(0x52,0x04); //loopdiv=0;use second-order PLL
HDMI_WriteI2C_Byte(0x69,0x0e); //CP_PRESET_DIV_RATIO
HDMI_WriteI2C_Byte(0x69,0x8e);
HDMI_WriteI2C_Byte(0x6a,0x00);
HDMI_WriteI2C_Byte(0x6c,0xb8); //RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8]
HDMI_WriteI2C_Byte(0x6b,0x51);
HDMI_WriteI2C_Byte(0x04,0xfb); //core pll reset
HDMI_WriteI2C_Byte(0x04,0xff);
}
void Lvds_Pll_Reset(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x02,0xf7); //lvds pll reset
HDMI_WriteI2C_Byte(0x02,0xff);
}
void Scaler_bypass(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x7f,0x00);//disable scaler
HDMI_WriteI2C_Byte(0xa8,0x13);
}
void Scaler_setup(struct video_timing *input_video,struct panel_parameter *panel)
{
//for example: 720P to 1280x800
//These register base on MIPI resolution and LVDS panel resolution.
u32 h_ratio,v_ratio;
u8 i;
u32 htotal;
// h_ratio = input_video->hact*4096.00/panel->hact;
// v_ratio = input_video->vact*4096.00/panel->vact;
h_ratio = input_video->hact*4096/panel->hact;
v_ratio = input_video->vact*4096/panel->vact;
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x80,0x00);
HDMI_WriteI2C_Byte(0x81,0xff);
HDMI_WriteI2C_Byte(0x82,0x03);
HDMI_WriteI2C_Byte(0x83,(u8)(input_video->hact%256));
HDMI_WriteI2C_Byte(0x84,(u8)(input_video->hact/256));
HDMI_WriteI2C_Byte(0x85,0x80);
HDMI_WriteI2C_Byte(0x86,0x10);
HDMI_WriteI2C_Byte(0x87,(u8)(panel->htotal%256));
HDMI_WriteI2C_Byte(0x88,(u8)(panel->htotal/256));
HDMI_WriteI2C_Byte(0x89,(u8)(panel->hs%256));
HDMI_WriteI2C_Byte(0x8a,(u8)(panel->hbp%256));
HDMI_WriteI2C_Byte(0x8b,(u8)(panel->vs%256));
HDMI_WriteI2C_Byte(0x8c,(u8)(panel->hact%256));
HDMI_WriteI2C_Byte(0x8d,(u8)(panel->vact%256));
HDMI_WriteI2C_Byte(0x8e,(u8)(panel->vact/256)*16+(panel->hact/256));
HDMI_WriteI2C_Byte(0x8f,(u8)(h_ratio%256));
HDMI_WriteI2C_Byte(0x90,(u8)(h_ratio/256));
HDMI_WriteI2C_Byte(0x91,(u8)(v_ratio%256));
HDMI_WriteI2C_Byte(0x92,(u8)(v_ratio/256));
HDMI_WriteI2C_Byte(0x7f,0x96);
//HDMI_WriteI2C_Byte(0x7f,0xb0);
//HDMI_WriteI2C_Byte(0xa8,0x3b);
HDMI_WriteI2C_Byte(0xa8,0x13);
HDMI_WriteI2C_Byte(0x02,0xf7);//lvds pll reset
HDMI_WriteI2C_Byte(0x02,0xff);
HDMI_WriteI2C_Byte(0x03,0xcf);//scaler reset
HDMI_WriteI2C_Byte(0x03,0xff);
HDMI_WriteI2C_Byte(0x7f,0xb0);
for(i = 0; i < 300; i++)
{
if(HDMI_ReadI2C_Byte(0xa7)&0x20)
{
htotal = (HDMI_ReadI2C_Byte(0xa7)&0x0f)*0x100 + HDMI_ReadI2C_Byte(0xa6);
printk("%s scaler setup htotal = %d.\n",LOG_FLAG,htotal);
break;
//please set "htotal" to panel_parameter's htotal.
}
printk("%s scaler loop = %d\n",LOG_FLAG, i);
msleep(100);
}
}
void LvdsPowerUp(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x44,0x30);
HDMI_WriteI2C_Byte(0x51,0x05);
}
void LvdsPowerDown(void)
{
I2CADR = 0x90;
//HDMI_WriteI2C_Byte(0x44,0x31);
HDMI_WriteI2C_Byte(0x51,0x15); //
//HDMI_WriteI2C_Byte(0x03,0xfb);
}
void LvdsBypass(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x50,0x24); //cp=50uA
HDMI_WriteI2C_Byte(0x51,0x2d); //Pix_clk as reference,second order passive LPF PLL
HDMI_WriteI2C_Byte(0x52,0x04); //loopdiv=0;use second-order PLL
HDMI_WriteI2C_Byte(0x69,0x0e); //CP_PRESET_DIV_RATIO
HDMI_WriteI2C_Byte(0x69,0x8e);
HDMI_WriteI2C_Byte(0x6a,0x00);
HDMI_WriteI2C_Byte(0x6c,0xb8); //RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8]
HDMI_WriteI2C_Byte(0x6b,0x51);
HDMI_WriteI2C_Byte(0x04,0xfb); //core pll reset
HDMI_WriteI2C_Byte(0x04,0xff);
HDMI_WriteI2C_Byte(0x7f,0x00); //disable scaler
HDMI_WriteI2C_Byte(0xa8,0x13); //0x13:VSEA ; 0x33:JEIDA;
}
void LvdsOutput(bool on)
{
if(on)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x02,0xf7); //lvds pll reset
HDMI_WriteI2C_Byte(0x02,0xff); //scaler module reset
HDMI_WriteI2C_Byte(0x03,0xcb); //lvds tx module reset
HDMI_WriteI2C_Byte(0x03,0xfb);
HDMI_WriteI2C_Byte(0x03,0xff);
HDMI_WriteI2C_Byte(0x44,0x30); //enbale lvds output
printk("%s LT8912_lvds_output_enable!\n",LOG_FLAG);
}else{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x44,0x31);
}
}
void HdmiOutput(bool on)
{
if(on)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x33,0x0e); //enable hdmi output
printk("%s HDMI output Enable.\n",LOG_FLAG);
}
else
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x33,0x0c); //disable hdmi output
printk("%s HDMI output Disable.\n",LOG_FLAG);
}
}
void LvdsScalerResult(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x7f,0xb0);
}
void ScalerReset(void)
{
I2CADR = 0x90;
HDMI_WriteI2C_Byte(0x03,0xcf);
HDMI_WriteI2C_Byte(0x03,0xff);
}
void lt8912_check_dds(void)
{
u8 reg_920c, reg_920d, reg_920e, reg_920f;
u8 i;
for(i = 0; i < 10; i++)
{
I2CADR = 0x92;
reg_920c = HDMI_ReadI2C_Byte(0x0c);
reg_920d = HDMI_ReadI2C_Byte(0x0d);
reg_920e = HDMI_ReadI2C_Byte(0x0e);
reg_920f = HDMI_ReadI2C_Byte(0x0f);
printk("%s 0x0c~0f = %02x, %02x, %02x\n",LOG_FLAG,reg_920c, reg_920d, reg_920e);
// if((reg_920e == 0xd2)&&(reg_920d < 0xff)&&(reg_920d > 0xd0)) //shall update threshold here base on actual dds result.
// {
// printk("%s lvds_check_dds: stable!\n",LOG_FLAG);
// break;
// }
msleep(500);
}
}
void lvds_output_cfg(void)
{
LvdsPowerUp();
#ifdef _lvds_bypass
LvdsBypass();
#else
//Core_Pll_setup(&AA070M0C1);
Core_Pll_setup(&KD101FM_1_C001A);
Scaler_setup(&video_1280x720_60Hz,&KD101FM_1_C001A);
#endif
}
void MIPI_Input_det(void)
{
I2CADR = 0x90;
Hsync_L = HDMI_ReadI2C_Byte(0x9c);
Hsync_H = HDMI_ReadI2C_Byte(0x9d);
Vsync_L = HDMI_ReadI2C_Byte(0x9e);
Vsync_H = HDMI_ReadI2C_Byte(0x9f);
if((Hsync_H!=Hsync_H_last)||(Vsync_H!=Vsync_H_last)) /*hiht byte changed*/
{
printk("%s 0x9c~9f = %x, %x, %x, %x.\n", LOG_FLAG,Hsync_H, Hsync_L,Vsync_H, Vsync_L);
if(Vsync_H==0x02 && Vsync_L <= 0xef&&Vsync_L >= 0xec)//0x2EE
{
video = &video_1280x720_60Hz;
printk("%s videoformat = VESA_1280x720_60\n",LOG_FLAG);
}
else if(Vsync_H == 0x03 && Vsync_L <= 0x3a &&Vsync_L >= 0x34)//0x337
{
video = &video_1280x800_60Hz;
printk("%s videoformat = VESA_1280x800_60\n",LOG_FLAG);
}
else if(Vsync_H == 0x04 && Vsync_L <= 0x67&&Vsync_L >= 0x63)//0x465
{
video = &video_1920x1080_60Hz;
printk("%s videoformat = VESA_1920x1080_60\n",LOG_FLAG);
}
else
{
printk("%s videoformat = video_none\n",LOG_FLAG);
}
Hsync_L_last = Hsync_L;
Hsync_H_last = Hsync_H;
Vsync_L_last = Vsync_L;
Vsync_H_last = Vsync_H;
MIPI_Video_Setup(video);
AviInfoframe(video);
MIPIRxLogicRes();
}
}
//void dds_clock_debug(void)
//{
// #ifdef dds_debug
// u8 reg_920c, reg_920d, reg_920e, reg_920f;
//
// while(1)
// {
// I2CADR = 0x92;
// reg_920c = HDMI_ReadI2C_Byte(0x0c);
// reg_920d = HDMI_ReadI2C_Byte(0x0d);
// reg_920e = HDMI_ReadI2C_Byte(0x0e);
// reg_920f = HDMI_ReadI2C_Byte(0x0f);
//
// printk("\r\n0x0c~0e = %02x, %02x, %02x",reg_920c, reg_920d, reg_920e);
// printk("\r\nEnter the dds_clock_debug cycle");
//
// msleep(1000);
// }
// #endif
//}
void pattern_test(void)
{
u32 DDS_initial_value;
u8 pclk_Mhz;
// video = &video_640x480_60Hz;
// video = &video_720x480_60Hz;
// video = &video_800x600_60Hz;
// video = &video_1280x720_60Hz;
// video = &video_1280x800_60Hz;
video = &video_1920x1080_60Hz;
DigitalClockEn();
TxAnalog();
CbusAnalog();
HDMIPllAnalog();
AudioIIsEn();
AviInfoframe(video);
lvds_output_cfg();
I2CADR = 0x92;
//////////////////Pattern resolution set////////////////////
HDMI_WriteI2C_Byte(0x72,0x12);
HDMI_WriteI2C_Byte(0x73,(u8)((video->hs+video->hbp)%256)); //RGD_PTN_DE_DLY[7:0]
HDMI_WriteI2C_Byte(0x74,(u8)((video->hs+video->hbp)/256)); //RGD_PTN_DE_DLY[11:8]
HDMI_WriteI2C_Byte(0x75,(u8)((video->vs+video->vbp)%256)); //RGD_PTN_DE_TOP[6:0]
HDMI_WriteI2C_Byte(0x76,(u8)(video->hact%256)); //RGD_PTN_DE_CNT[7:0]
HDMI_WriteI2C_Byte(0x77,(u8)(video->vact%256)); //RGD_PTN_DE_LIN[7:0]
HDMI_WriteI2C_Byte(0x78,((((u8)(video->vact/256))<<4)+((u8)(video->hact/256)))); //RGD_PTN_DE_LIN[10:8],RGD_PTN_DE_CNT[11:8]
HDMI_WriteI2C_Byte(0x79,(u8)(video->htotal%256)); //RGD_PTN_H_TOTAL[7:0]
HDMI_WriteI2C_Byte(0x7a,(u8)(video->vtotal%256)); //RGD_PTN_V_TOTAL[7:0]
HDMI_WriteI2C_Byte(0x7b,((((u8)(video->vtotal/256))<<4)+((u8)(video->htotal/256)))); //RGD_PTN_V_TOTAL[10:8],RGD_PTN_H_TOTAL[11:8]
HDMI_WriteI2C_Byte(0x7c,(u8)(video->hs%256)); //RGD_PTN_HWIDTH[7:0]
HDMI_WriteI2C_Byte(0x7d,((((u8)(video->hs/256))<<6)+((u8)(video->vs%256)))); //RGD_PTN_HWIDTH[9:8],RGD_PTN_VWIDTH[5:0]
HDMI_WriteI2C_Byte(0x70,0x80); //pattern enable
HDMI_WriteI2C_Byte(0x71,0x51);
HDMI_WriteI2C_Byte(0x42,0x12);
///////////////////////////////////////////////////////////
HDMI_WriteI2C_Byte(0x1e,0x67); //h v d pol hdmi sel pll sel
//////////////////pattern pixl clock set///////////////////
pclk_Mhz = (u8)(video->pclk_khz/1000);
DDS_initial_value = (u32)(pclk_Mhz*0x16C16);
HDMI_WriteI2C_Byte(0x4e,(u8)(DDS_initial_value&0x000000ff)); //strm_sw_freq_word[ 7: 0]
HDMI_WriteI2C_Byte(0x4f,(u8)((DDS_initial_value&0x0000ff00)>>8)); //strm_sw_freq_word[15: 8]
HDMI_WriteI2C_Byte(0x50,(u8)((DDS_initial_value&0x00ff0000)>>16)); //strm_sw_freq_word[23:16]
HDMI_WriteI2C_Byte(0x51,0x80);
// HDMI_WriteI2C_Byte(0x4e,0x3E); //strm_sw_freq_word[ 7: 0]
// HDMI_WriteI2C_Byte(0x4f,0xE9); //strm_sw_freq_word[15: 8]
// HDMI_WriteI2C_Byte(0x50,0xD3); //strm_sw_freq_word[23:16]
// HDMI_WriteI2C_Byte(0x51,0x80); //pattern en
///////////////////////////////////////////////////////////
HdmiOutput(1);
LvdsOutput(1);
}
u8 LT8912_Get_HPD(void)
{
//(0x90)0xc1[bit7] description HPD is High or Low
I2CADR = 0x90;
if((HDMI_ReadI2C_Byte(0xc1)&0x80)==0x80)
{
printk("%s LT8912_Get_HPD: high\n",LOG_FLAG);
return 1;
}
else
{
printk("%s LT8912_Get_HPD: low\n",LOG_FLAG);
return 0;
}
}
void LT8912B_chip_ID(void)
{
I2CADR=0x90;
printk("%s chip ID: 0x%x, 0x%x\n",LOG_FLAG,HDMI_ReadI2C_Byte(0x00), HDMI_ReadI2C_Byte(0x01));
}
void LT8912B_Suspend(bool on)
{
//9mA,HPD detect is normal.
if(on)
{
if(!suspend_on)
{
// enter suspend mode
I2CADR = 0x90;
HDMI_WriteI2C_Byte( 0x54, 0x1d );
HDMI_WriteI2C_Byte( 0x51, 0x15 );
HDMI_WriteI2C_Byte( 0x44, 0x31 );
HDMI_WriteI2C_Byte( 0x41, 0xbd );
HDMI_WriteI2C_Byte( 0x5c, 0x11 );
suspend_on = 1;
printk("%s suspend on.\n",LOG_FLAG);
}
}else{
if(suspend_on)
{
//exist suspend mode
I2CADR = 0x90;
HDMI_WriteI2C_Byte( 0x5c, 0x10 );
HDMI_WriteI2C_Byte( 0x54, 0x1c );
HDMI_WriteI2C_Byte( 0x51, 0x2d );
HDMI_WriteI2C_Byte( 0x44, 0x30 );
HDMI_WriteI2C_Byte( 0x41, 0xbc );
msleep(10);
HDMI_WriteI2C_Byte(0x03,0x7f);
msleep(10);
HDMI_WriteI2C_Byte(0x03,0xff);
HDMI_WriteI2C_Byte(0x05,0xfb);
msleep(10);
HDMI_WriteI2C_Byte(0x05,0xff);
suspend_on = 0;
printk("%s suspend off.\n",LOG_FLAG);
}
}
}
void LT8912B_Config(void)
{
LT8912B_chip_ID();
#ifdef _pattern_test_
pattern_test();
while(Main_Loop);
#else
DigitalClockEn();
TxAnalog();
CbusAnalog();
HDMIPllAnalog();
MipiAnalog();
MipiBasicSet();
DDSConfig();
MIPI_Video_Setup(&video_1920x1080_60Hz);
MIPI_Input_det();
AudioIIsEn();
#ifdef dds_debug
lt8912_check_dds(); // can be removed when debug stage.
#endif
#ifdef _lvds_bypass
lvds_output_cfg();
LvdsOutput(1);
#endif
///////////////////////////////////////////////////////////// test use
// HdmiOutput(1);
// while(1);
/////////////////////////////////////////////////////////////
#ifdef _hdmi_output
if(LT8912_Get_HPD())
{
if(!Tx_HPD)
{
HdmiOutput(1);
Tx_HPD = 1;
printk("%s LT8912_Get_HPD: high\n",LOG_FLAG);
}
}else{
if(Tx_HPD)
{
LT8912B_Suspend(1);
printk("%s LT8912 Suspend!\n",LOG_FLAG);
HdmiOutput(0);
Tx_HPD = 0;
printk("%s LT8912_Get_HPD: low\n",LOG_FLAG);
}
}
#endif
#endif
while(Main_Loop)
{
MIPI_Input_det();
msleep(300);
#ifdef _hdmi_output
if(LT8912_Get_HPD())
{
if(!Tx_HPD)
{
LT8912B_Suspend(0);
HdmiOutput(1);
Tx_HPD = 1;
}
}else{
if(Tx_HPD)
{
LT8912B_Suspend(1);
HdmiOutput(0);
Tx_HPD = 0;
}
}
#endif
}
}
HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/LT8912B_Main.c
-35
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@@ -1,35 +0,0 @@
#include "../include/include.h"
void LT8912B_Power_On(void)
{
gpiod_set_value(lt8912b->power_gpio,1);
msleep(5);
printk("%s Set power High level.\n ",LOG_FLAG);
}
void LT8912B_Reset(void)
{
//complete chip reset logic
gpiod_set_value(lt8912b->reset_gpio,1);
msleep(5);
gpiod_set_value(lt8912b->reset_gpio,0);
msleep(5);
gpiod_set_value(lt8912b->reset_gpio,1);
msleep(100);
printk("%s Reset chip.\n",LOG_FLAG);
}
int LT8912B_Main(void *data)
{
printk("%s Init Start!\n",LOG_FLAG);
LT8912B_Power_On();
LT8912B_Reset();
LT8912B_Config();
Tx_HPD = 0;
return 0;
}
HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/LontiumDrv.c
-385
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@@ -1,385 +0,0 @@
#include "../include/include.h"
struct _lt8912b *lt8912b;
static struct task_struct *kthread_obj;
volatile bool Main_Loop=true;
char *ChipName = "lt8912b"; //Define Lontium Chip Name
static int major = 0;
static struct cdev chip_cdev;
static struct class *chip_class;
const char *LOG_FLAG = "LT8912B";
u8 I2CADR;
u8 addr_1_value = 0x00;
u8 addr_2_value = 0x00;
static int chip_open(struct inode *inode, struct file *filp)
{
printk("chip open\n");
return 0;
}
static int chip_close (struct inode *node, struct file *file)
{
printk("chip close\n");
return 0;
}
static ssize_t chip_read(struct file *filp, char __user *buf, size_t cnt, loff_t *offt)
{
Chip_Control_Args parameter;
if (copy_from_user(&parameter, buf, sizeof(parameter))) {
return -EFAULT;
}
parameter.value = HDMI_ReadI2C_Byte(parameter.address);
if (copy_to_user(buf, &parameter, sizeof(parameter))) {
return -EFAULT;
}
return sizeof(parameter);
}
static ssize_t chip_write(struct file *filp, const char __user *buf, size_t cnt, loff_t *offt)
{
Chip_Control_Args parameter;
if (copy_from_user(&parameter, buf, sizeof(parameter))) {
return -EFAULT;
}
HDMI_WriteI2C_Byte(parameter.address, parameter.value);
return sizeof(parameter);
}
static struct file_operations chip_drv = {
.owner = THIS_MODULE,
.open = chip_open,
.release = chip_close,
.read = chip_read,
.write = chip_write,
};
static int chip_dev_init(void)
{
int ret;
dev_t devid;
ret = alloc_chrdev_region(&devid, 0, 1, ChipName);
if (ret < 0) {
return ret;
}
major = MAJOR(devid);
cdev_init(&chip_cdev, &chip_drv);
cdev_add(&chip_cdev, devid, 1);
chip_class = class_create(THIS_MODULE, "chip_class");
if (IS_ERR(chip_class)) {
unregister_chrdev(major, ChipName);
return -1;
}
device_create(chip_class, NULL, MKDEV(major, 0), NULL, ChipName); /* /dev/ChipName */
return 0;
}
static void chip_dev_exit(void)
{
device_destroy(chip_class, MKDEV(major, 0));
class_destroy(chip_class);
cdev_del(&chip_cdev);
unregister_chrdev_region(MKDEV(major,0), 1);
}
static const struct regmap_range chip_ranges[] = {
{ .range_min = 0, .range_max = 0xffff },
};
static const struct regmap_access_table chip_table = {
.yes_ranges = chip_ranges,
.n_yes_ranges = ARRAY_SIZE(chip_ranges),
};
static const struct regmap_config chip_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_table = &chip_table,
.cache_type = REGCACHE_NONE,
};
static int chip_parse_dts(struct device *dev)
{
/*
* devm_gpiod_get_optional - If this fails, NULL is returned and no error pointer.
*
* devm_gpiod_get - If this fails, an error pointer is returned, usually ERR_PTR(-ENOENT).
*
* The devm_gpiod_get function is recommended for practical use.
*/
//Gets the handle to power gpio in dts
lt8912b->power_gpio=devm_gpiod_get_optional(dev, "power", GPIOD_OUT_HIGH);
if (IS_ERR(lt8912b->power_gpio)) {
dev_err(dev, "Failed to get power GPIO\n");
return PTR_ERR(lt8912b->power_gpio);
}
//Gets the handle to reset gpio in dts
lt8912b->reset_gpio=devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(lt8912b->reset_gpio)) {
dev_err(dev, "Failed to get reset GPIO\n");
return PTR_ERR(lt8912b->reset_gpio);
}
// Additional GPIO pins can be added here if needed
return 0;
}
static int chip_probe(struct i2c_client *client, const struct i2c_device_id *id)
{
struct i2c_board_info addr_1_board_info = {
I2C_BOARD_INFO("lt8912b_addr_1", addr_1_value),
};
struct i2c_board_info addr_2_board_info = {
I2C_BOARD_INFO("lt8912b_addr_2", addr_2_value),
};
struct device_node *np = client->dev.of_node;
struct device_node *addr_1_node;
struct device_node *addr_2_node;
int ret;
if (!np) {
dev_err(&client->dev, "Device tree node missing");
return -EINVAL;
}
chip_dev_init();
lt8912b = devm_kzalloc(&client->dev, sizeof(*lt8912b), GFP_KERNEL);
if (lt8912b == NULL)
return -ENOMEM;
lt8912b->i2c_stu = client;
lt8912b->dev = &client->dev;
////////////////////////////////////////////////
//addr_0
lt8912b->chip_regmap = devm_regmap_init_i2c(client, &chip_regmap_config);
if (IS_ERR(lt8912b->chip_regmap)) {
dev_err(&client->dev, "Failed to initialize regmap\n");
return PTR_ERR(lt8912b->chip_regmap);
}
////////////////////////////////////////////////
/////////////////////////////////////////////////
//addr_1
addr_1_node = of_get_child_by_name(np, "lt8912b_addr_1");
if (!addr_1_node) {
dev_err(&client->dev, "Failed to find lt8912b_addr_1 node");
return -EINVAL;
}
lt8912b->addr_1 = devm_kzalloc(&client->dev, sizeof(struct addr_1), GFP_KERNEL);
if (!lt8912b->addr_1)
return -ENOMEM;
if (of_property_read_u8(addr_1_node, "addr_1_reg", &addr_1_value)) {
dev_err(&client->dev, "Failed to get addr_1_reg address");
return -EINVAL;
}
addr_1_board_info.addr =addr_1_value;
lt8912b->addr_1->i2c_stu = i2c_new_device(client->adapter, &addr_1_board_info);
if (!lt8912b->addr_1->i2c_stu) {
dev_err(&client->dev, "Failed to create I2C client for addr_1");
return -ENODEV;
}
lt8912b->addr_1->regmap = devm_regmap_init_i2c(lt8912b->addr_1->i2c_stu, &chip_regmap_config);
if (IS_ERR(lt8912b->addr_1->regmap)) {
dev_err(&client->dev, "Failed to initialize addr_1 regmap");
i2c_unregister_device(lt8912b->addr_1->i2c_stu);
return PTR_ERR(lt8912b->addr_1->regmap);
}
///////////////////////////////////////////////////
/////////////////////////////////////////////////
//addr_2
addr_2_node = of_get_child_by_name(np, "lt8912b_addr_2");
if (!addr_2_node) {
dev_err(&client->dev, "Failed to find lt8912b_addr_2 node");
return -EINVAL;
}
lt8912b->addr_2 = devm_kzalloc(&client->dev, sizeof(struct addr_2), GFP_KERNEL);
if (!lt8912b->addr_2)
return -ENOMEM;
if (of_property_read_u8(addr_2_node, "addr_2_reg", &addr_2_value)) {
dev_err(&client->dev, "Failed to get addr_2_reg address");
return -EINVAL;
}
addr_2_board_info.addr =addr_2_value;
lt8912b->addr_2->i2c_stu = i2c_new_device(client->adapter, &addr_2_board_info);
if (!lt8912b->addr_2->i2c_stu) {
dev_err(&client->dev, "Failed to create I2C client for addr_2");
return -ENODEV;
}
lt8912b->addr_2->regmap = devm_regmap_init_i2c(lt8912b->addr_2->i2c_stu, &chip_regmap_config);
if (IS_ERR(lt8912b->addr_2->regmap)) {
dev_err(&client->dev, "Failed to initialize addr_2 regmap");
i2c_unregister_device(lt8912b->addr_2->i2c_stu);
return PTR_ERR(lt8912b->addr_2->regmap);
}
///////////////////////////////////////////////////
mutex_init(&lt8912b->ocm_lock);
ret = chip_parse_dts(lt8912b->dev);
if (ret<0){
dev_err(&client->dev, "Failed to parse device tree\n");
return ret;
}
i2c_set_clientdata(client, lt8912b);
kthread_obj = kthread_run(LT8912B_Main, NULL, "LT8912B_kthread");
if (IS_ERR(kthread_obj)) {
dev_err(&client->dev, "Failed to create kernel thread\n");
return PTR_ERR(kthread_obj);
}
return 0;
}
static int chip_remove(struct i2c_client *client)
{
Main_Loop = false;
msleep(500);
mutex_destroy(&lt8912b->ocm_lock);
i2c_unregister_device(lt8912b->addr_1->i2c_stu);
i2c_unregister_device(lt8912b->addr_2->i2c_stu);
chip_dev_exit();
printk("driver removed\n");
return 0;
}
static int chip_suspend(struct device *dev)
{
printk(KERN_INFO "%s Suspend.\n",LOG_FLAG);
gpiod_set_value(lt8912b->reset_gpio,0);
msleep(10);
Main_Loop =false;
return 0;
}
static int chip_resume(struct device *dev)
{
printk(KERN_INFO "%s Resume.\n",LOG_FLAG);
gpiod_set_value(lt8912b->reset_gpio,1);
msleep(5);
Main_Loop = true;
msleep(5);
kthread_obj = kthread_run(LT8912B_Main, NULL, "LT8912B_kthread");
return 0;
}
static const struct dev_pm_ops chip_pm_ops = {
.suspend = chip_suspend,
.resume = chip_resume,
};
static const struct i2c_device_id chip_ids[] = {
{"lt8912b", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, chip_ids);
static const struct of_device_id chip_id_table[] = {
{.compatible = "lontium,lt8912b"},
{ }
};
MODULE_DEVICE_TABLE(of, chip_id_table);
static struct i2c_driver chip_driver = {
.driver = {
.owner = THIS_MODULE,
.name = "lt8912b",
.pm = &chip_pm_ops,
.of_match_table = chip_id_table,
},
.probe = chip_probe,
.remove = chip_remove,
.id_table = chip_ids,
};
module_i2c_driver(chip_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("LT8912B driver");
MODULE_AUTHOR("Tony Yang<syyang@lontium.com>");
HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/OcmI2cMaster.c
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@@ -1,91 +0,0 @@
#include "../include/include.h"
int HDMI_WriteI2C_Byte(u8 addr,u8 data)
{
int ret = 0;
mutex_lock(&lt8912b->ocm_lock);
if(I2CADR==0x90)
{
ret = regmap_write(lt8912b->chip_regmap, addr, data);
if (ret < 0) {
printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d",
lt8912b->i2c_stu->addr, addr, data, ret);
mutex_unlock(&lt8912b->ocm_lock);
return ret;
}
}else if(I2CADR==0x92){
ret = regmap_write(lt8912b->addr_1->regmap, addr, data);
if (ret < 0) {
printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d",
lt8912b->addr_1->i2c_stu->addr, addr, data, ret);
mutex_unlock(&lt8912b->ocm_lock);
return ret;
}
}else if(I2CADR==0x94){
ret = regmap_write(lt8912b->addr_2->regmap, addr, data);
if (ret < 0) {
printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d",
lt8912b->addr_2->i2c_stu->addr, addr, data, ret);
mutex_unlock(&lt8912b->ocm_lock);
return ret;
}
}
mutex_unlock(&lt8912b->ocm_lock);
return 0;
}
int HDMI_ReadI2C_Byte(u8 addr)
{
int ret = 0;
unsigned int val = 0;
mutex_lock(&lt8912b->ocm_lock);
if(I2CADR==0x90){
ret = regmap_read(lt8912b->chip_regmap, addr, &val);
if (ret < 0) {
printk("regmap_read error: (0x%02x 0x%02x) %d",
lt8912b->i2c_stu->addr, addr, ret);
mutex_unlock(&lt8912b->ocm_lock);
return ret;
}
}else if(I2CADR==0x92){
ret = regmap_read(lt8912b->addr_1->regmap, addr, &val);
if (ret < 0) {
printk("regmap_read error: (0x%02x 0x%02x) %d",
lt8912b->addr_1->i2c_stu->addr, addr, ret);
mutex_unlock(&lt8912b->ocm_lock);
return ret;
}
}else if(I2CADR==0x94){
ret = regmap_read(lt8912b->addr_2->regmap, addr, &val);
if (ret < 0) {
printk("regmap_read error: (0x%02x 0x%02x) %d",
lt8912b->addr_2->i2c_stu->addr, addr, ret);
mutex_unlock(&lt8912b->ocm_lock);
return ret;
}
}
mutex_unlock(&lt8912b->ocm_lock);
return (u8)val;
}
EXPORT_SYMBOL(HDMI_WriteI2C_Byte);
EXPORT_SYMBOL(HDMI_ReadI2C_Byte);
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/LT8912B.SearchResults
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---- _LVDS_Bypass_ Matches (3 in 3 files) ----
LT8912B.c (src):#ifdef _LVDS_Bypass_
Main.c:#ifdef _LVDS_Bypass_
Main.h (inc)://#define _LVDS_Bypass_
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/TAGS_Filelist.txt
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main.c␍
src\i2c_master.c␍
src\interrupt.c␍
src\stm8s_clk.c␍
src\stm8s_exti.c␍
src\stm8s_gpio.c␍
src\stm8s_itc.c␍
stm8_interrupt_vector.c␍
inc\i2c_master.h␍
inc\include.h␍
inc\lt8522ex.h␍
inc\stm8s.h␍
inc\stm8s_clk.h␍
inc\stm8s_conf.h␍
inc\stm8s_exti.h␍
inc\stm8s_it.h␍
inc\stm8s_macro.h␍
inc\stm8s_type.h␍
..\..\..\..\..\..\..\..\program files (x86)\cosmic\cxstm8_32k\hstm8\mods0.h␍
..\..\..\..\..\..\..\..\program files (x86)\cosmic\cxstm8_32k\hstm8\string.h␍
inc\edid.h␍
inc\main.h␍
inc\stm8s_gpio.h␍
inc\stm8s_itc.h␍
inc\stm8s_iwdg.h␍
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/checkres.spy
-9
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;
; ** Welcome to ST Visual Debug SPY System **
; ** Copyright STMicroelectronics (c) 1999, all rights reserved **
; Level 1
; Date 04/12/14
; Time 11:09:57
;
<.\confmenu.cpp:170-11:09:57>
Error: resource handle has not been restored in .\mainfrm.cpp:3205
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/Delay.h
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#ifndef _Delay_H
#define _Delay_H
extern void Timer0_Delay100us(UINT32 u32CNT);
extern void Timer0_Delay1ms(UINT32 u32CNT);
extern void Timer1_Delay10ms(UINT32 u32CNT);
extern void Timer2_Delay500us(UINT32 u32CNT);
extern void Timer3_Delay100ms(UINT32 u32CNT);
extern void Timer0_Delay40ms(UINT32 u32CNT);
extern void Timer3_Delay10us(UINT32 u32CNT);
extern bit BIT_TMP;
#endif
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/Function_Define.h
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/*--------------------------------------------------------------------------
N76E003 Function_define.h V1.02
All function define inital setting file for Nuvoton N76E003
--------------------------------------------------------------------------*/
#include <intrins.h>
#include <stdio.h>
#define nop _nop_( );
//16 --> 8 x 2
#define HIBYTE( v1 ) ( (UINT8)( ( v1 ) >> 8 ) ) //v1 is UINT16
#define LOBYTE( v1 ) ( (UINT8)( ( v1 ) & 0xFF ) )
//8 x 2 --> 16
#define MAKEWORD( v1, v2 ) ( ( ( (UINT16)( v1 ) ) << 8 ) + (UINT16)( v2 ) ) //v1,v2 is UINT8
//8 x 4 --> 32
#define MAKELONG( v1, v2, v3, v4 ) (UINT32)( ( v1 << 32 ) + ( v2 << 16 ) + ( v3 << 8 ) + v4 ) //v1,v2,v3,v4 is UINT8
//32 --> 16 x 2
#define YBYTE1( v1 ) ( (UINT16)( ( v1 ) >> 16 ) ) //v1 is UINT32
#define YBYTE0( v1 ) ( (UINT16)( ( v1 ) & 0xFFFF ) )
//32 --> 8 x 4
#define TBYTE3( v1 ) ( (UINT8)( ( v1 ) >> 24 ) ) //v1 is UINT32
#define TBYTE2( v1 ) ( (UINT8)( ( v1 ) >> 16 ) )
#define TBYTE1( v1 ) ( (UINT8)( ( v1 ) >> 8 ) )
#define TBYTE0( v1 ) ( (UINT8)( ( v1 ) & 0xFF ) )
#define SET_BIT0 0x01
#define SET_BIT1 0x02
#define SET_BIT2 0x04
#define SET_BIT3 0x08
#define SET_BIT4 0x10
#define SET_BIT5 0x20
#define SET_BIT6 0x40
#define SET_BIT7 0x80
#define SET_BIT8 0x0100
#define SET_BIT9 0x0200
#define SET_BIT10 0x0400
#define SET_BIT11 0x0800
#define SET_BIT12 0x1000
#define SET_BIT13 0x2000
#define SET_BIT14 0x4000
#define SET_BIT15 0x8000
#define CLR_BIT0 0xFE
#define CLR_BIT1 0xFD
#define CLR_BIT2 0xFB
#define CLR_BIT3 0xF7
#define CLR_BIT4 0xEF
#define CLR_BIT5 0xDF
#define CLR_BIT6 0xBF
#define CLR_BIT7 0x7F
#define CLR_BIT8 0xFEFF
#define CLR_BIT9 0xFDFF
#define CLR_BIT10 0xFBFF
#define CLR_BIT11 0xF7FF
#define CLR_BIT12 0xEFFF
#define CLR_BIT13 0xDFFF
#define CLR_BIT14 0xBFFF
#define CLR_BIT15 0x7FFF
#define FAIL 1
#define PASS 0
/*****************************************************************************************
* For GPIO INIT setting
*****************************************************************************************/
//------------------- Define Port as Quasi mode -------------------
#define P00_Quasi_Mode P0M1 &= ~SET_BIT0; P0M2 &= ~SET_BIT0
#define P01_Quasi_Mode P0M1 &= ~SET_BIT1; P0M2 &= ~SET_BIT1
#define P02_Quasi_Mode P0M1 &= ~SET_BIT2; P0M2 &= ~SET_BIT2
#define P03_Quasi_Mode P0M1 &= ~SET_BIT3; P0M2 &= ~SET_BIT3
#define P04_Quasi_Mode P0M1 &= ~SET_BIT4; P0M2 &= ~SET_BIT4
#define P05_Quasi_Mode P0M1 &= ~SET_BIT5; P0M2 &= ~SET_BIT5
#define P06_Quasi_Mode P0M1 &= ~SET_BIT6; P0M2 &= ~SET_BIT6
#define P07_Quasi_Mode P0M1 &= ~SET_BIT7; P0M2 &= ~SET_BIT7
#define P10_Quasi_Mode P1M1 &= ~SET_BIT0; P1M2 &= ~SET_BIT0
#define P11_Quasi_Mode P1M1 &= ~SET_BIT1; P1M2 &= ~SET_BIT1
#define P12_Quasi_Mode P1M1 &= ~SET_BIT2; P1M2 &= ~SET_BIT2
#define P13_Quasi_Mode P1M1 &= ~SET_BIT3; P1M2 &= ~SET_BIT3
#define P14_Quasi_Mode P1M1 &= ~SET_BIT4; P1M2 &= ~SET_BIT4
#define P15_Quasi_Mode P1M1 &= ~SET_BIT5; P1M2 &= ~SET_BIT5
#define P16_Quasi_Mode P1M1 &= ~SET_BIT6; P1M2 &= ~SET_BIT6
#define P17_Quasi_Mode P1M1 &= ~SET_BIT7; P1M2 &= ~SET_BIT7
#define P30_Quasi_Mode P3M1 &= ~SET_BIT0; P3M2 &= ~SET_BIT0
//------------------- Define Port as Push Pull mode -------------------
#define P00_PushPull_Mode P0M1 &= ~SET_BIT0; P0M2 |= SET_BIT0
#define P01_PushPull_Mode P0M1 &= ~SET_BIT1; P0M2 |= SET_BIT1
#define P02_PushPull_Mode P0M1 &= ~SET_BIT2; P0M2 |= SET_BIT2
#define P03_PushPull_Mode P0M1 &= ~SET_BIT3; P0M2 |= SET_BIT3
#define P04_PushPull_Mode P0M1 &= ~SET_BIT4; P0M2 |= SET_BIT4
#define P05_PushPull_Mode P0M1 &= ~SET_BIT5; P0M2 |= SET_BIT5
#define P06_PushPull_Mode P0M1 &= ~SET_BIT6; P0M2 |= SET_BIT6
#define P07_PushPull_Mode P0M1 &= ~SET_BIT7; P0M2 |= SET_BIT7
#define P10_PushPull_Mode P1M1 &= ~SET_BIT0; P1M2 |= SET_BIT0
#define P11_PushPull_Mode P1M1 &= ~SET_BIT1; P1M2 |= SET_BIT1
#define P12_PushPull_Mode P1M1 &= ~SET_BIT2; P1M2 |= SET_BIT2
#define P13_PushPull_Mode P1M1 &= ~SET_BIT3; P1M2 |= SET_BIT3
#define P14_PushPull_Mode P1M1 &= ~SET_BIT4; P1M2 |= SET_BIT4
#define P15_PushPull_Mode P1M1 &= ~SET_BIT5; P1M2 |= SET_BIT5
#define P16_PushPull_Mode P1M1 &= ~SET_BIT6; P1M2 |= SET_BIT6
#define P17_PushPull_Mode P1M1 &= ~SET_BIT7; P1M2 |= SET_BIT7
#define P30_PushPull_Mode P3M1 &= ~SET_BIT0; P3M2 |= SET_BIT0
#define GPIO1_PushPull_Mode P1M1 &= ~SET_BIT0; P1M2 |= SET_BIT0
//------------------- Define Port as Input Only mode -------------------
#define P00_Input_Mode P0M1 |= SET_BIT0; P0M2 &= ~SET_BIT0
#define P01_Input_Mode P0M1 |= SET_BIT1; P0M2 &= ~SET_BIT1
#define P02_Input_Mode P0M1 |= SET_BIT2; P0M2 &= ~SET_BIT2
#define P03_Input_Mode P0M1 |= SET_BIT3; P0M2 &= ~SET_BIT3
#define P04_Input_Mode P0M1 |= SET_BIT4; P0M2 &= ~SET_BIT4
#define P05_Input_Mode P0M1 |= SET_BIT5; P0M2 &= ~SET_BIT5
#define P06_Input_Mode P0M1 |= SET_BIT6; P0M2 &= ~SET_BIT6
#define P07_Input_Mode P0M1 |= SET_BIT7; P0M2 &= ~SET_BIT7
#define P10_Input_Mode P1M1 |= SET_BIT0; P1M2 &= ~SET_BIT0
#define P11_Input_Mode P1M1 |= SET_BIT1; P1M2 &= ~SET_BIT1
#define P12_Input_Mode P1M1 |= SET_BIT2; P1M2 &= ~SET_BIT2
#define P13_Input_Mode P1M1 |= SET_BIT3; P1M2 &= ~SET_BIT3
#define P14_Input_Mode P1M1 |= SET_BIT4; P1M2 &= ~SET_BIT4
#define P15_Input_Mode P1M1 |= SET_BIT5; P1M2 &= ~SET_BIT5
#define P16_Input_Mode P1M1 |= SET_BIT6; P1M2 &= ~SET_BIT6
#define P17_Input_Mode P1M1 |= SET_BIT7; P1M2 &= ~SET_BIT7
#define P30_Input_Mode P3M1 |= SET_BIT0; P3M2 &= ~SET_BIT0
//-------------------Define Port as Open Drain mode -------------------
#define P00_OpenDrain_Mode P0M1 |= SET_BIT0; P0M2 |= SET_BIT0
#define P01_OpenDrain_Mode P0M1 |= SET_BIT1; P0M2 |= SET_BIT1
#define P02_OpenDrain_Mode P0M1 |= SET_BIT2; P0M2 |= SET_BIT2
#define P03_OpenDrain_Mode P0M1 |= SET_BIT3; P0M2 |= SET_BIT3
#define P04_OpenDrain_Mode P0M1 |= SET_BIT4; P0M2 |= SET_BIT4
#define P05_OpenDrain_Mode P0M1 |= SET_BIT5; P0M2 |= SET_BIT5
#define P06_OpenDrain_Mode P0M1 |= SET_BIT6; P0M2 |= SET_BIT6
#define P07_OpenDrain_Mode P0M1 |= SET_BIT7; P0M2 |= SET_BIT7
#define P10_OpenDrain_Mode P1M1 |= SET_BIT0; P1M2 |= SET_BIT0
#define P11_OpenDrain_Mode P1M1 |= SET_BIT1; P1M2 |= SET_BIT1
#define P12_OpenDrain_Mode P1M1 |= SET_BIT2; P1M2 |= SET_BIT2
#define P13_OpenDrain_Mode P1M1 |= SET_BIT3; P1M2 |= SET_BIT3
#define P14_OpenDrain_Mode P1M1 |= SET_BIT4; P1M2 |= SET_BIT4
#define P15_OpenDrain_Mode P1M1 |= SET_BIT5; P1M2 |= SET_BIT5
#define P16_OpenDrain_Mode P1M1 |= SET_BIT6; P1M2 |= SET_BIT6
#define P17_OpenDrain_Mode P1M1 |= SET_BIT7; P1M2 |= SET_BIT7
#define P30_OpenDrain_Mode P3M1 |= SET_BIT0; P3M2 |= SET_BIT0
//--------- Define all port as quasi mode ---------
#define Set_All_GPIO_Quasi_Mode P0M1 = 0; P0M2 = 0; P1M1 = 0; P1M2 = 0; P3M1 = 0; P3M2 = 0
#define set_GPIO1 P12 = 1
#define clr_GPIO1 P12 = 0
/****************************************************************************
Enable INT port 0~3
***************************************************************************/
#define Enable_INT_Port0 PICON &= 0xFB;
#define Enable_INT_Port1 PICON |= 0x01;
#define Enable_INT_Port2 PICON |= 0x02;
#define Enable_INT_Port3 PICON |= 0x03;
/*****************************************************************************
Enable each bit low level trig mode
*****************************************************************************/
#define Enable_BIT7_LowLevel_Trig PICON &= 0x7F; PINEN |= 0x80; PIPEN &= 0x7F
#define Enable_BIT6_LowLevel_Trig PICON &= 0x7F; PINEN |= 0x40; PIPEN &= 0xBF
#define Enable_BIT5_LowLevel_Trig PICON &= 0xBF; PINEN |= 0x20; PIPEN &= 0xDF
#define Enable_BIT4_LowLevel_Trig PICON &= 0xBF; PINEN |= 0x10; PIPEN &= 0xEF
#define Enable_BIT3_LowLevel_Trig PICON &= 0xDF; PINEN |= 0x08; PIPEN &= 0xF7
#define Enable_BIT2_LowLevel_Trig PICON &= 0xEF; PINEN |= 0x04; PIPEN &= 0xFB
#define Enable_BIT1_LowLevel_Trig PICON &= 0xF7; PINEN |= 0x02; PIPEN &= 0xFD
#define Enable_BIT0_LowLevel_Trig PICON &= 0xFD; PINEN |= 0x01; PIPEN &= 0xFE
/*****************************************************************************
Enable each bit high level trig mode
*****************************************************************************/
#define Enable_BIT7_HighLevel_Trig PICON &= 0x7F; PINEN &= 0x7F; PIPEN |= 0x80
#define Enable_BIT6_HighLevel_Trig PICON &= 0x7F; PINEN &= 0xBF; PIPEN |= 0x40
#define Enable_BIT5_HighLevel_Trig PICON &= 0xBF; PINEN &= 0xDF; PIPEN |= 0x20
#define Enable_BIT4_HighLevel_Trig PICON &= 0xBF; PINEN &= 0xEF; PIPEN |= 0x10
#define Enable_BIT3_HighLevel_Trig PICON &= 0xDF; PINEN &= 0xF7; PIPEN |= 0x08
#define Enable_BIT2_HighLevel_Trig PICON &= 0xEF; PINEN &= 0xFB; PIPEN |= 0x04
#define Enable_BIT1_HighLevel_Trig PICON &= 0xF7; PINEN &= 0xFD; PIPEN |= 0x02
#define Enable_BIT0_HighLevel_Trig PICON &= 0xFD; PINEN &= 0xFE; PIPEN |= 0x01
/*****************************************************************************
Enable each bit falling edge trig mode
*****************************************************************************/
#define Enable_BIT7_FallEdge_Trig PICON |= 0x80; PINEN |= 0x80; PIPEN &= 0x7F
#define Enable_BIT6_FallEdge_Trig PICON |= 0x80; PINEN |= 0x40; PIPEN &= 0xBF
#define Enable_BIT5_FallEdge_Trig PICON |= 0x40; PINEN |= 0x20; PIPEN &= 0xDF
#define Enable_BIT4_FallEdge_Trig PICON |= 0x40; PINEN |= 0x10; PIPEN &= 0xEF
#define Enable_BIT3_FallEdge_Trig PICON |= 0x20; PINEN |= 0x08; PIPEN &= 0xF7
#define Enable_BIT2_FallEdge_Trig PICON |= 0x10; PINEN |= 0x04; PIPEN &= 0xFB
#define Enable_BIT1_FallEdge_Trig PICON |= 0x08; PINEN |= 0x02; PIPEN &= 0xFD
#define Enable_BIT0_FallEdge_Trig PICON |= 0x04; PINEN |= 0x01; PIPEN &= 0xFE
/*****************************************************************************
Enable each bit rasing edge trig mode
*****************************************************************************/
#define Enable_BIT7_RasingEdge_Trig PICON |= 0x80; PINEN &= 0x7F; PIPEN |= 0x80
#define Enable_BIT6_RasingEdge_Trig PICON |= 0x80; PINEN &= 0xBF; PIPEN |= 0x40
#define Enable_BIT5_RasingEdge_Trig PICON |= 0x40; PINEN &= 0xDF; PIPEN |= 0x20
#define Enable_BIT4_RasingEdge_Trig PICON |= 0x40; PINEN &= 0xEF; PIPEN |= 0x10
#define Enable_BIT3_RasingEdge_Trig PICON |= 0x20; PINEN &= 0xF7; PIPEN |= 0x08
#define Enable_BIT2_RasingEdge_Trig PICON |= 0x10; PINEN &= 0xFB; PIPEN |= 0x04
#define Enable_BIT1_RasingEdge_Trig PICON |= 0x08; PINEN |= 0xFD; PIPEN &= 0x02
#define Enable_BIT0_RasingEdge_Trig PICON |= 0x04; PINEN |= 0xFE; PIPEN &= 0x01
/*****************************************************************************************
* For TIMER VALUE setting is base on " option -> C51 -> Preprocesser Symbols -> Define "
*****************************************************************************************/
#ifdef FOSC_110592 // if Fsys = 11.0592MHz
#define TIMER_DIV12_VALUE_10us 65536 - 9 //9*12/11.0592 = 10 uS, // Timer divider = 12 for TM0/TM1
#define TIMER_DIV12_VALUE_1ms 65536 - 923 //923*12/11.0592 = 1 mS // Timer divider = 12
#define TIMER_DIV12_VALUE_10ms 65536 - 9216 //18432*12/22118400 = 10 ms // Timer divider = 12
#define TIMER_DIV4_VALUE_10us 65536 - 28 //28*4/11.0592 = 10 uS // Timer divider = 4 for TM2/TM3
#define TIMER_DIV4_VALUE_1ms 65536 - 2765 //2765*4/11.0592 = 1 mS // Timer divider = 4
#define TIMER_DIV4_VALUE_100us 65536 - 277 //553*4/22118400 = 100 us // Timer divider = 4
#define TIMER_DIV4_VALUE_200us 65536 - 553 //1106*4/22118400 = 200 us // Timer divider = 4
#define TIMER_DIV4_VALUE_500us 65536 - 1383 //2765*4/22118400 = 500 us // Timer divider = 4
#define TIMER_DIV16_VALUE_10ms 65536 - 6912 //1500*16/22118400 = 10 ms // Timer divider = 16
#define TIMER_DIV64_VALUE_30ms 65536 - 5184 //10368*64/22118400 = 30 ms // Timer divider = 64
#define TIMER_DIV128_VALUE_100ms 65536 - 8640 //17280*128/22118400 = 100 ms // Timer divider = 128
#define TIMER_DIV128_VALUE_200ms 65536 - 17280 //34560*128/22118400 = 200 ms // Timer divider = 128
#define TIMER_DIV256_VALUE_500ms 65536 - 21600 //43200*256/22118400 = 500 ms // Timer divider = 256
#define TIMER_DIV512_VALUE_1s 65536 - 21600 //43200*512/22118400 = 1 s // Timer divider = 512
#endif
#ifdef FOSC_160000 // if Fsys = 16MHz
#define TIMER_DIV12_VALUE_10us 65536 - 13 //13*12/16000000 = 10 uS, // Timer divider = 12 for TM0/TM1
#define TIMER_DIV12_VALUE_100us 65536 - 130 //130*12/16000000 = 10 uS, // Timer divider = 12
#define TIMER_DIV12_VALUE_1ms 65536 - 1334 //1334*12/16000000 = 1 mS, // Timer divider = 12
#define TIMER_DIV12_VALUE_10ms 65536 - 13334 //13334*12/16000000 = 10 mS // Timer divider = 12
#define TIMER_DIV12_VALUE_40ms 65536 - 53336 //53336*12/16000000 = 40 ms // Timer divider = 12
#define TIMER_DIV4_VALUE_10us 65536 - 40 //40*4/16000000 = 10 uS, // Timer divider = 4 for TM2/TM3
#define TIMER_DIV4_VALUE_100us 65536 - 400 //400*4/16000000 = 100 us // Timer divider = 4
#define TIMER_DIV4_VALUE_200us 65536 - 800 //800*4/16000000 = 200 us // Timer divider = 4
#define TIMER_DIV4_VALUE_500us 65536 - 2000 //2000*4/16000000 = 500 us // Timer divider = 4
#define TIMER_DIV4_VALUE_1ms 65536 - 4000 //4000*4/16000000 = 1 mS, // Timer divider = 4
#define TIMER_DIV16_VALUE_10ms 65536 - 10000 //10000*16/16000000 = 10 ms // Timer divider = 16
#define TIMER_DIV64_VALUE_30ms 65536 - 7500 //7500*64/16000000 = 30 ms // Timer divider = 64
#define TIMER_DIV128_VALUE_100ms 65536 - 12500 //12500*128/16000000 = 100 ms // Timer divider = 128
#define TIMER_DIV128_VALUE_200ms 65536 - 25000 //25000*128/16000000 = 200 ms // Timer divider = 128
#define TIMER_DIV256_VALUE_500ms 65536 - 31250 //31250*256/16000000 = 500 ms // Timer divider = 256
#define TIMER_DIV512_VALUE_1s 65536 - 31250 //31250*512/16000000 = 1 s. // Timer Divider = 512
#endif
#ifdef FOSC_184320 // if Fsys = 18.432MHz
#define TIMER_DIV12_VALUE_10us 65536 - 15 //15*12/18.432 = 10 uS, Timer Clock = Fsys/12
#define TIMER_DIV12_VALUE_1ms 65536 - 1536 //1536*12/18.432 = 1 mS, Timer Clock = Fsys/12
#define TIMER_DIV4_VALUE_10us 65536 - 46 //46*4/18.432 = 10 uS, Timer Clock = Fsys/4
#define TIMER_DIV4_VALUE_1ms 65536 - 4608 //4608*4/18.432 = 1 mS, Timer Clock = Fsys/4
#endif
#ifdef FOSC_200000 // if Fsys = 20 MHz
#define TIMER_DIV12_VALUE_10us 65536 - 17 //17*12/20000000 = 10 uS, Timer Clock = Fsys/12
#define TIMER_DIV12_VALUE_1ms 65536 - 1667 //1667*12/20000000 = 1 mS, Timer Clock = Fsys/12
#define TIMER_DIV4_VALUE_10us 65536 - 50 //50*4/20000000 = 10 uS, Timer Clock = Fsys/4
#define TIMER_DIV4_VALUE_1ms 65536 - 5000 //5000*4/20000000 = 1 mS, Timer Clock = Fsys/4
#endif
#ifdef FOSC_221184 // if Fsys = 22.1184 MHz
#define TIMER_DIV12_VALUE_10us 65536 - 18 //18*12/22118400 = 10 uS, // Timer divider = 12
#define TIMER_DIV12_VALUE_1ms 65536 - 1843 //1843*12/22118400 = 1 mS, // Timer divider = 12
#define TIMER_DIV12_VALUE_10ms 65536 - 18432 //18432*12/22118400 = 10 ms // Timer divider = 12
#define TIMER_DIV4_VALUE_10us 65536 - 56 //9*4/22118400 = 10 uS, // Timer divider = 4
#define TIMER_DIV4_VALUE_1ms 65536 - 5530 //923*4/22118400 = 1 mS, // Timer divider = 4
#define TIMER_DIV4_VALUE_100us 65536 - 553 //553*4/22118400 = 100 us // Timer divider = 4
#define TIMER_DIV4_VALUE_200us 65536 - 1106 //1106*4/22118400 = 200 us // Timer divider = 4
#define TIMER_DIV4_VALUE_500us 65536 - 2765 //2765*4/22118400 = 500 us // Timer divider = 4
#define TIMER_DIV16_VALUE_10ms 65536 - 13824 //1500*16/22118400 = 10 ms // Timer divider = 16
#define TIMER_DIV64_VALUE_30ms 65536 - 10368 //10368*64/22118400 = 30 ms // Timer divider = 64
#define TIMER_DIV128_VALUE_100ms 65536 - 17280 //17280*128/22118400 = 100 ms // Timer divider = 128
#define TIMER_DIV128_VALUE_200ms 65536 - 34560 //34560*128/22118400 = 200 ms // Timer divider = 128
#define TIMER_DIV256_VALUE_500ms 65536 - 43200 //43200*256/22118400 = 500 ms // Timer divider = 256
#define TIMER_DIV512_VALUE_1s 65536 - 43200 //43200*512/22118400 = 1 s // Timer divider = 512
#endif
#ifdef FOSC_240000 // if Fsys = 20 MHz
#define TIMER_DIV12_VALUE_10us 65536 - 20 //20*12/24000000 = 10 uS, // Timer divider = 12
#define TIMER_DIV12_VALUE_1ms 65536 - 2000 //2000*12/24000000 = 1 mS, // Timer divider = 12
#define TIMER_DIV12_VALUE_10ms 65536 - 20000 //2000*12/24000000 = 10 mS // Timer divider = 12
#define TIMER_DIV4_VALUE_10us 65536 - 60 //60*4/24000000 = 10 uS, // Timer divider = 4
#define TIMER_DIV4_VALUE_100us 65536 - 600 //600*4/24000000 = 100 us // Timer divider = 4
#define TIMER_DIV4_VALUE_200us 65536 - 1200 //1200*4/24000000 = 200 us // Timer divider = 4
#define TIMER_DIV4_VALUE_500us 65536 - 3000 //3000*4/24000000 = 500 us // Timer divider = 4
#define TIMER_DIV4_VALUE_1ms 65536 - 6000 //6000*4/24000000 = 1 mS, // Timer divider = 4
#define TIMER_DIV16_VALUE_10ms 65536 - 15000 //15000*16/24000000 = 10 ms // Timer divider = 16
#define TIMER_DIV64_VALUE_30ms 65536 - 11250 //11250*64/24000000 = 30 ms // Timer divider = 64
#define TIMER_DIV128_VALUE_100ms 65536 - 18750 //37500*128/24000000 = 200 ms // Timer divider = 128
#define TIMER_DIV128_VALUE_200ms 65536 - 37500 //37500*128/24000000 = 200 ms // Timer divider = 128
#define TIMER_DIV256_VALUE_500ms 65536 - 46875 //46875*256/24000000 = 500 ms // Timer divider = 256
#define TIMER_DIV512_VALUE_1s 65536 - 46875 //46875*512/24000000 = 1 s. // Timer Divider = 512
#endif
//-------------------- Timer0 function define --------------------
#define TIMER1_MODE0_ENABLE TMOD &= 0x0F
#define TIMER1_MODE1_ENABLE TMOD &= 0x0F; TMOD |= 0x10
#define TIMER1_MODE2_ENABLE TMOD &= 0x0F; TMOD |= 0x20
#define TIMER1_MODE3_ENABLE TMOD &= 0x0F; TMOD |= 0x3F
//-------------------- Timer1 function define --------------------
#define TIMER0_MODE0_ENABLE TMOD &= 0xF0
#define TIMER0_MODE1_ENABLE TMOD &= 0xF0; TMOD |= 0x01
#define TIMER0_MODE2_ENABLE TMOD &= 0xF0; TMOD |= 0x02
#define TIMER0_MODE3_ENABLE TMOD &= 0xF0; TMOD |= 0xF3
//-------------------- Timer2 function define --------------------
#define TIMER2_DIV_4 T2MOD |= 0x10; T2MOD &= 0x9F
#define TIMER2_DIV_16 T2MOD |= 0x20; T2MOD &= 0xAF
#define TIMER2_DIV_32 T2MOD |= 0x30; T2MOD &= 0xBF
#define TIMER2_DIV_64 T2MOD |= 0x40; T2MOD &= 0xCF
#define TIMER2_DIV_128 T2MOD |= 0x50; T2MOD &= 0xDF
#define TIMER2_DIV_256 T2MOD |= 0x60; T2MOD &= 0xEF
#define TIMER2_DIV_512 T2MOD |= 0x70
#define TIMER2_Auto_Reload_Delay_Mode T2CON &= ~SET_BIT0; T2MOD |= SET_BIT7; T2MOD |= SET_BIT3
#define TIMER2_Compare_Capture_Mode T2CON |= SET_BIT0; T2MOD &= ~SET_BIT7; T2MOD |= SET_BIT2
#define TIMER2_CAP0_Capture_Mode T2CON &= ~SET_BIT0; T2MOD = 0x89
#define TIMER2_CAP1_Capture_Mode T2CON &= ~SET_BIT0; T2MOD = 0x8A
#define TIMER2_CAP2_Capture_Mode T2CON &= ~SET_BIT0; T2MOD = 0x8B
//-------------------- Timer2 Capture define --------------------
//--- Falling Edge -----
#define IC0_P12_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC1_P11_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x01; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC2_P10_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x02; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC3_P00_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x03; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC3_P04_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x04; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC4_P01_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x05; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC5_P03_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x06; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC6_P05_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x07; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC7_P15_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x08; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC0_P12_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5
#define IC1_P11_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x10; CAPCON0 |= SET_BIT5; CAPCON0 |= SET_BIT5
#define IC2_P10_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x20; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5
#define IC3_P00_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x30; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5
#define IC3_P04_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x40; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5
#define IC4_P01_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x50; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5
#define IC5_P03_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x60; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5
#define IC6_P05_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x70; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5
#define IC7_P15_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x80; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5
#define IC0_P12_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6
#define IC1_P11_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x10; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6
#define IC2_P10_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x20; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6
#define IC3_P00_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x30; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6
#define IC3_P04_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x40; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6
#define IC4_P01_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x50; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6
#define IC5_P03_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x60; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6
#define IC6_P05_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x70; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6
#define IC7_P15_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x80; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6
//----- Rising edge ----
#define IC0_P12_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4;
#define IC1_P11_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x01; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4;
#define IC2_P10_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x02; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4;
#define IC3_P00_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x03; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4;
#define IC3_P04_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x04; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4;
#define IC4_P01_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x05; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4;
#define IC5_P03_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x06; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4;
#define IC6_P05_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x07; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4;
#define IC7_P15_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x08; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4;
#define IC0_P12_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0FCAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC1_P11_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x10; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC2_P10_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x20; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC3_P00_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x30; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC3_P04_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x40; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC4_P01_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x50; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC5_P03_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x60; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC6_P05_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x70; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC7_P15_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x80; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC0_P12_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC1_P11_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x01; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC2_P10_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x02; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC3_P00_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x03; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC3_P04_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x04; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC4_P01_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x05; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC5_P03_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x06; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC6_P05_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x07; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC7_P15_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x08; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
//-----BOTH edge ----
#define IC0_P12_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC1_P11_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x01; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC2_P10_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x02; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC3_P00_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x03; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC3_P04_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x04; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC4_P01_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x05; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC5_P03_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x06; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC6_P05_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x07; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC7_P15_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x08; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4
#define IC0_P12_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5
#define IC1_P11_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x10; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC2_P10_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x20; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC3_P00_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x30; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC3_P04_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x40; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC4_P01_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x50; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC5_P03_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x60; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC6_P05_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x70; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC7_P15_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x80; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5;
#define IC0_P12_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC1_P11_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x01; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC2_P10_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x02; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC3_P00_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x03; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC3_P04_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x04; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC4_P01_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x05; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC5_P03_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x06; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC6_P05_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x07; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define IC7_P15_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x08; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6;
#define TIMER2_IC2_DISABLE CAPCON0 &= ~SET_BIT6
#define TIMER2_IC1_DISABLE CAPCON0 &= ~SET_BIT5
#define TIMER2_IC0_DISABLE CAPCON0 &= ~SET_BIT4
/*****************************************************************************************
* For PWM setting
*****************************************************************************************/
//--------- PMW clock source select define ---------------------
#define PWM_CLOCK_FSYS CKCON &= 0xBF
#define PWM_CLOCK_TIMER1 CKCON |= 0x40
//--------- PWM clock devide define ----------------------------
#define PWM_CLOCK_DIV_2 PWMCON1 |= 0x01; PWMCON1 &= 0xF9
#define PWM_CLOCK_DIV_4 PWMCON1 |= 0x02; PWMCON1 &= 0xFA
#define PWM_CLOCK_DIV_8 PWMCON1 |= 0x03; PWMCON1 &= 0xFB
#define PWM_CLOCK_DIV_16 PWMCON1 |= 0x04; PWMCON1 &= 0xFC
#define PWM_CLOCK_DIV_32 PWMCON1 |= 0x05; PWMCON1 &= 0xFD
#define PWM_CLOCK_DIV_64 PWMCON1 |= 0x06; PWMCON1 &= 0xFE
#define PWM_CLOCK_DIV_128 PWMCON1 |= 0x07
//--------- PWM I/O select define ------------------------------
#define PWM5_P15_OUTPUT_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 |= 0x20; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P1.5 as PWM5 output enable
#define PWM5_P03_OUTPUT_ENABLE PIOCON0 |= 0x20 //P0.3 as PWM5
#define PWM4_P01_OUTPUT_ENABLE PIOCON0 |= 0x10 //P0.1 as PWM4 output enable
#define PWM3_P04_OUTPUT_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 |= 0x08; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P0.4 as PWM3 output enable
#define PWM3_P00_OUTPUT_ENABLE PIOCON0 |= 0x08 //P0.0 as PWM3
#define PWM2_P05_OUTPUT_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 |= 0x04; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P1.0 as PWM2 output enable
#define PWM2_P10_OUTPUT_ENABLE PIOCON0 |= 0x04 //P1.0 as PWM2
#define PWM1_P14_OUTPUT_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 |= 0x02; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P1.4 as PWM1 output enable
#define PWM1_P11_OUTPUT_ENABLE PIOCON0 |= 0x02 //P1.1 as PWM1
#define PWM0_P12_OUTPUT_ENABLE PIOCON0 |= 0x01 //P1.2 as PWM0 output enable
#define ALL_PWM_OUTPUT_ENABLE PIOCON0 = 0xFF; PIOCON1 = 0xFF
#define PWM5_P15_OUTPUT_DISABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 &= 0xDF; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P1.5 as PWM5 output disable
#define PWM5_P03_OUTPUT_DISABLE PIOCON0 &= 0xDF //P0.3 as PWM5
#define PWM4_P01_OUTPUT_DISABLE PIOCON0 &= 0xEF //P0.1 as PWM4 output disable
#define PWM3_P04_OUTPUT_DISABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 &= 0xF7; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P0.4 as PWM3 output disable
#define PWM3_P00_OUTPUT_DISABLE PIOCON0 &= 0xF7 //P0.0 as PWM3
#define PWM2_P05_OUTPUT_DISABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 &= 0xFB; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P1.0 as PWM2 output disable
#define PWM2_P10_OUTPUT_DISABLE PIOCON0 &= 0xFB //P1.0 as PWM2
#define PWM1_P14_OUTPUT_DISABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 &= 0xFD; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P1.4 as PWM1 output disable
#define PWM1_P11_OUTPUT_DISABLE PIOCON0 &= 0xFD //P1.1 as PWM1
#define PWM0_P12_OUTPUT_DISABLE PIOCON0 &= 0xFE //P1.2 as PWM0 output disable
#define ALL_PWM_OUTPUT_DISABLE PIOCON0 = 0x00; PIOCON1 = 0x00
//--------- PWM I/O Polarity Control ---------------------------
#define PWM5_OUTPUT_INVERSE PNP |= 0x20
#define PWM4_OUTPUT_INVERSE PNP |= 0x10
#define PWM3_OUTPUT_INVERSE PNP |= 0x08
#define PWM2_OUTPUT_INVERSE PNP |= 0x04
#define PWM1_OUTPUT_INVERSE PNP |= 0x02
#define PWM0_OUTPUT_INVERSE PNP |= 0x01
#define PWM_OUTPUT_ALL_INVERSE PNP = 0xFF
#define PWM5_OUTPUT_NORMAL PNP &= 0xDF
#define PWM4_OUTPUT_NORMAL PNP &= 0xEF
#define PWM3_OUTPUT_NORMAL PNP &= 0xF7
#define PWM2_OUTPUT_NORMAL PNP &= 0xFB
#define PWM1_OUTPUT_NORMAL PNP &= 0xFD
#define PWM0_OUTPUT_NORMAL PNP &= 0xFE
#define PWM_OUTPUT_ALL_NORMAL PNP = 0x00
//--------- PWM type define ------------------------------------
#define PWM_EDGE_TYPE PWMCON1 &= ~SET_BIT4
#define PWM_CENTER_TYPE PWMCON1 |= SET_BIT4
//--------- PWM mode define ------------------------------------
#define PWM_IMDEPENDENT_MODE PWMCON1 &= 0x3F
#define PWM_COMPLEMENTARY_MODE PWMCON1 |= 0x40; PWMCON1 &= 0x7F
#define PWM_SYNCHRONIZED_MODE PWMCON1 |= 0x80; PWMCON1 &= 0xBF
#define PWM_GP_MODE_ENABLE PWMCON1 |= 0x20
#define PWM_GP_MODE_DISABLE PWMCON1 &= 0xDF
//--------- PMW interrupt setting ------------------------------
#define PWM_FALLING_INT BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xCF; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP
#define PWM_RISING_INT BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC |= 0x10; PWMCON0 &= 0xDF; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP
#define PWM_CENTRAL_POINT_INT BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC |= 0x20; PWMCON0 &= 0xEF; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP
#define PWM_PERIOD_END_INT BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC |= 0x30; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP
//--------- PWM interrupt pin select ---------------------------
#define PWM_INT_PWM0 BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xF8; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP
#define PWM_INT_PWM1 BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xF8; PWMINTC |= 0x01; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP
#define PWM_INT_PWM2 BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xF8; PWMINTC |= 0x02; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP
#define PWM_INT_PWM3 BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xF8; PWMINTC |= 0x03; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP
#define PWM_INT_PWM4 BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xF8; PWMINTC |= 0x04; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP
#define PWM_INT_PWM5 BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xF8; PWMINTC |= 0x05; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP
//--------- PWM Dead time setting ------------------------------
#define PWM45_DEADTIME_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; PDTEN |= 0x04; EA = BIT_TMP
#define PWM34_DEADTIME_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; PDTEN |= 0x02; EA = BIT_TMP
#define PWM01_DEADTIME_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; PDTEN |= 0x01; EA = BIT_TMP
/*****************************************************************************************
* For ADC INIT setting
*****************************************************************************************/
#define Enable_ADC_AIN0 ADCCON0 &= 0xF0; P17_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT0; ADCCON1 |= SET_BIT0 //P17
#define Enable_ADC_AIN1 ADCCON0 &= 0xF0; ADCCON0 |= 0x01; P30_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT1; ADCCON1 |= SET_BIT0 //P30
#define Enable_ADC_AIN2 ADCCON0 &= 0xF0; ADCCON0 |= 0x02; P07_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT2; ADCCON1 |= SET_BIT0 //P07
#define Enable_ADC_AIN3 ADCCON0 &= 0xF0; ADCCON0 |= 0x03; P06_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT3; ADCCON1 |= SET_BIT0 //P06
#define Enable_ADC_AIN4 ADCCON0 &= 0xF0; ADCCON0 |= 0x04; P05_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT4; ADCCON1 |= SET_BIT0 //P05
#define Enable_ADC_AIN5 ADCCON0 &= 0xF0; ADCCON0 |= 0x05; P04_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT5; ADCCON1 |= SET_BIT0 //P04
#define Enable_ADC_AIN6 ADCCON0 &= 0xF0; ADCCON0 |= 0x06; P03_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT6; ADCCON1 |= SET_BIT0 //P03
#define Enable_ADC_AIN7 ADCCON0 &= 0xF0; ADCCON0 |= 0x07; P11_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT7; ADCCON1 |= SET_BIT0 //P11
#define Enable_ADC_BandGap ADCCON0 |= SET_BIT3; ADCCON0 &= 0xF8; ADCCON1 |= SET_BIT0 //Band-gap 1.22V
#define PWM0_FALLINGEDGE_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 &= ~SET_BIT3; ADCCON1 &= ~SET_BIT2; ADCCON1 |= SET_BIT1
#define PWM2_FALLINGEDGE_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 |= SET_BIT4; ADCCON1 &= ~SET_BIT3; ADCCON1 &= ~SET_BIT2; ADCCON1 |= SET_BIT1
#define PWM4_FALLINGEDGE_TRIG_ADC ADCCON0 |= SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 &= ~SET_BIT3; ADCCON1 &= ~SET_BIT2; ADCCON1 |= SET_BIT1
#define PWM0_RISINGEDGE_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 &= ~SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1
#define PWM2_RISINGEDGE_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 |= SET_BIT4; ADCCON1 &= ~SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1
#define PWM4_RISINGEDGE_TRIG_ADC ADCCON0 |= SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 &= ~SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1
#define PWM0_CENTRAL_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 |= SET_BIT3; ADCCON1 &= ~SET_BIT2; ADCCON1 |= SET_BIT1
#define PWM2_CENTRAL_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 |= SET_BIT4; ADCCON1 |= SET_BIT3; ADCCON1 &= ~SET_BIT2; ADCCON1 |= SET_BIT1
#define PWM4_CENTRAL_TRIG_ADC ADCCON0 |= SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 |= SET_BIT3; ADCCON1 &= ~SET_BIT2; ADCCON1 |= SET_BIT1
#define PWM0_END_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 |= SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1
#define PWM2_END_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 |= SET_BIT4; ADCCON1 |= SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1
#define PWM4_END_TRIG_ADC ADCCON0 |= SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 |= SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1
#define P04_FALLINGEDGE_TRIG_ADC ADCCON0 |= 0x30; ADCCON1 &= 0xF3; ADCCON1 |= SET_BIT1; ADCCON1 &= ~SET_BIT6
#define P13_FALLINGEDGE_TRIG_ADC ADCCON0 |= 0x30; ADCCON1 &= 0xF3; ADCCON1 |= SET_BIT1; ADCCON1 |= SET_BIT6
#define P04_RISINGEDGE_TRIG_ADC ADCCON0 |= 0x30; ADCCON1 &= ~SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1; ADCCON1 &= ~SET_BIT6
#define P13_RISINGEDGE_TRIG_ADC ADCCON0 |= 0x30; ADCCON1 &= ~SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1; ADCCON1 |= SET_BIT6
/*****************************************************************************************
* For SPI INIT setting
*****************************************************************************************/
#define SPICLK_DIV2 clr_SPR0; clr_SPR1
#define SPICLK_DIV4 set_SPR0; clr_SPR1
#define SPICLK_DIV8 clr_SPR0; set_SPR1
#define SPICLK_DIV16 set_SPR0; set_SPR1
#define Enable_SPI_Interrupt set_ESPI; set_EA
#define SS P15
/************************************** The End Of File **************************************/
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/I2C_Master.h
-27
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/************************************************************
* ProjectName: LT8522EX
* FileName: lt8522ex.c
* BuildData: 2014-03-27
* Version£º V1.00
* Company: Lontium
************************************************************/
//#include "stm8s.h"
#ifndef _I2C_MASTER_H
#define _I2C_MASTER_H
extern bit FLAG_I2C_ERROR;
extern u8 I2CADR;
//extern Pin_Status GET_GPIO_InputPin(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
extern void Delay_ms(u16 mscount);
extern u8 HDMI_ReadI2C_Byte(u8 RegAddr);
//extern bit HDMI_ReadI2C_ByteN(u8 RegAddr,u8 *p_data,u8 N);
extern bool HDMI_WriteI2C_Byte(u8 RegAddr, u8 d);
extern bool HDMI_WriteI2C_ByteN(u8 RegAddr, u8 *d,u8 N);
#endif
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/LT8912B.h
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/************************************************************
* ProjectName: LT8619C
* FileName: LT8912B.h
* BuildData: 2017-04-20
* Version£º V1.00
* Company: Lontium
************************************************************/
#ifndef _LT8912B_H
#define _LT8912B_H
#define _LT8912B_EVB_
#define _VESA_ 0x00
#define _JEIDA_ 0x20
#define _De_mode_ 0x08
#define _Sync_Mode_ 0x00
#define _8_Bit_Color_ 0x13
#define _6_Bit_Color_ 0x17
#define _HDMI_Output_ 0x01
#define _DVI_Output_ 0x00
#define _IIS_Output_ TRUE
#define _SPDIF_Output_ FALSE
#define _PLL_Devider_1 0x00; // no devide
#define _PLL_Devider_2 0x20; // /2 devide 2
#define _PLL_Devider_4 0x40; // /4 devide 4
#define _PLL_Devider_8 0x60; // /8 devide 8
#define _Channel_3210 0xa8
#define _Channel_0123 0x00
#define _PN_Swap_En 0x20
#define _PN_Swap_Dis 0x00
//*/
union Temp
{
u8 Temp8[4];
u16 Temp16[2];
u32 Temp32;
};
union Temp2
{
u8 Temp8[2];
u16 Temp16;//[2];
};
enum
{
H_act = 0,
V_act,
H_tol,
V_tol,
H_bp,
H_sync,
V_sync,
V_bp
};
//*
#define VESA_720x480_60 0
//#define VESA_800x600_60 1
#define VESA_1024x768_60 (VESA_720x480_60+1)
#define VESA_1280x720_60 (VESA_1024x768_60+1)
//#define VESA_1280x768_60 4
#define VESA_1280x800_60 (VESA_1280x720_60+1)
//#define VESA_1280x1024_60 6
//#define VESA_1360x768_60 7
//#define VESA_1366x768_60NB (VESA_1280x800_60+1)
#define VESA_1024x600_60 (VESA_1280x800_60+1)
//#define VESA_1400x1050_60 9
//#define VESA_1440x900_60 10
//#define VESA_1600x900_60RB 11
//#define VESA_1600x1200_60 12
//#define VESA_1680x1050_60 13
#define VESA_1920x1080_60 (VESA_1024x600_60+1)
//#define VESA_1920x1200_60 (VESA_1920x1080_60+1)
//#define VESA_1280x480_60 (VESA_1920x1080_60+1)
//#define VESA_1080x1920_60 16
//*/
extern u8 videoformat;
extern u8 Pre_videoformat;
extern void LT812B_Config(void);
extern void MIPI_Input_det(void);
extern void MIPIDig_Format_Config(void);
extern void DDSConfig(void);
extern void AudioIIsEn(void);
extern void MIPIRxLogicRes(void);
extern void LvdsPowerUp(void);
extern void LvdsPowerDown(void);
extern void Collpll_Config(void);
extern void LVDS_ScaleRatioConfig(void);
extern void LVDS_Bypass_Config( void );
extern void GCMWindow1080P(void);
extern void GCMWindow720P(void);
extern void GCMWindow480P(void);
extern void GCMWindow576P(void);
extern void GCMWindow1024x600P( void );
void GCMWindow1280x800P( void );
#endif
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/N76E003.h
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/*--------------------------------------------------------------------------
N76E003.H
Header file for Nuvoton N76E003
--------------------------------------------------------------------------*/
/*
51系列单片机内部主要有四大功能模块，分别是I/O口模块、中断模块、定时器模块和
串口通信模块(串行I/O口)
51单片机内部共有21个SFR，其布局如图2，从图中可以看出，每个SFR占1个字节，
多数字节单元中的每一位又有专用的“位名称”。这21个SFR又按是否可以位寻址
分为两大部分，ACC、IE、P1等11个可以位寻址，SP、TMOD等不可以位寻址。
*/
//*
sfr P0 = 0x80;
sfr SP = 0x81;
sfr DPL = 0x82;
sfr DPH = 0x83;
sfr RCTRIM0 = 0x84;
sfr RCTRIM1 = 0x85;
sfr RWK = 0x86;
sfr PCON = 0x87;
sfr TCON = 0x88;
sfr TMOD = 0x89;
sfr TL0 = 0x8A;
sfr TL1 = 0x8B;
sfr TH0 = 0x8C;
sfr TH1 = 0x8D;
sfr CKCON = 0x8E;
sfr WKCON = 0x8F;
sfr P1 = 0x90;
sfr SFRS = 0x91; //TA Protection
sfr CAPCON0 = 0x92;
sfr CAPCON1 = 0x93;
sfr CAPCON2 = 0x94;
sfr CKDIV = 0x95;
sfr CKSWT = 0x96; //TA Protection
sfr CKEN = 0x97; //TA Protection
sfr SCON = 0x98;
sfr SBUF = 0x99;
sfr SBUF_1 = 0x9A;
sfr EIE = 0x9B;
sfr EIE1 = 0x9C;
sfr CHPCON = 0x9F; //TA Protection
sfr P2 = 0xA0;
sfr AUXR1 = 0xA2;
sfr BODCON0 = 0xA3; //TA Protection
sfr IAPTRG = 0xA4; //TA Protection
sfr IAPUEN = 0xA5; //TA Protection
sfr IAPAL = 0xA6;
sfr IAPAH = 0xA7;
sfr IE = 0xA8;
sfr SADDR = 0xA9;
sfr WDCON = 0xAA; //TA Protection
sfr BODCON1 = 0xAB; //TA Protection
sfr P3M1 = 0xAC;
sfr P3S = 0xAC; //Page1
sfr P3M2 = 0xAD;
sfr P3SR = 0xAD; //Page1
sfr IAPFD = 0xAE;
sfr IAPCN = 0xAF;
sfr P3 = 0xB0;
sfr P0M1 = 0xB1;
sfr P0S = 0xB1; //Page1
sfr P0M2 = 0xB2;
sfr P0SR = 0xB2; //Page1
sfr P1M1 = 0xB3;
sfr P1S = 0xB3; //Page1
sfr P1M2 = 0xB4;
sfr P1SR = 0xB4; //Page1
sfr P2S = 0xB5;
sfr IPH = 0xB7;
sfr PWMINTC = 0xB7; //Page1
sfr IP = 0xB8;
sfr SADEN = 0xB9;
sfr SADEN_1 = 0xBA;
sfr SADDR_1 = 0xBB;
sfr I2DAT = 0xBC;
sfr I2STAT = 0xBD;
sfr I2CLK = 0xBE;
sfr I2TOC = 0xBF;
sfr I2CON = 0xC0;
sfr I2ADDR = 0xC1;
sfr ADCRL = 0xC2;
sfr ADCRH = 0xC3;
sfr T3CON = 0xC4;
sfr PWM4H = 0xC4; //Page1
sfr RL3 = 0xC5;
sfr PWM5H = 0xC5; //Page1
sfr RH3 = 0xC6;
sfr PIOCON1 = 0xC6; //Page1
sfr TA = 0xC7;
sfr T2CON = 0xC8;
sfr T2MOD = 0xC9;
sfr RCMP2L = 0xCA;
sfr RCMP2H = 0xCB;
sfr TL2 = 0xCC;
sfr PWM4L = 0xCC; //Page1
sfr TH2 = 0xCD;
sfr PWM5L = 0xCD; //Page1
sfr ADCMPL = 0xCE;
sfr ADCMPH = 0xCF;
sfr PSW = 0xD0;
sfr PWMPH = 0xD1;
sfr PWM0H = 0xD2;
sfr PWM1H = 0xD3;
sfr PWM2H = 0xD4;
sfr PWM3H = 0xD5;
sfr PNP = 0xD6;
sfr FBD = 0xD7;
sfr PWMCON0 = 0xD8;
sfr PWMPL = 0xD9;
sfr PWM0L = 0xDA;
sfr PWM1L = 0xDB;
sfr PWM2L = 0xDC;
sfr PWM3L = 0xDD;
sfr PIOCON0 = 0xDE;
sfr PWMCON1 = 0xDF;
sfr ACC = 0xE0;
sfr ADCCON1 = 0xE1;
sfr ADCCON2 = 0xE2;
sfr ADCDLY = 0xE3;
sfr C0L = 0xE4;
sfr C0H = 0xE5;
sfr C1L = 0xE6;
sfr C1H = 0xE7;
sfr ADCCON0 = 0xE8;
sfr PICON = 0xE9;
sfr PINEN = 0xEA;
sfr PIPEN = 0xEB;
sfr PIF = 0xEC;
sfr C2L = 0xED;
sfr C2H = 0xEE;
sfr EIP = 0xEF;
sfr B = 0xF0;
sfr CAPCON3 = 0xF1;
sfr CAPCON4 = 0xF2;
sfr SPCR = 0xF3;
sfr SPCR2 = 0xF3; //Page1
sfr SPSR = 0xF4;
sfr SPDR = 0xF5;
sfr AINDIDS = 0xF6;
sfr EIPH = 0xF7;
sfr SCON_1 = 0xF8;
sfr PDTEN = 0xF9; //TA Protection
sfr PDTCNT = 0xFA; //TA Protection
sfr PMEN = 0xFB;
sfr PMD = 0xFC;
sfr EIP1 = 0xFE;
sfr EIPH1 = 0xFF;
/* BIT Registers */
/* SCON_1 */
sbit SM0_1 = SCON_1^7;
sbit FE_1 = SCON_1^7;
sbit SM1_1 = SCON_1^6;
sbit SM2_1 = SCON_1^5;
sbit REN_1 = SCON_1^4;
sbit TB8_1 = SCON_1^3;
sbit RB8_1 = SCON_1^2;
sbit TI_1 = SCON_1^1;
sbit RI_1 = SCON_1^0;
/* ADCCON0 */
sbit ADCF = ADCCON0^7;
sbit ADCS = ADCCON0^6;
sbit ETGSEL1 = ADCCON0^5;
sbit ETGSEL0 = ADCCON0^4;
sbit ADCHS3 = ADCCON0^3;
sbit ADCHS2 = ADCCON0^2;
sbit ADCHS1 = ADCCON0^1;
sbit ADCHS0 = ADCCON0^0;
/* PWMCON0 */
sbit PWMRUN = PWMCON0^7;
sbit LOAD = PWMCON0^6;
sbit PWMF = PWMCON0^5;
sbit CLRPWM = PWMCON0^4;
/* PSW */
sbit CY = PSW^7;
sbit AC = PSW^6;
sbit F0 = PSW^5;
sbit RS1 = PSW^4;
sbit RS0 = PSW^3;
sbit OV = PSW^2;
sbit P = PSW^0;
/* T2CON */
sbit TF2 = T2CON^7;
sbit TR2 = T2CON^2;
sbit CM_RL2 = T2CON^0;
/* I2CON */
sbit I2CEN = I2CON^6;
sbit STA = I2CON^5;
sbit STO = I2CON^4;
sbit SI = I2CON^3;
sbit AA = I2CON^2;
sbit I2CPX = I2CON^0;
/* IP */
sbit PADC = IP^6;
sbit PBOD = IP^5;
sbit PS = IP^4;
sbit PT1 = IP^3;
sbit PX1 = IP^2;
sbit PT0 = IP^1;
sbit PX0 = IP^0;
/* P3 */
sbit P30 = P3^0;
/* IE */
sbit EA = IE^7;
sbit EADC = IE^6;
sbit EBOD = IE^5;
sbit ES = IE^4;
sbit ET1 = IE^3;
sbit EX1 = IE^2;
sbit ET0 = IE^1;
sbit EX0 = IE^0;
/* P2 */
sbit P20 = P2^0;
/* SCON */
sbit SM0 = SCON^7;
sbit FE = SCON^7;
sbit SM1 = SCON^6;
sbit SM2 = SCON^5;
sbit REN = SCON^4;
sbit TB8 = SCON^3;
sbit RB8 = SCON^2;
sbit TI = SCON^1;
sbit RI = SCON^0;
/* P1 */
sbit P17 = P1^7;
sbit P16 = P1^6;
sbit TXD_1 = P1^6;
sbit P15 = P1^5;
sbit P14 = P1^4;
sbit SDA = P1^4;
sbit P13 = P1^3;
sbit SCL = P1^3;
sbit P12 = P1^2;
sbit P11 = P1^1;
sbit P10 = P1^0;
/* TCON */
sbit TF1 = TCON^7;
sbit TR1 = TCON^6;
sbit TF0 = TCON^5;
sbit TR0 = TCON^4;
sbit IE1 = TCON^3;
sbit IT1 = TCON^2;
sbit IE0 = TCON^1;
sbit IT0 = TCON^0;
/* P0 */
sbit P07 = P0^7;
sbit RXD = P0^7;
sbit P06 = P0^6;
sbit TXD = P0^6;
sbit P05 = P0^5;
sbit P04 = P0^4;
sbit STADC = P0^4;
sbit P03 = P0^3;
sbit P02 = P0^2;
sbit RXD_1 = P0^2;
sbit P01 = P0^1;
sbit MISO = P0^1;
sbit P00 = P0^0;
sbit MOSI = P0^0;
//*/
typedef bit BIT;
typedef unsigned char UINT8;
typedef unsigned int UINT16;
typedef unsigned long UINT32;
typedef unsigned char uint8_t;
typedef unsigned int uint16_t;
typedef unsigned long uint32_t;
typedef unsigned char u8;
typedef unsigned int u16;
typedef unsigned long u32;
typedef enum {FALSE = 0, TRUE = !FALSE} PinStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
typedef enum
{
Bit_RESET = 0,
Bit_SET = !Bit_RESET
}bool;
typedef enum
{
OFF = 0,
ON = 1
}
Fun_Status;
typedef enum
{
LOW = 0,
HIGH = !LOW
}
Pin_Status;
typedef enum
{
Input = 0,
Output = !Input
}
GPIO_Status;
#define CID_READ 0x0B
#define DID_READ 0x0C
#define ERASE_APROM 0x22
#define READ_APROM 0x00
#define PROGRAM_APROM 0x21
#define ERASE_LDROM
#define READ_LDROM
#define PROGRAM_LDROM
#define READ_CFG 0xC0
#define PROGRAM_CFG 0xE1
#define READ_UID 0x04
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/SFR_Macro.h
-1161
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/include.h
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/************************************************************
* ProjectName: LT8619C
* FileName: Include.h
* BuildData: 2014-03-27
* Version£º V1.00
* Company: Lontium
************************************************************/
#ifndef _INCLUDE_H
#define _INCLUDE_H
#define _N76E003_
#include <stdarg.h>
#include "N76E003.h"
#include "SFR_Macro.h"
#include "Function_define.h"
#include "string.h"
#include "Delay.h"
#include "stdio.h"
#include "type.h"
#include "Uart0.h"
#include "main.h"
#include "i2c_master.h"
#include "LT8912B.h"
//#include "interrupt.h"
#endif
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/main.h
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/************************************************************
* ProjectName: LT86104EX
* FileName: main.h
* BuildData: 2013-01-05
* Version£º V3.20
* Company: Lontium
************************************************************/
#ifndef _MAIN_H
#define _MAIN_H
#define _uart_debug_
//#define _LVDS_Output_
#ifdef _LVDS_Output_
//#define _LVDS_Bypass_
//extern bit LVDS_Output_En; // = 1; //
extern u16 Panel_Pixel_CLK; // = 4925; // 49.25MHz
extern u8 PLL_Devider;
extern u8 LVDS_Map; // = _VESA_;
extern u8 LVDS_mode; // = _Sync_Mode_;
extern u8 Color_Depth; // = _8_Bit_Color_;
extern const u16 Panel_Timing[8];
#endif
extern u8 MIPI_Lane; // = 2; // 2 lane ; 0 : 4 lane
extern u8 MIPI_Lane_CH_Swap;
extern u8 MIPI_Lane_PN_Swap;
extern u8 HDMI_DVI_Output;
extern bit IIS_Format_En; // 1: IIS ; 0 : SPDIF
extern bit Test_Pattern_En;
extern bit SDA_Ack;
extern const u16 MIPI_Timing[6][8];
extern void GPIO_Initial( void );
//extern void CLK_Configuration( void );
#endif
/************************************** The End Of File **************************************/
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/type.h
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#ifndef _TYPE_H
#define _TYPE_H
//Variable Type Definition
typedef char CHAR, *PCHAR ;
typedef unsigned char uchar, *puchar ;
typedef unsigned char UCHAR, *PUCHAR ;
typedef unsigned char byte, *pbyte ;
typedef unsigned char BYTE, *PBYTE ;
typedef short SHORT, *PSHORT ;
typedef unsigned short ushort, *pushort ;
typedef unsigned short USHORT, *PUSHORT ;
typedef unsigned short word, *pword ;
typedef unsigned short WORD, *PWORD ;
typedef long LONG, *PLONG ;
typedef unsigned long ulong, *pulong ;
typedef unsigned long ULONG, *PULONG ;
typedef unsigned long dword, *pdword ;
typedef unsigned long DWORD, *PDWORD ;
typedef unsigned int UINT, uint;
//Public Definition
#define HIGH 1
#define LOW 0
#ifndef NULL
#define NULL (void *)0
#endif
#endif
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/uart0.h
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#ifndef _UART0_H
#define _UART0_H
void InitialUART0_Timer1(UINT32 u32Baudrate); //T1M = 1, SMOD = 1
void InitialUART0_Timer3(UINT32 u32Baudrate); //Timer3 as Baudrate, SMOD=1, Prescale=0
//void Send_Data_To_UART0(UINT8 c);
//UINT8 Receive_Data_From_UART0(void);
//
//UINT8 UID_BYTE(UINT8 Addr);
//void READ_MCU_UID(void);
//void Debug_printf(unsigned char *str);
//void printByte(u8 U8Data);
//void printByteWithSpace(u8 U8Data);
//void printWord(u16 U16Data);
extern void printdec_u32(u32 u32_dec);
extern void print(char* fmt, ...);
extern void printhex(int hex);
#endif
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/main.c
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/************************************************************
* ProjectName: LT8619C
* FileName: Main.c
* BuildData: 2017-04-20
* Version： V1.00
* Company: Lontium
************************************************************/
#include "include.h"
u8 MIPI_Lane; // = 2; // 2 lane ; 0 : 4 lane
u8 MIPI_Lane_CH_Swap;
u8 MIPI_Lane_PN_Swap;
u8 HDMI_DVI_Output; // _HDMI_Output_ ; _DVI_Output_
bit IIS_Format_En; // 1: IIS ; 0 : SPDIF
bit Test_Pattern_En;
// bit LT8912B_IIC_En;
bit SDA_Ack;
const u16 MIPI_Timing[6][8] =
{
//H_act V_act H_total V_total H_BP H_sync V_sync V_BP
{ 720, 480, 858, 525, 60, 62, 6, 30 }, // 480P Vesa Timing
{ 1024, 768, 1344, 806, 160, 136, 6, 29 }, // 1024x768
{ 1280, 720, 1650, 750, 220, 40, 5, 20 }, // 720P Vesa Timing
{ 1280, 800, 1440, 823, 80, 32, 6, 14 }, // 1280x800 timing
{ 1024, 600, 1344, 635, 140, 20, 3, 20 }, // 1024x600
// { 1024, 600, 1274, 645, 80, 10, 10, 23 }, // 1024x600
{ 1920, 1080, 2200, 1125, 148, 44, 5, 36 }, // 1080P Vesa Timing
// { 1920, 1200, 2080, 1235, 80, 32, 6, 26 }, // 1920x1200 154MHz Vesa Timing
// { 1280, 480, 1460, 530, 80, 20, 10, 20 }, // 1280x480
};
#ifdef _LVDS_Output_
// bit LVDS_Output_En; // = 1; //
u16 Panel_Pixel_CLK; // = 4925; // 49.25MHz
u8 PLL_Devider;
u8 LVDS_Map; // = _VESA_;
u8 LVDS_mode; // = _Sync_Mode_;
u8 Color_Depth; // = _8_Bit_Color_;
// 根据LVDS屏规格书设置LVDS输出s的屏参:
const u16 Panel_Timing[8] =
//H_act V_act H_total V_total H_BP H_sync V_sync V_BP
// {1920, 1080, 2200, 1125, 148, 44, 5, 36};// 1080P Vesa Timing
// {1280, 800, 1440, 823, 80, 32, 6, 14};// 1280x800
{ 1024, 600, 1344, 635, 140, 20, 3, 20 }; // 1024x600
// { 1024, 600, 1274, 645, 80, 10, 10, 23 }; // 1024x600
// { 1280, 480, 1460, 530, 80, 20, 10, 20 };
#endif
#ifdef _LT8912B_EVB_ // for 8912B demo board
/***********************************************************
***********************************************************/
void GPIO_Initial( void )
{
P03_OpenDrain_Mode; // OpenDrain_Mode // 8912 SDA
P04_OpenDrain_Mode; // OpenDrain_Mode // 8912 SCL
P00_OpenDrain_Mode; // 8912 Reset // P03_PushPull_Mode; P03_OpenDrain_Mode
// P01_Input_Mode; // IRQ
P13_Input_Mode;
P14_Input_Mode;
// P11_PushPull_Mode;
//EA=1;
InitialUART0_Timer1( 115200 ); //UART_INTI
// Enable_INT_Port0;
// Enable_BIT1_FallEdge_Trig;
// set_EPI;
//set_EX1;
//set_IT1;
//set_IE1;
// set_EA;
}
#endif
#define _LT8912B_RSTN_LOW P00 = 0
#define _LT8912B_RSTN_High P00 = 1
#ifdef _LT8912B_EVB_ // for 8912B demo
/***********************************************************
****************************/
void Initstate_LT8912B( void )
{
// LT8912_IIC_En = 1;
I2CADR = 0x92;
}
#endif
#ifdef _LT8912B_EVB_ // for 8912B demo
/***********************************************************
***********************************************************/
void LT8912B_Reset( void )
{
_LT8912B_RSTN_LOW;
Delay_ms( 100 );
_LT8912B_RSTN_High;
Delay_ms( 100 );
}
#endif
/***********************************************************
***********************************************************/
void LT8912B_Config( void )
{
HDMI_DVI_Output = _HDMI_Output_; // _HDMI_Output_ ; _DVI_Output_
IIS_Format_En = _IIS_Output_; // 1: IIS ; 0 : SPDIF
MIPI_Lane = 4; // 4 lane ; 0 ~ 4 lane
MIPI_Lane_CH_Swap = _Channel_0123; // _Channel_3210; _Channel_0123
MIPI_Lane_PN_Swap = _PN_Swap_Dis; // _PN_Swap_En; _PN_Swap_Dis
Test_Pattern_En = 1; //
#ifdef _LVDS_Output_
// if( LVDS_Output_En )
{
Panel_Pixel_CLK = 5125; // 51.25MHz
PLL_Devider = _PLL_Devider_1; // _PLL_Devider_1;_PLL_Devider_2;_PLL_Devider_4;_PLL_Devider_8
LVDS_Map = _VESA_; // _VESA_ ; _JEIDA_
LVDS_mode = _Sync_Mode_; // _Sync_Mode_ ; _De_Mode_
Color_Depth = _8_Bit_Color_; // _8_Bit_Color_ ; _6_Bit_Color_
}
#endif
}
/***********************************************************
***********************************************************/
void main( void )
{
u8 temp = 0x00;
// CLK_Configuration( );
GPIO_Initial( );
Delay_ms( 200 );
Delay_ms( 200 );
Delay_ms( 200 );
Delay_ms( 200 );
Delay_ms( 200 );
print( "\r\n**********************start*************************" );
Initstate_LT8912B( );
LT8912B_Reset( );
print( "\r\n " );
print( "\r\n*****************LT8912B reset done*****************" );
LT8912B_Config( );
videoformat = VESA_1280x800_60; // VESA_1280x800_60 ;
LT812B_Config( );
print( "\r\n " );
print( "\r\n****************LT8912B Initial done****************" );
print( "\r\n " );
/*
if( Test_Pattern_En )
{
GCMWindow1080P( );
// GCMWindow1280x480P();
// GCMWindow720P( );
// GCMWindow480P( );
// GCMWindow576P( );
}
//*/
#ifdef _LVDS_Output_
// if( LVDS_Output_En )
{
Collpll_Config( );
LVDS_ScaleRatioConfig( );
Delay_ms( 300 );
LvdsPowerUp( );
}
#endif
Delay_ms( 200 );
while( 1 )
{
#if 1
if( temp < 10 )
{
// temp++;
MIPI_Input_det( );
if( Pre_videoformat != videoformat )
{
Pre_videoformat = videoformat;
if( videoformat != 0xff )
{
#ifdef _LVDS_Output_
// if( LVDS_Output_En )
{
LvdsPowerDown( );
}
#endif
//*
MIPIDig_Format_Config( );
DDSConfig( );
AudioIIsEn( );
MIPIRxLogicRes( );
I2CADR = 0x92;
HDMI_WriteI2C_Byte( 0x70, 0x00 ); // pattern disable
print( "\r\n " );
print( "\r\nLT8912B HDMI config done..." );
print( "\r\n " );
//*/
// LT812B_Config( );
#ifdef _LVDS_Output_
#ifdef _LVDS_Bypass_
LVDS_Bypass_Config( );
#else
Collpll_Config( );
LVDS_ScaleRatioConfig( );
#endif
Delay_ms( 300 );
LvdsPowerUp( );
#endif
}
//*
else
if( Test_Pattern_En )
{
GCMWindow1280x800P( );
#ifdef _LVDS_Output_
videoformat = VESA_1024x600_60;
Collpll_Config( );
LVDS_ScaleRatioConfig( );
Delay_ms( 300 );
LvdsPowerUp( );
videoformat = 0xff;
#endif
// GCMWindow1280x480P();
// GCMWindow720P( );
// GCMWindow480P( );
// GCMWindow576P( );
} //*/
}
Delay_ms( 1000 );
}
#endif
}
}
/************************************** The End Of File **************************************/
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/LT8912B_EVB.uvgui.HUAWEI
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<Header>### uVision Project, (C) Keil Software</Header>
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<lExt>*.lib</lExt>
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/LT8912B_EVB.uvproj
-463
View File
@@ -1,463 +0,0 @@
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/Delay.lst
-163
View File
@@ -1,163 +0,0 @@
C51 COMPILER V9.54 DELAY 06/12/2026 11:01:29 PAGE 1
C51 COMPILER V9.54, COMPILATION OF MODULE DELAY
OBJECT MODULE PLACED IN .\Objects\Delay.obj
COMPILER INVOKED BY: D:\Keil\MDK\download\C51\BIN\C51.EXE ..\src\Delay.c LARGE OPTIMIZE(8,SPEED) BROWSE INCDIR(..\inc) D
-EFINE(FOSC_160000) DEBUG OBJECTEXTEND PRINT(.\Listings\Delay.lst) TABS(2) OBJECT(.\Objects\Delay.obj)
line level source
1 /*--------------------------------------------------------------------------------------------------------
--*/
2 /*
- */
3 /* Copyright(c) 2016 Nuvoton Technology Corp. All rights reserved.
- */
4 /*
- */
5 /*--------------------------------------------------------------------------------------------------------
--*/
6
7 //********************************************************************************************************
-***
8 // Nuvoton Technoledge Corp.
9 // Website: http://www.nuvoton.com
10 // E-Mail : MicroC-8bit@nuvoton.com
11 // Date : Apr/21/2016
12 //********************************************************************************************************
-***
13
14 #include "Include.h"
15
16 bit BIT_TMP;
17
18
19 /***********************************************************
20
21 ***********************************************************/
22 void Timer0_Delay100us( UINT32 u32CNT )
23 {
24 1 clr_T0M; //T0M=0, Timer0 Clock = Fsys/12
25 1 TMOD |= 0x01; //Timer0 is 16-bit mode
26 1 set_TR0; //Start Timer0
27 1 while( u32CNT != 0 )
28 1 {
29 2 TL0 = LOBYTE( TIMER_DIV12_VALUE_100us ); //Find define in "Function_define.h" "TIMER VALUE"
30 2 TH0 = HIBYTE( TIMER_DIV12_VALUE_100us );
31 2 while( TF0 != 1 )
32 2 {
33 3 ; //Check Timer0 Time-Out Flag
34 3 }
35 2 clr_TF0;
36 2 u32CNT--;
37 2 }
38 1 clr_TR0; //Stop Timer0
39 1 }
40
41 /***********************************************************
42
43 ***********************************************************/
44 void Timer0_Delay1ms( UINT32 u32CNT )
45 {
46 1 clr_T0M; //T0M=0, Timer0 Clock = Fsys/12
47 1 TMOD |= 0x01; //Timer0 is 16-bit mode
C51 COMPILER V9.54 DELAY 06/12/2026 11:01:29 PAGE 2
48 1 set_TR0; //Start Timer0
49 1 while( u32CNT != 0 )
50 1 {
51 2 TL0 = LOBYTE( TIMER_DIV12_VALUE_1ms ); //Find define in "Function_define.h" "TIMER VALUE"
52 2 TH0 = HIBYTE( TIMER_DIV12_VALUE_1ms );
53 2 while( TF0 != 1 )
54 2 {
55 3 ; //Check Timer0 Time-Out Flag
56 3 }
57 2 clr_TF0;
58 2 u32CNT--;
59 2 }
60 1 clr_TR0; //Stop Timer0
61 1 }
62
63 /*
64 //------------------------------------------------------------------------------
65 void Timer1_Delay10ms(UINT32 u32CNT)
66 {
67 clr_T1M; //T1M=0, Timer1 Clock = Fsys/12
68 TMOD |= 0x10; //Timer1 is 16-bit mode
69 set_TR1; //Start Timer1
70 while (u32CNT != 0)
71 {
72 TL1 = LOBYTE(TIMER_DIV12_VALUE_10ms); //Find define in "Function_define.h" "TIMER VALUE"
73 TH1 = HIBYTE(TIMER_DIV12_VALUE_10ms);
74 while (TF1 != 1); //Check Timer1 Time-Out Flag
75 clr_TF1;
76 u32CNT --;
77 }
78 clr_TR1; //Stop Timer1
79 }
80 //------------------------------------------------------------------------------
81 void Timer2_Delay500us(UINT32 u32CNT)
82 {
83 clr_T2DIV2; //Timer2 Clock = Fsys/4
84 clr_T2DIV1;
85 set_T2DIV0;
86 set_TR2; //Start Timer2
87 while (u32CNT != 0)
88 {
89 TL2 = LOBYTE(TIMER_DIV4_VALUE_500us); //Find define in "Function_define.h" "TIMER VALUE"
90 TH2 = HIBYTE(TIMER_DIV4_VALUE_500us);
91 while (TF2 != 1); //Check Timer2 Time-Out Flag
92 clr_TF2;
93 u32CNT --;
94 }
95 clr_TR2; //Stop Timer2
96 }
97 //------------------------------------------------------------------------------
98 void Timer3_Delay100ms(UINT32 u32CNT)
99 {
100 T3CON = 0x07; //Timer3 Clock = Fsys/128
101 set_TR3; //Trigger Timer3
102 while (u32CNT != 0)
103 {
104 RL3 = LOBYTE(TIMER_DIV128_VALUE_100ms); //Find define in "Function_define.h" "TIMER VALUE"
105 RH3 = HIBYTE(TIMER_DIV128_VALUE_100ms);
106 while ((T3CON&SET_BIT4) != SET_BIT4); //Check Timer3 Time-Out Flag
107 clr_TF3;
108 u32CNT --;
109 }
C51 COMPILER V9.54 DELAY 06/12/2026 11:01:29 PAGE 3
110 clr_TR3; //Stop Timer3
111 }
112 //------------------------------------------------------------------------------
113 void Timer3_Delay10us(UINT32 u32CNT)
114 {
115 T3CON = 0x07; //Timer3 Clock = Fsys/128
116 set_TR3; //Trigger Timer3
117 while (u32CNT != 0)
118 {
119 RL3 = LOBYTE(TIMER_DIV4_VALUE_10us); //Find define in "Function_define.h" "TIMER VALUE"
120 RH3 = HIBYTE(TIMER_DIV4_VALUE_10us);
121 while ((T3CON&SET_BIT4) != SET_BIT4); //Check Timer3 Time-Out Flag
122 clr_TF3;
123 u32CNT --;
124 }
125 clr_TR3; //Stop Timer3
126 }
127 //*/
128
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 178 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- 8
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = 1 ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/I2C_MASTER.lst
-294
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@@ -1,294 +0,0 @@
C51 COMPILER V9.54 I2C_MASTER 06/12/2026 11:01:29 PAGE 1
C51 COMPILER V9.54, COMPILATION OF MODULE I2C_MASTER
OBJECT MODULE PLACED IN .\Objects\I2C_MASTER.obj
COMPILER INVOKED BY: D:\Keil\MDK\download\C51\BIN\C51.EXE ..\src\I2C_MASTER.C LARGE OPTIMIZE(8,SPEED) BROWSE INCDIR(..\i
-nc) DEFINE(FOSC_160000) DEBUG OBJECTEXTEND PRINT(.\Listings\I2C_MASTER.lst) TABS(2) OBJECT(.\Objects\I2C_MASTER.obj)
line level source
1 /************************************************************
2 * ProjectName: LT8522EX
3 * FileName: lt8522ex.c
4 * BuildData: 2014-03-27
5 * Version£º V1.00
6 * Company: Lontium
7 ************************************************************/
8
9 #include "include.h"
10
11 //bit FLAG_I2C_ERROR;
12 bit ack;
13 u8 I2CADR = 0x90;
14
15 void Delay_ms( u16 mscount )
16 {
17 1 u16 i, x;
18 1 for( i = 0; i < mscount; i++ )
19 1 {
20 2 for( x = 0; x < 2000; x++ )
21 2 {
22 3 ;
23 3 }
24 2 // IWDG_ReloadCounter();
25 2 }
26 1 }
27
28 #define SCL_H P04=1
29 #define SCL_L P04=0
30
31 #define SDA_H P03=1
32 #define SDA_L P03=0
33
34 #define I2C_SDA_READ P03
35
36 static void I2C_Delay_us(u8 uscount)
37 {
38 1 u8 x;
39 1 for(x=0; x<uscount; x++)
40 1 {
41 2 ;
42 2 }
43 1 }
44
45 static void Start_I2c(void)
46 {
47 1 SDA_H;
48 1 I2C_Delay_us(1);
49 1 SCL_H;
50 1 I2C_Delay_us(10);
51 1 SDA_L;
52 1 I2C_Delay_us(7);
53 1 SCL_L;
54 1 I2C_Delay_us(1);
C51 COMPILER V9.54 I2C_MASTER 06/12/2026 11:01:29 PAGE 2
55 1 }
56
57 static void Stop_I2c(void)
58 {
59 1 SDA_L;
60 1 I2C_Delay_us(2);
61 1 SCL_H;
62 1 I2C_Delay_us(10);
63 1 SDA_H;
64 1 I2C_Delay_us(10);
65 1 }
66
67
68 static void I2C_SendByte(u8 c)
69 {
70 1 u8 bit_Cnt;
71 1
72 1 for(bit_Cnt=0; bit_Cnt<8; bit_Cnt++)
73 1 {
74 2 if((c<<bit_Cnt) & 0x80)
75 2 {
76 3 SDA_H;
77 3 }
78 2 else
79 2 {
80 3 SDA_L;
81 3 }
82 2 I2C_Delay_us(3);
83 2 SCL_H;
84 2 I2C_Delay_us(4);
85 2 SCL_L;
86 2 }
87 1
88 1 I2C_Delay_us(1);
89 1 SDA_H;
90 1 I2C_Delay_us(3);
91 1 SCL_H;
92 1 I2C_Delay_us(3);
93 1
94 1 if(I2C_SDA_READ != 0)
95 1 {
96 2 ack=0;
97 2 }
98 1 else
99 1 {
100 2 ack=1;
101 2 }
102 1 SCL_L;
103 1 I2C_Delay_us(3);
104 1 }
105
106 static u8 RcvByte(void)
107 {
108 1 u8 retc;
109 1 u8 bit_Cnt;
110 1
111 1 retc=0;
112 1 SDA_H;
113 1 for (bit_Cnt=0; bit_Cnt<8; bit_Cnt++)
114 1 {
115 2 I2C_Delay_us(1);
116 2 SCL_L;
C51 COMPILER V9.54 I2C_MASTER 06/12/2026 11:01:29 PAGE 3
117 2 I2C_Delay_us(4);
118 2 SCL_H;
119 2 I2C_Delay_us(2);
120 2 retc=retc<<1;
121 2 if (I2C_SDA_READ != 0)
122 2 {
123 3 retc = retc+1;
124 3 }
125 2 I2C_Delay_us(2);
126 2 }
127 1 SCL_L;
128 1 I2C_Delay_us(5);
129 1 return retc;
130 1 }
131
132 static void Ack_I2c(bool a)
133 {
134 1 if (a == 0)
135 1 {
136 2 SDA_L;
137 2 }
138 1 else
139 1 {
140 2 SDA_H;
141 2 }
142 1
143 1 I2C_Delay_us(8);
144 1 SCL_H;
145 1 I2C_Delay_us(15);
146 1 SCL_L;
147 1 I2C_Delay_us(8);
148 1 }
149
150 static bool i2c_write_byte(u8 sla,u8 suba,u8 *s,u8 no)
151 {
152 1 u8 i;
153 1
154 1 Start_I2c();
155 1
156 1 I2C_SendByte(sla);
157 1
158 1 if(ack==0)
159 1 {
160 2 Stop_I2c();
161 2 return FALSE;
162 2 }
163 1 I2C_SendByte(suba);
164 1 if(ack == 0)
165 1 {
166 2 Stop_I2c();
167 2 return FALSE;
168 2 }
169 1
170 1 for(i=0;i<no;i++)
171 1 {
172 2 I2C_SendByte(*s);
173 2 if(ack == 0)
174 2 {
175 3 Stop_I2c();
176 3 return FALSE;
177 3 }
178 2 s++;
C51 COMPILER V9.54 I2C_MASTER 06/12/2026 11:01:29 PAGE 4
179 2 }
180 1 Stop_I2c();
181 1 return TRUE;
182 1 }
183
184 static bool i2c_read_byte(u8 sla,u8 suba,u8 *s,u8 no)
185 {
186 1 u8 i;
187 1 Start_I2c();
188 1 I2C_SendByte(sla);
189 1 if(ack==0)
190 1 {
191 2 Stop_I2c();
192 2 *s = 0x00;
193 2 return FALSE;
194 2 }
195 1 I2C_SendByte(suba);
196 1 if (ack == 0)
197 1 {
198 2 Stop_I2c();
199 2 *s = 0x00;
200 2 return FALSE;
201 2 }
202 1 Start_I2c();
203 1 I2C_SendByte(sla+1);
204 1 if (ack == 0)
205 1 {
206 2 Stop_I2c();
207 2 *s = 0x00;
208 2 return FALSE;
209 2 }
210 1 for (i=0; i<no-1; i++)
211 1 {
212 2 *s= RcvByte();
213 2 Ack_I2c(0);
214 2 s++;
215 2 }
216 1 *s = RcvByte();
217 1 Ack_I2c(1);
218 1 Stop_I2c();
219 1 return TRUE;
220 1 }
221
222 u8 HDMI_ReadI2C_Byte(u8 RegAddr)
223 {
224 1 u8 p_data=0;
225 1
226 1 if (i2c_read_byte(I2CADR, RegAddr, &p_data,1) != FALSE)
227 1 {
228 2 return p_data;
229 2 }
230 1 return 0;
231 1 }
232
233 bool HDMI_ReadI2C_ByteN(u8 RegAddr,u8 *p_data,u8 N)
234 {
235 1 bool flag;
236 1
237 1 flag = i2c_read_byte(I2CADR, RegAddr, p_data,N);
238 1
239 1 return flag;
240 1 }
C51 COMPILER V9.54 I2C_MASTER 06/12/2026 11:01:29 PAGE 5
241
242 bool HDMI_WriteI2C_Byte(u8 RegAddr, u8 d)
243 {
244 1 bool flag;
245 1
246 1 flag=i2c_write_byte(I2CADR, RegAddr,&d,1);
247 1
248 1 return flag;
249 1 }
250
251 bool HDMI_WriteI2C_ByteN(u8 RegAddr, u8 *d,u8 N)
252 {
253 1 bool flag;
254 1
255 1 flag=i2c_write_byte(I2CADR, RegAddr,d,N) ;
256 1
257 1 return flag;
258 1 }
259
260 /************************************** The End Of File **************************************/
261
262
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 559 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = 1 26
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = 1 ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/LT8912B.lst
-1142
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/LT8912B_EVB.m51
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File diff suppressed because it is too large Load Diff
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/STARTUP.lst
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A51 MACRO ASSEMBLER STARTUP 06/12/2026 11:01:29 PAGE 1
MACRO ASSEMBLER A51 V8.02c
OBJECT MODULE PLACED IN .\Objects\STARTUP.obj
ASSEMBLER INVOKED BY: D:\Keil\MDK\download\C51\BIN\A51.EXE STARTUP.A51 SET(LARGE) DEBUG PRINT(.\Listings\STARTUP.lst) OB
JECT(.\Objects\STARTUP.obj) EP
LOC OBJ LINE SOURCE
1 $nomod51
2 ;------------------------------------------------------------------------------
3 ; This file is part of the C51 Compiler package
4 ; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc.
5 ; Version 8.01
6 ;
7 ; *** <<< Use Configuration Wizard in Context Menu >>> ***
8 ;------------------------------------------------------------------------------
9 ; STARTUP.A51: This code is executed after processor reset.
10 ;
11 ; To translate this file use A51 with the following invocation:
12 ;
13 ; A51 STARTUP.A51
14 ;
15 ; To link the modified STARTUP.OBJ file to your application use the following
16 ; Lx51 invocation:
17 ;
18 ; Lx51 your object file list, STARTUP.OBJ controls
19 ;
20 ;------------------------------------------------------------------------------
21 ;
22 ; User-defined <h> Power-On Initialization of Memory
23 ;
24 ; With the following EQU statements the initialization of memory
25 ; at processor reset can be defined:
26 ;
27 ; <o> IDATALEN: IDATA memory size <0x0-0x100>
28 ; <i> Note: The absolute start-address of IDATA memory is always 0
29 ; <i> The IDATA space overlaps physically the DATA and BIT areas.
0080 30 IDATALEN EQU 80H
31 ;
32 ; <o> XDATASTART: XDATA memory start address <0x0-0xFFFF>
33 ; <i> The absolute start address of XDATA memory
0000 34 XDATASTART EQU 0
35 ;
36 ; <o> XDATALEN: XDATA memory size <0x0-0xFFFF>
37 ; <i> The length of XDATA memory in bytes.
0000 38 XDATALEN EQU 0
39 ;
40 ; <o> PDATASTART: PDATA memory start address <0x0-0xFFFF>
41 ; <i> The absolute start address of PDATA memory
0000 42 PDATASTART EQU 0H
43 ;
44 ; <o> PDATALEN: PDATA memory size <0x0-0xFF>
45 ; <i> The length of PDATA memory in bytes.
0000 46 PDATALEN EQU 0H
47 ;
48 ;</h>
49 ;------------------------------------------------------------------------------
50 ;
51 ;<h> Reentrant Stack Initialization
52 ;
53 ; The following EQU statements define the stack pointer for reentrant
54 ; functions and initialized it:
55 ;
56 ; <h> Stack Space for reentrant functions in the SMALL model.
57 ; <q> IBPSTACK: Enable SMALL model reentrant stack
A51 MACRO ASSEMBLER STARTUP 06/12/2026 11:01:29 PAGE 2
58 ; <i> Stack space for reentrant functions in the SMALL model.
0000 59 IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
60 ; <o> IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF>
61 ; <i> Set the top of the stack to the highest location.
0100 62 IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
63 ; </h>
64 ;
65 ; <h> Stack Space for reentrant functions in the LARGE model.
66 ; <q> XBPSTACK: Enable LARGE model reentrant stack
67 ; <i> Stack space for reentrant functions in the LARGE model.
0000 68 XBPSTACK EQU 0 ; set to 1 if large reentrant is used.
69 ; <o> XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF>
70 ; <i> Set the top of the stack to the highest location.
0000 71 XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1
72 ; </h>
73 ;
74 ; <h> Stack Space for reentrant functions in the COMPACT model.
75 ; <q> PBPSTACK: Enable COMPACT model reentrant stack
76 ; <i> Stack space for reentrant functions in the COMPACT model.
0000 77 PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
78 ;
79 ; <o> PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF>
80 ; <i> Set the top of the stack to the highest location.
0100 81 PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
82 ; </h>
83 ;</h>
84 ;------------------------------------------------------------------------------
85 ;
86 ; Memory Page for Using the Compact Model with 64 KByte xdata RAM
87 ; <e>Compact Model Page Definition
88 ;
89 ; <i>Define the XDATA page used for PDATA variables.
90 ; <i>PPAGE must conform with the PPAGE set in the linker invocation.
91 ;
92 ; Enable pdata memory page initalization
0000 93 PPAGEENABLE EQU 0 ; set to 1 if pdata object are used.
94 ;
95 ; <o> PPAGE number <0x0-0xFF>
96 ; <i> uppermost 256-byte address of the page used for PDATA variables.
0000 97 PPAGE EQU 0
98 ;
99 ; <o> SFR address which supplies uppermost address byte <0x0-0xFF>
100 ; <i> most 8051 variants use P2 as uppermost address byte
00A0 101 PPAGE_SFR DATA 0A0H
102 ;
103 ; </e>
104 ;------------------------------------------------------------------------------
105
106 ; Standard SFR Symbols
00E0 107 ACC DATA 0E0H
00F0 108 B DATA 0F0H
0081 109 SP DATA 81H
0082 110 DPL DATA 82H
0083 111 DPH DATA 83H
112
113 NAME ?C_STARTUP
114
115
116 ?C_C51STARTUP SEGMENT CODE
117 ?STACK SEGMENT IDATA
118
---- 119 RSEG ?STACK
0000 120 DS 1
121
122 EXTRN CODE (?C_START)
123 PUBLIC ?C_STARTUP
A51 MACRO ASSEMBLER STARTUP 06/12/2026 11:01:29 PAGE 3
124
---- 125 CSEG AT 0
0000 020000 F 126 ?C_STARTUP: LJMP STARTUP1
127
---- 128 RSEG ?C_C51STARTUP
129
0000 130 STARTUP1:
131
132 IF IDATALEN <> 0
0000 787F 133 MOV R0,#IDATALEN - 1
0002 E4 134 CLR A
0003 F6 135 IDATALOOP: MOV @R0,A
0004 D8FD 136 DJNZ R0,IDATALOOP
137 ENDIF
138
139 IF XDATALEN <> 0
MOV DPTR,#XDATASTART
MOV R7,#LOW (XDATALEN)
IF (LOW (XDATALEN)) <> 0
MOV R6,#(HIGH (XDATALEN)) +1
ELSE
MOV R6,#HIGH (XDATALEN)
ENDIF
CLR A
XDATALOOP: MOVX @DPTR,A
INC DPTR
DJNZ R7,XDATALOOP
DJNZ R6,XDATALOOP
ENDIF
153
154 IF PPAGEENABLE <> 0
MOV PPAGE_SFR,#PPAGE
ENDIF
157
158 IF PDATALEN <> 0
MOV R0,#LOW (PDATASTART)
MOV R7,#LOW (PDATALEN)
CLR A
PDATALOOP: MOVX @R0,A
INC R0
DJNZ R7,PDATALOOP
ENDIF
166
167 IF IBPSTACK <> 0
EXTRN DATA (?C_IBP)
MOV ?C_IBP,#LOW IBPSTACKTOP
ENDIF
172
173 IF XBPSTACK <> 0
EXTRN DATA (?C_XBP)
MOV ?C_XBP,#HIGH XBPSTACKTOP
MOV ?C_XBP+1,#LOW XBPSTACKTOP
ENDIF
179
180 IF PBPSTACK <> 0
EXTRN DATA (?C_PBP)
MOV ?C_PBP,#LOW PBPSTACKTOP
ENDIF
184
0006 758100 F 185 MOV SP,#?STACK-1
186
187 ; This code is required if you use L51_BANK.A51 with Banking Mode 4
188 ;<h> Code Banking
189 ; <q> Select Bank 0 for L51_BANK.A51 Mode 4
A51 MACRO ASSEMBLER STARTUP 06/12/2026 11:01:29 PAGE 4
190
195 ;</h>
0009 020000 F 196 LJMP ?C_START
197
198 END
A51 MACRO ASSEMBLER STARTUP 06/12/2026 11:01:29 PAGE 5
SYMBOL TABLE LISTING
------ ----- -------
N A M E T Y P E V A L U E ATTRIBUTES
?C_C51STARTUP. . . C SEG 000CH REL=UNIT
?C_START . . . . . C ADDR ----- EXT
?C_STARTUP . . . . C ADDR 0000H A
?STACK . . . . . . I SEG 0001H REL=UNIT
ACC. . . . . . . . D ADDR 00E0H A
B. . . . . . . . . D ADDR 00F0H A
DPH. . . . . . . . D ADDR 0083H A
DPL. . . . . . . . D ADDR 0082H A
IBPSTACK . . . . . N NUMB 0000H A
IBPSTACKTOP. . . . N NUMB 0100H A
IDATALEN . . . . . N NUMB 0080H A
IDATALOOP. . . . . C ADDR 0003H R SEG=?C_C51STARTUP
PBPSTACK . . . . . N NUMB 0000H A
PBPSTACKTOP. . . . N NUMB 0100H A
PDATALEN . . . . . N NUMB 0000H A
PDATASTART . . . . N NUMB 0000H A
PPAGE. . . . . . . N NUMB 0000H A
PPAGEENABLE. . . . N NUMB 0000H A
PPAGE_SFR. . . . . D ADDR 00A0H A
SP . . . . . . . . D ADDR 0081H A
STARTUP1 . . . . . C ADDR 0000H R SEG=?C_C51STARTUP
XBPSTACK . . . . . N NUMB 0000H A
XBPSTACKTOP. . . . N NUMB 0000H A
XDATALEN . . . . . N NUMB 0000H A
XDATASTART . . . . N NUMB 0000H A
REGISTER BANK(S) USED: 0
ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/main.lst
-327
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C51 COMPILER V9.54 MAIN 06/12/2026 11:01:29 PAGE 1
C51 COMPILER V9.54, COMPILATION OF MODULE MAIN
OBJECT MODULE PLACED IN .\Objects\main.obj
COMPILER INVOKED BY: D:\Keil\MDK\download\C51\BIN\C51.EXE ..\main.c LARGE OPTIMIZE(8,SPEED) BROWSE INCDIR(..\inc) DEFINE
-(FOSC_160000) DEBUG OBJECTEXTEND PRINT(.\Listings\main.lst) TABS(2) OBJECT(.\Objects\main.obj)
line level source
1 /************************************************************
2 * ProjectName: LT8619C
3 * FileName: Main.c
4 * BuildData: 2017-04-20
5 * Version： V1.00
6 * Company: Lontium
7 ************************************************************/
8 #include "include.h"
9
10 u8 MIPI_Lane; // = 2; // 2 lane ; 0 : 4 lane
11
12 u8 MIPI_Lane_CH_Swap;
13
14 u8 MIPI_Lane_PN_Swap;
15
16 u8 HDMI_DVI_Output; // _HDMI_Output_ ; _DVI_Output_
17
18 bit IIS_Format_En; // 1: IIS ; 0 : SPDIF
19
20 bit Test_Pattern_En;
21
22 // bit LT8912B_IIC_En;
23
24 bit SDA_Ack;
25
26 const u16 MIPI_Timing[6][8] =
27 {
28 //H_act V_act H_total V_total H_BP H_sync V_sync V_BP
29 { 720, 480, 858, 525, 60, 62, 6, 30 }, // 480P Vesa Timing
30 { 1024, 768, 1344, 806, 160, 136, 6, 29 }, // 1024x768
31 { 1280, 720, 1650, 750, 220, 40, 5, 20 }, // 720P Vesa Timing
32
33 { 1280, 800, 1440, 823, 80, 32, 6, 14 }, // 1280x800 timing
34
35 { 1024, 600, 1344, 635, 140, 20, 3, 20 }, // 1024x600
36 // { 1024, 600, 1274, 645, 80, 10, 10, 23 }, // 1024x600
37 { 1920, 1080, 2200, 1125, 148, 44, 5, 36 }, // 1080P Vesa Timing
38 // { 1920, 1200, 2080, 1235, 80, 32, 6, 26 }, // 1920x1200 154MHz Vesa Timing
39 // { 1280, 480, 1460, 530, 80, 20, 10, 20 }, // 1280x480
40 };
41
42 #ifdef _LVDS_Output_
// bit LVDS_Output_En; // = 1; //
u16 Panel_Pixel_CLK; // = 4925; // 49.25MHz
u8 PLL_Devider;
u8 LVDS_Map; // = _VESA_;
u8 LVDS_mode; // = _Sync_Mode_;
u8 Color_Depth; // = _8_Bit_Color_;
C51 COMPILER V9.54 MAIN 06/12/2026 11:01:29 PAGE 2
// 根据LVDS屏规格书设置LVDS输出s的屏参:
const u16 Panel_Timing[8] =
//H_act V_act H_total V_total H_BP H_sync V_sync V_BP
// {1920, 1080, 2200, 1125, 148, 44, 5, 36};// 1080P Vesa Timing
// {1280, 800, 1440, 823, 80, 32, 6, 14};// 1280x800
{ 1024, 600, 1344, 635, 140, 20, 3, 20 }; // 1024x600
// { 1024, 600, 1274, 645, 80, 10, 10, 23 }; // 1024x600
// { 1280, 480, 1460, 530, 80, 20, 10, 20 };
#endif
66
67 #ifdef _LT8912B_EVB_ // for 8912B demo board
68
69
70 /***********************************************************
71
72 ***********************************************************/
73 void GPIO_Initial( void )
74 {
75 1 P03_OpenDrain_Mode; // OpenDrain_Mode // 8912 SDA
76 1 P04_OpenDrain_Mode; // OpenDrain_Mode // 8912 SCL
77 1 P00_OpenDrain_Mode; // 8912 Reset // P03_PushPull_Mode; P03_OpenDrain_Mode
78 1
79 1 // P01_Input_Mode; // IRQ
80 1
81 1 P13_Input_Mode;
82 1 P14_Input_Mode;
83 1
84 1 // P11_PushPull_Mode;
85 1
86 1 //EA=1;
87 1 InitialUART0_Timer1( 115200 ); //UART_INTI
88 1
89 1 // Enable_INT_Port0;
90 1 // Enable_BIT1_FallEdge_Trig;
91 1 // set_EPI;
92 1
93 1 //set_EX1;
94 1 //set_IT1;
95 1 //set_IE1;
96 1 // set_EA;
97 1 }
98
99 #endif
100
101 #define _LT8912B_RSTN_LOW P00 = 0
102 #define _LT8912B_RSTN_High P00 = 1
103
104 #ifdef _LT8912B_EVB_ // for 8912B demo
105
106
107 /***********************************************************
108 ****************************/
109 void Initstate_LT8912B( void )
110 {
111 1 // LT8912_IIC_En = 1;
112 1
113 1 I2CADR = 0x92;
114 1 }
115
116 #endif
C51 COMPILER V9.54 MAIN 06/12/2026 11:01:29 PAGE 3
117
118 #ifdef _LT8912B_EVB_ // for 8912B demo
119
120
121 /***********************************************************
122
123 ***********************************************************/
124 void LT8912B_Reset( void )
125 {
126 1 _LT8912B_RSTN_LOW;
127 1 Delay_ms( 100 );
128 1 _LT8912B_RSTN_High;
129 1 Delay_ms( 100 );
130 1 }
131
132 #endif
133
134
135 /***********************************************************
136
137 ***********************************************************/
138 void LT8912B_Config( void )
139 {
140 1 HDMI_DVI_Output = _HDMI_Output_; // _HDMI_Output_ ; _DVI_Output_
141 1
142 1 IIS_Format_En = _IIS_Output_; // 1: IIS ; 0 : SPDIF
143 1
144 1 MIPI_Lane = 4; // 4 lane ; 0 ~ 4 lane
145 1
146 1 MIPI_Lane_CH_Swap = _Channel_0123; // _Channel_3210; _Channel_0123
147 1 MIPI_Lane_PN_Swap = _PN_Swap_Dis; // _PN_Swap_En; _PN_Swap_Dis
148 1
149 1 Test_Pattern_En = 1; //
150 1
151 1 #ifdef _LVDS_Output_
// if( LVDS_Output_En )
{
Panel_Pixel_CLK = 5125; // 51.25MHz
PLL_Devider = _PLL_Devider_1; // _PLL_Devider_1;_PLL_Devider_2;_PLL_Devider_4;_PLL_Devider_8
LVDS_Map = _VESA_; // _VESA_ ; _JEIDA_
LVDS_mode = _Sync_Mode_; // _Sync_Mode_ ; _De_Mode_
Color_Depth = _8_Bit_Color_; // _8_Bit_Color_ ; _6_Bit_Color_
}
#endif
166 1 }
167
168 /***********************************************************
169
170 ***********************************************************/
171 void main( void )
172 {
173 1 u8 temp = 0x00;
174 1 // CLK_Configuration( );
175 1 GPIO_Initial( );
176 1
177 1 Delay_ms( 200 );
178 1 Delay_ms( 200 );
C51 COMPILER V9.54 MAIN 06/12/2026 11:01:29 PAGE 4
179 1 Delay_ms( 200 );
180 1 Delay_ms( 200 );
181 1 Delay_ms( 200 );
182 1
183 1 print( "\r\n**********************start*************************" );
184 1 Initstate_LT8912B( );
185 1 LT8912B_Reset( );
186 1 print( "\r\n " );
187 1 print( "\r\n*****************LT8912B reset done*****************" );
188 1
189 1 LT8912B_Config( );
190 1
191 1 videoformat = VESA_1280x800_60; // VESA_1280x800_60 ;
192 1 LT812B_Config( );
193 1 print( "\r\n " );
194 1 print( "\r\n****************LT8912B Initial done****************" );
195 1 print( "\r\n " );
196 1
197 1
198 1 /*
199 1 if( Test_Pattern_En )
200 1 {
201 1 GCMWindow1080P( );
202 1 // GCMWindow1280x480P();
203 1 // GCMWindow720P( );
204 1 // GCMWindow480P( );
205 1 // GCMWindow576P( );
206 1 }
207 1 //*/
208 1 #ifdef _LVDS_Output_
// if( LVDS_Output_En )
{
Collpll_Config( );
LVDS_ScaleRatioConfig( );
Delay_ms( 300 );
LvdsPowerUp( );
}
#endif
218 1
219 1 Delay_ms( 200 );
220 1
221 1 while( 1 )
222 1 {
223 2 #if 1
224 2 if( temp < 10 )
225 2 {
226 3 // temp++;
227 3 MIPI_Input_det( );
228 3
229 3 if( Pre_videoformat != videoformat )
230 3 {
231 4 Pre_videoformat = videoformat;
232 4 if( videoformat != 0xff )
233 4 {
234 5 #ifdef _LVDS_Output_
// if( LVDS_Output_En )
{
LvdsPowerDown( );
}
#endif
240 5 //*
C51 COMPILER V9.54 MAIN 06/12/2026 11:01:29 PAGE 5
241 5 MIPIDig_Format_Config( );
242 5 DDSConfig( );
243 5 AudioIIsEn( );
244 5 MIPIRxLogicRes( );
245 5
246 5 I2CADR = 0x92;
247 5 HDMI_WriteI2C_Byte( 0x70, 0x00 ); // pattern disable
248 5 print( "\r\n " );
249 5 print( "\r\nLT8912B HDMI config done..." );
250 5 print( "\r\n " );
251 5 //*/
252 5 // LT812B_Config( );
253 5 #ifdef _LVDS_Output_
#ifdef _LVDS_Bypass_
LVDS_Bypass_Config( );
#else
Collpll_Config( );
LVDS_ScaleRatioConfig( );
#endif
Delay_ms( 300 );
LvdsPowerUp( );
#endif
264 5 }
265 4 //*
266 4 else
267 4 if( Test_Pattern_En )
268 4 {
269 5 GCMWindow1280x800P( );
270 5
271 5 #ifdef _LVDS_Output_
videoformat = VESA_1024x600_60;
Collpll_Config( );
LVDS_ScaleRatioConfig( );
Delay_ms( 300 );
LvdsPowerUp( );
videoformat = 0xff;
#endif
280 5 // GCMWindow1280x480P();
281 5 // GCMWindow720P( );
282 5 // GCMWindow480P( );
283 5 // GCMWindow576P( );
284 5 } //*/
285 4 }
286 3
287 3 Delay_ms( 1000 );
288 3 }
289 2 #endif
290 2 }
291 1 }
292
293 /************************************** The End Of File **************************************/
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 312 ----
CONSTANT SIZE = 199 ----
XDATA SIZE = 100 1
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
C51 COMPILER V9.54 MAIN 06/12/2026 11:01:29 PAGE 6
BIT SIZE = 3 ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/uart0.lst
-442
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@@ -1,442 +0,0 @@
C51 COMPILER V9.54 UART0 06/12/2026 11:01:30 PAGE 1
C51 COMPILER V9.54, COMPILATION OF MODULE UART0
OBJECT MODULE PLACED IN .\Objects\uart0.obj
COMPILER INVOKED BY: D:\Keil\MDK\download\C51\BIN\C51.EXE ..\src\uart0.c LARGE OPTIMIZE(8,SPEED) BROWSE INCDIR(..\inc) D
-EFINE(FOSC_160000) DEBUG OBJECTEXTEND PRINT(.\Listings\uart0.lst) TABS(2) OBJECT(.\Objects\uart0.obj)
line level source
1
2 #include "include.h"
3
4
5 //----------------------------------------------------------------------------------
6 // UART0 baud rate initial setting
7 //----------------------------------------------------------------------------------
8 void InitialUART0_Timer1(UINT32 u32Baudrate) //T1M = 1, SMOD = 1
9 {
10 1 P06_Quasi_Mode; //Setting UART pin as Quasi mode for transmit
11 1 P07_Quasi_Mode; //Setting UART pin as Quasi mode for transmit
12 1
13 1 SCON = 0x50; //UART0 Mode1,REN=1,TI=1
14 1 TMOD |= 0x20; //Timer1 Mode1
15 1
16 1 set_SMOD; //UART0 Double Rate Enable
17 1 set_T1M;
18 1 clr_BRCK; //Serial port 0 baud rate clock source = Timer1
19 1
20 1 #ifdef FOSC_160000
21 1 TH1 = 256 - (1000000/u32Baudrate+1); /*16 MHz */
22 1 #endif
23 1 #ifdef FOSC_166000
TH1 = 256 - (1037500/u32Baudrate); /*16.6 MHz */
#endif
26 1 set_TR1;
27 1 set_TI; //For printf function must setting TI = 1
28 1 }
29 //---------------------------------------------------------------
30 void InitialUART0_Timer3(UINT32 u32Baudrate) //use timer3 as Baudrate generator
31 {
32 1 P06_Quasi_Mode; //Setting UART pin as Quasi mode for transmit
33 1 P07_Quasi_Mode; //Setting UART pin as Quasi mode for transmit
34 1
35 1 SCON = 0x50; //UART0 Mode1,REN=1,TI=1
36 1 set_SMOD; //UART0 Double Rate Enable
37 1 T3CON &= 0xF8; //T3PS2=0,T3PS1=0,T3PS0=0(Prescale=1)
38 1 set_BRCK; //UART0 baud rate clock source = Timer3
39 1
40 1 #ifdef FOSC_160000
41 1 RH3 = HIBYTE(65536 - (1000000/u32Baudrate)-1); /*16 MHz */
42 1 RL3 = LOBYTE(65536 - (1000000/u32Baudrate)-1); /*16 MHz */
43 1 #endif
44 1 #ifdef FOSC_166000
RH3 = HIBYTE(65536 - (1037500/u32Baudrate)); /*16.6 MHz */
RL3 = LOBYTE(65536 - (1037500/u32Baudrate)); /*16.6 MHz */
#endif
48 1 set_TR3; //Trigger Timer3
49 1 set_TI; //For printf function must setting TI = 1
50 1 }
51
52 UINT8 Receive_Data_From_UART0(void)
53 {
54 1 UINT8 c;
C51 COMPILER V9.54 UART0 06/12/2026 11:01:30 PAGE 2
55 1 while (!RI);
56 1 c = SBUF;
57 1 RI = 0;
58 1 return (c);
59 1 }
60
61 void Send_Data_To_UART0 (UINT8 c)
62 {
63 1 TI = 0;
64 1 SBUF = c;
65 1 while(TI==0);
66 1 }
67
68 void printByte(u8 UData)
69 {
70 1 u8 reg_H,reg_L;
71 1 reg_L=UData&0x0f;
72 1 reg_H=(UData&0xf0)>>4;
73 1
74 1 reg_L = (reg_L<0x0a) ? (reg_L+0x30):(reg_L+0x37); //map reg_L to asicc 'a' to a (0x41), a = 0x37 + 0
-x0a = 0x41
75 1 reg_H = (reg_H<0x0a) ? (reg_H+0x30):(reg_H+0x37);
76 1 Send_Data_To_UART0(reg_H);
77 1 Send_Data_To_UART0(reg_L);
78 1 Send_Data_To_UART0(0x20); //space
79 1 }
80
81 void printnewline(void)
82 {
83 1 Send_Data_To_UART0(0x0a); //huanhang
84 1 }
85
86
87 void Debug_printf(unsigned char *str)
88 {
89 1 #ifdef _uart_debug_
90 1 printf(str);
91 1 #endif
92 1 }
93
94 void printWord(u16 U16Data)
95 {
96 1 printByte((U16Data&0xFF00)>>8);
97 1 printByte((U16Data&0x00FF));
98 1 Send_Data_To_UART0(0x0a); //???
99 1 }
100
101
102 void printByteWithSpace(u8 U8Data)
103 {
104 1 Send_Data_To_UART0(U8Data);
105 1 Send_Data_To_UART0(0x20); //space
106 1 //0x3c |, 0x3e ~
107 1 }
108 /*
109 出厂前，每颗 N76E003都会预烧一个96位的序列号
110 ，用以确保该芯片的唯一性，这个唯一代码被称为
111 序列号UID (Unique Code)。用户获得序列号的唯
112 一方式是通过 IAP指令读取，
113 */
114 UINT8 UID_BYTE(UINT8 Addr)
115 {
C51 COMPILER V9.54 UART0 06/12/2026 11:01:30 PAGE 3
116 1 UINT8 DATATEMP;
117 1 set_IAPEN;
118 1 IAPAL = Addr;
119 1 IAPAH = 0x00;
120 1 IAPCN = READ_UID;
121 1 set_IAPGO;
122 1 DATATEMP = IAPFD;
123 1 clr_IAPEN;
124 1 return DATATEMP;
125 1 }
126
127 void READ_MCU_UID(void)
128 {
129 1 UINT8 READ1,READ2;
130 1
131 1 READ1 = UID_BYTE(0x02);
132 1 READ2 = UID_BYTE(0x05);
133 1
134 1 printf ("\n UID1 = 0x%bx",READ1);
135 1 printf ("\n UID2 = 0x%bx",READ2);
136 1 }
137
138
139
140 void printch(char ch)
141 {
142 1 Send_Data_To_UART0(ch);
143 1 }
144
145 void printdec(int dec)
146 {
147 1 if((dec/10) < 10)
148 1 {
149 2 printch((char)((dec/10) + '0'));
150 2 }
151 1 else
152 1 {
153 2 printch((char)((dec/10) - 10 + 'a' ));
154 2 }
155 1
156 1 if((dec%10) < 10)
157 1 {
158 2 printch((char)(dec%10 + '0'));
159 2 }
160 1 else
161 1 {
162 2 printch((char)(dec%10 - 10 + 'a' ));
163 2 }
164 1 }
165
166 void printhex(int hex)
167 {
168 1 printf("0x");
169 1 Timer0_Delay1ms(2);
170 1
171 1 if((hex/16) < 10)
172 1 {
173 2 printch((char)((hex/16) + '0'));
174 2 }
175 1 else
176 1 {
177 2 printch((char)((hex/16) - 10 + 'a' ));
C51 COMPILER V9.54 UART0 06/12/2026 11:01:30 PAGE 4
178 2 }
179 1
180 1 if((hex%16) < 10)
181 1 {
182 2 printch((char)(hex%16 + '0'));
183 2 }
184 1 else
185 1 {
186 2 printch((char)(hex%16 - 10 + 'a' ));
187 2 }
188 1 }
189
190
191 /* max input 99999999*/
192 void printdec_u32(u32 u32_dec)
193 {
194 1 #ifdef _uart_debug_
195 1 bool start_flag = 0;
196 1 u32 dec = 0;
197 1 dec = u32_dec;
198 1
199 1 printch((char)(' ')); //print blank；
200 1
201 1 if(dec > 9999999)
202 1 {
203 2 if((dec/10000000) < 10)
204 2 {
205 3 printch((char)((dec/10000000) + '0'));
206 3 }
207 2 else
208 2 {
209 3 printch((char)((dec/10000000) - 10 + 'a' ));
210 3 }
211 2 dec %= 10000000;
212 2 start_flag = 1;
213 2 }
214 1
215 1 if(dec > 999999)
216 1 {
217 2 if((dec/1000000) < 10)
218 2 {
219 3 printch((char)((dec/1000000) + '0'));
220 3 }
221 2 else
222 2 {
223 3 printch((char)((dec/1000000) - 10 + 'a' ));
224 3 }
225 2 dec %= 1000000;
226 2 start_flag = 1;
227 2 }else
228 1 {
229 2 if(start_flag)
230 2 printch((char)('0'));
231 2 }
232 1
233 1
234 1 if(dec > 99999)
235 1 {
236 2 if((dec/100000) < 10)
237 2 {
238 3 printch((char)((dec/100000) + '0'));
239 3 }
C51 COMPILER V9.54 UART0 06/12/2026 11:01:30 PAGE 5
240 2 else
241 2 {
242 3 printch((char)((dec/100000) - 10 + 'a' ));
243 3 }
244 2 dec %= 100000;
245 2 start_flag = 1;
246 2 }else
247 1 {
248 2 if(start_flag)
249 2 printch((char)('0'));
250 2 }
251 1
252 1 if(dec > 9999)
253 1 {
254 2 if((dec/10000) < 10)
255 2 {
256 3 printch((char)((dec/10000) + '0'));
257 3 }
258 2 else
259 2 {
260 3 printch((char)((dec/10000) - 10 + 'a' ));
261 3 }
262 2 dec %= 10000;
263 2 start_flag = 1;
264 2 }else
265 1 {
266 2 if(start_flag)
267 2 printch((char)('0'));
268 2 }
269 1
270 1 if(dec > 999)
271 1 {
272 2 if((dec/1000) < 10)
273 2 {
274 3 printch((char)((dec/1000) + '0'));
275 3 }
276 2 else
277 2 {
278 3 printch((char)((dec/1000) - 10 + 'a' ));
279 3 }
280 2 dec %= 1000;
281 2 start_flag = 1;
282 2 }else
283 1 {
284 2 if(start_flag)
285 2 printch((char)('0'));
286 2 }
287 1
288 1 if(dec > 99)
289 1 {
290 2 if((dec/100) < 10)
291 2 {
292 3 printch((char)((dec/100) + '0'));
293 3 }
294 2 else
295 2 {
296 3 printch((char)((dec/100) - 10 + 'a' ));
297 3 }
298 2 dec %= 100;
299 2 start_flag = 1;
300 2 }
301 1 else
C51 COMPILER V9.54 UART0 06/12/2026 11:01:30 PAGE 6
302 1 {
303 2 if(start_flag)
304 2 printch((char)('0'));
305 2 }
306 1
307 1 if((dec/10) < 10)
308 1 {
309 2 printch((char)((dec/10) + '0'));
310 2 }
311 1 else
312 1 {
313 2 printch((char)((dec/10) - 10 + 'a' ));
314 2 }
315 1
316 1 if((dec%10) < 10)
317 1 {
318 2 printch((char)(dec%10 + '0'));
319 2 }
320 1 else
321 1 {
322 2 printch((char)(dec%10 - 10 + 'a' ));
323 2 }
324 1 #endif
325 1 }
326
327
328 void print(char* fmt, ...)
329 {
330 1 #ifdef _uart_debug_
331 1 double vargflt = 0;
332 1 int vargint = 0;
333 1 char* vargpch = NULL;
334 1 char vargch = 0;
335 1 char* pfmt = NULL;
336 1 va_list vp;
337 1
338 1 va_start(vp, fmt);
339 1 pfmt = fmt;
340 1
341 1 while(*pfmt)
342 1 {
343 2 if(*pfmt == '%')
344 2 {
345 3 switch(*(++pfmt))
346 3 {
347 4
348 4 case 'c':
349 4 vargch = va_arg(vp, int);
350 4 /* va_arg(ap, type), if type is narrow type (char, short, float) an error is given in
- strict ANSI
351 4 mode, or a warning otherwise.In non-strict ANSI mode, 'type' is allowed to be any
-expression. */
352 4 printch(vargch);
353 4 break;
354 4 case 'd':
355 4 case 'D':
356 4 vargint = va_arg(vp, u8);
357 4 printdec((u8)vargint);
358 4
359 4 break;
360 4 //
361 4 // case 'f':
C51 COMPILER V9.54 UART0 06/12/2026 11:01:30 PAGE 7
362 4 // case 'F':
363 4 // vargflt = va_arg(vp, double);
364 4 // /* va_arg(ap, type), if type is narrow type (char, short, float) an error is give
-n in strict ANSI
365 4 // mode, or a warning otherwise.In non-strict ANSI mode, 'type' is allowed to be an
-y expression. */
366 4 // printflt(vargflt);
367 4 // break;
368 4 // case 's':
369 4 // case 'S':
370 4 // vargpch = va_arg(vp, char*);
371 4 // printstr(vargpch);
372 4 // break;
373 4 // case 'b':
374 4 // case 'B':
375 4 // vargint = va_arg(vp, int);
376 4 // printbin(vargint);
377 4 // break;
378 4 case 'x':;
379 4 case 'X':
380 4 vargint = va_arg(vp,u8);
381 4 printhex(vargint);
382 4 break;
383 4
384 4 case '%':
385 4 printch('%');
386 4 break;
387 4 default:
388 4 break;
389 4 }
390 3 pfmt++;
391 3 }
392 2 else
393 2 {
394 3 printch(*pfmt++);
395 3 //*pfmt++;
396 3 }
397 2 }
398 1 va_end(vp);
399 1 #endif
400 1 }
401
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 2158 ----
CONSTANT SIZE = 33 ----
XDATA SIZE = ---- 75
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Nu_Link_8051_Driver.ini
-22
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@@ -1,22 +0,0 @@
[Version]
Nu_LinkVersion=V1.2
[Process]
ProcessID=0x00007710
ProcessCreationTime_L=0x55c986ac
ProcessCreationTime_H=0x01dcfa08
NuLinkID=0x77886a52
NuLinkIDs_Count=0x00000001
NuLinkID0=0x77886a52
[Option]
MaxClock=1
EnablePCLK=1
Erase=0
Program=1
Verify=1
ResetAndRun=1
UpdateSprom=0
IOVoltage=3300
EnableMemAcc=0
MemAccPeriod=1000
MemAccShowDelay=0
EnableLog=0
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Objects/Delay.obj
BIN
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Objects/I2C_MASTER.obj
BIN
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Objects/LT8912B.obj
BIN
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Objects/LT8912B_EVB
BIN
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Objects/LT8912B_EVB.build_log.htm
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<html>
<body>
<pre>
<h1>礦ision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: μVision V5.24.2.0
Copyright (C) 2017 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: 1 admin, 1, LIC=UJ5FJ-UG2KK-D8YFM-XTN5V-H7EGL-DYRC5
Tool Versions:
Toolchain: PK51 Prof. Developers Kit Version: 9.54
Toolchain Path: D:\Keil\MDK\download\C51\BIN
C Compiler: C51.exe V9.54
Assembler: A51.exe V8.02c
Linker/Locator: BL51.exe V6.22
Library Manager: LIB51.exe V4.30.1.0
Hex Converter: OH51.exe V2.7.0.0
CPU DLL: S8051.DLL V3.100.0.0
Dialog DLL: DP51.DLL V2.62.0.1
Target DLL: Nuvoton_8051_Keil_uVision_Driver.dll V3.21
Dialog DLL: TP51.DLL V2.58
<h2>Project:</h2>
D:\昂宇电子\我的\龙讯\测试程序\6911C-9211C-9611\LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003\sourcecode\pro\LT8912B_EVB.uvproj
Project File Date: 06/11/2026
<h2>Output:</h2>
Rebuild target 'Target 1'
assembling STARTUP.A51...
compiling Delay.c...
compiling I2C_MASTER.C...
compiling LT8912B.c...
compiling main.c...
compiling uart0.c...
linking...
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?_TIMER0_DELAY100US?DELAY
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?_HDMI_READI2C_BYTEN?I2C_MASTER
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?_HDMI_WRITEI2C_BYTEN?I2C_MASTER
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?GCMWINDOW1080P?LT8912B
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?GCMWINDOW1024X600P?LT8912B
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?LT8912B_STANDBY?LT8912B
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?_INITIALUART0_TIMER3?UART0
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?RECEIVE_DATA_FROM_UART0?UART0
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?PRINTNEWLINE?UART0
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?_DEBUG_PRINTF?UART0
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?_PRINTWORD?UART0
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?_PRINTBYTEWITHSPACE?UART0
*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
SEGMENT: ?PR?READ_MCU_UID?UART0
Program Size: data=15.6 xdata=265 code=9843
creating hex file from ".\Objects\LT8912B_EVB"...
".\Objects\LT8912B_EVB" - 0 Error(s), 13 Warning(s).
Build Time Elapsed: 00:00:01
</pre>
</body>
</html>
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Objects/LT8912B_EVB.hex
-685
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@@ -1,685 +0,0 @@
:03000000021CB32C
:0C1CB300787FE4F6D8FD758121021CFA50
:102034009000FF120674538EF7438901D28CE4FF9B
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Objects/LT8912B_EVB.lnp
-8
View File
@@ -1,8 +0,0 @@
".\Objects\STARTUP.obj",
".\Objects\Delay.obj",
".\Objects\I2C_MASTER.obj",
".\Objects\LT8912B.obj",
".\Objects\main.obj",
".\Objects\uart0.obj"
TO ".\Objects\LT8912B_EVB"
PRINT(".\Listings\LT8912B_EVB.m51") RAMSIZE(256)
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Objects/LT8912B_EVB_1280x480_test_pattern_20190408.hex
-713
View File
@@ -1,713 +0,0 @@
:03000000021C14CB
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Objects/LT8912B_EVB_1280x480_test_pattern_52M_20190408.hex
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Objects/STARTUP.obj
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$NOMOD51
;------------------------------------------------------------------------------
; This file is part of the C51 Compiler package
; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc.
; Version 8.01
;
; *** <<< Use Configuration Wizard in Context Menu >>> ***
;------------------------------------------------------------------------------
; STARTUP.A51: This code is executed after processor reset.
;
; To translate this file use A51 with the following invocation:
;
; A51 STARTUP.A51
;
; To link the modified STARTUP.OBJ file to your application use the following
; Lx51 invocation:
;
; Lx51 your object file list, STARTUP.OBJ controls
;
;------------------------------------------------------------------------------
;
; User-defined <h> Power-On Initialization of Memory
;
; With the following EQU statements the initialization of memory
; at processor reset can be defined:
;
; <o> IDATALEN: IDATA memory size <0x0-0x100>
; <i> Note: The absolute start-address of IDATA memory is always 0
; <i> The IDATA space overlaps physically the DATA and BIT areas.
IDATALEN EQU 80H
;
; <o> XDATASTART: XDATA memory start address <0x0-0xFFFF>
; <i> The absolute start address of XDATA memory
XDATASTART EQU 0
;
; <o> XDATALEN: XDATA memory size <0x0-0xFFFF>
; <i> The length of XDATA memory in bytes.
XDATALEN EQU 0
;
; <o> PDATASTART: PDATA memory start address <0x0-0xFFFF>
; <i> The absolute start address of PDATA memory
PDATASTART EQU 0H
;
; <o> PDATALEN: PDATA memory size <0x0-0xFF>
; <i> The length of PDATA memory in bytes.
PDATALEN EQU 0H
;
;</h>
;------------------------------------------------------------------------------
;
;<h> Reentrant Stack Initialization
;
; The following EQU statements define the stack pointer for reentrant
; functions and initialized it:
;
; <h> Stack Space for reentrant functions in the SMALL model.
; <q> IBPSTACK: Enable SMALL model reentrant stack
; <i> Stack space for reentrant functions in the SMALL model.
IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
; <o> IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF>
; <i> Set the top of the stack to the highest location.
IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
; </h>
;
; <h> Stack Space for reentrant functions in the LARGE model.
; <q> XBPSTACK: Enable LARGE model reentrant stack
; <i> Stack space for reentrant functions in the LARGE model.
XBPSTACK EQU 0 ; set to 1 if large reentrant is used.
; <o> XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF>
; <i> Set the top of the stack to the highest location.
XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1
; </h>
;
; <h> Stack Space for reentrant functions in the COMPACT model.
; <q> PBPSTACK: Enable COMPACT model reentrant stack
; <i> Stack space for reentrant functions in the COMPACT model.
PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
;
; <o> PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF>
; <i> Set the top of the stack to the highest location.
PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
; </h>
;</h>
;------------------------------------------------------------------------------
;
; Memory Page for Using the Compact Model with 64 KByte xdata RAM
; <e>Compact Model Page Definition
;
; <i>Define the XDATA page used for PDATA variables.
; <i>PPAGE must conform with the PPAGE set in the linker invocation.
;
; Enable pdata memory page initalization
PPAGEENABLE EQU 0 ; set to 1 if pdata object are used.
;
; <o> PPAGE number <0x0-0xFF>
; <i> uppermost 256-byte address of the page used for PDATA variables.
PPAGE EQU 0
;
; <o> SFR address which supplies uppermost address byte <0x0-0xFF>
; <i> most 8051 variants use P2 as uppermost address byte
PPAGE_SFR DATA 0A0H
;
; </e>
;------------------------------------------------------------------------------
; Standard SFR Symbols
ACC DATA 0E0H
B DATA 0F0H
SP DATA 81H
DPL DATA 82H
DPH DATA 83H
NAME ?C_STARTUP
?C_C51STARTUP SEGMENT CODE
?STACK SEGMENT IDATA
RSEG ?STACK
DS 1
EXTRN CODE (?C_START)
PUBLIC ?C_STARTUP
CSEG AT 0
?C_STARTUP: LJMP STARTUP1
RSEG ?C_C51STARTUP
STARTUP1:
IF IDATALEN <> 0
MOV R0,#IDATALEN - 1
CLR A
IDATALOOP: MOV @R0,A
DJNZ R0,IDATALOOP
ENDIF
IF XDATALEN <> 0
MOV DPTR,#XDATASTART
MOV R7,#LOW (XDATALEN)
IF (LOW (XDATALEN)) <> 0
MOV R6,#(HIGH (XDATALEN)) +1
ELSE
MOV R6,#HIGH (XDATALEN)
ENDIF
CLR A
XDATALOOP: MOVX @DPTR,A
INC DPTR
DJNZ R7,XDATALOOP
DJNZ R6,XDATALOOP
ENDIF
IF PPAGEENABLE <> 0
MOV PPAGE_SFR,#PPAGE
ENDIF
IF PDATALEN <> 0
MOV R0,#LOW (PDATASTART)
MOV R7,#LOW (PDATALEN)
CLR A
PDATALOOP: MOVX @R0,A
INC R0
DJNZ R7,PDATALOOP
ENDIF
IF IBPSTACK <> 0
EXTRN DATA (?C_IBP)
MOV ?C_IBP,#LOW IBPSTACKTOP
ENDIF
IF XBPSTACK <> 0
EXTRN DATA (?C_XBP)
MOV ?C_XBP,#HIGH XBPSTACKTOP
MOV ?C_XBP+1,#LOW XBPSTACKTOP
ENDIF
IF PBPSTACK <> 0
EXTRN DATA (?C_PBP)
MOV ?C_PBP,#LOW PBPSTACKTOP
ENDIF
MOV SP,#?STACK-1
; This code is required if you use L51_BANK.A51 with Banking Mode 4
;<h> Code Banking
; <q> Select Bank 0 for L51_BANK.A51 Mode 4
#if 0
; <i> Initialize bank mechanism to code bank 0 when using L51_BANK.A51 with Banking Mode 4.
EXTRN CODE (?B_SWITCH0)
CALL ?B_SWITCH0 ; init bank mechanism to code bank 0
#endif
;</h>
LJMP ?C_START
END
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/src/Delay.c
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/*---------------------------------------------------------------------------------------------------------*/
/* */
/* Copyright(c) 2016 Nuvoton Technology Corp. All rights reserved. */
/* */
/*---------------------------------------------------------------------------------------------------------*/
//***********************************************************************************************************
// Nuvoton Technoledge Corp.
// Website: http://www.nuvoton.com
// E-Mail : MicroC-8bit@nuvoton.com
// Date : Apr/21/2016
//***********************************************************************************************************
#include "Include.h"
bit BIT_TMP;
/***********************************************************
***********************************************************/
void Timer0_Delay100us( UINT32 u32CNT )
{
clr_T0M; //T0M=0, Timer0 Clock = Fsys/12
TMOD |= 0x01; //Timer0 is 16-bit mode
set_TR0; //Start Timer0
while( u32CNT != 0 )
{
TL0 = LOBYTE( TIMER_DIV12_VALUE_100us ); //Find define in "Function_define.h" "TIMER VALUE"
TH0 = HIBYTE( TIMER_DIV12_VALUE_100us );
while( TF0 != 1 )
{
; //Check Timer0 Time-Out Flag
}
clr_TF0;
u32CNT--;
}
clr_TR0; //Stop Timer0
}
/***********************************************************
***********************************************************/
void Timer0_Delay1ms( UINT32 u32CNT )
{
clr_T0M; //T0M=0, Timer0 Clock = Fsys/12
TMOD |= 0x01; //Timer0 is 16-bit mode
set_TR0; //Start Timer0
while( u32CNT != 0 )
{
TL0 = LOBYTE( TIMER_DIV12_VALUE_1ms ); //Find define in "Function_define.h" "TIMER VALUE"
TH0 = HIBYTE( TIMER_DIV12_VALUE_1ms );
while( TF0 != 1 )
{
; //Check Timer0 Time-Out Flag
}
clr_TF0;
u32CNT--;
}
clr_TR0; //Stop Timer0
}
/*
//------------------------------------------------------------------------------
void Timer1_Delay10ms(UINT32 u32CNT)
{
clr_T1M; //T1M=0, Timer1 Clock = Fsys/12
TMOD |= 0x10; //Timer1 is 16-bit mode
set_TR1; //Start Timer1
while (u32CNT != 0)
{
TL1 = LOBYTE(TIMER_DIV12_VALUE_10ms); //Find define in "Function_define.h" "TIMER VALUE"
TH1 = HIBYTE(TIMER_DIV12_VALUE_10ms);
while (TF1 != 1); //Check Timer1 Time-Out Flag
clr_TF1;
u32CNT --;
}
clr_TR1; //Stop Timer1
}
//------------------------------------------------------------------------------
void Timer2_Delay500us(UINT32 u32CNT)
{
clr_T2DIV2; //Timer2 Clock = Fsys/4
clr_T2DIV1;
set_T2DIV0;
set_TR2; //Start Timer2
while (u32CNT != 0)
{
TL2 = LOBYTE(TIMER_DIV4_VALUE_500us); //Find define in "Function_define.h" "TIMER VALUE"
TH2 = HIBYTE(TIMER_DIV4_VALUE_500us);
while (TF2 != 1); //Check Timer2 Time-Out Flag
clr_TF2;
u32CNT --;
}
clr_TR2; //Stop Timer2
}
//------------------------------------------------------------------------------
void Timer3_Delay100ms(UINT32 u32CNT)
{
T3CON = 0x07; //Timer3 Clock = Fsys/128
set_TR3; //Trigger Timer3
while (u32CNT != 0)
{
RL3 = LOBYTE(TIMER_DIV128_VALUE_100ms); //Find define in "Function_define.h" "TIMER VALUE"
RH3 = HIBYTE(TIMER_DIV128_VALUE_100ms);
while ((T3CON&SET_BIT4) != SET_BIT4); //Check Timer3 Time-Out Flag
clr_TF3;
u32CNT --;
}
clr_TR3; //Stop Timer3
}
//------------------------------------------------------------------------------
void Timer3_Delay10us(UINT32 u32CNT)
{
T3CON = 0x07; //Timer3 Clock = Fsys/128
set_TR3; //Trigger Timer3
while (u32CNT != 0)
{
RL3 = LOBYTE(TIMER_DIV4_VALUE_10us); //Find define in "Function_define.h" "TIMER VALUE"
RH3 = HIBYTE(TIMER_DIV4_VALUE_10us);
while ((T3CON&SET_BIT4) != SET_BIT4); //Check Timer3 Time-Out Flag
clr_TF3;
u32CNT --;
}
clr_TR3; //Stop Timer3
}
//*/
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/src/I2C_MASTER.C
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/************************************************************
* ProjectName: LT8522EX
* FileName: lt8522ex.c
* BuildData: 2014-03-27
* Version£º V1.00
* Company: Lontium
************************************************************/
#include "include.h"
//bit FLAG_I2C_ERROR;
bit ack;
u8 I2CADR = 0x90;
void Delay_ms( u16 mscount )
{
u16 i, x;
for( i = 0; i < mscount; i++ )
{
for( x = 0; x < 2000; x++ )
{
;
}
// IWDG_ReloadCounter();
}
}
#define SCL_H P04=1
#define SCL_L P04=0
#define SDA_H P03=1
#define SDA_L P03=0
#define I2C_SDA_READ P03
static void I2C_Delay_us(u8 uscount)
{
u8 x;
for(x=0; x<uscount; x++)
{
;
}
}
static void Start_I2c(void)
{
SDA_H;
I2C_Delay_us(1);
SCL_H;
I2C_Delay_us(10);
SDA_L;
I2C_Delay_us(7);
SCL_L;
I2C_Delay_us(1);
}
static void Stop_I2c(void)
{
SDA_L;
I2C_Delay_us(2);
SCL_H;
I2C_Delay_us(10);
SDA_H;
I2C_Delay_us(10);
}
static void I2C_SendByte(u8 c)
{
u8 bit_Cnt;
for(bit_Cnt=0; bit_Cnt<8; bit_Cnt++)
{
if((c<<bit_Cnt) & 0x80)
{
SDA_H;
}
else
{
SDA_L;
}
I2C_Delay_us(3);
SCL_H;
I2C_Delay_us(4);
SCL_L;
}
I2C_Delay_us(1);
SDA_H;
I2C_Delay_us(3);
SCL_H;
I2C_Delay_us(3);
if(I2C_SDA_READ != 0)
{
ack=0;
}
else
{
ack=1;
}
SCL_L;
I2C_Delay_us(3);
}
static u8 RcvByte(void)
{
u8 retc;
u8 bit_Cnt;
retc=0;
SDA_H;
for (bit_Cnt=0; bit_Cnt<8; bit_Cnt++)
{
I2C_Delay_us(1);
SCL_L;
I2C_Delay_us(4);
SCL_H;
I2C_Delay_us(2);
retc=retc<<1;
if (I2C_SDA_READ != 0)
{
retc = retc+1;
}
I2C_Delay_us(2);
}
SCL_L;
I2C_Delay_us(5);
return retc;
}
static void Ack_I2c(bool a)
{
if (a == 0)
{
SDA_L;
}
else
{
SDA_H;
}
I2C_Delay_us(8);
SCL_H;
I2C_Delay_us(15);
SCL_L;
I2C_Delay_us(8);
}
static bool i2c_write_byte(u8 sla,u8 suba,u8 *s,u8 no)
{
u8 i;
Start_I2c();
I2C_SendByte(sla);
if(ack==0)
{
Stop_I2c();
return FALSE;
}
I2C_SendByte(suba);
if(ack == 0)
{
Stop_I2c();
return FALSE;
}
for(i=0;i<no;i++)
{
I2C_SendByte(*s);
if(ack == 0)
{
Stop_I2c();
return FALSE;
}
s++;
}
Stop_I2c();
return TRUE;
}
static bool i2c_read_byte(u8 sla,u8 suba,u8 *s,u8 no)
{
u8 i;
Start_I2c();
I2C_SendByte(sla);
if(ack==0)
{
Stop_I2c();
*s = 0x00;
return FALSE;
}
I2C_SendByte(suba);
if (ack == 0)
{
Stop_I2c();
*s = 0x00;
return FALSE;
}
Start_I2c();
I2C_SendByte(sla+1);
if (ack == 0)
{
Stop_I2c();
*s = 0x00;
return FALSE;
}
for (i=0; i<no-1; i++)
{
*s= RcvByte();
Ack_I2c(0);
s++;
}
*s = RcvByte();
Ack_I2c(1);
Stop_I2c();
return TRUE;
}
u8 HDMI_ReadI2C_Byte(u8 RegAddr)
{
u8 p_data=0;
if (i2c_read_byte(I2CADR, RegAddr, &p_data,1) != FALSE)
{
return p_data;
}
return 0;
}
bool HDMI_ReadI2C_ByteN(u8 RegAddr,u8 *p_data,u8 N)
{
bool flag;
flag = i2c_read_byte(I2CADR, RegAddr, p_data,N);
return flag;
}
bool HDMI_WriteI2C_Byte(u8 RegAddr, u8 d)
{
bool flag;
flag=i2c_write_byte(I2CADR, RegAddr,&d,1);
return flag;
}
bool HDMI_WriteI2C_ByteN(u8 RegAddr, u8 *d,u8 N)
{
bool flag;
flag=i2c_write_byte(I2CADR, RegAddr,d,N) ;
return flag;
}
/************************************** The End Of File **************************************/
HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/src/LT8912B.c
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HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/src/uart0.c
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#include "include.h"
//----------------------------------------------------------------------------------
// UART0 baud rate initial setting
//----------------------------------------------------------------------------------
void InitialUART0_Timer1(UINT32 u32Baudrate) //T1M = 1, SMOD = 1
{
P06_Quasi_Mode; //Setting UART pin as Quasi mode for transmit
P07_Quasi_Mode; //Setting UART pin as Quasi mode for transmit
SCON = 0x50; //UART0 Mode1,REN=1,TI=1
TMOD |= 0x20; //Timer1 Mode1
set_SMOD; //UART0 Double Rate Enable
set_T1M;
clr_BRCK; //Serial port 0 baud rate clock source = Timer1
#ifdef FOSC_160000
TH1 = 256 - (1000000/u32Baudrate+1); /*16 MHz */
#endif
#ifdef FOSC_166000
TH1 = 256 - (1037500/u32Baudrate); /*16.6 MHz */
#endif
set_TR1;
set_TI; //For printf function must setting TI = 1
}
//---------------------------------------------------------------
void InitialUART0_Timer3(UINT32 u32Baudrate) //use timer3 as Baudrate generator
{
P06_Quasi_Mode; //Setting UART pin as Quasi mode for transmit
P07_Quasi_Mode; //Setting UART pin as Quasi mode for transmit
SCON = 0x50; //UART0 Mode1,REN=1,TI=1
set_SMOD; //UART0 Double Rate Enable
T3CON &= 0xF8; //T3PS2=0,T3PS1=0,T3PS0=0(Prescale=1)
set_BRCK; //UART0 baud rate clock source = Timer3
#ifdef FOSC_160000
RH3 = HIBYTE(65536 - (1000000/u32Baudrate)-1); /*16 MHz */
RL3 = LOBYTE(65536 - (1000000/u32Baudrate)-1); /*16 MHz */
#endif
#ifdef FOSC_166000
RH3 = HIBYTE(65536 - (1037500/u32Baudrate)); /*16.6 MHz */
RL3 = LOBYTE(65536 - (1037500/u32Baudrate)); /*16.6 MHz */
#endif
set_TR3; //Trigger Timer3
set_TI; //For printf function must setting TI = 1
}
UINT8 Receive_Data_From_UART0(void)
{
UINT8 c;
while (!RI);
c = SBUF;
RI = 0;
return (c);
}
void Send_Data_To_UART0 (UINT8 c)
{
TI = 0;
SBUF = c;
while(TI==0);
}
void printByte(u8 UData)
{
u8 reg_H,reg_L;
reg_L=UData&0x0f;
reg_H=(UData&0xf0)>>4;
reg_L = (reg_L<0x0a) ? (reg_L+0x30):(reg_L+0x37); //map reg_L to asicc 'a' to a (0x41), a = 0x37 + 0x0a = 0x41
reg_H = (reg_H<0x0a) ? (reg_H+0x30):(reg_H+0x37);
Send_Data_To_UART0(reg_H);
Send_Data_To_UART0(reg_L);
Send_Data_To_UART0(0x20); //space
}
void printnewline(void)
{
Send_Data_To_UART0(0x0a); //huanhang
}
void Debug_printf(unsigned char *str)
{
#ifdef _uart_debug_
printf(str);
#endif
}
void printWord(u16 U16Data)
{
printByte((U16Data&0xFF00)>>8);
printByte((U16Data&0x00FF));
Send_Data_To_UART0(0x0a); //???
}
void printByteWithSpace(u8 U8Data)
{
Send_Data_To_UART0(U8Data);
Send_Data_To_UART0(0x20); //space
//0x3c |, 0x3e ~
}
/*
出厂前，每颗 N76E003都会预烧一个96位的序列号
，用以确保该芯片的唯一性，这个唯一代码被称为
序列号UID (Unique Code)。用户获得序列号的唯
一方式是通过 IAP指令读取，
*/
UINT8 UID_BYTE(UINT8 Addr)
{
UINT8 DATATEMP;
set_IAPEN;
IAPAL = Addr;
IAPAH = 0x00;
IAPCN = READ_UID;
set_IAPGO;
DATATEMP = IAPFD;
clr_IAPEN;
return DATATEMP;
}
void READ_MCU_UID(void)
{
UINT8 READ1,READ2;
READ1 = UID_BYTE(0x02);
READ2 = UID_BYTE(0x05);
printf ("\n UID1 = 0x%bx",READ1);
printf ("\n UID2 = 0x%bx",READ2);
}
void printch(char ch)
{
Send_Data_To_UART0(ch);
}
void printdec(int dec)
{
if((dec/10) < 10)
{
printch((char)((dec/10) + '0'));
}
else
{
printch((char)((dec/10) - 10 + 'a' ));
}
if((dec%10) < 10)
{
printch((char)(dec%10 + '0'));
}
else
{
printch((char)(dec%10 - 10 + 'a' ));
}
}
void printhex(int hex)
{
printf("0x");
Timer0_Delay1ms(2);
if((hex/16) < 10)
{
printch((char)((hex/16) + '0'));
}
else
{
printch((char)((hex/16) - 10 + 'a' ));
}
if((hex%16) < 10)
{
printch((char)(hex%16 + '0'));
}
else
{
printch((char)(hex%16 - 10 + 'a' ));
}
}
/* max input 99999999*/
void printdec_u32(u32 u32_dec)
{
#ifdef _uart_debug_
bool start_flag = 0;
u32 dec = 0;
dec = u32_dec;
printch((char)(' ')); //print blank；
if(dec > 9999999)
{
if((dec/10000000) < 10)
{
printch((char)((dec/10000000) + '0'));
}
else
{
printch((char)((dec/10000000) - 10 + 'a' ));
}
dec %= 10000000;
start_flag = 1;
}
if(dec > 999999)
{
if((dec/1000000) < 10)
{
printch((char)((dec/1000000) + '0'));
}
else
{
printch((char)((dec/1000000) - 10 + 'a' ));
}
dec %= 1000000;
start_flag = 1;
}else
{
if(start_flag)
printch((char)('0'));
}
if(dec > 99999)
{
if((dec/100000) < 10)
{
printch((char)((dec/100000) + '0'));
}
else
{
printch((char)((dec/100000) - 10 + 'a' ));
}
dec %= 100000;
start_flag = 1;
}else
{
if(start_flag)
printch((char)('0'));
}
if(dec > 9999)
{
if((dec/10000) < 10)
{
printch((char)((dec/10000) + '0'));
}
else
{
printch((char)((dec/10000) - 10 + 'a' ));
}
dec %= 10000;
start_flag = 1;
}else
{
if(start_flag)
printch((char)('0'));
}
if(dec > 999)
{
if((dec/1000) < 10)
{
printch((char)((dec/1000) + '0'));
}
else
{
printch((char)((dec/1000) - 10 + 'a' ));
}
dec %= 1000;
start_flag = 1;
}else
{
if(start_flag)
printch((char)('0'));
}
if(dec > 99)
{
if((dec/100) < 10)
{
printch((char)((dec/100) + '0'));
}
else
{
printch((char)((dec/100) - 10 + 'a' ));
}
dec %= 100;
start_flag = 1;
}
else
{
if(start_flag)
printch((char)('0'));
}
if((dec/10) < 10)
{
printch((char)((dec/10) + '0'));
}
else
{
printch((char)((dec/10) - 10 + 'a' ));
}
if((dec%10) < 10)
{
printch((char)(dec%10 + '0'));
}
else
{
printch((char)(dec%10 - 10 + 'a' ));
}
#endif
}
void print(char* fmt, ...)
{
#ifdef _uart_debug_
double vargflt = 0;
int vargint = 0;
char* vargpch = NULL;
char vargch = 0;
char* pfmt = NULL;
va_list vp;
va_start(vp, fmt);
pfmt = fmt;
while(*pfmt)
{
if(*pfmt == '%')
{
switch(*(++pfmt))
{
case 'c':
vargch = va_arg(vp, int);
/* va_arg(ap, type), if type is narrow type (char, short, float) an error is given in strict ANSI
mode, or a warning otherwise.In non-strict ANSI mode, 'type' is allowed to be any expression. */
printch(vargch);
break;
case 'd':
case 'D':
vargint = va_arg(vp, u8);
printdec((u8)vargint);
break;
//
// case 'f':
// case 'F':
// vargflt = va_arg(vp, double);
// /* va_arg(ap, type), if type is narrow type (char, short, float) an error is given in strict ANSI
// mode, or a warning otherwise.In non-strict ANSI mode, 'type' is allowed to be any expression. */
// printflt(vargflt);
// break;
// case 's':
// case 'S':
// vargpch = va_arg(vp, char*);
// printstr(vargpch);
// break;
// case 'b':
// case 'B':
// vargint = va_arg(vp, int);
// printbin(vargint);
// break;
case 'x':;
case 'X':
vargint = va_arg(vp,u8);
printhex(vargint);
break;
case '%':
printch('%');
break;
default:
break;
}
pfmt++;
}
else
{
printch(*pfmt++);
//*pfmt++;
}
}
va_end(vp);
#endif
}
HDMI/LT8912B/LT8912B应用指南.xls
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HDMI/LT8912B/LT8912B调试AP Note.xls
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HDMI/SBC-1/disp_i2c_lt8912b.h
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// SPDX-License-Identifier: GPL-2.0+
/*
* Author(s): Hammer Hsieh <hammer.hsieh@sunplus.com>
*/
#ifndef __DISP_I2C_LT8912B_H__
#define __DISP_I2C_LT8912B_H__
#include <i2c.h>
#include <linux/delay.h>
#define LT8912B_I2C_ADDR_MAIN 0x48
#define LT8912B_I2C_ADDR_CEC_DSI 0x49
#define LT8912B_I2C_ADDR_HDMITX_DSI 0x4a
/*
* lt8912_input_timing[x][y]
* y = 0-1, LT8912 width & height
* y = 2-9, LT8912 HSA & HFP & HBP & HACT & VSA & VFP & VBP & VACT
*/
static const u32 lt8912_input_timing[11][10] = {
/* (w h) HSA HFP HBP HACT VSA VFP VBP VACT */
{ 720, 480, 0x3e, 0x10, 0x3c, 720, 0x6, 0x9, 0x1E, 480}, /* 480P */
{ 720, 576, 0x80, 0x28, 0x58, 720, 0x4, 0x1, 0x17, 576}, /* 576P */
{1280, 720, 0x28, 0x6e, 0xdc, 1280, 0x5, 0x5, 0x14, 720}, /* 720P */
{1920, 1080, 0x2c, 0x58, 0x94, 1920, 0x5, 0x4, 0x24, 1080}, /* 1080P */
{ 64, 64, 0x14, 0x28, 0x58, 64, 0x5, 0x5, 0x24, 64}, /* 64x64 */
{ 128, 128, 0x14, 0x28, 0x58, 128, 0x5, 0x5, 0x24, 128}, /* 128x128 */
{ 64, 2880, 0x14, 0x28, 0x58, 64, 0x5, 0x5, 0x24, 2880}, /* 64x2880 */
{3840, 64, 0x14, 0x28, 0x58, 3840, 0x5, 0x5, 0x24, 64}, /* 3840x64 */
{3840, 2880, 0x14, 0x28, 0x58, 3840, 0x5, 0x5, 0x24, 2880}, /* 3840x2880 */
{ 800, 480, 0x14, 0x28, 0x58, 800, 0x5, 0x5, 0x24, 480}, /* 800x480 */
{1024, 600, 0x14, 0x28, 0x58, 1024, 0x5, 0x5, 0x24, 600} /* 1024x600 */
};
void lt8912_write_init_config(struct udevice *p1)
{
//printf("lt8912_write_init_config\n");
/* Digital clock en*/
dm_i2c_reg_write(p1, 0x08, 0xff); /* power down */
dm_i2c_reg_write(p1, 0x09, 0xff); /* HPD override */
dm_i2c_reg_write(p1, 0x0a, 0xff); /* color space */
dm_i2c_reg_write(p1, 0x0b, 0x7c); /* fixed */
dm_i2c_reg_write(p1, 0x0c, 0xff); /* HDCP */
dm_i2c_reg_write(p1, 0x42, 0x04);
/*Tx Analog*/
dm_i2c_reg_write(p1, 0x31, 0xb1); /* fixed a1 or b1 ? */
dm_i2c_reg_write(p1, 0x32, 0xb1); /* V1P2 */
dm_i2c_reg_write(p1, 0x33, 0x0e); /* fixed 0e or 03*/
dm_i2c_reg_write(p1, 0x37, 0x00); /* fixed */
dm_i2c_reg_write(p1, 0x38, 0x22); /* fixed */
dm_i2c_reg_write(p1, 0x60, 0x82); /* fixed */
/*Cbus Analog*/
dm_i2c_reg_write(p1, 0x39, 0x45); /* fixed */
dm_i2c_reg_write(p1, 0x3a, 0x00); /* fixed for improve hdmi output signal */
dm_i2c_reg_write(p1, 0x3b, 0x00); /* fixed */
/*HDMI Pll Analog*/
dm_i2c_reg_write(p1, 0x44, 0x31); /* fixed */
dm_i2c_reg_write(p1, 0x55, 0x44); /* fixed */
dm_i2c_reg_write(p1, 0x57, 0x01); /* fixed */
dm_i2c_reg_write(p1, 0x5a, 0x02); /* fixed */
/*MIPI Analog*/
//org
dm_i2c_reg_write(p1, 0x3e, 0xd6); /* fixed d6 or c6 or 8e ? */
dm_i2c_reg_write(p1, 0x3f, 0xd4); /* fixed d4 or not setting */
dm_i2c_reg_write(p1, 0x41, 0x3c); /* fixed 3c or 7c ? */
dm_i2c_reg_write(p1, 0xB2, 0x00); /* fixed 00 or not setting */
dm_i2c_reg_write(p1, 0x42, 0x05); /* fixed 04 or 05 ? */
#if 0
//test
dm_i2c_reg_write(p1, 0x3e, 0xc6);
//dm_i2c_reg_write(p1, 0x3f, 0xd4);
dm_i2c_reg_write(p1, 0x41, 0x7c);
dm_i2c_reg_write(p1, 0xB2, 0x00);
#endif
}
void lt8912_write_mipi_basic_config(struct udevice *p2)
{
//printf("lt8912_write_mipi_basic_config\n");
dm_i2c_reg_write(p2, 0x12, 0x04);
dm_i2c_reg_write(p2, 0x14, 0x00);
dm_i2c_reg_write(p2, 0x15, 0x00); /* fixed 00 or 06 ? */
dm_i2c_reg_write(p2, 0x1a, 0x03);
dm_i2c_reg_write(p2, 0x1b, 0x03);
}
void lt8912_write_param_by_resolution(struct udevice *p2, int w, int h)
{
u32 hactive, h_total, hpw, hfp, hbp;
u32 vactive, v_total, vpw, vfp, vbp;
u8 settle = 0x08;
int i;
//printf("lt8912_write_param_by_resolution\n");
for (i = 0; i < 11; i++) {
if ((lt8912_input_timing[i][0] == w) &&
(lt8912_input_timing[i][1] == h)) {
//time_cnt = i;
break;
}
}
//printf("Disp: i %d\n", i);
if (i >= 11) i = 0;
hactive = lt8912_input_timing[i][5];
hfp = lt8912_input_timing[i][3];
hpw = lt8912_input_timing[i][2];
hbp = lt8912_input_timing[i][4];
h_total = hactive + hfp + hpw + hbp;
vactive = lt8912_input_timing[i][9];
vfp = lt8912_input_timing[i][7];
vpw = lt8912_input_timing[i][6];
vbp = lt8912_input_timing[i][8];
v_total = vactive + vfp + vpw + vbp;
dm_i2c_reg_write(p2, 0x10, 0x01); //fix
if (vactive <= 600)
settle = 0x04;
else if (vactive == 1080)
settle = 0x0a;
dm_i2c_reg_write(p2, 0x11, settle); //0x04 or 0x0a
dm_i2c_reg_write(p2, 0x18, hpw);
dm_i2c_reg_write(p2, 0x19, vpw);
dm_i2c_reg_write(p2, 0x1c, hactive & 0xff);
dm_i2c_reg_write(p2, 0x1d, hactive >> 8);
//dm_i2c_reg_write(p2, 0x1e, 0x67);
dm_i2c_reg_write(p2, 0x2f, 0x0c);
dm_i2c_reg_write(p2, 0x34, h_total & 0xff);
dm_i2c_reg_write(p2, 0x35, h_total >> 8);
dm_i2c_reg_write(p2, 0x36, v_total & 0xff);
dm_i2c_reg_write(p2, 0x37, v_total >> 8);
dm_i2c_reg_write(p2, 0x38, vbp & 0xff);
dm_i2c_reg_write(p2, 0x39, vbp >> 8);
dm_i2c_reg_write(p2, 0x3a, vfp & 0xff);
dm_i2c_reg_write(p2, 0x3b, vfp >> 8);
dm_i2c_reg_write(p2, 0x3c, hbp & 0xff);
dm_i2c_reg_write(p2, 0x3d, hbp >> 8);
dm_i2c_reg_write(p2, 0x3e, hfp & 0xff);
dm_i2c_reg_write(p2, 0x3f, hfp >> 8);
}
void lt8912_write_dds_config(struct udevice *p2)
{
//printf("lt8912_write_dds_config\n");
dm_i2c_reg_write(p2, 0x4e, 0xff);
dm_i2c_reg_write(p2, 0x4f, 0x56);
dm_i2c_reg_write(p2, 0x50, 0x69);
dm_i2c_reg_write(p2, 0x51, 0x80);
dm_i2c_reg_write(p2, 0x1f, 0x5e);
dm_i2c_reg_write(p2, 0x20, 0x01);
dm_i2c_reg_write(p2, 0x21, 0x2c);
dm_i2c_reg_write(p2, 0x22, 0x01);
dm_i2c_reg_write(p2, 0x23, 0xfa);
dm_i2c_reg_write(p2, 0x24, 0x00);
dm_i2c_reg_write(p2, 0x25, 0xc8);
dm_i2c_reg_write(p2, 0x26, 0x00);
dm_i2c_reg_write(p2, 0x27, 0x5e);
dm_i2c_reg_write(p2, 0x28, 0x01);
dm_i2c_reg_write(p2, 0x29, 0x2c);
dm_i2c_reg_write(p2, 0x2a, 0x01);
dm_i2c_reg_write(p2, 0x2b, 0xfa);
dm_i2c_reg_write(p2, 0x2c, 0x00);
dm_i2c_reg_write(p2, 0x2d, 0xc8);
dm_i2c_reg_write(p2, 0x2e, 0x00);
dm_i2c_reg_write(p2, 0x42, 0x64);
dm_i2c_reg_write(p2, 0x43, 0x00);
dm_i2c_reg_write(p2, 0x44, 0x04);
dm_i2c_reg_write(p2, 0x45, 0x00);
dm_i2c_reg_write(p2, 0x46, 0x59);
dm_i2c_reg_write(p2, 0x47, 0x00);
dm_i2c_reg_write(p2, 0x48, 0xf2);
dm_i2c_reg_write(p2, 0x49, 0x06);
dm_i2c_reg_write(p2, 0x4a, 0x00);
dm_i2c_reg_write(p2, 0x4b, 0x72);
dm_i2c_reg_write(p2, 0x4c, 0x45);
dm_i2c_reg_write(p2, 0x4d, 0x00);
dm_i2c_reg_write(p2, 0x52, 0x08);
dm_i2c_reg_write(p2, 0x53, 0x00);
dm_i2c_reg_write(p2, 0x54, 0xb2);
dm_i2c_reg_write(p2, 0x55, 0x00);
dm_i2c_reg_write(p2, 0x56, 0xe4);
dm_i2c_reg_write(p2, 0x57, 0x0d);
dm_i2c_reg_write(p2, 0x58, 0x00);
dm_i2c_reg_write(p2, 0x59, 0xe4);
dm_i2c_reg_write(p2, 0x5a, 0x8a);
dm_i2c_reg_write(p2, 0x5b, 0x00);
dm_i2c_reg_write(p2, 0x5c, 0x34);
dm_i2c_reg_write(p2, 0x1e, 0x4f);
dm_i2c_reg_write(p2, 0x51, 0x00);
}
void lt8912_write_rxlogicres_config(struct udevice *p1)
{
//printf("lt8912_write_rxlogicres_config\n");
dm_i2c_reg_write(p1, 0x03, 0x7f);
udelay(10000); //delay 10ms ~ 20ms
dm_i2c_reg_write(p1, 0x03, 0xff);
}
void lt8912_write_lvds_config(struct udevice *p2)
{
//printf("lt8912_write_lvds_config\n");
#if 0
dm_i2c_reg_write(p2, 0x44, 0x30);
dm_i2c_reg_write(p2, 0x51, 0x05);
dm_i2c_reg_write(p2, 0x50, 0x24);
dm_i2c_reg_write(p2, 0x51, 0x2d);
dm_i2c_reg_write(p2, 0x52, 0x04);
dm_i2c_reg_write(p2, 0x69, 0x0e);
dm_i2c_reg_write(p2, 0x69, 0x8e);
dm_i2c_reg_write(p2, 0x6a, 0x00);
dm_i2c_reg_write(p2, 0x6c, 0xb8);
dm_i2c_reg_write(p2, 0x6b, 0x51);
dm_i2c_reg_write(p2, 0x04, 0xfb);
dm_i2c_reg_write(p2, 0x04, 0xff);
dm_i2c_reg_write(p2, 0x7f, 0x00);
dm_i2c_reg_write(p2, 0xa8, 0x13);
dm_i2c_reg_write(p2, 0x02, 0xf7);
dm_i2c_reg_write(p2, 0x02, 0xff);
dm_i2c_reg_write(p2, 0x03, 0xcf);
dm_i2c_reg_write(p2, 0x03, 0xff);
#endif
}
void lt8912_write_test_pattern(struct udevice *p2)
{
#if 0
/* test pattern for 480P */
dm_i2c_reg_write(p2, 0x72, 0x12);
dm_i2c_reg_write(p2, 0x73, 0x7a); //RGD_PTN_DE_DLY[7:0]
dm_i2c_reg_write(p2, 0x74, 0x00); //RGD_PTN_DE_DLY[11:8]
dm_i2c_reg_write(p2, 0x75, 0x24); //RGD_PTN_DE_TOP[6:0]
dm_i2c_reg_write(p2, 0x76, 0xd0); //RGD_PTN_DE_CNT[7:0]
dm_i2c_reg_write(p2, 0x77, 0xe0); //RGD_PTN_DE_LIN[7:0]
dm_i2c_reg_write(p2, 0x78, 0x12); //RGD_PTN_DE_LIN[11:8],RGD_PTN_DE_CNT[11:8]
dm_i2c_reg_write(p2, 0x79, 0x5a); //RGD_PTN_H_TOTAL[7:0]
dm_i2c_reg_write(p2, 0x7a, 0x0d); //RGD_PTN_V_TOTAL[7:0]
dm_i2c_reg_write(p2, 0x7b, 0x23); //RGD_PTN_V_TOTAL[11:8],RGD_PTN_H_TOTAL[11:8]
dm_i2c_reg_write(p2, 0x7c, 0x3e); //RGD_PTN_HWIDTH[7:0]
dm_i2c_reg_write(p2, 0x7d, 0x06); //RGD_PTN_HWIDTH[9:8],RGD_PTN_VWIDTH[5:0]
dm_i2c_reg_write(p2, 0x70, 0x80);
dm_i2c_reg_write(p2, 0x71, 0x51);
//DDS ?? CLK
dm_i2c_reg_write(p2, 0x4e, 0x66);
dm_i2c_reg_write(p2, 0x4f, 0x66);
dm_i2c_reg_write(p2, 0x50, 0x26);
dm_i2c_reg_write(p2, 0x51, 0x80); //pattern_en
#endif
#if 0
/* test pattern for 1080P */
dm_i2c_reg_write(p2, 0x72, 0x12);
dm_i2c_reg_write(p2, 0x73, 0xc0); //RGD_PTN_DE_DLY[7:0]
dm_i2c_reg_write(p2, 0x74, 0x00); //RGD_PTN_DE_DLY[11:8]
dm_i2c_reg_write(p2, 0x75, 0x29); //RGD_PTN_DE_TOP[6:0]
dm_i2c_reg_write(p2, 0x76, 0x80); //RGD_PTN_DE_CNT[7:0]
dm_i2c_reg_write(p2, 0x77, 0x38); //RGD_PTN_DE_LIN[7:0]
dm_i2c_reg_write(p2, 0x78, 0x47); //RGD_PTN_DE_LIN[11:8],RGD_PTN_DE_CNT[11:8]
dm_i2c_reg_write(p2, 0x79, 0x98); //RGD_PTN_H_TOTAL[7:0]
dm_i2c_reg_write(p2, 0x7a, 0x65); //RGD_PTN_V_TOTAL[7:0]
dm_i2c_reg_write(p2, 0x7b, 0x48); //RGD_PTN_V_TOTAL[11:8],RGD_PTN_H_TOTAL[11:8]
dm_i2c_reg_write(p2, 0x7c, 0x2c); //RGD_PTN_HWIDTH[7:0]
dm_i2c_reg_write(p2, 0x7d, 0x05); //RGD_PTN_HWIDTH[9:8],RGD_PTN_VWIDTH[5:0]
dm_i2c_reg_write(p2, 0x70, 0x80);
dm_i2c_reg_write(p2, 0x71, 0x76);
//DDS 148.5M CLK
dm_i2c_reg_write(p2, 0x4e, 0x33);
dm_i2c_reg_write(p2, 0x4f, 0x33);
dm_i2c_reg_write(p2, 0x50, 0xd3);
dm_i2c_reg_write(p2, 0x51, 0x80); //pattern_en
#endif
}
void lt8912_hdmi_mode_setup(struct udevice *p1, int hdmi_dvi_sel)
{
if (hdmi_dvi_sel) {
//printf("Disp: set lt8912b hdmi mode\n");
dm_i2c_reg_write(p1, 0xb2, 0x01); //HDMI Mode
} else {
//printf("Disp: set lt8912b dvi mode\n");
dm_i2c_reg_write(p1, 0xb2, 0x00); //DVI Mode (default)
}
}
void lt8912_audio_setup(struct udevice *p1, struct udevice *p3, int w, int h)
{
u8 avi_pb0, avi_pb1, avi_pb2, avi_pb4, chksum;
u8 avi_pb6, avi_pb7, avi_pb8, avi_pb9;
u8 avi_pb10, avi_pb11, avi_pb12, avi_pb13;
dm_i2c_reg_write(p3, 0x06, 0x08);
dm_i2c_reg_write(p3, 0x07, 0xf0);
dm_i2c_reg_write(p3, 0x09, 0x00);
#if 1 //audio 48k
dm_i2c_reg_write(p3, 0x0f, 0x2b); //set 48kHz
dm_i2c_reg_write(p3, 0x37, 0x00);
dm_i2c_reg_write(p3, 0x36, 0x18);
dm_i2c_reg_write(p3, 0x35, 0x00); //N = 6144(0x1800)
#else //audio 44.1k
dm_i2c_reg_write(p3, 0x0f, 0x0b); //set 44.1kHz
dm_i2c_reg_write(p3, 0x37, 0x00);
dm_i2c_reg_write(p3, 0x36, 0x18);
dm_i2c_reg_write(p3, 0x35, 0x80); //N = 6272(0x1880)
#endif
dm_i2c_reg_write(p3, 0x34, 0xe2);
dm_i2c_reg_write(p3, 0x3c, 0x41);
dm_i2c_reg_write(p3, 0x3e, 0x0a);
if ((w == 720) && (h == 480)) {
dm_i2c_reg_write(p1, 0xab, 0x0c);
avi_pb1 = 0x1C;
avi_pb2 = 0x58;
avi_pb4 = 0x02; //VIC_CODE = 2
avi_pb6 = 0x24; //36
avi_pb7 = 0x00;
avi_pb8 = 0x04; //516
avi_pb9 = 0x02;
avi_pb10 = 0x7a; //122
avi_pb11 = 0x00;
avi_pb12 = 0x4a; //842
avi_pb13 = 0x03;
} else if ((w == 1280) && (h == 720)) {
dm_i2c_reg_write(p1, 0xab, 0x03);
avi_pb1 = 0x1C;
avi_pb2 = 0xa8;
avi_pb4 = 0x04; //VIC_CODE = 4
avi_pb6 = 0x19; //25
avi_pb7 = 0x00;
avi_pb8 = 0xe9; //745
avi_pb9 = 0x02;
avi_pb10 = 0x04; //260
avi_pb11 = 0x01;
avi_pb12 = 0x04; //1540
avi_pb13 = 0x06;
} else if ((w == 1920) && (h == 1080)) {
dm_i2c_reg_write(p1, 0xab, 0x03);
avi_pb1 = 0x1C;
avi_pb2 = 0xa8;
avi_pb4 = 0x10; //VIC_CODE = 16
avi_pb6 = 0x29; //41
avi_pb7 = 0x00;
avi_pb8 = 0x61; //1121
avi_pb9 = 0x04;
avi_pb10 = 0xc0; //192
avi_pb11 = 0x00;
avi_pb12 = 0x40; //2112
avi_pb13 = 0x08;
} else { //1080P
dm_i2c_reg_write(p1, 0xab, 0x03);
avi_pb1 = 0x1C;
avi_pb2 = 0xa8;
avi_pb4 = 0x10; //VIC_CODE = 16
avi_pb6 = 0x29; //41
avi_pb7 = 0x00;
avi_pb8 = 0x61; //1121
avi_pb9 = 0x04;
avi_pb10 = 0xc0; //192
avi_pb11 = 0x00;
avi_pb12 = 0x40; //2112
avi_pb13 = 0x08;
}
chksum = 0x82 + 0x02 + 0x0d + avi_pb1 + avi_pb2 + avi_pb4;
chksum += (avi_pb6 + avi_pb7 +avi_pb8 + avi_pb9);
chksum += (avi_pb10 + avi_pb11 +avi_pb12 + avi_pb13);
avi_pb0 = 0x100 - chksum;
dm_i2c_reg_write(p3, 0x43, avi_pb0);
dm_i2c_reg_write(p3, 0x44, avi_pb1);
dm_i2c_reg_write(p3, 0x45, avi_pb2);
//dm_i2c_reg_write(p3, 0x46, 0x00);
dm_i2c_reg_write(p3, 0x47, avi_pb4);
//dm_i2c_reg_write(p3, 0x48, 0x00);
dm_i2c_reg_write(p3, 0x49, avi_pb6);
dm_i2c_reg_write(p3, 0x4a, avi_pb7);
dm_i2c_reg_write(p3, 0x4b, avi_pb8);
dm_i2c_reg_write(p3, 0x4c, avi_pb9);
dm_i2c_reg_write(p3, 0x4d, avi_pb10);
dm_i2c_reg_write(p3, 0x4e, avi_pb11);
dm_i2c_reg_write(p3, 0x4f, avi_pb12);
dm_i2c_reg_write(p3, 0x50, avi_pb13);
}
#endif //__DISP_I2C_LT8912B_H__
HDMI/SBC-1/disp_osd.c
-142
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@@ -1,142 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Author(s): Hammer Hsieh <hammer.hsieh@sunplus.com>
*/
#include <common.h>
#include <cpu_func.h>
#include "reg_disp.h"
#include "display2.h"
#include "disp_osd.h"
#include "disp_palette.h"
/**************************************************************************
* C O N S T A N T S *
**************************************************************************/
// OSD Header config0
#define OSD_HDR_C0_CULT 0x80
#define OSD_HDR_C0_TRANS 0x40
// OSD Header config1
#define OSD_HDR_C1_BS 0x10
#define OSD_HDR_C1_BL2 0x04
#define OSD_HDR_C1_BL 0x01
// OSD control register
#define OSD_CTRL_COLOR_MODE_YUV (0 << 10)
#define OSD_CTRL_COLOR_MODE_RGB (1 << 10)
#define OSD_CTRL_NOT_FETCH_EN (1 << 8)
#define OSD_CTRL_CLUT_FMT_GBRA (0 << 7)
#define OSD_CTRL_CLUT_FMT_ARGB (1 << 7)
#define OSD_CTRL_LATCH_EN (1 << 5)
#define OSD_CTRL_A32B32_EN (1 << 4)
#define OSD_CTRL_FIFO_DEPTH (7 << 0)
//#define OSD0_BASE_ADDR 0x12000000 //tmp setting TBD
/**************************************************************************
* F U N C T I O N I M P L E M E N T A T I O N S *
**************************************************************************/
void DRV_OSD_Init(int width, int height)
{
//u32 value;
//printf("DRV_OSD_Init w %d h %d\n", width, height);
#if 0
G189_OSD0_REG->osd_ctrl = 0x000000a7;
G189_OSD0_REG->osd_en = 0x00000001;
G189_OSD0_REG->osd_base_addr = OSD0_BASE_ADDR;
value = 0x00000000;
value = value | (width << 0);
G189_OSD0_REG->osd_hvld_width = value;
value = 0x00000000;
value = value | (height << 0);
G189_OSD0_REG->osd_vvld_height = value;
#endif
//G189_OSD0_REG->osd_bist_ctrl = 0x00000080; //G189.21 , color bar en , color bar
//G189_OSD0_REG->osd_bist_ctrl = 0x000000C0; //G189.21 , color bar en , border
}
int API_OSD_UI_Init(int w, int h, u32 fb_addr, int input_fmt)
{
UINT32 UI_width = w;
UINT32 UI_height = h;
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_LT8912B_BRIDGE)
if ((CONFIG_VIDEO_SP7350_MAX_XRES == 480) && (CONFIG_VIDEO_SP7350_MAX_YRES == 272)){
UI_width = 480;
UI_height = 272;
}
#endif
if(input_fmt == DRV_OSD_REGION_FORMAT_8BPP)
osd0_header[0] = SWAP32(0x82001000);
//osd0_header[0] = SWAP32(0x820011ff);
else
//osd0_header[0] = SWAP32(0x00001132 | (input_fmt << 24)); alpha value force change
osd0_header[0] = SWAP32(0x00001000 | (input_fmt << 24));
osd0_header[1] = SWAP32((UI_height << 16) | UI_width);
osd0_header[2] = 0;
osd0_header[3] = 0;
osd0_header[4] = 0;
if (input_fmt == DRV_OSD_REGION_FORMAT_YUY2)
osd0_header[5] = SWAP32(0x00040000 | UI_width);
else
osd0_header[5] = SWAP32(0x00010000 | UI_width);
osd0_header[6] = SWAP32(0xFFFFFFE0);
osd0_header[7] = SWAP32(fb_addr);
G189_OSD0_REG->osd_en = 0;
//flush_cache((u32)osd0_header, 128+1024); //Update osd0_header
flush_cache((uintptr_t)osd0_header, 128+1024); //Update osd0_header
//printf("*** [S] dump osd0_header info *** \n");
//printf("0x%08x 0x%08x 0x%08x 0x%08x \n", SWAP32(osd0_header[0]),SWAP32(osd0_header[1]),SWAP32(osd0_header[2]),SWAP32(osd0_header[3]));
//printf("0x%08x 0x%08x 0x%08x 0x%08x \n", SWAP32(osd0_header[4]),SWAP32(osd0_header[5]),SWAP32(osd0_header[6]),SWAP32(osd0_header[7]));
//printf("0x%08x 0x%08x 0x%08x 0x%08x \n", SWAP32(osd0_header[56]),SWAP32(osd0_header[57]),SWAP32(osd0_header[58]),SWAP32(osd0_header[59]));
//printf("0x%08x 0x%08x 0x%08x 0x%08x \n", SWAP32(osd0_header[60]),SWAP32(osd0_header[61]),SWAP32(osd0_header[62]),SWAP32(osd0_header[63]));
//printf("*** [E] dump osd0_header info *** \n");
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_LT8912B_BRIDGE)
if ((CONFIG_VIDEO_SP7350_MAX_XRES == 480) && (CONFIG_VIDEO_SP7350_MAX_YRES == 272)){
UI_width = 720;
UI_height = 480;
}
#endif
G189_OSD0_REG->osd_base_addr = (u32)(uintptr_t)&osd0_header;
G189_OSD0_REG->osd_ctrl = OSD_CTRL_COLOR_MODE_RGB
| OSD_CTRL_CLUT_FMT_ARGB
| OSD_CTRL_LATCH_EN
| OSD_CTRL_A32B32_EN
| OSD_CTRL_FIFO_DEPTH;
G189_OSD0_REG->osd_hvld_offset = 0;
G189_OSD0_REG->osd_vvld_offset = 0;
G189_OSD0_REG->osd_hvld_width = UI_width;
G189_OSD0_REG->osd_vvld_height = UI_height;
//G189_OSD0_REG->osd_data_fetch_ctrl = 0x0af8;
G189_OSD0_REG->osd_bist_ctrl = 0x0;
//G189_OSD0_REG->osd_bist_ctrl = 0x00000080; //G189.21 , color bar en , color bar
//G189_OSD0_REG->osd_bist_ctrl = 0x000000C0; //G189.21 , color bar en , border
G189_OSD0_REG->osd_3d_h_offset = 0x0;
G189_OSD0_REG->osd_src_decimation_sel = 0x0;
G189_OSD0_REG->osd_en = 1;
//GPOST bypass
G193_GPOST0_REG->gpost0_config = 0;
G193_GPOST0_REG->gpost0_master_en = 0;
G193_GPOST0_REG->gpost0_bg1 = 0x8010;
G193_GPOST0_REG->gpost0_bg2 = 0x0080;
//GPOST PQ disable
G193_GPOST0_REG->gpost0_contrast_config = 0x0;
return 0;
}
HDMI/SBC-1/lontium,lt8912b.yaml
-103
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@@ -1,103 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/lontium,lt8912b.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Lontium LT8912B MIPI to HDMI Bridge
maintainers:
- Adrien Grassein <adrien.grassein@gmail.com>
description: |
The LT8912B is a bridge device which convert DSI to HDMI
properties:
compatible:
enum:
- lontium,lt8912b
reg:
maxItems: 1
reset-gpios:
maxItems: 1
description: GPIO connected to active high RESET pin.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Primary MIPI port for MIPI input
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes: true
required:
- data-lanes
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: |
HDMI port, should be connected to a node compatible with the
hdmi-connector binding.
required:
- port@0
- port@1
required:
- compatible
- reg
- reset-gpios
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
hdmi-bridge@48 {
compatible = "lontium,lt8912b";
reg = <0x48>;
reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_out_in: endpoint {
data-lanes = <0 1 2 3>;
remote-endpoint = <&mipi_dsi_out>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
};
...
HDMI/SBC-1/lontium-ly8912b.c
-1028
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File diff suppressed because it is too large Load Diff
HDMI/SBC-1/sp7350_disp_lt8912b.c
-667
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@@ -1,667 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Sunplus SP7350 SoC Display driver
* (Builtin LT8912B BRIDGE I2C controller)
*
* Author: Hammer Hsieh <hammer.hsieh@sunplus.com>
*
* This lt8912b bridge i2c driver is inspired
* from the Linux Kernel driver
* drivers/gpu/drm/bridge/lontium-lt8912b.c
*/
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_of.h>
#include <video/videomode.h>
#define I2C_MAIN 0
#define I2C_ADDR_MAIN 0x48
#define I2C_CEC_DSI 1
#define I2C_ADDR_CEC_DSI 0x49
#define I2C_HDMITX_DSI 2
#define I2C_ADDR_HDMITX_DSI 0x4a
#define I2C_MAX_IDX 3
struct lt8912 {
struct device *dev;
struct i2c_client *i2c_client[I2C_MAX_IDX];
struct regmap *regmap[I2C_MAX_IDX];
struct device_node *host_node;
struct drm_bridge *hdmi_port;
struct mipi_dsi_device *dsi;
struct gpio_desc *gp_reset;
struct videomode mode;
u32 mode_sel;
u32 hdmi_dvi_sel;
u8 data_lanes;
};
struct lt8912 *g_lt;
int lt8912_write_init_config(struct lt8912 *lt)
{
const struct reg_sequence seq[] = {
/* Digital clock en*/
{0x08, 0xff},
{0x09, 0xff},
{0x0a, 0xff},
{0x0b, 0x7c},
{0x0c, 0xff},
{0x42, 0x05},
/*Tx Analog*/
{0x31, 0xb1},
{0x32, 0xb1},
{0x33, 0x0e},
{0x37, 0x00},
{0x38, 0x22},
{0x60, 0x82},
/*Cbus Analog*/
{0x39, 0x45},
{0x3a, 0x00},
{0x3b, 0x00},
/*HDMI Pll Analog*/
{0x44, 0x31},
{0x55, 0x44},
{0x57, 0x01},
{0x5a, 0x02},
/*MIPI Analog*/
{0x3e, 0xd6},
{0x3f, 0xd4},
{0x41, 0x3c},
{0xB2, 0x00},
};
return regmap_multi_reg_write(lt->regmap[I2C_MAIN], seq, ARRAY_SIZE(seq));
}
int lt8912_write_mipi_basic_config(struct lt8912 *lt)
{
const struct reg_sequence seq[] = {
{0x12, 0x04},
{0x14, 0x00},
{0x15, 0x00},
{0x1a, 0x03},
{0x1b, 0x03},
};
return regmap_multi_reg_write(lt->regmap[I2C_CEC_DSI], seq, ARRAY_SIZE(seq));
};
int lt8912_write_dds_config(struct lt8912 *lt)
{
const struct reg_sequence seq[] = {
{0x4e, 0xff},
{0x4f, 0x56},
{0x50, 0x69},
{0x51, 0x80},
{0x1f, 0x5e},
{0x20, 0x01},
{0x21, 0x2c},
{0x22, 0x01},
{0x23, 0xfa},
{0x24, 0x00},
{0x25, 0xc8},
{0x26, 0x00},
{0x27, 0x5e},
{0x28, 0x01},
{0x29, 0x2c},
{0x2a, 0x01},
{0x2b, 0xfa},
{0x2c, 0x00},
{0x2d, 0xc8},
{0x2e, 0x00},
{0x42, 0x64},
{0x43, 0x00},
{0x44, 0x04},
{0x45, 0x00},
{0x46, 0x59},
{0x47, 0x00},
{0x48, 0xf2},
{0x49, 0x06},
{0x4a, 0x00},
{0x4b, 0x72},
{0x4c, 0x45},
{0x4d, 0x00},
{0x52, 0x08},
{0x53, 0x00},
{0x54, 0xb2},
{0x55, 0x00},
{0x56, 0xe4},
{0x57, 0x0d},
{0x58, 0x00},
{0x59, 0xe4},
{0x5a, 0x8a},
{0x5b, 0x00},
{0x5c, 0x34},
{0x1e, 0x4f},
{0x51, 0x00},
};
return regmap_multi_reg_write(lt->regmap[I2C_CEC_DSI], seq, ARRAY_SIZE(seq));
}
int lt8912_write_rxlogicres_config(struct lt8912 *lt)
{
int ret;
ret = regmap_write(lt->regmap[I2C_MAIN], 0x03, 0x7f);
usleep_range(10000, 20000);
ret |= regmap_write(lt->regmap[I2C_MAIN], 0x03, 0xff);
return ret;
};
#if 0
static int lt8912_write_lvds_config(struct lt8912 *lt)
{
const struct reg_sequence seq[] = {
{0x44, 0x30},
{0x51, 0x05},
{0x50, 0x24},
{0x51, 0x2d},
{0x52, 0x04},
{0x69, 0x0e},
{0x69, 0x8e},
{0x6a, 0x00},
{0x6c, 0xb8},
{0x6b, 0x51},
{0x04, 0xfb},
{0x04, 0xff},
{0x7f, 0x00},
{0xa8, 0x13},
{0x02, 0xf7},
{0x02, 0xff},
{0x03, 0xcf},
{0x03, 0xff},
};
return regmap_multi_reg_write(lt->regmap[I2C_CEC_DSI], seq, ARRAY_SIZE(seq));
};
#endif
static const struct regmap_config lt8912_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xff,
};
static int lt8912_init_i2c(struct lt8912 *lt, struct i2c_client *client)
{
unsigned int i;
/*
* At this time we only initialize 2 chips, but the lt8912 provides
* a third interface for the audio over HDMI configuration.
*/
struct i2c_board_info info[] = {
{ I2C_BOARD_INFO("lt8912p0", I2C_ADDR_MAIN), },
{ I2C_BOARD_INFO("lt8912p1", I2C_ADDR_CEC_DSI), },
{ I2C_BOARD_INFO("lt8912p2", I2C_ADDR_HDMITX_DSI), },
};
if (!lt)
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(info); i++) {
if (i > 0) {
lt->i2c_client[i] = i2c_new_dummy_device(client->adapter,
info[i].addr);
if (IS_ERR(lt->i2c_client[i]))
return PTR_ERR(lt->i2c_client[i]);
}
lt->regmap[i] = devm_regmap_init_i2c(lt->i2c_client[i],
&lt8912_regmap_config);
if (IS_ERR(lt->regmap[i]))
return PTR_ERR(lt->regmap[i]);
}
return 0;
}
static int lt8912_free_i2c(struct lt8912 *lt)
{
unsigned int i;
for (i = 1; i < I2C_MAX_IDX; i++)
i2c_unregister_device(lt->i2c_client[i]);
return 0;
}
int lt8912_video_setup(struct lt8912 *lt)
{
u32 hactive, h_total, hpw, hfp, hbp;
u32 vactive, v_total, vpw, vfp, vbp;
u8 settle = 0x08;
int ret;
if (!lt)
return -EINVAL;
hactive = lt->mode.hactive;
hfp = lt->mode.hfront_porch;
hpw = lt->mode.hsync_len;
hbp = lt->mode.hback_porch;
h_total = hactive + hfp + hpw + hbp;
vactive = lt->mode.vactive;
vfp = lt->mode.vfront_porch;
vpw = lt->mode.vsync_len;
vbp = lt->mode.vback_porch;
v_total = vactive + vfp + vpw + vbp;
if (vactive <= 600)
settle = 0x04;
else if (vactive == 1080)
settle = 0x0a;
ret = regmap_write(lt->regmap[I2C_CEC_DSI], 0x10, 0x01);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x11, settle);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x18, hpw);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x19, vpw);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x1c, hactive & 0xff);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x1d, hactive >> 8);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x2f, 0x0c);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x34, h_total & 0xff);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x35, h_total >> 8);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x36, v_total & 0xff);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x37, v_total >> 8);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x38, vbp & 0xff);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x39, vbp >> 8);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x3a, vfp & 0xff);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x3b, vfp >> 8);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x3c, hbp & 0xff);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x3d, hbp >> 8);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x3e, hfp & 0xff);
ret |= regmap_write(lt->regmap[I2C_CEC_DSI], 0x3f, hfp >> 8);
return ret;
}
int lt8912_audio_setup(struct lt8912 *lt)
{
u8 avi_pb0, avi_pb1, avi_pb2, avi_pb4, chksum;
u8 avi_pb6, avi_pb7, avi_pb8, avi_pb9;
u8 avi_pb10, avi_pb11, avi_pb12, avi_pb13;
int ret;
if (!lt)
return -EINVAL;
/*
* bit0 : HDMI Mode 0: DVI mode, 1: HDMI mode
*/
ret = regmap_update_bits(lt->regmap[I2C_MAIN], 0xb2, BIT(0), BIT(0));
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x6, 0x08);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x7, 0xf0);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x9, 0x00);
/*
* bit7-4 : Set Audio Freq
* 0x0: 44.1k, 0x2: 48k, 0x3: 32k,
* 0x8: 88.2k, 0xa:96k, 0xc: 176.4k, 0xe: 192k
*/
#if 1 //audio 48k
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0xf, 0x2b); // set audio 48kHz
/*
* N Value : 32k:4096, 44.1k:6272, 48k:6144,
* 88.2k:12544, 96k:12288, 176k:25088, 196k:24576
*/
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x37, 0x00);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x36, 0x18);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x35, 0x00); //N = 6144(0x1800)
#else //audio 44.1k
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0xf, 0x0b); // set audio 44.1kHz
/*
* N Value : 32k:4096, 44.1k:6272, 48k:6144,
* 88.2k:12544, 96k:12288, 176k:25088, 196k:24576
*/
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x37, 0x00);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x36, 0x18);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x35, 0x80); //N = 6272(0x1880)
#endif
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x34, 0xe2); //0x52 --> 0xE2
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x3c, 0x41); //0x40 --> 0x41
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x3e, 0x0a); //0x0a (default)
//avi settings
if (lt->mode_sel == 0x02) { //720P60
ret |= regmap_write(lt->regmap[I2C_MAIN], 0xab, 0x03); //Positive Polarity
avi_pb1 = 0x1C;
avi_pb2 = 0xa8;
avi_pb4 = 0x04; //VIC_CODE = 4
avi_pb6 = 0x19; //25
avi_pb7 = 0x00;
avi_pb8 = 0xe9; //745
avi_pb9 = 0x02;
avi_pb10 = 0x04; //260
avi_pb11 = 0x01;
avi_pb12 = 0x04; //1540
avi_pb13 = 0x06;
} else if (lt->mode_sel == 0x03) { //1080P60
ret |= regmap_write(lt->regmap[I2C_MAIN], 0xab, 0x03); //Positive Polarity
avi_pb1 = 0x1C;
avi_pb2 = 0xa8;
avi_pb4 = 0x10; //VIC_CODE = 16
avi_pb6 = 0x29; //41
avi_pb7 = 0x00;
avi_pb8 = 0x61; //1121
avi_pb9 = 0x04;
avi_pb10 = 0xc0; //192
avi_pb11 = 0x00;
avi_pb12 = 0x40; //2112
avi_pb13 = 0x08;
} else if (lt->mode_sel == 0x00) { //480P60
ret |= regmap_write(lt->regmap[I2C_MAIN], 0xab, 0x0c); //Negtive Polarity
avi_pb1 = 0x1C;
avi_pb2 = 0x58;
avi_pb4 = 0x02; //VIC_CODE = 2
avi_pb6 = 0x24; //36
avi_pb7 = 0x00;
avi_pb8 = 0x04; //516
avi_pb9 = 0x02;
avi_pb10 = 0x7a; //122
avi_pb11 = 0x00;
avi_pb12 = 0x4a; //842
avi_pb13 = 0x03;
} else {
avi_pb1 = 0x00;
avi_pb2 = 0x00;
avi_pb4 = 0x00;
}
chksum = 0x82 + 0x02 + 0x0d + avi_pb1 + avi_pb2 + avi_pb4;
chksum += (avi_pb6 + avi_pb7 +avi_pb8 + avi_pb9);
chksum += (avi_pb10 + avi_pb11 +avi_pb12 + avi_pb13);
avi_pb0 = 0x100 - chksum;
/*
* 43: avi info pb0 checksum
*/
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x43, avi_pb0);
/*
* 44 - 47: avi info PB1 - PB4
*/
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x44, avi_pb1);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x45, avi_pb2);
//ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x46, 0x00); //fixed 0
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x47, avi_pb4);
//ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x48, 0x00); //fixed 0
/*
* 49 - 50: avi info PB6 - PB13
*/
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x49, avi_pb6);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x4a, avi_pb7);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x4b, avi_pb8);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x4c, avi_pb9);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x4d, avi_pb10);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x4e, avi_pb11);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x4f, avi_pb12);
ret |= regmap_write(lt->regmap[I2C_HDMITX_DSI], 0x50, avi_pb13);
return ret;
}
int lt8912_soft_power_on(struct lt8912 *lt)
{
u32 lanes = 0;
lanes = lt->data_lanes;
lt8912_write_init_config(lt);
regmap_write(lt->regmap[I2C_CEC_DSI], 0x13, lanes & 3);
lt8912_write_mipi_basic_config(lt);
return 0;
}
/*
* lt8912_input_timing[x][y]
* y = 0-1, LT8912 width & height
* y = 2-9, LT8912 HSA & HFP & HBP & HACT & VSA & VFP & VBP & VACT
*/
static const u32 lt8912_input_timing[11][10] = {
/* (w h) HSA HFP HBP HACT VSA VFP VBP VACT */
{ 720, 480, 0x3e, 0x10, 0x3c, 720, 0x6, 0x9, 0x1E, 480}, /* 480P */
{ 720, 576, 0x80, 0x28, 0x58, 720, 0x4, 0x1, 0x17, 576}, /* 576P */
{1280, 720, 0x28, 0x6e, 0xdc, 1280, 0x5, 0x5, 0x14, 720}, /* 720P */
{1920, 1080, 0x2c, 0x58, 0x94, 1920, 0x5, 0x4, 0x24, 1080}, /* 1080P */
{ 64, 64, 0x14, 0x28, 0x58, 64, 0x5, 0x5, 0x24, 64}, /* 64x64 */
{ 128, 128, 0x14, 0x28, 0x58, 128, 0x5, 0x5, 0x24, 128}, /* 128x128 */
{ 64, 2880, 0x14, 0x28, 0x58, 64, 0x5, 0x5, 0x24, 2880}, /* 64x2880 */
{3840, 64, 0x14, 0x28, 0x58, 3840, 0x5, 0x5, 0x24, 64}, /* 3840x64 */
{3840, 2880, 0x14, 0x28, 0x58, 3840, 0x5, 0x5, 0x24, 2880}, /* 3840x2880 */
{ 800, 480, 0x14, 0x28, 0x58, 800, 0x5, 0x5, 0x24, 480}, /* 800x480 */
{1024, 600, 0x14, 0x28, 0x58, 1024, 0x5, 0x5, 0x24, 600} /* 1024x600 */
};
int lt8912_video_on(struct lt8912 *lt)
{
int ret;
u32 i;
i = lt->mode_sel;
if (i > 3) i = 3;
lt->mode.hactive = lt8912_input_timing[i][5];
lt->mode.hfront_porch = lt8912_input_timing[i][3];
lt->mode.hsync_len = lt8912_input_timing[i][2];
lt->mode.hback_porch = lt8912_input_timing[i][4];
lt->mode.vactive = lt8912_input_timing[i][9];
lt->mode.vfront_porch = lt8912_input_timing[i][7];
lt->mode.vsync_len = lt8912_input_timing[i][6];
lt->mode.vback_porch = lt8912_input_timing[i][8];
ret = lt8912_video_setup(lt);
if (ret < 0)
goto end;
ret = lt8912_write_dds_config(lt);
if (ret < 0)
goto end;
ret = lt8912_write_rxlogicres_config(lt);
if (ret < 0)
goto end;
//ret = lt8912_write_lvds_config(lt);
//if (ret < 0)
// goto end;
if (lt->hdmi_dvi_sel) {
pr_info("lt8912 bridge in hdmi mode\n");
ret = lt8912_audio_setup(lt);
if (ret < 0)
goto end;
} else {
pr_info("lt8912 bridge in dvi mode\n");
}
end:
return ret;
}
static int lt8912_parse_dt(struct lt8912 *lt)
{
struct gpio_desc *gp_reset;
struct device *dev = lt->dev;
int ret;
int data_lanes;
u32 hdmi_mode;
u32 mode;
struct device_node *port_node;
struct device_node *endpoint;
gp_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(gp_reset)) {
ret = PTR_ERR(gp_reset);
if (ret != -EPROBE_DEFER)
dev_err(dev, "Failed to get reset gpio: %d\n", ret);
return ret;
}
lt->gp_reset = gp_reset;
ret = of_property_read_u32(dev->of_node, "hdmi-mode", &hdmi_mode);
if (ret)
lt->hdmi_dvi_sel = 0;
else
lt->hdmi_dvi_sel = hdmi_mode;
ret = of_property_read_u32(dev->of_node, "hdmi-timing", &mode);
if (ret)
lt->mode_sel = 0;
else
lt->mode_sel = mode;
endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
if (!endpoint)
return -ENODEV;
data_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
of_node_put(endpoint);
if (data_lanes < 0) {
dev_err(lt->dev, "%s: Bad data-lanes property\n", __func__);
return data_lanes;
}
lt->data_lanes = data_lanes;
lt->host_node = of_graph_get_remote_node(dev->of_node, 0, -1);
if (!lt->host_node) {
dev_err(lt->dev, "%s: Failed to get remote port\n", __func__);
return -ENODEV;
}
port_node = of_graph_get_remote_node(dev->of_node, 1, -1);
if (!port_node) {
dev_err(lt->dev, "%s: Failed to get connector port\n", __func__);
ret = -ENODEV;
goto err_free_host_node;
}
//lt->hdmi_port = of_drm_find_bridge(port_node);
//if (!lt->hdmi_port) {
// dev_err(lt->dev, "%s: Failed to get hdmi port\n", __func__);
// ret = -ENODEV;
// goto err_free_host_node;
//}
if (!of_device_is_compatible(port_node, "hdmi-connector")) {
dev_err(lt->dev, "%s: Failed to get hdmi port\n", __func__);
ret = -EINVAL;
goto err_free_host_node;
}
of_node_put(port_node);
return 0;
err_free_host_node:
of_node_put(port_node);
of_node_put(lt->host_node);
return ret;
}
static int lt8912_probe(struct i2c_client *client)
{
static struct lt8912 *lt;
int ret = 0;
struct device *dev = &client->dev;
lt = devm_kzalloc(dev, sizeof(struct lt8912), GFP_KERNEL);
if (!lt)
return -ENOMEM;
lt->dev = dev;
lt->i2c_client[0] = client;
g_lt = lt;
ret = lt8912_parse_dt(lt);
if (ret)
goto err_dt_parse;
ret = lt8912_init_i2c(lt, client);
if (ret)
goto err_i2c;
i2c_set_clientdata(client, lt);
lt8912_soft_power_on(lt);
lt8912_video_on(lt);
pr_info("sp7350_disp_%s\n", __func__);
return 0;
err_i2c:
err_dt_parse:
return ret;
}
static void lt8912_remove(struct i2c_client *client)
{
struct lt8912 *lt = i2c_get_clientdata(client);
lt8912_free_i2c(lt);
}
static const struct of_device_id lt8912_dt_match[] = {
{.compatible = "lontium,lt8912b-builtin"},
{}
};
MODULE_DEVICE_TABLE(of, lt8912_dt_match);
static const struct i2c_device_id lt8912_id[] = {
{"lt8912b", 0},
{},
};
MODULE_DEVICE_TABLE(i2c, lt8912_id);
static struct i2c_driver lt8912_i2c_driver = {
.driver = {
.name = "lt8912b",
.of_match_table = lt8912_dt_match,
.owner = THIS_MODULE,
},
.probe = lt8912_probe,
.remove = lt8912_remove,
.id_table = lt8912_id,
};
module_i2c_driver(lt8912_i2c_driver);
MODULE_AUTHOR("Hammer Hsieh <hammer.hsieh@sunplus.com>");
MODULE_DESCRIPTION("lt8912 i2c driver");
MODULE_LICENSE("GPL v2");
HDMI/SBC-1/sp7350_display.c
-329
View File
@@ -1,329 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* MIPI CSI/DSI TX display driver
*
* hammer.hsieh <hammer.hsieh@sunplus.com>
*/
#include <common.h>
#include <display.h>
#include <dm.h>
#include <malloc.h>
#include <video.h>
#include <dm/uclass-internal.h>
#include <linux/io.h>
#include "display2.h"
#include "reg_disp.h"
#include "disp_dmix.h"
#include "disp_tgen.h"
#include "disp_tcon.h"
#include "disp_vpp.h"
#include "disp_osd.h"
#include "disp_mipitx.h"
#include <asm/gpio.h>
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_LT8912B_BRIDGE)
#include "disp_i2c_lt8912b.h"
#elif CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_RASPBERRYPI_DSI_PANEL)
#include "disp_i2c_raspberrypi.h"
#endif
//#define debug printf
extern u32 osd0_header[];
struct sp7350_disp_priv *sp_gpio;
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_RASPBERRYPI_DSI_PANEL)
extern int raspberrypi_check_exist(struct udevice *p1);
extern void raspberrypi_pre_init(struct udevice *p1);
extern void raspberrypi_post_init(struct udevice *p1);
#endif
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_LT8912B_BRIDGE)
extern void lt8912_write_init_config(struct udevice *p1);
extern void lt8912_write_mipi_basic_config(struct udevice *p2);
extern void lt8912_write_param_by_resolution(struct udevice *p2, int w, int h);
extern void lt8912_write_dds_config(struct udevice *p2);
extern void lt8912_write_rxlogicres_config(struct udevice *p1);
extern void lt8912_write_lvds_config(struct udevice *p2);
extern void lt8912_hdmi_mode_setup(struct udevice *p1, int hdmi_dvi_sel);
extern void lt8912_audio_setup(struct udevice *p1, struct udevice *p3, int w, int h);
#endif
DECLARE_GLOBAL_DATA_PTR;
static int sp7350_display_probe(struct udevice *dev)
{
struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
int max_bpp = 8; //default 8BPP format
int is_mipi_dsi_tx = 1; //default MIPI_DSI_TX out
int width, height;
void *fb_alloc;
u32 osd_base_addr;
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_LT8912B_BRIDGE)
int i;
unsigned int lt8912b_hdmi_dvi_sel = 0;
#elif CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_RASPBERRYPI_DSI_PANEL)
int i;
#endif
struct sp7350_disp_priv *priv = dev_get_priv(dev);
int ret;
width = CONFIG_VIDEO_SP7350_MAX_XRES;
height = CONFIG_VIDEO_SP7350_MAX_YRES;
printf("Disp: probe ... \n");
DISP_MOON2_REG->sft_cfg[3] = 0xffffffff; //enable all disp clken
printf("Disp: init %dx%d settings\n", width, height);
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_LT8912B_BRIDGE)
if ((CONFIG_VIDEO_SP7350_MAX_XRES == 480) && (CONFIG_VIDEO_SP7350_MAX_YRES == 272)){
width = 720;
height = 480;
}
#endif
#if 0
/*
* refer to kernel dts reserved-memory disp_reserve
*/
fb_alloc = (void *)0x5c000000;
#else
/*
* alloc memory in uboot
*/
fb_alloc = malloc((width*height*
(CONFIG_VIDEO_SP7350_MAX_BPP >> 3)) + 64 );
#endif
//printf("Disp: fb_alloc = 0x%p\n", fb_alloc);
//printf("Disp: fb_alloc = %ld\n", sizeof(fb_alloc));
if (fb_alloc == NULL) {
printf("Error: malloc in %s failed! \n",__func__);
return -EINVAL;
}
if(((uintptr_t)fb_alloc & 0xffffffff00000000) != 0) {
printf("Error: malloc addr over 4GB(%s)\n",__func__);
return -EINVAL;
}
if(((uintptr_t)fb_alloc & 0x3f) != 0)
fb_alloc = (void *)(((uintptr_t)fb_alloc + 64 ) & ~0x3f);
DRV_DMIX_Init();
DRV_TGEN_Init(width, height);
DRV_TCON_Init(width, height);
DRV_VPP_Init(width, height);
DRV_OSD_Init(width, height);
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_LT8912B_BRIDGE)
lt8912b_hdmi_dvi_sel = dev_read_u32_default(dev,"sunplus,lt8912b_hdmi_mode", 0);
//printf("Disp: sunplus,lt8912b_hdmi_mode %d \n", lt8912b_hdmi_dvi_sel);
#elif CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_RASPBERRYPI_DSI_PANEL)
#else
if (is_mipi_dsi_tx) {
ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset, GPIOD_IS_OUT);
if (ret) {
printf("reset-gpios not found\n");
if (ret != -ENOENT)
return ret;
}
}
#endif
sp_gpio = priv;
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_LT8912B_BRIDGE)
DRV_mipitx_Init_1(is_mipi_dsi_tx, width, height);
#else
DRV_mipitx_Init(is_mipi_dsi_tx, width, height);
#endif
//osd_base_addr = (u32)((uintptr_t)fb_alloc & 0x00000000ffffffff);
osd_base_addr = (u32)((uintptr_t)fb_alloc);
if(CONFIG_VIDEO_SP7350_MAX_BPP == 8) {
API_OSD_UI_Init(width ,height, osd_base_addr, DRV_OSD_REGION_FORMAT_8BPP);
max_bpp = 8;
}
else if(CONFIG_VIDEO_SP7350_MAX_BPP == 16) {
API_OSD_UI_Init(width ,height, osd_base_addr, DRV_OSD_REGION_FORMAT_RGB_565);
max_bpp = 16;
}
else if(CONFIG_VIDEO_SP7350_MAX_BPP == 32) {
API_OSD_UI_Init(width ,height, osd_base_addr, DRV_OSD_REGION_FORMAT_ARGB_8888);
max_bpp = 32;
}
else {
//printf("only support 8/16/32\n",);
API_OSD_UI_Init(width ,height, osd_base_addr, DRV_OSD_REGION_FORMAT_8BPP);
max_bpp = 8;
}
//printf("G189.02 0x%08x\n", G189_OSD0_REG->osd_base_addr);
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_LT8912B_BRIDGE)
if ((CONFIG_VIDEO_SP7350_MAX_XRES == 480) && (CONFIG_VIDEO_SP7350_MAX_YRES == 272)){
width = 480;
height = 272;
}
#endif
uc_plat->base = (ulong)fb_alloc;
uc_plat->size = width * height * (max_bpp >> 3);
uc_priv->xsize = width;
uc_priv->ysize = height;
uc_priv->rot = CONFIG_VIDEO_SP7350_ROTATE;
if(CONFIG_VIDEO_SP7350_MAX_BPP == 16) {
uc_priv->bpix = VIDEO_BPP16;
uc_priv->format = VIDEO_FMT_RGB565;
}
else if(CONFIG_VIDEO_SP7350_MAX_BPP == 32) {
uc_priv->bpix = VIDEO_BPP32;
uc_priv->format = VIDEO_FMT_ARGB8888;
}
else {
uc_priv->bpix = VIDEO_BPP8;
uc_priv->format = VIDEO_FMT_8BPP_ARGB;
}
#ifdef CONFIG_BMP_8BPP_UPDATE_CMAP
if(uc_priv->bpix == VIDEO_BPP8) {
uc_priv->cmap = (u32 *)(uintptr_t)(osd0_header+32);
}
#endif
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_RASPBERRYPI_DSI_PANEL)
for (i = 0; i < 8; i++) {
ret = i2c_get_chip_for_busnum(i, ATMEL_MCU_I2C_ADDR, 1, &priv->chip1);
//printf("i2c bus%d chip1 scan ret %d\n", i, ret);
if (ret) {
//printf("i2c bus%d chip1 scan ret %d\n", i, ret);
if (i == 7) {
printf("Disp: dsi panel not found\n");
goto skip_attiny88;
}
} else {
break;
}
}
ret = raspberrypi_check_exist(priv->chip1);
//if (ret)
// goto skip_attiny88;
raspberrypi_pre_init(priv->chip1);
DRV_mipitx_Init(is_mipi_dsi_tx, width, height);
raspberrypi_post_init(priv->chip1);
printf("Disp: init dsi panel RASPBERRYPI_DSI_PANEL\n");
//printf("MIPITX DSI Panel : RASPBERRYPI_DSI_PANEL(%dx%d)\n", width, height);
skip_attiny88:
#endif
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_SP7350_LT8912B_BRIDGE)
for (i = 0; i < 8; i++) {
ret = i2c_get_chip_for_busnum(i, LT8912B_I2C_ADDR_MAIN, 1, &priv->chip1);
if (ret) {
//printf("i2c bus%d chip1 scan ret %d\n", i, ret);
if (i == 7) {
printf("Disp: lt8912b bridge not found\n");
goto skip_lt8912b;
} else {
continue;
}
}
ret = i2c_get_chip_for_busnum(i, LT8912B_I2C_ADDR_CEC_DSI, 1, &priv->chip2);
if (ret) {
//printf("i2c bus%d chip2 scan ret %d\n", i, ret);
return ret;
} else {
;//break;
}
ret = i2c_get_chip_for_busnum(i, LT8912B_I2C_ADDR_HDMITX_DSI, 1, &priv->chip3);
if (ret) {
//printf("i2c bus%d chip3 scan ret %d\n", i, ret);
return ret;
} else {
break;
}
}
if ((CONFIG_VIDEO_SP7350_MAX_XRES == 480) && (CONFIG_VIDEO_SP7350_MAX_YRES == 272)){
lt8912b_hdmi_dvi_sel = 0; //dvi mode only
width = 720;
height = 480;
}
if (lt8912b_hdmi_dvi_sel)
printf("Disp:: init lt8912b bridge ic\n");
else
printf("Disp: init lt8912b bridge ic\n");
lt8912_write_init_config(priv->chip1);
lt8912_write_mipi_basic_config(priv->chip2);
lt8912_write_param_by_resolution(priv->chip2, width, height);
lt8912_write_dds_config(priv->chip2);
lt8912_write_rxlogicres_config(priv->chip1);
lt8912_write_lvds_config(priv->chip2);
if (lt8912b_hdmi_dvi_sel)
lt8912_hdmi_mode_setup(priv->chip1, 1); //0: DVI Mode, (1: HDMI Mode)
else
lt8912_hdmi_mode_setup(priv->chip1, 0); //(0: DVI Mode), 1: HDMI Mode
lt8912_audio_setup(priv->chip1, priv->chip3, width, height);
skip_lt8912b:
#endif
video_set_flush_dcache(dev, true);
printf("Disp: probe done \n");
return 0;
}
static int sp7350_display_bind(struct udevice *dev)
{
struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
uc_plat->size = 0;
return 0;
}
static const struct video_ops sp7350_display_ops = {
};
static const struct udevice_id sp7350_display_ids[] = {
{ .compatible = "sunplus,sp7350-display" },
{ .compatible = "sunplus,sp7350-display-subsystem" },
{ }
};
U_BOOT_DRIVER(sp7350_display) = {
.name = "sp7350_display",
.id = UCLASS_VIDEO,
.ops = &sp7350_display_ops,
.of_match = sp7350_display_ids,
.bind = sp7350_display_bind,
.probe = sp7350_display_probe,
.priv_auto = sizeof(struct sp7350_disp_priv),
};