diff --git a/HDMI/LT8912B-HDMI-extra.patch b/HDMI/LT8912B-HDMI-extra.patch deleted file mode 100644 index 86f3fa86b..000000000 --- a/HDMI/LT8912B-HDMI-extra.patch +++ /dev/null @@ -1,301 +0,0 @@ -diff --git a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi ---- a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -+++ b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -@@ -42,9 +42,9 @@ - hfront-porch = <88>; - hsync-len = <44>; - hback-porch = <148>; -- vfront-porch = <56>; -- vsync-len = <6>; -- vback-porch = <60>; -+ vfront-porch = <4>; -+ vsync-len = <5>; -+ vback-porch = <36>; - }; - }; - }; -diff --git a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi ---- a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -+++ b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -@@ -42,9 +42,9 @@ - hfront-porch = <88>; - hsync-len = <44>; - hback-porch = <148>; -- vfront-porch = <56>; -- vsync-len = <6>; -- vback-porch = <60>; -+ vfront-porch = <4>; -+ vsync-len = <5>; -+ vback-porch = <36>; - }; - }; - }; -diff --git a/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi ---- a/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -+++ b/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -@@ -47,9 +47,9 @@ - hfront-porch = <88>; - hsync-len = <44>; - hback-porch = <148>; -- vfront-porch = <56>; -+ vfront-porch = <38>; - vsync-len = <6>; -- vback-porch = <60>; -+ vback-porch = <40>; - }; - }; - }; -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c -@@ -9,6 +9,7 @@ - u8 Hsync_L, Hsync_H, Vsync_L, Vsync_H; - u8 mipi_det_fail_count = 0; - u8 mipi_relock_count = 0; -+bool mipi_video_ready = 0; - - - bool suspend_on = 0; -@@ -24,11 +25,13 @@ - struct video_timing video_1280x720_60Hz = {110, 40, 220, 1280, 1650, 5, 5, 20, 720, 750, 1,1, 4, AR_16_9, 74250}; - struct video_timing video_1280x800_60Hz = {28, 32, 100, 1280, 1440, 2, 6, 15, 800, 823, 0,0, 0, AR_16_9, 71000}; - //struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 4, 5, 36, 1080, 1125, 1,1,16, AR_16_9, 148500}; --struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 56, 6, 60, 1080, 1202, 1,1, 0, AR_16_9, 153600}; -+struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 4, 5, 36, 1080, 1125, 1,1,16, AR_16_9, 153600}; - - struct video_timing *video; - --void DDSConfig(void); -+void DDSConfig(struct video_timing *video_format); -+void HdmiOutput(bool on); -+u8 LT8912_Get_HPD(void); - - void DigitalClockEn(void) - { -@@ -72,25 +75,66 @@ - { - u8 VIC = video_format->vic; - u8 AR = video_format->aspact_ratio; -- u8 pb0,pb2,pb4,Sync_Polarity; -+ u8 pb0,pb1,pb2,pb4,Sync_Polarity; -+ u8 pb6, pb7, pb8, pb9, pb10, pb11, pb12, pb13; -+ u8 checksum; - - I2CADR = 0x94; - HDMI_WriteI2C_Byte(0x3c,0x41); //enable null package - - Sync_Polarity = (video_format->h_polarity*0x02) + (video_format->v_polarity*0x01); -- pb2 = (AR<<4) + 0x08; -- pb4 = VIC; -- pb0 = (((pb2 + pb4) <= 0x5f)?(0x5f - pb2 - pb4):(0x15f - pb2 - pb4)); -+ if (video_format->hact == 1920 && video_format->vact == 1080) { -+ Sync_Polarity = 0x03; -+ pb1 = 0x1c; -+ pb2 = 0xa8; -+ pb4 = 0x10; -+ pb6 = 0x29; -+ pb7 = 0x00; -+ pb8 = 0x61; -+ pb9 = 0x04; -+ pb10 = 0xc0; -+ pb11 = 0x00; -+ pb12 = 0x40; -+ pb13 = 0x08; -+ } else { -+ pb1 = 0x10; -+ pb2 = (AR<<4) + 0x08; -+ pb4 = VIC; -+ pb6 = 0x00; -+ pb7 = 0x00; -+ pb8 = 0x00; -+ pb9 = 0x00; -+ pb10 = 0x00; -+ pb11 = 0x00; -+ pb12 = 0x00; -+ pb13 = 0x00; -+ } -+ -+ checksum = 0x82 + 0x02 + 0x0d + pb1 + pb2 + pb4; -+ checksum += pb6 + pb7 + pb8 + pb9; -+ checksum += pb10 + pb11 + pb12 + pb13; -+ pb0 = 0x100 - checksum; - - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0xab,Sync_Polarity); //sync polarity - - I2CADR = 0x94; - HDMI_WriteI2C_Byte(0x43,pb0); //PB0:check sum -- HDMI_WriteI2C_Byte(0x44,0x10); //PB1:RGB888 -+ HDMI_WriteI2C_Byte(0x44,pb1); //PB1 - HDMI_WriteI2C_Byte(0x45,pb2); //PB2 - HDMI_WriteI2C_Byte(0x46,0x00); //PB3 - HDMI_WriteI2C_Byte(0x47,pb4); //PB4:vic -+ HDMI_WriteI2C_Byte(0x49,pb6); -+ HDMI_WriteI2C_Byte(0x4a,pb7); -+ HDMI_WriteI2C_Byte(0x4b,pb8); -+ HDMI_WriteI2C_Byte(0x4c,pb9); -+ HDMI_WriteI2C_Byte(0x4d,pb10); -+ HDMI_WriteI2C_Byte(0x4e,pb11); -+ HDMI_WriteI2C_Byte(0x4f,pb12); -+ HDMI_WriteI2C_Byte(0x50,pb13); -+ printk("%s AviInfoframe %ux%u pb0=0x%02x pb1=0x%02x pb2=0x%02x vic=%u sync=0x%02x\n", -+ LOG_FLAG, video_format->hact, video_format->vact, -+ pb0, pb1, pb2, pb4, Sync_Polarity); - } - - void MipiAnalog(void) -@@ -128,7 +172,13 @@ - - void MIPI_Video_Setup(struct video_timing *video_format) - { -+ u8 settle = 0x10; -+ -+ if (video_format->vact == 1080) -+ settle = 0x0a; -+ - I2CADR = 0x92; -+ HDMI_WriteI2C_Byte(0x11, settle); // settle - HDMI_WriteI2C_Byte(0x18,(u8)(video_format->hs%256)); // hwidth - HDMI_WriteI2C_Byte(0x19,(u8)(video_format->vs%256)); // vwidth - HDMI_WriteI2C_Byte(0x1c,(u8)(video_format->hact%256)); // H_active[7:0] -@@ -146,6 +196,10 @@ - HDMI_WriteI2C_Byte(0x3d,(u8)(video_format->hbp/256)); // HBP[15:8] - HDMI_WriteI2C_Byte(0x3e,(u8)(video_format->hfp%256)); // HFP[7:0] - HDMI_WriteI2C_Byte(0x3f,(u8)(video_format->hfp/256)); // HFP[15:8] -+ printk("%s MIPI_Video_Setup %ux%u total=%ux%u pclk=%u settle=0x%02x vic=%u\n", -+ LOG_FLAG, video_format->hact, video_format->vact, -+ video_format->htotal, video_format->vtotal, -+ video_format->pclk_khz, settle, video_format->vic); - video = video_format; - } - -@@ -168,19 +222,26 @@ - - MipiAnalog(); - MipiBasicSet(); -- DDSConfig(); -+ DDSConfig(&video_1920x1080_60Hz); - MIPI_Video_Setup(&video_1920x1080_60Hz); - AviInfoframe(&video_1920x1080_60Hz); - MIPIRxLogicRes(); - } - --void DDSConfig(void) -+void DDSConfig(struct video_timing *video_format) - { -+ u32 dds_word; -+ -+ dds_word = (video_format->pclk_khz / 1000) * 0x16C16; -+ dds_word += ((video_format->pclk_khz % 1000) * 0x16C16 + 500) / 1000; -+ - I2CADR = 0x92; -- HDMI_WriteI2C_Byte(0x4e,0x93);//strm_sw_freq_word[ 7: 0] -- HDMI_WriteI2C_Byte(0x4f,0x3E);//strm_sw_freq_word[15: 8] -- HDMI_WriteI2C_Byte(0x50,0x29);//strm_sw_freq_word[23:16] -+ HDMI_WriteI2C_Byte(0x4e,(u8)(dds_word & 0xff));//strm_sw_freq_word[ 7: 0] -+ HDMI_WriteI2C_Byte(0x4f,(u8)((dds_word >> 8) & 0xff));//strm_sw_freq_word[15: 8] -+ HDMI_WriteI2C_Byte(0x50,(u8)((dds_word >> 16) & 0xff));//strm_sw_freq_word[23:16] - HDMI_WriteI2C_Byte(0x51,0x80);//[0]=strm_sw_freq_word[24] -+ printk("%s DDSConfig pclk=%u kHz word=0x%06x\n", -+ LOG_FLAG, video_format->pclk_khz, dds_word); - HDMI_WriteI2C_Byte(0x1e,0x4f); - HDMI_WriteI2C_Byte(0x1f,0x5e);//full_value 464 - HDMI_WriteI2C_Byte(0x20,0x01); -@@ -231,8 +292,15 @@ - I2CADR = 0x94; - HDMI_WriteI2C_Byte(0x06,0x08); - HDMI_WriteI2C_Byte(0x07,0xF0); -- HDMI_WriteI2C_Byte(0x34,0xD2);//0xE2:32FS; 0xD2:64FS -+ HDMI_WriteI2C_Byte(0x09,0x00); -+ HDMI_WriteI2C_Byte(0x34,0xE2);//0xE2:32FS; 0xD2:64FS -+ HDMI_WriteI2C_Byte(0x35,0x00);//N = 6144(0x1800) -+ HDMI_WriteI2C_Byte(0x36,0x18); -+ HDMI_WriteI2C_Byte(0x37,0x00); -+ HDMI_WriteI2C_Byte(0x3c,0x41); -+ HDMI_WriteI2C_Byte(0x3e,0x0a); - HDMI_WriteI2C_Byte(0x0F,0x2B); -+ printk("%s HDMI audio packet setup: 48k N=0x1800\n", LOG_FLAG); - } - - void AudioSpdifEn(void) -@@ -500,11 +568,8 @@ - if (mipi_det_fail_count < 0xff) - mipi_det_fail_count++; - -- if (mipi_det_fail_count >= 10 && mipi_relock_count < 5) { -- mipi_relock_count++; -- mipi_det_fail_count = 0; -- LT8912B_MIPI_Relock(); -- } -+ if (mipi_det_fail_count == 10) -+ printk("%s MIPI input invalid, skip auto relock\n", LOG_FLAG); - } else { - mipi_det_fail_count = 0; - } -@@ -525,7 +590,7 @@ - video_valid = true; - printk("%s videoformat = VESA_1280x800_60\n",LOG_FLAG); - } -- else if(Vsync_H == 0x04 && Vsync_L <= 0xb6&&Vsync_L >= 0x63)//0x4b2 -+ else if(Vsync_H == 0x04 && Vsync_L <= 0x67&&Vsync_L >= 0x63)//0x465 - { - video = &video_1920x1080_60Hz; - video_valid = true; -@@ -544,9 +609,21 @@ - if (video_valid) { - mipi_det_fail_count = 0; - mipi_relock_count = 0; -+ mipi_video_ready = 1; -+ DDSConfig(video); - MIPI_Video_Setup(video); - AviInfoframe(video); - MIPIRxLogicRes(); -+ -+ #ifdef _hdmi_output -+ if (LT8912_Get_HPD() && !Tx_HPD) { -+ msleep(50); -+ HdmiOutput(1); -+ Tx_HPD = 1; -+ printk("%s HDMI output enabled after valid MIPI video\n", -+ LOG_FLAG); -+ } -+ #endif - } - } - -@@ -716,7 +793,7 @@ - HDMIPllAnalog(); - MipiAnalog(); - MipiBasicSet(); -- DDSConfig(); -+ DDSConfig(&video_1920x1080_60Hz); - MIPI_Video_Setup(&video_1920x1080_60Hz); - MIPI_Input_det(); - AudioIIsEn(); -@@ -726,7 +803,7 @@ - lt8912_check_dds(); // can be removed when debug stage. - #endif - -- #ifdef _lvds_bypass -+ #ifdef _lvds_output - lvds_output_cfg(); - LvdsOutput(1); - #endif -@@ -737,7 +814,7 @@ - ///////////////////////////////////////////////////////////// - - #ifdef _hdmi_output -- if(LT8912_Get_HPD()) -+ if(LT8912_Get_HPD() && mipi_video_ready) - { - if(!Tx_HPD) - { -@@ -769,7 +846,7 @@ - #ifdef _hdmi_output - if(LT8912_Get_HPD()) - { -- if(!Tx_HPD) -+ if(mipi_video_ready && !Tx_HPD) - { - LT8912B_Suspend(0); - HdmiOutput(1); diff --git a/HDMI/LT8912B-HDMI.patch b/HDMI/LT8912B-HDMI.patch deleted file mode 100644 index 16538c92e..000000000 --- a/HDMI/LT8912B-HDMI.patch +++ /dev/null @@ -1,3596 +0,0 @@ -LT8912B HDMI bring-up patch for UIS7885-2H10 - -Generated from current workspace HDMI-related source changes. -Apply from source_sync_rls_25c with: - patch -p1 < ../HDMI/LT8912B-HDMI.patch - -diff --git a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4.bb b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4.bb -index 664cdf2e..a1aa82ad 100755 ---- a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4.bb -+++ b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4.bb -@@ -22,6 +22,7 @@ SRC_URI = "file://serial.cfg \ - file://kernel-config/8021q_vlan.cfg \ - ${KERNEL_MACHINE_PATCH} \ - ${@bb.utils.contains('USERDEBUG', 'userdebug', 'file://userdebug.cfg', 'file://user.cfg', d)} \ -+ file://enable-8912.cfg \ - " - - PV = "5.4" -diff --git a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts -index 02c344bd..3396f85d 100755 ---- a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts -+++ b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts -@@ -7,7 +7,7 @@ - #include - #include "lcd/lcd_g40396_truly_mipi_fhd.dtsi" - #include "lcd/lcd_nt36672e_truly_mipi_fhd_nodsc.dtsi" --#include "lcd/lcd_dummy_mipi.dtsi" -+#include "lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi" - #include "tp/ums9620-tp.dtsi" - #include - #include -@@ -223,8 +223,8 @@ - compatible = "unisoc,marlin3lite_sdio"; - m2-wakeup-ap-gpios = <&ap_gpio 128 GPIO_ACTIVE_LOW>; - reset-gpios = <&ap_gpio 172 GPIO_ACTIVE_LOW>; -- enable-gpios = <&ap_gpio 171 GPIO_ACTIVE_LOW>; -- m2-to-ap-irq-gpios = <&ap_gpio 173 GPIO_ACTIVE_LOW>; -+ enable-gpios = <&ap_gpio 151 GPIO_ACTIVE_LOW>; -+ m2-to-ap-irq-gpios = <&ap_gpio 177 GPIO_ACTIVE_LOW>; - xtal-26m-clk-type = "TCXO"; - avdd12-supply = <&vddwcn>; - avdd33-supply = <&vddwifipa>; -@@ -234,8 +234,8 @@ - clocks = <&aonapb_gate CLK_AUX0>, - <&ext_32k>, - <&aonapb_gate CLK_AUX0_EB>; -- extcon = <&sdio1>; -- sdhci-name = <&sdio1>; -+ extcon = <&sdio2>; -+ sdhci-name = <&sdio2>; - sprd,btwf-file-name = "/dev/block/by-name/wcnmodem"; - sprd,gnss-file-name = "/vendor/firmware/gnssmodem.bin"; - adma-tx; -@@ -354,7 +354,7 @@ - }; - - &chosen { -- bootargs = "earlycon console=ttyS1,921600n8 loglevel=1 init=/sbin/init root=/dev/mmcblk0p31 rootfstype=ext4 ro rootwait printk.devkmsg=on sprdboot.boot_devices=soc/soc:ap-ahb/20600000.sdio dummy_hcd.num=0 swiotlb=1 initcall_debug=1"; -+ bootargs = "earlycon console=ttyS1,921600n8 loglevel=1 init=/sbin/init root=/dev/mmcblk0p31 rootfstype=ext4 ro rootwait printk.devkmsg=on dummy_hcd.num=0 swiotlb=1 initcall_debug=1"; - bootargs_ext = "sprdboot.hardware=uis7885_2h10 sprdboot.dtbo_idx=0"; - }; - -@@ -407,13 +407,6 @@ - #address-cells = <1>; - #size-cells = <0>; - -- ucp1301_spk: ucp1301@58 { -- compatible = "sprd,ucp1301-spk"; -- reg = <0x58>; -- reset-gpios = <&ap_gpio 120 GPIO_ACTIVE_HIGH>; -- #sound-dai-cells = <1>; -- }; -- - bq2560x_chg: charger@6b { - compatible = "ti,bq2560x_chg"; - reg = <0x6b>; -@@ -426,7 +419,6 @@ - bq2597x_chg: charger@65 { - compatible = "ti,bq2597x-standalone"; - reg = <0x65>; -- irq-gpio = <&ap_gpio 193 GPIO_ACTIVE_LOW>; - - ti,bq2597x,bus-therm-disable = <1>; - ti,bq2597x,regulation-disable = <1>; -@@ -472,7 +464,36 @@ - - &usb { - extcon = <&extcon_gpio>, <&pmic_typec>; -- vbus-supply = <&vddvbus>; -+ /*vbus-supply = <&vddvbus>;*/ -+ status = "okay"; -+}; -+ -+&ap_gpio { -+ hdmi_5v_en { -+ gpio-hog; -+ gpios = <187 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "hdmi-5v-en"; -+ }; -+ -+ rtl8111_3v3_en { -+ gpio-hog; -+ gpios = <147 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "rtl8111-3v3-en"; -+ }; -+ -+ serial_level_en { -+ gpio-hog; -+ gpios = <140 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "serial-level-en"; -+ }; -+}; -+ -+&pwms { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm2_pwmc>; - status = "okay"; - }; - -@@ -486,7 +507,7 @@ - - &usb3 { - extcon = <&extcon_gpio>, <&pmic_typec>; -- vbus-supply = <&vddvbus>; -+ /*vbus-supply = <&vddvbus>;*/ - status = "okay"; - }; - -@@ -523,7 +544,14 @@ - }; - - &sdio0 { -- cd-gpios = <&eic_sync 35 GPIO_ACTIVE_HIGH>; -+ cd-gpios = <&eic_sync 35 GPIO_ACTIVE_LOW>; -+}; -+ -+&pmic_typec { -+ /*usb-channel-switch-hub;*/ -+ usb-hub-en = <&ap_gpio 41 GPIO_ACTIVE_HIGH>; -+ usb-hub-5v-en = <&ap_gpio 146 GPIO_ACTIVE_HIGH>; -+ usb-channel-sw = <&ap_gpio 188 GPIO_ACTIVE_HIGH>; - }; - - &pmic_fgu { -@@ -564,10 +592,7 @@ - }; - - &panel { -- sprd,backlight = <&pwm_backlight>; -- avdd-gpio = <&ap_gpio 192 GPIO_ACTIVE_HIGH>; -- avee-gpio = <&ap_gpio 191 GPIO_ACTIVE_HIGH>; -- reset-gpio = <&ap_gpio 11 GPIO_ACTIVE_HIGH>; -+ sprd,backlight = <&pwm_backlight>; - }; - - &dpu { -@@ -637,76 +662,39 @@ - }; - - &i2c0 { -- status = "okay"; -+ status = "disabled"; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -- -- sensor_main: sensor-main@20 { -- compatible = "sprd,sensor-main"; -- reg = <0x20>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR0>,<&mm_gate CLK_SENSOR0_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama0>; -- vddcamd-supply = <&vddcamd0>; -- vddcammot-supply = <&vddcammot0>; -- reset-gpios = <&ap_gpio 40 0>; -- power-down-gpios = <&ap_gpio 46 0>; -- sprd,phyid = <0>; -- csi = <&csi0>; -- power-domains = <&mm_domain>; -- }; -- -- sensor_sub: sensor-sub@5a { -- compatible = "sprd,sensor-sub"; -- reg = <0x5a>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR0>,<&mm_gate CLK_SENSOR0_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama0>; -- vddcamd-supply = <&vddcamd0>; -- vddcammot-supply = <&vddcammot0>; -- reset-gpios = <&ap_gpio 39 0>; -- power-down-gpios = <&ap_gpio 45 0>; -- sprd,phyid = <1>; -- csi = <&csi1>; -- power-domains = <&mm_domain>; -- }; - }; - - &i2c1 { -+ status = "disabled"; -+ clock-frequency = <400000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+}; -+ -+&i2c2 { - status = "okay"; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - -- sensor_main2: sensor-main2@20 { -- compatible = "sprd,sensor-main2"; -- reg = <0x20>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR1>,<&mm_gate CLK_SENSOR1_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama1>; -- vddcamd-supply = <&vddcamd1>; -- avdd-gpios = <&ap_gpio 79 0>; -- reset-gpios = <&ap_gpio 41 0>; -- power-down-gpios = <&ap_gpio 47 0>; -- sprd,phyid = <3>;/*6*/ -- csi = <&csi3>; -- power-domains = <&mm_domain>; -+ lt8912b: lt8912b@48 { -+ compatible = "lontium,lt8912b"; -+ reg = <0x48>; -+ power-gpios = <&ap_gpio 99 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&ap_gpio 11 GPIO_ACTIVE_HIGH>; -+ interrupt-gpios = <&ap_gpio 132 GPIO_ACTIVE_HIGH>; -+ -+ lt8912b_addr_1: lt8912b_addr_1@49 { -+ addr_1_reg = /bits/ 8 <0x49>; -+ }; -+ -+ lt8912b_addr_2: lt8912b_addr_2@4a { -+ addr_2_reg = /bits/ 8 <0x4a>; -+ }; - }; - }; - -@@ -716,9 +704,9 @@ - #address-cells = <1>; - #size-cells = <0>; - -- sensor_main3: sensor-main3@20 { -- compatible = "sprd,sensor-main3"; -- reg = <0x20>; -+ sensor_imx258_a: sensor-imx258-a@1a { -+ compatible = "sprd,sensor-main"; -+ reg = <0x1a>; - clock-names = "clk_src","sensor_eb", - "clk_96m","clk_64m", - "clk_51m2","clk_48m","clk_26m"; -@@ -726,15 +714,13 @@ - <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, - <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; - vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama2>; -- vddcamd-supply = <&vddcamd2>; -- vddcammot-supply = <&vddcammot1>; -- mot-gpios = <&ap_gpio 78 0>; - reset-gpios = <&ap_gpio 42 0>; -- sprd,phyid = <2>;/*4*/ -+ power-down-gpios = <&ap_gpio 47 0>; -+ sprd,phyid = <2>; - csi = <&csi2>; - power-domains = <&mm_domain>; - }; -+ - }; - - &i2c5 { -@@ -742,44 +728,6 @@ - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -- -- sensor_sub2: sensor-sensor_sub2@2a { -- compatible = "sprd,sensor-sub2"; -- reg = <0x2a>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR1>,<&mm_gate CLK_SENSOR1_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama1>; -- vddcamd-supply = <&vddcamd1>; -- reset-gpios = <&ap_gpio 44 0>; -- power-down-gpios = <&ap_gpio 50 0>; -- sprd,phyid = <5>; -- csi = <&csi2>; -- power-domains = <&mm_domain>; -- }; -- -- sensor_sub3: sensor-sensor_sub3@2e { -- compatible = "sprd,sensor-sub3"; -- reg = <0x2e>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR3>,<&mm_gate CLK_SENSOR3_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama2>; -- vddcamd-supply = <&vddcamd2>; -- reset-gpios = <&ap_gpio 43 0>; -- power-down-gpios = <&ap_gpio 49 0>; -- sprd,phyid = <7>; -- csi = <&csi3>; -- power-domains = <&mm_domain>; -- }; - }; - - &i2c6 { -@@ -788,10 +736,19 @@ - #address-cells = <1>; - #size-cells = <0>; - -+ aw87xxx_pa@58 { -+ compatible = "awinic,aw87xxx_pa"; -+ reg = <0x58>; -+ /* reset-gpio = <&ap_gpio 1 0>;*/ -+ dev_index = < 0 >; -+ status = "okay"; -+ }; -+ - flash_ic: flash-ic@63 { - compatible = "sprd,flash-ocp8137"; - reg = <0x63>; - sprd,flash-ic = <8137>; -+ status = "disabled"; - sprd,torch = <1>; - sprd,preflash = <1>; - sprd,highlight = <1>; -@@ -806,54 +763,99 @@ - }; - }; - -+&i2c7 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ wm8960: codec@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ #sound-dai-cells = <0>; -+ wlf,shared-lrclk; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart3 { -+ status = "okay"; -+}; -+ - &pdm_dmic { - status = "okay"; - }; - -+&spi0 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_grp &spi0_di_grp>; -+ num-chipselect = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ spidev0: spidev@0 { -+ compatible = "rohm,dh2228fv"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ -+&i2s0 { -+ compatible = "unisoc,i2s"; -+ status = "okay"; -+ -+ sprd,config_type = "i2s"; -+ sprd,fs = <48000>; -+ sprd,bus_type = <0>; -+ sprd,slave_mode = <0>; -+ sprd,rtx_mode = <3>; -+ sprd,byte_per_chan = <2>; -+ sprd,lsb = <0>; -+ sprd,lrck = <0>; -+ sprd,clk_inv = <0>; -+ sprd,tx_watermark = <12>; -+ sprd,rx_watermark = <20>; -+}; -+ -+&vbc_v4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ap_iis0_5>; -+}; -+ -+&sound_sprd_ap_alliis { -+ status = "okay"; -+ -+ sprd-audio-card,dai-link@0 { -+ format = "i2s"; -+ bitclock-master = <&wm8960_cpu>; -+ frame-master = <&wm8960_cpu>; -+ -+ plat { -+ sound-dai = <&sprd_pcm_iis>; -+ }; -+ -+ wm8960_cpu: cpu { -+ sound-dai = <&i2s0>; -+ }; -+ -+ codec { -+ sound-dai = <&wm8960>; -+ }; -+ }; -+}; -+ - &sprd_headset { - status = "okay"; -- extcon = <&pmic_typec>; -- mic-gpios = <&ap_gpio 62 GPIO_ACTIVE_HIGH>; -- lr-gpios = <&ap_gpio 61 GPIO_ACTIVE_HIGH>; -- sprd,3pole-adc-threshold = <112>; -+ sprd,jack-type = <1>; /* 0: normal-open jack; 1: normal-close jack */ - }; - - &sound_vbc_v4_sprd_codec { - status = "okay"; -- sprd-audio-card,routing = -- "HPMIC Pin", "HP Mic Jack", -- "MIC Pin", "Mic Jack", -- "MIC2 Pin", "Aux Mic Jack", -- "MIC3 Pin", "Aux Mic2 Jack", -- "HeadPhone Jack", "HP Pin", -- "Ext Spk", "SPK Pin", -- "UCP1301 SPK ON", "SPK Pin", -- "Ext Spk", "UCP1301 SPK", -- "PDM DMIC2 ON", "SPK Pin", -- "Ext Spk", "PDM_DMIC2", -- "DMIC Pin", "DMic Jack", -- "DMIC1 Pin", "DMic1 Jack", -- "Ext Ear", "EAR Pin"; -- -- /* 35: ucp1301 normal ap01 */ -- sprd-audio-card,dai-link@53 { -- ignore-suspend = <1>; -- link-name = "BE_NORMAL_AP01_UCPSPK"; -- stream-name = "BE_ST_NORMAL_AP01_UCPSPK"; -- no-pcm = <1>; -- dpcm-playback = <1>; -- be-id = <0>; -- dai-format = "i2s"; -- plat { -- sound-dai = <&sprd_route_pcm>; -- }; -- cpu { -- sound-dai = <&vbc_v4 31>; -- }; -- codec { -- sound-dai = <&ucp1301_spk 0>; -- }; -- }; -+ extral-iic-pa-cnt = <1>; - - /* - * node 54 and node 55 (index 36 and 37) are reserved for -@@ -950,4 +952,32 @@ - pins = "QOGIRN6PRO_KEYOUT1"; - function = "func4"; - }; -+ -+ pwm2_pwmc: pwmc { -+ pins = "QOGIRN6PRO_PWMC"; -+ function = "func1"; -+ }; -+ -+ spi0_grp: spi0_grp { -+ pins = "QOGIRN6PRO_SPI0_CLK", -+ "QOGIRN6PRO_SPI0_DO", -+ "QOGIRN6PRO_SPI0_CSN"; -+ function = "func1"; -+ }; -+ -+ spi0_di_grp: spi0-di-grp { -+ pins = "QOGIRN6PRO_SPI0_DI"; -+ function = "func1"; -+ input-enable; -+ bias-disable; -+ }; -+ -+ iis1_pins: iis1-grp { -+ pins = "QOGIRN6PRO_IIS1CLK", -+ "QOGIRN6PRO_IIS1LRCK", -+ "QOGIRN6PRO_IIS1DO", -+ "QOGIRN6PRO_IIS1DI"; -+ function = "func1"; -+ bias-disable; -+ }; - }; -diff --git a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/enable-8912.cfg b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/enable-8912.cfg -new file mode 100644 ---- a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/enable-8912.cfg -+++ b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/enable-8912.cfg -@@ -0,0 +1 @@ -+CONFIG_LT8912B=y -\ No newline at end of file -diff --git a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -new file mode 100644 ---- a/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -+++ b/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -@@ -0,0 +1,54 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * LT8912B MIPI-DSI to HDMI 1080p dummy panel config. -+ */ -+ -+/ { -+ fragment { -+ target-path = "/"; -+ __overlay__ { -+ lcds { -+ lcd_dummy_mipi_hd: lcd_dummy_mipi_hd { -+ sprd,dsi-work-mode = <2>; /* video pulse mode */ -+ sprd,dsi-lane-number = <4>; -+ sprd,dsi-color-format = "rgb888"; -+ -+ sprd,phy-bit-clock = <1200000>; /* kbps 921600 1200000 */ -+ sprd,phy-escape-clock = <20000>; /* kHz */ -+ sprd,video-lp-cmd-enable = <0>; -+ sprd,hporch-lp-disable = <1>; -+ sprd,width-mm = <121>; -+ sprd,height-mm = <68>; -+ sprd,esd-check-enable = <0>; -+ sprd,esd-check-mode = <1>; -+ sprd,esd-check-period = <1000>; -+ sprd,panel-if-type = <2>; -+ sprd,reset-on-sequence = <1 5>, <0 5>, <1 5>, <0 5>, <1 20>; -+ sprd,reset-off-sequence = <0 20>; -+ sprd,initial-command = [ -+ ]; -+ sprd,sleep-in-command = [ -+ ]; -+ sprd,sleep-out-command = [ -+ ]; -+ -+ display-timings { -+ native-mode = <<8912b_1080p_timing0>; -+ -+ lt8912b_1080p_timing0: timing0 { -+ clock-frequency = <153600000>; -+ hactive = <1920>; -+ vactive = <1080>; -+ hfront-porch = <88>; -+ hsync-len = <44>; -+ hback-porch = <148>; -+ vfront-porch = <56>; -+ vsync-len = <6>; -+ vback-porch = <60>; -+ }; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -diff --git a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/uis7885-2h10-overlay.dts b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/uis7885-2h10-overlay.dts -index 6faf7c901cf3..3396f85d05d4 100755 ---- a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/uis7885-2h10-overlay.dts -+++ b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/uis7885-2h10-overlay.dts -@@ -7,7 +7,7 @@ - #include - #include "lcd/lcd_g40396_truly_mipi_fhd.dtsi" - #include "lcd/lcd_nt36672e_truly_mipi_fhd_nodsc.dtsi" --#include "lcd/lcd_dummy_mipi.dtsi" -+#include "lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi" - #include "tp/ums9620-tp.dtsi" - #include - #include -@@ -223,8 +223,8 @@ - compatible = "unisoc,marlin3lite_sdio"; - m2-wakeup-ap-gpios = <&ap_gpio 128 GPIO_ACTIVE_LOW>; - reset-gpios = <&ap_gpio 172 GPIO_ACTIVE_LOW>; -- enable-gpios = <&ap_gpio 171 GPIO_ACTIVE_LOW>; -- m2-to-ap-irq-gpios = <&ap_gpio 173 GPIO_ACTIVE_LOW>; -+ enable-gpios = <&ap_gpio 151 GPIO_ACTIVE_LOW>; -+ m2-to-ap-irq-gpios = <&ap_gpio 177 GPIO_ACTIVE_LOW>; - xtal-26m-clk-type = "TCXO"; - avdd12-supply = <&vddwcn>; - avdd33-supply = <&vddwifipa>; -@@ -234,8 +234,8 @@ - clocks = <&aonapb_gate CLK_AUX0>, - <&ext_32k>, - <&aonapb_gate CLK_AUX0_EB>; -- extcon = <&sdio1>; -- sdhci-name = <&sdio1>; -+ extcon = <&sdio2>; -+ sdhci-name = <&sdio2>; - sprd,btwf-file-name = "/dev/block/by-name/wcnmodem"; - sprd,gnss-file-name = "/vendor/firmware/gnssmodem.bin"; - adma-tx; -@@ -354,7 +354,7 @@ - }; - - &chosen { -- bootargs = "earlycon console=ttyS1,115200n8 loglevel=1 init=/sbin/init root=/dev/mmcblk0p31 rootfstype=ext4 ro rootwait printk.devkmsg=on sprdboot.boot_devices=soc/soc:ap-ahb/20600000.sdio dummy_hcd.num=0 swiotlb=1 initcall_debug=1"; -+ bootargs = "earlycon console=ttyS1,921600n8 loglevel=1 init=/sbin/init root=/dev/mmcblk0p31 rootfstype=ext4 ro rootwait printk.devkmsg=on dummy_hcd.num=0 swiotlb=1 initcall_debug=1"; - bootargs_ext = "sprdboot.hardware=uis7885_2h10 sprdboot.dtbo_idx=0"; - }; - -@@ -407,13 +407,6 @@ - #address-cells = <1>; - #size-cells = <0>; - -- ucp1301_spk: ucp1301@58 { -- compatible = "sprd,ucp1301-spk"; -- reg = <0x58>; -- reset-gpios = <&ap_gpio 120 GPIO_ACTIVE_HIGH>; -- #sound-dai-cells = <1>; -- }; -- - bq2560x_chg: charger@6b { - compatible = "ti,bq2560x_chg"; - reg = <0x6b>; -@@ -426,7 +419,6 @@ - bq2597x_chg: charger@65 { - compatible = "ti,bq2597x-standalone"; - reg = <0x65>; -- irq-gpio = <&ap_gpio 193 GPIO_ACTIVE_LOW>; - - ti,bq2597x,bus-therm-disable = <1>; - ti,bq2597x,regulation-disable = <1>; -@@ -472,7 +464,36 @@ - - &usb { - extcon = <&extcon_gpio>, <&pmic_typec>; -- vbus-supply = <&vddvbus>; -+ /*vbus-supply = <&vddvbus>;*/ -+ status = "okay"; -+}; -+ -+&ap_gpio { -+ hdmi_5v_en { -+ gpio-hog; -+ gpios = <187 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "hdmi-5v-en"; -+ }; -+ -+ rtl8111_3v3_en { -+ gpio-hog; -+ gpios = <147 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "rtl8111-3v3-en"; -+ }; -+ -+ serial_level_en { -+ gpio-hog; -+ gpios = <140 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "serial-level-en"; -+ }; -+}; -+ -+&pwms { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm2_pwmc>; - status = "okay"; - }; - -@@ -486,7 +507,7 @@ - - &usb3 { - extcon = <&extcon_gpio>, <&pmic_typec>; -- vbus-supply = <&vddvbus>; -+ /*vbus-supply = <&vddvbus>;*/ - status = "okay"; - }; - -@@ -523,7 +544,14 @@ - }; - - &sdio0 { -- cd-gpios = <&eic_sync 35 GPIO_ACTIVE_HIGH>; -+ cd-gpios = <&eic_sync 35 GPIO_ACTIVE_LOW>; -+}; -+ -+&pmic_typec { -+ /*usb-channel-switch-hub;*/ -+ usb-hub-en = <&ap_gpio 41 GPIO_ACTIVE_HIGH>; -+ usb-hub-5v-en = <&ap_gpio 146 GPIO_ACTIVE_HIGH>; -+ usb-channel-sw = <&ap_gpio 188 GPIO_ACTIVE_HIGH>; - }; - - &pmic_fgu { -@@ -534,6 +562,10 @@ - fgu-capacity-track; - phys = <&ssphy>; - -+ sprd,relax-counter-threshold = <580>; -+ sprd,relax-current-threshold = <30>; -+ sprd,capacity-sleep-calibration; -+ - sprd,capacity-boot-calibration; - sprd,capacity-charge-cycle; - sprd,basp; -@@ -560,10 +592,7 @@ - }; - - &panel { -- sprd,backlight = <&pwm_backlight>; -- avdd-gpio = <&ap_gpio 192 GPIO_ACTIVE_HIGH>; -- avee-gpio = <&ap_gpio 191 GPIO_ACTIVE_HIGH>; -- reset-gpio = <&ap_gpio 11 GPIO_ACTIVE_HIGH>; -+ sprd,backlight = <&pwm_backlight>; - }; - - &dpu { -@@ -608,6 +637,14 @@ - status = "disabled"; - }; - -+&vddsim0 { -+ status = "disabled"; -+}; -+ -+&vddsim1 { -+ status = "disabled"; -+}; -+ - &avdd12 { - regulator-always-on; - }; -@@ -625,76 +662,39 @@ - }; - - &i2c0 { -- status = "okay"; -+ status = "disabled"; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -- -- sensor_main: sensor-main@20 { -- compatible = "sprd,sensor-main"; -- reg = <0x20>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR0>,<&mm_gate CLK_SENSOR0_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama0>; -- vddcamd-supply = <&vddcamd0>; -- vddcammot-supply = <&vddcammot0>; -- reset-gpios = <&ap_gpio 40 0>; -- power-down-gpios = <&ap_gpio 46 0>; -- sprd,phyid = <0>; -- csi = <&csi0>; -- power-domains = <&mm_domain>; -- }; -- -- sensor_sub: sensor-sub@5a { -- compatible = "sprd,sensor-sub"; -- reg = <0x5a>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR0>,<&mm_gate CLK_SENSOR0_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama0>; -- vddcamd-supply = <&vddcamd0>; -- vddcammot-supply = <&vddcammot0>; -- reset-gpios = <&ap_gpio 39 0>; -- power-down-gpios = <&ap_gpio 45 0>; -- sprd,phyid = <1>; -- csi = <&csi1>; -- power-domains = <&mm_domain>; -- }; - }; - - &i2c1 { -+ status = "disabled"; -+ clock-frequency = <400000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+}; -+ -+&i2c2 { - status = "okay"; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - -- sensor_main2: sensor-main2@20 { -- compatible = "sprd,sensor-main2"; -- reg = <0x20>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR1>,<&mm_gate CLK_SENSOR1_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama1>; -- vddcamd-supply = <&vddcamd1>; -- avdd-gpios = <&ap_gpio 79 0>; -- reset-gpios = <&ap_gpio 41 0>; -- power-down-gpios = <&ap_gpio 47 0>; -- sprd,phyid = <3>;/*6*/ -- csi = <&csi3>; -- power-domains = <&mm_domain>; -+ lt8912b: lt8912b@48 { -+ compatible = "lontium,lt8912b"; -+ reg = <0x48>; -+ power-gpios = <&ap_gpio 99 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&ap_gpio 11 GPIO_ACTIVE_HIGH>; -+ interrupt-gpios = <&ap_gpio 132 GPIO_ACTIVE_HIGH>; -+ -+ lt8912b_addr_1: lt8912b_addr_1@49 { -+ addr_1_reg = /bits/ 8 <0x49>; -+ }; -+ -+ lt8912b_addr_2: lt8912b_addr_2@4a { -+ addr_2_reg = /bits/ 8 <0x4a>; -+ }; - }; - }; - -@@ -704,9 +704,9 @@ - #address-cells = <1>; - #size-cells = <0>; - -- sensor_main3: sensor-main3@20 { -- compatible = "sprd,sensor-main3"; -- reg = <0x20>; -+ sensor_imx258_a: sensor-imx258-a@1a { -+ compatible = "sprd,sensor-main"; -+ reg = <0x1a>; - clock-names = "clk_src","sensor_eb", - "clk_96m","clk_64m", - "clk_51m2","clk_48m","clk_26m"; -@@ -714,15 +714,13 @@ - <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, - <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; - vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama2>; -- vddcamd-supply = <&vddcamd2>; -- vddcammot-supply = <&vddcammot1>; -- mot-gpios = <&ap_gpio 78 0>; - reset-gpios = <&ap_gpio 42 0>; -- sprd,phyid = <2>;/*4*/ -+ power-down-gpios = <&ap_gpio 47 0>; -+ sprd,phyid = <2>; - csi = <&csi2>; - power-domains = <&mm_domain>; - }; -+ - }; - - &i2c5 { -@@ -730,44 +728,6 @@ - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -- -- sensor_sub2: sensor-sensor_sub2@2a { -- compatible = "sprd,sensor-sub2"; -- reg = <0x2a>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR1>,<&mm_gate CLK_SENSOR1_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama1>; -- vddcamd-supply = <&vddcamd1>; -- reset-gpios = <&ap_gpio 44 0>; -- power-down-gpios = <&ap_gpio 50 0>; -- sprd,phyid = <5>; -- csi = <&csi2>; -- power-domains = <&mm_domain>; -- }; -- -- sensor_sub3: sensor-sensor_sub3@2e { -- compatible = "sprd,sensor-sub3"; -- reg = <0x2e>; -- clock-names = "clk_src","sensor_eb", -- "clk_96m","clk_64m", -- "clk_51m2","clk_48m","clk_26m"; -- clocks = <&mm_clk CLK_SENSOR3>,<&mm_gate CLK_SENSOR3_EN>, -- <&g5l_pll CLK_TGPLL_96M>,<&g5l_pll CLK_TGPLL_64M>, -- <&g5l_pll CLK_TGPLL_51M2>,<&g5l_pll CLK_TGPLL_48M>,<&ext_26m>; -- vddio-supply = <&vddcamio>; -- vddcama-supply = <&vddcama2>; -- vddcamd-supply = <&vddcamd2>; -- reset-gpios = <&ap_gpio 43 0>; -- power-down-gpios = <&ap_gpio 49 0>; -- sprd,phyid = <7>; -- csi = <&csi3>; -- power-domains = <&mm_domain>; -- }; - }; - - &i2c6 { -@@ -776,10 +736,19 @@ - #address-cells = <1>; - #size-cells = <0>; - -+ aw87xxx_pa@58 { -+ compatible = "awinic,aw87xxx_pa"; -+ reg = <0x58>; -+ /* reset-gpio = <&ap_gpio 1 0>;*/ -+ dev_index = < 0 >; -+ status = "okay"; -+ }; -+ - flash_ic: flash-ic@63 { - compatible = "sprd,flash-ocp8137"; - reg = <0x63>; - sprd,flash-ic = <8137>; -+ status = "disabled"; - sprd,torch = <1>; - sprd,preflash = <1>; - sprd,highlight = <1>; -@@ -794,54 +763,99 @@ - }; - }; - -+&i2c7 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ wm8960: codec@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ #sound-dai-cells = <0>; -+ wlf,shared-lrclk; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart3 { -+ status = "okay"; -+}; -+ - &pdm_dmic { - status = "okay"; - }; - -+&spi0 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_grp &spi0_di_grp>; -+ num-chipselect = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ spidev0: spidev@0 { -+ compatible = "rohm,dh2228fv"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ -+&i2s0 { -+ compatible = "unisoc,i2s"; -+ status = "okay"; -+ -+ sprd,config_type = "i2s"; -+ sprd,fs = <48000>; -+ sprd,bus_type = <0>; -+ sprd,slave_mode = <0>; -+ sprd,rtx_mode = <3>; -+ sprd,byte_per_chan = <2>; -+ sprd,lsb = <0>; -+ sprd,lrck = <0>; -+ sprd,clk_inv = <0>; -+ sprd,tx_watermark = <12>; -+ sprd,rx_watermark = <20>; -+}; -+ -+&vbc_v4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ap_iis0_5>; -+}; -+ -+&sound_sprd_ap_alliis { -+ status = "okay"; -+ -+ sprd-audio-card,dai-link@0 { -+ format = "i2s"; -+ bitclock-master = <&wm8960_cpu>; -+ frame-master = <&wm8960_cpu>; -+ -+ plat { -+ sound-dai = <&sprd_pcm_iis>; -+ }; -+ -+ wm8960_cpu: cpu { -+ sound-dai = <&i2s0>; -+ }; -+ -+ codec { -+ sound-dai = <&wm8960>; -+ }; -+ }; -+}; -+ - &sprd_headset { - status = "okay"; -- extcon = <&pmic_typec>; -- mic-gpios = <&ap_gpio 62 GPIO_ACTIVE_HIGH>; -- lr-gpios = <&ap_gpio 61 GPIO_ACTIVE_HIGH>; -- sprd,3pole-adc-threshold = <112>; -+ sprd,jack-type = <1>; /* 0: normal-open jack; 1: normal-close jack */ - }; - - &sound_vbc_v4_sprd_codec { - status = "okay"; -- sprd-audio-card,routing = -- "HPMIC Pin", "HP Mic Jack", -- "MIC Pin", "Mic Jack", -- "MIC2 Pin", "Aux Mic Jack", -- "MIC3 Pin", "Aux Mic2 Jack", -- "HeadPhone Jack", "HP Pin", -- "Ext Spk", "SPK Pin", -- "UCP1301 SPK ON", "SPK Pin", -- "Ext Spk", "UCP1301 SPK", -- "PDM DMIC2 ON", "SPK Pin", -- "Ext Spk", "PDM_DMIC2", -- "DMIC Pin", "DMic Jack", -- "DMIC1 Pin", "DMic1 Jack", -- "Ext Ear", "EAR Pin"; -- -- /* 35: ucp1301 normal ap01 */ -- sprd-audio-card,dai-link@53 { -- ignore-suspend = <1>; -- link-name = "BE_NORMAL_AP01_UCPSPK"; -- stream-name = "BE_ST_NORMAL_AP01_UCPSPK"; -- no-pcm = <1>; -- dpcm-playback = <1>; -- be-id = <0>; -- dai-format = "i2s"; -- plat { -- sound-dai = <&sprd_route_pcm>; -- }; -- cpu { -- sound-dai = <&vbc_v4 31>; -- }; -- codec { -- sound-dai = <&ucp1301_spk 0>; -- }; -- }; -+ extral-iic-pa-cnt = <1>; - - /* - * node 54 and node 55 (index 36 and 37) are reserved for -@@ -938,4 +952,32 @@ - pins = "QOGIRN6PRO_KEYOUT1"; - function = "func4"; - }; -+ -+ pwm2_pwmc: pwmc { -+ pins = "QOGIRN6PRO_PWMC"; -+ function = "func1"; -+ }; -+ -+ spi0_grp: spi0_grp { -+ pins = "QOGIRN6PRO_SPI0_CLK", -+ "QOGIRN6PRO_SPI0_DO", -+ "QOGIRN6PRO_SPI0_CSN"; -+ function = "func1"; -+ }; -+ -+ spi0_di_grp: spi0-di-grp { -+ pins = "QOGIRN6PRO_SPI0_DI"; -+ function = "func1"; -+ input-enable; -+ bias-disable; -+ }; -+ -+ iis1_pins: iis1-grp { -+ pins = "QOGIRN6PRO_IIS1CLK", -+ "QOGIRN6PRO_IIS1LRCK", -+ "QOGIRN6PRO_IIS1DO", -+ "QOGIRN6PRO_IIS1DI"; -+ function = "func1"; -+ bias-disable; -+ }; - }; -diff --git a/source/kernel/kernel5.4/drivers/gpu/drm/sprd/dsi/sprd_dsi_api.c b/source/kernel/kernel5.4/drivers/gpu/drm/sprd/dsi/sprd_dsi_api.c -index d7ab66e11d6c..d4600032cd51 100644 ---- a/source/kernel/kernel5.4/drivers/gpu/drm/sprd/dsi/sprd_dsi_api.c -+++ b/source/kernel/kernel5.4/drivers/gpu/drm/sprd/dsi/sprd_dsi_api.c -@@ -4,8 +4,10 @@ - */ - - #include -+#include - - #include "sprd_dsi_hal.h" -+#include "core/dsi_ctrl_r1p0.h" - - static int dsi_wait_tx_payload_fifo_empty(struct sprd_dsi *dsi) - { -@@ -140,6 +142,29 @@ static u16 round_video_size(int coding, u16 video_size) - return video_size; - } - -+static void sprd_dsi_dump_video_regs(struct sprd_dsi *dsi, const char *tag) -+{ -+ struct dsi_reg *reg = (struct dsi_reg *)dsi->ctx.base; -+ -+ pr_info("DSI regs[%s]: VERSION=0x%08x SOFT_RESET=0x%08x MODE_CFG=0x%08x VCID=0x%08x DPI_FMT=0x%08x\n", -+ tag, readl(®->DSI_VERSION), readl(®->SOFT_RESET), -+ readl(®->DSI_MODE_CFG), readl(®->VIRTUAL_CHANNEL_ID), -+ readl(®->DPI_VIDEO_FORMAT)); -+ pr_info("DSI regs[%s]: VID_PKT=0x%08x HBLK=0x%08x HLINE=0x%08x VBLK=0x%08x VACT=0x%08x VID_MODE=0x%08x NULLPKT=0x%08x SIG_DELAY=0x%08x\n", -+ tag, readl(®->VIDEO_PKT_CONFIG), -+ readl(®->VIDEO_LINE_HBLK_TIME), -+ readl(®->VIDEO_LINE_TIME), readl(®->VIDEO_VBLK_LINES), -+ readl(®->VIDEO_VACTIVE_LINES), readl(®->VID_MODE_CFG), -+ readl(®->VIDEO_NULLPKT_SIZE), -+ readl(®->VIDEO_SIG_DELAY_CONFIG)); -+ pr_info("DSI regs[%s]: PHY_STATUS=0x%08x PHY_LANE_NUM=0x%08x PHY_CLK_TIME=0x%08x PHY_DATA_TIME=0x%08x EOTP_EN=0x%08x\n", -+ tag, readl(®->PHY_STATUS), -+ readl(®->PHY_LANE_NUM_CONFIG), -+ readl(®->PHY_CLKLANE_TIME_CONFIG), -+ readl(®->PHY_DATALANE_TIME_CONFIG), -+ readl(®->EOTP_EN)); -+} -+ - #define SPRD_MIPI_DSI_FMT_DSC 0xff - static u32 fmt_to_coding(u32 fmt) - { -@@ -298,7 +323,8 @@ int sprd_dsi_dpi_video(struct sprd_dsi *dsi) - dsi_hal_vblk_cmd_trans_limit(dsi, 0x80); - if (!ctx->hporch_lp_disable) - dsi_hal_dpi_hporch_lp_en(dsi, 1); -- dsi_hal_dpi_vporch_lp_en(dsi, 1); -+ dsi_hal_dpi_hporch_lp_en(dsi, 0); -+ dsi_hal_dpi_vporch_lp_en(dsi, 0); - dsi_hal_dpi_hsync_pol(dsi, 0); - dsi_hal_dpi_vsync_pol(dsi, 0); - dsi_hal_dpi_data_en_pol(dsi, 0); -@@ -319,6 +345,11 @@ int sprd_dsi_dpi_video(struct sprd_dsi *dsi) - dsi_hal_dpi_video_packet_size(dsi, video_size); - dsi_hal_dpi_null_packet_size(dsi, 0); - dsi_hal_dpi_chunk_num(dsi, 0); -+ pr_info("DSI DPI video: burst=%u coding=%u video_size=%u chunks=%u null=%u Bpp_x100=%u ratio_x1000=%u hline=%u hs=%u hbp=%u vact=%u vfp=%u vbp=%u vs=%u hporch_lp_disable=%u\n", -+ ctx->burst_mode, coding, video_size, 0, 0, Bpp_x100, -+ ratio_x1000, hline, vm->hsync_len, vm->hback_porch, -+ vm->vactive, vm->vfront_porch, vm->vback_porch, -+ vm->vsync_len, ctx->hporch_lp_disable); - } else { - /* non burst transmission */ - null_pkt_size = 0; -@@ -326,21 +357,34 @@ int sprd_dsi_dpi_video(struct sprd_dsi *dsi) - /* bytes to be sent - first as one chunk */ - bytes_per_chunk = vm->hactive * Bpp_x100 / 100 + pkt_header; - -- /* hline total bytes from the DPI interface */ -+ /* -+ * hline total bytes from the DPI interface. -+ * ctx->byte_clk is the byte clock for one data lane, so the -+ * available payload budget across the whole DSI link scales -+ * with the number of enabled lanes. -+ */ - total_bytes = (vm->hactive + vm->hfront_porch) * -- ratio_x1000 / ctx->lanes / 1000; -+ ratio_x1000 * ctx->lanes / 1000; -+ pr_info("DSI DPI budget: total=%u chunk=%u lanes=%u byte_clk=%u pclk=%lu ratio=%u hact=%u hfp=%u\n", -+ total_bytes, bytes_per_chunk, ctx->lanes, ctx->byte_clk, -+ vm->pixelclock, ratio_x1000, vm->hactive, -+ vm->hfront_porch); - - /* check if the pixels actually fit on the DSI link */ - if (total_bytes < bytes_per_chunk) { -- pr_err("current resolution can not be set\n"); -+ pr_err("current resolution can not be set: total=%u chunk=%u lanes=%u byte_clk=%u pclk=%lu\n", -+ total_bytes, bytes_per_chunk, ctx->lanes, -+ ctx->byte_clk, vm->pixelclock); -+ dsi_hal_power_en(dsi, 1); -+ sprd_dsi_dump_video_regs(dsi, "dpi-video-budget-fail"); - return -EINVAL; - } - - chunk_overhead = total_bytes - bytes_per_chunk; - -- /* overhead higher than 1 -> enable multi packets */ - if (chunk_overhead > 1) { - -+ /* overhead higher than 1 -> enable multi packets */ - /* multi packets */ - for (video_size = video_size_step; - video_size < vm->hactive; -@@ -383,11 +427,18 @@ int sprd_dsi_dpi_video(struct sprd_dsi *dsi) - dsi_hal_dpi_video_packet_size(dsi, video_size); - dsi_hal_dpi_null_packet_size(dsi, null_pkt_size); - dsi_hal_dpi_chunk_num(dsi, chunks); -+ pr_info("DSI DPI video: burst=%u coding=%u video_size=%u chunks=%u null=%u Bpp_x100=%u ratio_x1000=%u hline=%u hs=%u hbp=%u vact=%u vfp=%u vbp=%u vs=%u hporch_lp_disable=%u\n", -+ ctx->burst_mode, coding, video_size, chunks, -+ null_pkt_size, Bpp_x100, ratio_x1000, hline, -+ vm->hsync_len, vm->hback_porch, vm->vactive, -+ vm->vfront_porch, vm->vback_porch, vm->vsync_len, -+ ctx->hporch_lp_disable); - } - - dsi_hal_int0_mask(dsi, ctx->int0_mask); - dsi_hal_int1_mask(dsi, ctx->int1_mask); - dsi_hal_power_en(dsi, 1); -+ sprd_dsi_dump_video_regs(dsi, "after-dpi-video"); - - return 0; - } -diff --git a/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sprd_dsi.c b/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sprd_dsi.c -index 85e56d55fe16..5b29adf27337 100644 ---- a/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sprd_dsi.c -+++ b/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sprd_dsi.c -@@ -25,6 +25,7 @@ - #include "sprd_dsi.h" - #include "sprd_dsi_panel.h" - #include "dsi/sprd_dsi_api.h" -+#include "dsi/sprd_dsi_hal.h" - #include "dphy/sprd_dphy_api.h" - #include "sysfs/sysfs_display.h" - -@@ -37,6 +38,9 @@ - - static void sprd_dsi_enable(struct sprd_dsi *dsi) - { -+ DRM_INFO("sprd_dsi_enable: enter work_mode=%d burst_mode=%d\n", -+ dsi->ctx.work_mode, dsi->ctx.burst_mode); -+ - if (dsi->glb->power) - dsi->glb->power(&dsi->ctx, true); - if (dsi->glb->enable) -@@ -50,6 +54,9 @@ static void sprd_dsi_enable(struct sprd_dsi *dsi) - sprd_dsi_dpi_video(dsi); - else - sprd_dsi_edpi_video(dsi); -+ -+ DRM_INFO("sprd_dsi_enable: exit work_mode=%d burst_mode=%d\n", -+ dsi->ctx.work_mode, dsi->ctx.burst_mode); - } - - static void sprd_dsi_disable(struct sprd_dsi *dsi) -@@ -62,6 +69,38 @@ static void sprd_dsi_disable(struct sprd_dsi *dsi) - dsi->glb->power(&dsi->ctx, false); - } - -+static void sprd_dsi_dump_link_status(struct sprd_dsi *dsi, const char *tag) -+{ -+ DRM_INFO("DSI ctx[%s]: enabled=%d work_mode=%d burst_mode=%d lanes=%d phy_freq=%u byte_clk=%u esc_clk=%u dpi_clk_div=%d nc_clk=%d hporch_lp_disable=%d video_lp_cmd=%d frame_ack=%d phy_enabled=%d ulps_enable=%d\n", -+ tag, dsi->ctx.enabled, dsi->ctx.work_mode, -+ dsi->ctx.burst_mode, dsi->ctx.lanes, -+ dsi->phy ? dsi->phy->ctx.freq : 0, dsi->ctx.byte_clk, -+ dsi->ctx.esc_clk, dsi->ctx.dpi_clk_div, dsi->ctx.nc_clk_en, -+ dsi->ctx.hporch_lp_disable, dsi->ctx.video_lp_cmd_en, -+ dsi->ctx.frame_ack_en, -+ dsi->phy ? dsi->phy->ctx.enabled : 0, -+ dsi->phy ? dsi->phy->ctx.ulps_enable : 0); -+ DRM_INFO("DSI vm[%s]: pclk=%lu h=%u/%u/%u/%u v=%u/%u/%u/%u format=0x%x\n", -+ tag, dsi->ctx.vm.pixelclock, dsi->ctx.vm.hactive, -+ dsi->ctx.vm.hfront_porch, dsi->ctx.vm.hsync_len, -+ dsi->ctx.vm.hback_porch, dsi->ctx.vm.vactive, -+ dsi->ctx.vm.vfront_porch, dsi->ctx.vm.vsync_len, -+ dsi->ctx.vm.vback_porch, dsi->ctx.format); -+} -+ -+static bool sprd_panel_is_lt8912b_dummy(struct sprd_panel *panel) -+{ -+ return panel && panel->lcd_name && -+ !strcmp(panel->lcd_name, "lcd_dummy_mipi_hd"); -+} -+ -+static void sprd_dsi_disable_eotp_for_lt8912b(struct sprd_dsi *dsi) -+{ -+ dsi_hal_eotp_rx_en(dsi, 0); -+ dsi_hal_eotp_tx_en(dsi, 0); -+ DRM_INFO("LT8912B debug: force DSI TX/RX EOTP disabled\n"); -+} -+ - int dsi_panel_set_dpms_mode(struct sprd_dsi *dsi) - { - mutex_lock(&dsi->lock); -@@ -108,10 +147,14 @@ static void sprd_dsi_encoder_enable(struct drm_encoder *encoder) - struct sprd_dsi *dsi = encoder_to_dsi(encoder); - struct sprd_crtc *crtc = to_sprd_crtc(encoder->crtc); - struct sprd_dpu *dpu = crtc->priv; -+ struct sprd_panel *panel = NULL; - - DRM_INFO("%s(last_dpms=%d, dpms=%d)\n", - __func__, dsi->ctx.last_dpms, dsi->ctx.dpms); - -+ if (dsi->panel) -+ panel = container_of(dsi->panel, struct sprd_panel, base); -+ - mutex_lock(&dsi->lock); - /* add if condition to avoid resume dsi for SR feature. - * if esd recovery happened during display suspend, skip dsi resume. -@@ -134,6 +177,33 @@ static void sprd_dsi_encoder_enable(struct drm_encoder *encoder) - - if (dsi->ctx.enabled) { - DRM_INFO("dsi is initialized\n"); -+ sprd_dsi_dump_link_status(dsi, "already-enabled"); -+ if (!strcmp(dpu->ctx.version, "dpu-r6p0") && -+ dsi->ctx.work_mode == DSI_MODE_VIDEO) { -+ if (sprd_panel_is_lt8912b_dummy(panel)) -+ sprd_dsi_disable_eotp_for_lt8912b(dsi); -+ -+ /* -+ * Bootloader marks DSI as enabled, so the normal enable -+ * path is skipped. Do not reset/power-cycle DSI here: -+ * some bootloader handoff states lock up if we run the -+ * full enable path again. Just refresh the DPI video -+ * registers and make sure HS clock/video mode are selected. -+ */ -+ DRM_INFO("DSI already enabled, refresh DPI video path\n"); -+ sprd_dsi_dpi_video(dsi); -+ sprd_dsi_set_work_mode(dsi, dsi->ctx.work_mode); -+ sprd_dsi_state_reset(dsi); -+ if (dsi->ctx.nc_clk_en) -+ sprd_dsi_nc_clk_en(dsi, true); -+ else -+ sprd_dphy_hs_clk_en(dsi->phy, true); -+ if (!dpu->ctx.enabled) -+ sprd_dpu_resume(dpu); -+ dpu->ctx.stopped = true; -+ sprd_dpu_run(crtc->priv); -+ sprd_dsi_dump_link_status(dsi, "already-refresh"); -+ } - mutex_unlock(&dsi->lock); - return; - } -@@ -144,6 +214,9 @@ static void sprd_dsi_encoder_enable(struct drm_encoder *encoder) - sprd_dsi_enable(dsi); - sprd_dphy_enable(dsi->phy); - -+ if (sprd_panel_is_lt8912b_dummy(panel)) -+ sprd_dsi_disable_eotp_for_lt8912b(dsi); -+ - sprd_dsi_lp_cmd_enable(dsi, true); - - if (dsi->panel) { -@@ -167,6 +240,13 @@ static void sprd_dsi_encoder_enable(struct drm_encoder *encoder) - sprd_dsi_set_work_mode(dsi, dsi->ctx.work_mode); - sprd_dsi_state_reset(dsi); - -+ if (dsi->ctx.work_mode == DSI_MODE_VIDEO) { -+ DRM_INFO("DSI normal enable, refresh DPI video after mode set\n"); -+ sprd_dsi_dpi_video(dsi); -+ sprd_dsi_set_work_mode(dsi, dsi->ctx.work_mode); -+ sprd_dsi_state_reset(dsi); -+ } -+ - if ((dsi->ctx.work_mode == DSI_MODE_VIDEO) - && dsi->ctx.video_lp_cmd_en) - sprd_dsi_lp_cmd_enable(dsi, true); -@@ -200,6 +280,8 @@ static void sprd_dsi_encoder_enable(struct drm_encoder *encoder) - if (dsi->ctx.last_dpms != DRM_MODE_DPMS_SUSPEND) - sprd_dpu_run(crtc->priv); - -+ sprd_dsi_dump_link_status(dsi, "after-enable"); -+ - dsi->ctx.enabled = true; - dsi->ctx.last_dpms = dsi->ctx.dpms; - -diff --git a/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sysfs/sysfs_dphy.c b/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sysfs/sysfs_dphy.c -index f375be867e4a..b05c93de00f1 100644 ---- a/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sysfs/sysfs_dphy.c -+++ b/source/kernel/kernel5.4/drivers/gpu/drm/sprd/sysfs/sysfs_dphy.c -@@ -175,6 +175,8 @@ static ssize_t ssc_store(struct device *dev, - struct sprd_dphy *dphy = dev_get_drvdata(dev); - int ret; - -+ return count; -+ - mutex_lock(&dphy->ctx.lock); - if (!dphy->ctx.enabled) { - mutex_unlock(&dphy->ctx.lock); -@@ -215,6 +217,8 @@ static ssize_t hop_store(struct device *dev, - int ret; - int delta; - -+ return count; -+ - mutex_lock(&dphy->ctx.lock); - if (!dphy->ctx.enabled) { - mutex_unlock(&dphy->ctx.lock); -diff --git a/source/kernel/kernel5.4/drivers/video/Kconfig b/source/kernel/kernel5.4/drivers/video/Kconfig -index 427a993c7f57..2ae4f7e67db3 100644 ---- a/source/kernel/kernel5.4/drivers/video/Kconfig -+++ b/source/kernel/kernel5.4/drivers/video/Kconfig -@@ -25,6 +25,8 @@ endmenu - - source "drivers/video/backlight/Kconfig" - -+source "drivers/video/LT8912B/Kconfig" -+ - config VGASTATE - tristate - default n -diff --git a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -new file mode 100644 ---- a/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -+++ b/source/kernel/kernel5.4/arch/arm64/boot/dts/sprd/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -@@ -0,0 +1,54 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * LT8912B MIPI-DSI to HDMI 1080p dummy panel config. -+ */ -+ -+/ { -+ fragment { -+ target-path = "/"; -+ __overlay__ { -+ lcds { -+ lcd_dummy_mipi_hd: lcd_dummy_mipi_hd { -+ sprd,dsi-work-mode = <2>; /* video pulse mode */ -+ sprd,dsi-lane-number = <4>; -+ sprd,dsi-color-format = "rgb888"; -+ -+ sprd,phy-bit-clock = <1200000>; /* kbps 921600 1200000 */ -+ sprd,phy-escape-clock = <20000>; /* kHz */ -+ sprd,video-lp-cmd-enable = <0>; -+ sprd,hporch-lp-disable = <1>; -+ sprd,width-mm = <121>; -+ sprd,height-mm = <68>; -+ sprd,esd-check-enable = <0>; -+ sprd,esd-check-mode = <1>; -+ sprd,esd-check-period = <1000>; -+ sprd,panel-if-type = <2>; -+ sprd,reset-on-sequence = <1 5>, <0 5>, <1 5>, <0 5>, <1 20>; -+ sprd,reset-off-sequence = <0 20>; -+ sprd,initial-command = [ -+ ]; -+ sprd,sleep-in-command = [ -+ ]; -+ sprd,sleep-out-command = [ -+ ]; -+ -+ display-timings { -+ native-mode = <<8912b_1080p_timing0>; -+ -+ lt8912b_1080p_timing0: timing0 { -+ clock-frequency = <153600000>; -+ hactive = <1920>; -+ vactive = <1080>; -+ hfront-porch = <88>; -+ hsync-len = <44>; -+ hback-porch = <148>; -+ vfront-porch = <56>; -+ vsync-len = <6>; -+ vback-porch = <60>; -+ }; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/Kconfig b/source/kernel/kernel5.4/drivers/video/LT8912B/Kconfig -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/Kconfig -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/Kconfig -@@ -0,0 +1,9 @@ -+ -+config LT8912B -+ tristate "LT8912B Driver" -+ default n -+ help -+ Control LT8912B Chip -+ Select m:build as a separate module; -+ Select y:Build into the kernel -+ Select n:Not build -\ No newline at end of file -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/Makefile b/source/kernel/kernel5.4/drivers/video/LT8912B/Makefile -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/Makefile -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/Makefile -@@ -0,0 +1,4 @@ -+ -+lt8912b-y := src/LontiumDrv.o src/LT8912B_Main.o src/LT8912B.o src/OcmI2cMaster.o \ -+ -+obj-$(CONFIG_LT8912B) += lt8912b.o -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B.h b/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B.h -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B.h -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B.h -@@ -0,0 +1,72 @@ -+ -+#ifndef _LT8912B_H -+#define _LT8912B_H -+ -+#define _1080P_60Hz -+ -+/* output mode */ -+#define _hdmi_output -+#define _lvds_bypass -+ -+//#define _pattern_test_ -+ -+//#define _lane_swap_ //mipi input 3210 -+//#define _pn_swap_ //mipi input lane pn swap -+ -+#define dds_debug -+ -+/* lanes */ -+#define lane_cnt 0 /*0: 4lane; 1: 1lane; 2: 2lane; 3: 3lane;*/ -+ -+ -+typedef struct video_timing{ -+u16 hfp; -+u16 hs; -+u16 hbp; -+u16 hact; -+u16 htotal; -+u16 vfp; -+u16 vs; -+u16 vbp; -+u16 vact; -+u16 vtotal; -+bool h_polarity; -+bool v_polarity; -+u16 vic; -+u8 aspact_ratio; // 0=no data, 1=4:3, 2=16:9, 3=no data. -+u32 pclk_khz; -+}_video_timing; -+ -+typedef enum -+{ -+ I2S_2CH, -+ I2S_8CH, -+ SPDIF -+}_Audio_Input_Mode; -+ -+#define Audio_Input_Mode I2S_2CH -+ -+#define AR_ND 0x00 -+#define AR_4_3 0x01 -+#define AR_16_9 0x02 -+ -+typedef struct panel_parameter -+{ -+ u16 hfp; -+ u16 hs; -+ u16 hbp; -+ u16 hact; -+ u16 htotal; -+ u16 vfp; -+ u16 vs; -+ u16 vbp; -+ u16 vact; -+ u16 vtotal; -+ u32 pclk_khz; -+}_panel_parameter; -+ -+extern void LT8912B_Config(void); -+ -+extern u8 Tx_HPD; -+ -+#endif -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B_Main.h b/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B_Main.h -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B_Main.h -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/include/LT8912B_Main.h -@@ -0,0 +1,5 @@ -+#ifndef _LT8912B_MAIN_H_ -+#define _LT8912B_MAIN_H_ -+ -+extern int LT8912B_Main(void *data); -+#endif -\ No newline at end of file -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/include/LontiumDrv.h b/source/kernel/kernel5.4/drivers/video/LT8912B/include/LontiumDrv.h -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/include/LontiumDrv.h -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/include/LontiumDrv.h -@@ -0,0 +1,39 @@ -+#ifndef _LONTIUMDRV_H_ -+#define _LONTIUMDRV_H_ -+ -+ -+struct _lt8912b{ -+ struct device *dev; -+ struct mutex ocm_lock; -+ struct gpio_desc *reset_gpio; -+ struct gpio_desc *power_gpio; -+ struct i2c_client *i2c_stu; -+ struct regmap *chip_regmap; -+ struct addr_1{ -+ struct i2c_client *i2c_stu; -+ struct regmap *regmap; -+ }*addr_1; -+ struct addr_2{ -+ struct i2c_client *i2c_stu; -+ struct regmap *regmap; -+ }*addr_2; -+ -+}; -+ -+ -+ -+typedef struct -+{ -+ u8 address; -+ u8 value; -+} Chip_Control_Args; -+ -+ -+extern struct _lt8912b *lt8912b; -+extern volatile bool Main_Loop; -+extern const char *LOG_FLAG; -+ -+extern u8 addr_1; -+extern u8 addr_2; -+ -+#endif -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/include/OcmI2cMaster.h b/source/kernel/kernel5.4/drivers/video/LT8912B/include/OcmI2cMaster.h -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/include/OcmI2cMaster.h -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/include/OcmI2cMaster.h -@@ -0,0 +1,10 @@ -+#ifndef _OCMI2CMASTER_H_ -+#define _OCMI2CMASTER_H_ -+ -+ -+extern int HDMI_WriteI2C_Byte(u8 addr,u8 data); -+extern int HDMI_ReadI2C_Byte(u8 addr); -+ -+extern u8 I2CADR; -+ -+#endif -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/include/include.h b/source/kernel/kernel5.4/drivers/video/LT8912B/include/include.h -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/include/include.h -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/include/include.h -@@ -0,0 +1,41 @@ -+#ifndef _INCLUDE_H_ -+#define _INCLUDE_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+ -+#include "LontiumDrv.h" -+ -+#include "LT8912B_Main.h" -+#include "LT8912B.h" -+ -+ -+#include "OcmI2cMaster.h" -+ -+ -+ -+ -+#endif -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B.c -@@ -0,0 +1,790 @@ -+ -+#include "../include/include.h" -+ -+u8 Hsync_H_last = 0x00; -+u8 Hsync_L_last = 0x00; -+u8 Vsync_H_last = 0x00; -+u8 Vsync_L_last = 0x00; -+ -+u8 Hsync_L, Hsync_H, Vsync_L, Vsync_H; -+u8 mipi_det_fail_count = 0; -+u8 mipi_relock_count = 0; -+ -+ -+bool suspend_on = 0; -+ -+u8 Tx_HPD=0; -+ -+// hfp, hs, hbp, hact, htotal, vfp, vs, vbp, vact, vtotal, hfp, hs, hbp, hact, htotal, vfp, vs, vbp, vact, vtotal, h_polary, v_polary, vic, aspact_ratio, pclk_khz -+struct video_timing video_640x480_60Hz = {16, 96, 48, 640, 800, 10, 2, 33, 480, 525, 0,0, 1, AR_4_3, 25000}; -+struct video_timing video_720x480_60Hz = {16, 62, 60, 720, 858, 9, 6, 30, 480, 525, 0,0, 2, AR_4_3, 27000}; -+struct video_timing video_720x576_50Hz = {12, 64, 68, 720, 864, 5, 5, 39, 576, 625, 0,0,17, AR_4_3, 27000}; -+struct video_timing video_800x600_60Hz = {48, 128, 88, 800, 1056, 1, 4, 23, 600, 628, 1,1, 0, AR_16_9, 40000}; -+struct video_timing video_1024x768_60Hz = {24, 136, 160, 1024, 1344, 3, 6, 29, 768, 806, 0,0, 0, AR_16_9, 65000}; -+struct video_timing video_1280x720_60Hz = {110, 40, 220, 1280, 1650, 5, 5, 20, 720, 750, 1,1, 4, AR_16_9, 74250}; -+struct video_timing video_1280x800_60Hz = {28, 32, 100, 1280, 1440, 2, 6, 15, 800, 823, 0,0, 0, AR_16_9, 71000}; -+//struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 4, 5, 36, 1080, 1125, 1,1,16, AR_16_9, 148500}; -+struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 56, 6, 60, 1080, 1202, 1,1, 0, AR_16_9, 153600}; -+ -+struct video_timing *video; -+ -+void DDSConfig(void); -+ -+void DigitalClockEn(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x02,0xf7); -+ HDMI_WriteI2C_Byte(0x08,0xff); -+ HDMI_WriteI2C_Byte(0x09,0xff); -+ HDMI_WriteI2C_Byte(0x0a,0xff); -+ HDMI_WriteI2C_Byte(0x0b,0x7c); -+ HDMI_WriteI2C_Byte(0x0c,0xff); -+} -+void TxAnalog(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x31,0xE1); -+ HDMI_WriteI2C_Byte(0x32,0xE1); -+ HDMI_WriteI2C_Byte(0x33,0x0c); //en/disable hdmid output -+ HDMI_WriteI2C_Byte(0x37,0x00); -+ HDMI_WriteI2C_Byte(0x38,0x22); -+ HDMI_WriteI2C_Byte(0x60,0x82); -+} -+ -+void CbusAnalog(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x39,0x45); -+ HDMI_WriteI2C_Byte(0x3a,0x00); //20180719 -+ HDMI_WriteI2C_Byte(0x3b,0x00); -+} -+ -+void HDMIPllAnalog(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x44,0x31); -+ HDMI_WriteI2C_Byte(0x55,0x44); -+ HDMI_WriteI2C_Byte(0x57,0x01); -+ HDMI_WriteI2C_Byte(0x5a,0x02); -+} -+ -+void AviInfoframe(struct video_timing *video_format) -+{ -+ u8 VIC = video_format->vic; -+ u8 AR = video_format->aspact_ratio; -+ u8 pb0,pb2,pb4,Sync_Polarity; -+ -+ I2CADR = 0x94; -+ HDMI_WriteI2C_Byte(0x3c,0x41); //enable null package -+ -+ Sync_Polarity = (video_format->h_polarity*0x02) + (video_format->v_polarity*0x01); -+ pb2 = (AR<<4) + 0x08; -+ pb4 = VIC; -+ pb0 = (((pb2 + pb4) <= 0x5f)?(0x5f - pb2 - pb4):(0x15f - pb2 - pb4)); -+ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0xab,Sync_Polarity); //sync polarity -+ -+ I2CADR = 0x94; -+ HDMI_WriteI2C_Byte(0x43,pb0); //PB0:check sum -+ HDMI_WriteI2C_Byte(0x44,0x10); //PB1:RGB888 -+ HDMI_WriteI2C_Byte(0x45,pb2); //PB2 -+ HDMI_WriteI2C_Byte(0x46,0x00); //PB3 -+ HDMI_WriteI2C_Byte(0x47,pb4); //PB4:vic -+} -+ -+void MipiAnalog(void) -+{ -+ I2CADR = 0x90; -+ #ifdef _pn_swap_ -+ HDMI_WriteI2C_Byte(0x3e,0xf6); //P/N swap -+ #else -+ HDMI_WriteI2C_Byte(0x3e,0xd6); //if mipi pin map follow reference design, no need swap P/N. -+ #endif -+ -+ HDMI_WriteI2C_Byte(0x3f,0xd4);//EQ -+ HDMI_WriteI2C_Byte(0x41,0x3c);//EQ -+} -+ -+void MipiBasicSet(void) -+{ -+ I2CADR = 0x92; -+ HDMI_WriteI2C_Byte(0x10,0x01); // term en -+ HDMI_WriteI2C_Byte(0x11,0x10); // settle -+ //HDMI_WriteI2C_Byte(0x12,0x08); // trail -+ HDMI_WriteI2C_Byte(0x13,lane_cnt); //00 4 lane //01 1 lane //02 2 lane //03 3lane -+ HDMI_WriteI2C_Byte(0x14,0x00); //debug mux -+ -+ #ifdef _lane_swap_ //for EVB only, if mipi pin map follow reference design, no need swap lane. -+ HDMI_WriteI2C_Byte(0x15,0xa8); //lane swap:3210 -+ printk("%s nmipi basic set: lane swap 3210, %d\n",LOG_FLAG,lane_cnt); -+ #else -+ HDMI_WriteI2C_Byte(0x15,0x00); //lane swap:0123 -+ #endif -+ -+ HDMI_WriteI2C_Byte(0x1a,0x03); // hshift 3 -+ HDMI_WriteI2C_Byte(0x1b,0x03); // vshift 3 -+} -+ -+void MIPI_Video_Setup(struct video_timing *video_format) -+{ -+ I2CADR = 0x92; -+ HDMI_WriteI2C_Byte(0x18,(u8)(video_format->hs%256)); // hwidth -+ HDMI_WriteI2C_Byte(0x19,(u8)(video_format->vs%256)); // vwidth -+ HDMI_WriteI2C_Byte(0x1c,(u8)(video_format->hact%256)); // H_active[7:0] -+ HDMI_WriteI2C_Byte(0x1d,(u8)(video_format->hact/256)); // H_active[15:8] -+ HDMI_WriteI2C_Byte(0x2f,0x0c); // fifo_buff_length 12 -+ HDMI_WriteI2C_Byte(0x34,(u8)(video_format->htotal%256)); // H_total[7:0] -+ HDMI_WriteI2C_Byte(0x35,(u8)(video_format->htotal/256)); // H_total[15:8] -+ HDMI_WriteI2C_Byte(0x36,(u8)(video_format->vtotal%256)); // V_total[7:0] -+ HDMI_WriteI2C_Byte(0x37,(u8)(video_format->vtotal/256)); // V_total[15:8] -+ HDMI_WriteI2C_Byte(0x38,(u8)(video_format->vbp%256)); // VBP[7:0] -+ HDMI_WriteI2C_Byte(0x39,(u8)(video_format->vbp/256)); // VBP[15:8] -+ HDMI_WriteI2C_Byte(0x3a,(u8)(video_format->vfp%256)); // VFP[7:0] -+ HDMI_WriteI2C_Byte(0x3b,(u8)(video_format->vfp/256)); // VFP[15:8] -+ HDMI_WriteI2C_Byte(0x3c,(u8)(video_format->hbp%256)); // HBP[7:0] -+ HDMI_WriteI2C_Byte(0x3d,(u8)(video_format->hbp/256)); // HBP[15:8] -+ HDMI_WriteI2C_Byte(0x3e,(u8)(video_format->hfp%256)); // HFP[7:0] -+ HDMI_WriteI2C_Byte(0x3f,(u8)(video_format->hfp/256)); // HFP[15:8] -+ video = video_format; -+} -+ -+void MIPIRxLogicRes(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x03,0x7f); //mipi rx reset -+ msleep(10); -+ HDMI_WriteI2C_Byte(0x03,0xff); -+ -+ HDMI_WriteI2C_Byte(0x05,0xfb); //dds reset -+ msleep(10); -+ HDMI_WriteI2C_Byte(0x05,0xff); -+} -+ -+void LT8912B_MIPI_Relock(void) -+{ -+ printk("%s relock MIPI RX after detect timeout, retry=%u\n", -+ LOG_FLAG, mipi_relock_count); -+ -+ MipiAnalog(); -+ MipiBasicSet(); -+ DDSConfig(); -+ MIPI_Video_Setup(&video_1920x1080_60Hz); -+ AviInfoframe(&video_1920x1080_60Hz); -+ MIPIRxLogicRes(); -+} -+ -+void DDSConfig(void) -+{ -+ I2CADR = 0x92; -+ HDMI_WriteI2C_Byte(0x4e,0x93);//strm_sw_freq_word[ 7: 0] -+ HDMI_WriteI2C_Byte(0x4f,0x3E);//strm_sw_freq_word[15: 8] -+ HDMI_WriteI2C_Byte(0x50,0x29);//strm_sw_freq_word[23:16] -+ HDMI_WriteI2C_Byte(0x51,0x80);//[0]=strm_sw_freq_word[24] -+ HDMI_WriteI2C_Byte(0x1e,0x4f); -+ HDMI_WriteI2C_Byte(0x1f,0x5e);//full_value 464 -+ HDMI_WriteI2C_Byte(0x20,0x01); -+ HDMI_WriteI2C_Byte(0x21,0x2c);//full_value1 416 -+ HDMI_WriteI2C_Byte(0x22,0x01); -+ HDMI_WriteI2C_Byte(0x23,0xfa);//full_value2 400 -+ HDMI_WriteI2C_Byte(0x24,0x00); -+ HDMI_WriteI2C_Byte(0x25,0xc8);//full_value3 384 -+ HDMI_WriteI2C_Byte(0x26,0x00); -+ HDMI_WriteI2C_Byte(0x27,0x5e);//empty_value 464 -+ HDMI_WriteI2C_Byte(0x28,0x01); -+ HDMI_WriteI2C_Byte(0x29,0x2c);//empty_value1 416 -+ HDMI_WriteI2C_Byte(0x2a,0x01); -+ HDMI_WriteI2C_Byte(0x2b,0xfa);//empty_value2 400 -+ HDMI_WriteI2C_Byte(0x2c,0x00); -+ HDMI_WriteI2C_Byte(0x2d,0xc8);//empty_value3 384 -+ HDMI_WriteI2C_Byte(0x2e,0x00); -+ HDMI_WriteI2C_Byte(0x42,0x64);//tmr_set[ 7:0]:100us -+ HDMI_WriteI2C_Byte(0x43,0x00);//tmr_set[15:8]:100us -+ HDMI_WriteI2C_Byte(0x44,0x04);//timer step -+ HDMI_WriteI2C_Byte(0x45,0x00); -+ HDMI_WriteI2C_Byte(0x46,0x59); -+ HDMI_WriteI2C_Byte(0x47,0x00); -+ HDMI_WriteI2C_Byte(0x48,0xf2); -+ HDMI_WriteI2C_Byte(0x49,0x06); -+ HDMI_WriteI2C_Byte(0x4a,0x00); -+ HDMI_WriteI2C_Byte(0x4b,0x72); -+ HDMI_WriteI2C_Byte(0x4c,0x45); -+ HDMI_WriteI2C_Byte(0x4d,0x00); -+ HDMI_WriteI2C_Byte(0x52,0x08);// trend step -+ HDMI_WriteI2C_Byte(0x53,0x00); -+ HDMI_WriteI2C_Byte(0x54,0xb2); -+ HDMI_WriteI2C_Byte(0x55,0x00); -+ HDMI_WriteI2C_Byte(0x56,0xe4); -+ HDMI_WriteI2C_Byte(0x57,0x0d); -+ HDMI_WriteI2C_Byte(0x58,0x00); -+ HDMI_WriteI2C_Byte(0x59,0xe4); -+ HDMI_WriteI2C_Byte(0x5a,0x8a); -+ HDMI_WriteI2C_Byte(0x5b,0x00); -+ HDMI_WriteI2C_Byte(0x5c,0x34); -+ HDMI_WriteI2C_Byte(0x51,0x00); -+} -+ -+void AudioIIsEn(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0xB2,0x01);//DVI mode:0x00; HDMI mode:0x01; -+ I2CADR = 0x94; -+ HDMI_WriteI2C_Byte(0x06,0x08); -+ HDMI_WriteI2C_Byte(0x07,0xF0); -+ HDMI_WriteI2C_Byte(0x34,0xD2);//0xE2:32FS; 0xD2:64FS -+ HDMI_WriteI2C_Byte(0x0F,0x2B); -+} -+ -+void AudioSpdifEn(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0xB2,0x01); -+ I2CADR = 0x94; -+ HDMI_WriteI2C_Byte(0x06,0x0e); -+ HDMI_WriteI2C_Byte(0x07,0x00); -+ HDMI_WriteI2C_Byte(0x34,0xD2);//0xE2:32FS; 0xD2:64FS -+} -+ -+void Core_Pll_setup(struct panel_parameter *panel) -+{ -+ u8 cpll_m, cpll_k1,cpll_k2; //cpll_k3; -+ u32 temp; -+ -+ temp=(panel->pclk_khz*7)/25; -+ cpll_m=temp/1000; -+ -+ temp=(panel->pclk_khz*7)/25; -+ temp=temp%1000; -+ //temp=temp*16.384; -+ temp=temp*16384/1000; -+ -+ cpll_k1=temp%256; -+ cpll_k2=temp/256; -+ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x50,0x24);//cp=50uA -+ HDMI_WriteI2C_Byte(0x51,0x05);//xtal_clk as reference,second order passive LPF PLL -+ HDMI_WriteI2C_Byte(0x52,0x14);//use second-order PLL -+ HDMI_WriteI2C_Byte(0x69,cpll_m);//CP_PRESET_DIV_RATIO -+ HDMI_WriteI2C_Byte(0x69,(cpll_m|0x80)); -+ HDMI_WriteI2C_Byte(0x6c,(cpll_k2|0x80));//RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8] -+ HDMI_WriteI2C_Byte(0x6b,cpll_k1); -+ -+ HDMI_WriteI2C_Byte(0x04,0xfb);//core pll reset -+ HDMI_WriteI2C_Byte(0x04,0xff); -+} -+ -+void Core_Pll_bypass(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x50,0x24); //cp=50uA -+ HDMI_WriteI2C_Byte(0x51,0x2d); //Pix_clk as reference,second order passive LPF PLL -+ HDMI_WriteI2C_Byte(0x52,0x04); //loopdiv=0;use second-order PLL -+ HDMI_WriteI2C_Byte(0x69,0x0e); //CP_PRESET_DIV_RATIO -+ HDMI_WriteI2C_Byte(0x69,0x8e); -+ HDMI_WriteI2C_Byte(0x6a,0x00); -+ HDMI_WriteI2C_Byte(0x6c,0xb8); //RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8] -+ HDMI_WriteI2C_Byte(0x6b,0x51); -+ -+ HDMI_WriteI2C_Byte(0x04,0xfb); //core pll reset -+ HDMI_WriteI2C_Byte(0x04,0xff); -+} -+ -+void Lvds_Pll_Reset(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x02,0xf7); //lvds pll reset -+ HDMI_WriteI2C_Byte(0x02,0xff); -+} -+ -+ -+void Scaler_bypass(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x7f,0x00);//disable scaler -+ HDMI_WriteI2C_Byte(0xa8,0x13); -+} -+ -+void Scaler_setup(struct video_timing *input_video,struct panel_parameter *panel) -+{ -+ //for example: 720P to 1280x800 -+ //These register base on MIPI resolution and LVDS panel resolution. -+ u32 h_ratio,v_ratio; -+ u8 i; -+ u32 htotal; -+// h_ratio = input_video->hact*4096.00/panel->hact; -+// v_ratio = input_video->vact*4096.00/panel->vact; -+ h_ratio = input_video->hact*4096/panel->hact; -+ v_ratio = input_video->vact*4096/panel->vact; -+ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x80,0x00); -+ HDMI_WriteI2C_Byte(0x81,0xff); -+ HDMI_WriteI2C_Byte(0x82,0x03); -+ HDMI_WriteI2C_Byte(0x83,(u8)(input_video->hact%256)); -+ HDMI_WriteI2C_Byte(0x84,(u8)(input_video->hact/256)); -+ HDMI_WriteI2C_Byte(0x85,0x80); -+ HDMI_WriteI2C_Byte(0x86,0x10); -+ HDMI_WriteI2C_Byte(0x87,(u8)(panel->htotal%256)); -+ HDMI_WriteI2C_Byte(0x88,(u8)(panel->htotal/256)); -+ HDMI_WriteI2C_Byte(0x89,(u8)(panel->hs%256)); -+ HDMI_WriteI2C_Byte(0x8a,(u8)(panel->hbp%256)); -+ HDMI_WriteI2C_Byte(0x8b,(u8)(panel->vs%256)); -+ HDMI_WriteI2C_Byte(0x8c,(u8)(panel->hact%256)); -+ HDMI_WriteI2C_Byte(0x8d,(u8)(panel->vact%256)); -+ HDMI_WriteI2C_Byte(0x8e,(u8)(panel->vact/256)*16+(panel->hact/256)); -+ HDMI_WriteI2C_Byte(0x8f,(u8)(h_ratio%256)); -+ HDMI_WriteI2C_Byte(0x90,(u8)(h_ratio/256)); -+ HDMI_WriteI2C_Byte(0x91,(u8)(v_ratio%256)); -+ HDMI_WriteI2C_Byte(0x92,(u8)(v_ratio/256)); -+ HDMI_WriteI2C_Byte(0x7f,0x96); -+ //HDMI_WriteI2C_Byte(0x7f,0xb0); -+ //HDMI_WriteI2C_Byte(0xa8,0x3b); -+ HDMI_WriteI2C_Byte(0xa8,0x13); -+ -+ HDMI_WriteI2C_Byte(0x02,0xf7);//lvds pll reset -+ HDMI_WriteI2C_Byte(0x02,0xff); -+ -+ HDMI_WriteI2C_Byte(0x03,0xcf);//scaler reset -+ HDMI_WriteI2C_Byte(0x03,0xff); -+ -+ HDMI_WriteI2C_Byte(0x7f,0xb0); -+ -+ for(i = 0; i < 300; i++) -+ { -+ if(HDMI_ReadI2C_Byte(0xa7)&0x20) -+ { -+ htotal = (HDMI_ReadI2C_Byte(0xa7)&0x0f)*0x100 + HDMI_ReadI2C_Byte(0xa6); -+ printk("%s scaler setup htotal = %d.\n",LOG_FLAG,htotal); -+ -+ break; -+ //please set "htotal" to panel_parameter's htotal. -+ } -+ printk("%s scaler loop = %d\n",LOG_FLAG, i); -+ msleep(100); -+ } -+} -+void LvdsPowerUp(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x44,0x30); -+ HDMI_WriteI2C_Byte(0x51,0x05); -+} -+void LvdsPowerDown(void) -+{ -+ I2CADR = 0x90; -+ //HDMI_WriteI2C_Byte(0x44,0x31); -+ HDMI_WriteI2C_Byte(0x51,0x15); // -+ //HDMI_WriteI2C_Byte(0x03,0xfb); -+} -+ -+void LvdsBypass(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x50,0x24); //cp=50uA -+ HDMI_WriteI2C_Byte(0x51,0x2d); //Pix_clk as reference,second order passive LPF PLL -+ HDMI_WriteI2C_Byte(0x52,0x04); //loopdiv=0;use second-order PLL -+ HDMI_WriteI2C_Byte(0x69,0x0e); //CP_PRESET_DIV_RATIO -+ HDMI_WriteI2C_Byte(0x69,0x8e); -+ HDMI_WriteI2C_Byte(0x6a,0x00); -+ HDMI_WriteI2C_Byte(0x6c,0xb8); //RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8] -+ HDMI_WriteI2C_Byte(0x6b,0x51); -+ -+ HDMI_WriteI2C_Byte(0x04,0xfb); //core pll reset -+ HDMI_WriteI2C_Byte(0x04,0xff); -+ -+ HDMI_WriteI2C_Byte(0x7f,0x00); //disable scaler -+ HDMI_WriteI2C_Byte(0xa8,0x13); //0x13:VSEA ; 0x33:JEIDA; -+} -+ -+void LvdsOutput(bool on) -+{ -+ if(on) -+ { -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x02,0xf7); //lvds pll reset -+ HDMI_WriteI2C_Byte(0x02,0xff); //scaler module reset -+ HDMI_WriteI2C_Byte(0x03,0xcb); //lvds tx module reset -+ HDMI_WriteI2C_Byte(0x03,0xfb); -+ HDMI_WriteI2C_Byte(0x03,0xff); -+ HDMI_WriteI2C_Byte(0x44,0x30); //enbale lvds output -+ printk("%s LT8912_lvds_output_enable!\n",LOG_FLAG); -+ -+ }else{ -+ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x44,0x31); -+ } -+} -+ -+ -+void HdmiOutput(bool on) -+{ -+ if(on) -+ { -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x33,0x0e); //enable hdmi output -+ printk("%s HDMI output Enable.\n",LOG_FLAG); -+ } -+ else -+ { -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x33,0x0c); //disable hdmi output -+ printk("%s HDMI output Disable.\n",LOG_FLAG); -+ } -+} -+ -+ -+void LvdsScalerResult(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x7f,0xb0); -+} -+ -+ -+void ScalerReset(void) -+{ -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte(0x03,0xcf); -+ HDMI_WriteI2C_Byte(0x03,0xff); -+} -+ -+ -+void lt8912_check_dds(void) -+{ -+ u8 reg_920c, reg_920d, reg_920e, reg_920f; -+ u8 i; -+ for(i = 0; i < 10; i++) -+ { -+ I2CADR = 0x92; -+ reg_920c = HDMI_ReadI2C_Byte(0x0c); -+ reg_920d = HDMI_ReadI2C_Byte(0x0d); -+ reg_920e = HDMI_ReadI2C_Byte(0x0e); -+ reg_920f = HDMI_ReadI2C_Byte(0x0f); -+ printk("%s 0x0c~0f = %02x, %02x, %02x\n",LOG_FLAG,reg_920c, reg_920d, reg_920e); -+// if((reg_920e == 0xd2)&&(reg_920d < 0xff)&&(reg_920d > 0xd0)) //shall update threshold here base on actual dds result. -+// { -+// printk("%s lvds_check_dds: stable!\n",LOG_FLAG); -+// break; -+// } -+ -+ msleep(500); -+ } -+} -+ -+void lvds_output_cfg(void) -+{ -+ LvdsPowerUp(); -+ #ifdef _lvds_bypass -+ LvdsBypass(); -+ #else -+ //Core_Pll_setup(&AA070M0C1); -+ Core_Pll_setup(&KD101FM_1_C001A); -+ Scaler_setup(&video_1280x720_60Hz,&KD101FM_1_C001A); -+ #endif -+} -+ -+void MIPI_Input_det(void) -+{ -+ bool video_valid = false; -+ -+ I2CADR = 0x90; -+ Hsync_L = HDMI_ReadI2C_Byte(0x9c); -+ Hsync_H = HDMI_ReadI2C_Byte(0x9d); -+ Vsync_L = HDMI_ReadI2C_Byte(0x9e); -+ Vsync_H = HDMI_ReadI2C_Byte(0x9f); -+ printk("%s 0x9c~9f = %x, %x, %x, %x.\n", LOG_FLAG,Hsync_H, Hsync_L,Vsync_H, Vsync_L); -+ -+ if (Hsync_H == 0xff && Hsync_L == 0xff && -+ Vsync_H == 0x00 && Vsync_L == 0x00) { -+ if (mipi_det_fail_count < 0xff) -+ mipi_det_fail_count++; -+ -+ if (mipi_det_fail_count >= 10 && mipi_relock_count < 5) { -+ mipi_relock_count++; -+ mipi_det_fail_count = 0; -+ LT8912B_MIPI_Relock(); -+ } -+ } else { -+ mipi_det_fail_count = 0; -+ } -+ -+ if((Hsync_H!=Hsync_H_last)||(Vsync_H!=Vsync_H_last)) /*hiht byte changed*/ -+ { -+ printk("%s 0x9c~9f = %x, %x, %x, %x.\n", LOG_FLAG,Hsync_H, Hsync_L,Vsync_H, Vsync_L); -+ -+ if(Vsync_H==0x02 && Vsync_L <= 0xef&&Vsync_L >= 0xec)//0x2EE -+ { -+ video = &video_1280x720_60Hz; -+ video_valid = true; -+ printk("%s videoformat = VESA_1280x720_60\n",LOG_FLAG); -+ } -+ else if(Vsync_H == 0x03 && Vsync_L <= 0x3a &&Vsync_L >= 0x34)//0x337 -+ { -+ video = &video_1280x800_60Hz; -+ video_valid = true; -+ printk("%s videoformat = VESA_1280x800_60\n",LOG_FLAG); -+ } -+ else if(Vsync_H == 0x04 && Vsync_L <= 0xb6&&Vsync_L >= 0x63)//0x4b2 -+ { -+ video = &video_1920x1080_60Hz; -+ video_valid = true; -+ printk("%s videoformat = 1920x1080_153M6\n",LOG_FLAG); -+ } -+ else -+ { -+ printk("%s videoformat = video_none\n",LOG_FLAG); -+ } -+ -+ Hsync_L_last = Hsync_L; -+ Hsync_H_last = Hsync_H; -+ Vsync_L_last = Vsync_L; -+ Vsync_H_last = Vsync_H; -+ -+ if (video_valid) { -+ mipi_det_fail_count = 0; -+ mipi_relock_count = 0; -+ MIPI_Video_Setup(video); -+ AviInfoframe(video); -+ MIPIRxLogicRes(); -+ } -+ } -+ -+} -+ -+ -+//void dds_clock_debug(void) -+//{ -+// #ifdef dds_debug -+// u8 reg_920c, reg_920d, reg_920e, reg_920f; -+// -+// while(1) -+// { -+// I2CADR = 0x92; -+// reg_920c = HDMI_ReadI2C_Byte(0x0c); -+// reg_920d = HDMI_ReadI2C_Byte(0x0d); -+// reg_920e = HDMI_ReadI2C_Byte(0x0e); -+// reg_920f = HDMI_ReadI2C_Byte(0x0f); -+// -+// printk("\r\n0x0c~0e = %02x, %02x, %02x",reg_920c, reg_920d, reg_920e); -+// printk("\r\nEnter the dds_clock_debug cycle"); -+// -+// msleep(1000); -+// } -+// #endif -+//} -+ -+void pattern_test(void) -+{ -+ u32 DDS_initial_value; -+ u8 pclk_Mhz; -+ -+// video = &video_640x480_60Hz; -+// video = &video_720x480_60Hz; -+// video = &video_800x600_60Hz; -+// video = &video_1280x720_60Hz; -+// video = &video_1280x800_60Hz; -+ video = &video_1920x1080_60Hz; -+ -+ DigitalClockEn(); -+ TxAnalog(); -+ CbusAnalog(); -+ HDMIPllAnalog(); -+ AudioIIsEn(); -+ AviInfoframe(video); -+ lvds_output_cfg(); -+ -+ I2CADR = 0x92; -+ //////////////////Pattern resolution set//////////////////// -+ HDMI_WriteI2C_Byte(0x72,0x12); -+ HDMI_WriteI2C_Byte(0x73,(u8)((video->hs+video->hbp)%256)); //RGD_PTN_DE_DLY[7:0] -+ HDMI_WriteI2C_Byte(0x74,(u8)((video->hs+video->hbp)/256)); //RGD_PTN_DE_DLY[11:8] -+ HDMI_WriteI2C_Byte(0x75,(u8)((video->vs+video->vbp)%256)); //RGD_PTN_DE_TOP[6:0] -+ HDMI_WriteI2C_Byte(0x76,(u8)(video->hact%256)); //RGD_PTN_DE_CNT[7:0] -+ HDMI_WriteI2C_Byte(0x77,(u8)(video->vact%256)); //RGD_PTN_DE_LIN[7:0] -+ HDMI_WriteI2C_Byte(0x78,((((u8)(video->vact/256))<<4)+((u8)(video->hact/256)))); //RGD_PTN_DE_LIN[10:8],RGD_PTN_DE_CNT[11:8] -+ HDMI_WriteI2C_Byte(0x79,(u8)(video->htotal%256)); //RGD_PTN_H_TOTAL[7:0] -+ HDMI_WriteI2C_Byte(0x7a,(u8)(video->vtotal%256)); //RGD_PTN_V_TOTAL[7:0] -+ HDMI_WriteI2C_Byte(0x7b,((((u8)(video->vtotal/256))<<4)+((u8)(video->htotal/256)))); //RGD_PTN_V_TOTAL[10:8],RGD_PTN_H_TOTAL[11:8] -+ HDMI_WriteI2C_Byte(0x7c,(u8)(video->hs%256)); //RGD_PTN_HWIDTH[7:0] -+ HDMI_WriteI2C_Byte(0x7d,((((u8)(video->hs/256))<<6)+((u8)(video->vs%256)))); //RGD_PTN_HWIDTH[9:8],RGD_PTN_VWIDTH[5:0] -+ HDMI_WriteI2C_Byte(0x70,0x80); //pattern enable -+ HDMI_WriteI2C_Byte(0x71,0x51); -+ HDMI_WriteI2C_Byte(0x42,0x12); -+ /////////////////////////////////////////////////////////// -+ -+ HDMI_WriteI2C_Byte(0x1e,0x67); //h v d pol hdmi sel pll sel -+ -+ //////////////////pattern pixl clock set/////////////////// -+ pclk_Mhz = (u8)(video->pclk_khz/1000); -+ DDS_initial_value = (u32)(pclk_Mhz*0x16C16); -+ HDMI_WriteI2C_Byte(0x4e,(u8)(DDS_initial_value&0x000000ff)); //strm_sw_freq_word[ 7: 0] -+ HDMI_WriteI2C_Byte(0x4f,(u8)((DDS_initial_value&0x0000ff00)>>8)); //strm_sw_freq_word[15: 8] -+ HDMI_WriteI2C_Byte(0x50,(u8)((DDS_initial_value&0x00ff0000)>>16)); //strm_sw_freq_word[23:16] -+ HDMI_WriteI2C_Byte(0x51,0x80); -+ -+// HDMI_WriteI2C_Byte(0x4e,0x3E); //strm_sw_freq_word[ 7: 0] -+// HDMI_WriteI2C_Byte(0x4f,0xE9); //strm_sw_freq_word[15: 8] -+// HDMI_WriteI2C_Byte(0x50,0xD3); //strm_sw_freq_word[23:16] -+// HDMI_WriteI2C_Byte(0x51,0x80); //pattern en -+ /////////////////////////////////////////////////////////// -+ -+ HdmiOutput(1); -+ LvdsOutput(1); -+} -+ -+ -+u8 LT8912_Get_HPD(void) -+{ -+ //(0x90)0xc1[bit7] description HPD is High or Low -+ I2CADR = 0x90; -+ if((HDMI_ReadI2C_Byte(0xc1)&0x80)==0x80) -+ { -+ printk("%s LT8912_Get_HPD: high\n",LOG_FLAG); -+ return 1; -+ } -+ else -+ { -+ printk("%s LT8912_Get_HPD: low\n",LOG_FLAG); -+ return 0; -+ } -+} -+ -+void LT8912B_chip_ID(void) -+{ -+ I2CADR=0x90; -+ printk("%s chip ID: 0x%x, 0x%x\n",LOG_FLAG,HDMI_ReadI2C_Byte(0x00), HDMI_ReadI2C_Byte(0x01)); -+} -+ -+ -+void LT8912B_Suspend(bool on) -+{ -+ //9mA,HPD detect is normal. -+ if(on) -+ { -+ if(!suspend_on) -+ { -+ // enter suspend mode -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte( 0x54, 0x1d ); -+ HDMI_WriteI2C_Byte( 0x51, 0x15 ); -+ HDMI_WriteI2C_Byte( 0x44, 0x31 ); -+ HDMI_WriteI2C_Byte( 0x41, 0xbd ); -+ HDMI_WriteI2C_Byte( 0x5c, 0x11 ); -+ suspend_on = 1; -+ printk("%s suspend on.\n",LOG_FLAG); -+ } -+ -+ }else{ -+ -+ if(suspend_on) -+ { -+ //exist suspend mode -+ I2CADR = 0x90; -+ HDMI_WriteI2C_Byte( 0x5c, 0x10 ); -+ HDMI_WriteI2C_Byte( 0x54, 0x1c ); -+ HDMI_WriteI2C_Byte( 0x51, 0x2d ); -+ HDMI_WriteI2C_Byte( 0x44, 0x30 ); -+ HDMI_WriteI2C_Byte( 0x41, 0xbc ); -+ -+ msleep(10); -+ HDMI_WriteI2C_Byte(0x03,0x7f); -+ msleep(10); -+ HDMI_WriteI2C_Byte(0x03,0xff); -+ -+ HDMI_WriteI2C_Byte(0x05,0xfb); -+ msleep(10); -+ HDMI_WriteI2C_Byte(0x05,0xff); -+ suspend_on = 0; -+ printk("%s suspend off.\n",LOG_FLAG); -+ } -+ } -+} -+ -+ -+void LT8912B_Config(void) -+{ -+ LT8912B_chip_ID(); -+ -+ #ifdef _pattern_test_ -+ pattern_test(); -+ while(Main_Loop); -+ #else -+ DigitalClockEn(); -+ TxAnalog(); -+ CbusAnalog(); -+ HDMIPllAnalog(); -+ MipiAnalog(); -+ MipiBasicSet(); -+ DDSConfig(); -+ MIPI_Video_Setup(&video_1920x1080_60Hz); -+ MIPI_Input_det(); -+ AudioIIsEn(); -+ -+ -+ #ifdef dds_debug -+ lt8912_check_dds(); // can be removed when debug stage. -+ #endif -+ -+ #ifdef _lvds_bypass -+ lvds_output_cfg(); -+ LvdsOutput(1); -+ #endif -+ -+///////////////////////////////////////////////////////////// test use -+// HdmiOutput(1); -+// while(1); -+///////////////////////////////////////////////////////////// -+ -+ #ifdef _hdmi_output -+ if(LT8912_Get_HPD()) -+ { -+ if(!Tx_HPD) -+ { -+ HdmiOutput(1); -+ Tx_HPD = 1; -+ printk("%s LT8912_Get_HPD: high\n",LOG_FLAG); -+ } -+ -+ }else{ -+ -+ if(Tx_HPD) -+ { -+ LT8912B_Suspend(1); -+ printk("%s LT8912 Suspend!\n",LOG_FLAG); -+ HdmiOutput(0); -+ Tx_HPD = 0; -+ printk("%s LT8912_Get_HPD: low\n",LOG_FLAG); -+ } -+ } -+ #endif -+ -+ #endif -+ -+ while(Main_Loop) -+ { -+ MIPI_Input_det(); -+ msleep(300); -+ -+ #ifdef _hdmi_output -+ if(LT8912_Get_HPD()) -+ { -+ if(!Tx_HPD) -+ { -+ LT8912B_Suspend(0); -+ HdmiOutput(1); -+ Tx_HPD = 1; -+ } -+ -+ }else{ -+ -+ if(Tx_HPD) -+ { -+ LT8912B_Suspend(1); -+ HdmiOutput(0); -+ Tx_HPD = 0; -+ } -+ } -+ #endif -+ } -+} -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B_Main.c b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B_Main.c -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B_Main.c -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LT8912B_Main.c -@@ -0,0 +1,35 @@ -+#include "../include/include.h" -+ -+ -+void LT8912B_Power_On(void) -+{ -+ gpiod_set_value(lt8912b->power_gpio,1); -+ msleep(5); -+ printk("%s Set power High level.\n ",LOG_FLAG); -+ -+} -+ -+void LT8912B_Reset(void) -+{ -+ //complete chip reset logic -+ gpiod_set_value(lt8912b->reset_gpio,1); -+ msleep(5); -+ gpiod_set_value(lt8912b->reset_gpio,0); -+ msleep(5); -+ gpiod_set_value(lt8912b->reset_gpio,1); -+ msleep(100); -+ printk("%s Reset chip.\n",LOG_FLAG); -+} -+ -+ -+int LT8912B_Main(void *data) -+{ -+ printk("%s Init Start!\n",LOG_FLAG); -+ LT8912B_Power_On(); -+ LT8912B_Reset(); -+ LT8912B_Config(); -+ -+ Tx_HPD = 0; -+ -+ return 0; -+} -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LontiumDrv.c b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LontiumDrv.c -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/src/LontiumDrv.c -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/src/LontiumDrv.c -@@ -0,0 +1,386 @@ -+#include "../include/include.h" -+ -+ -+struct _lt8912b *lt8912b; -+static struct task_struct *kthread_obj; -+volatile bool Main_Loop=true; -+char *ChipName = "lt8912b"; //Define Lontium Chip Name -+static int major = 0; -+static struct cdev chip_cdev; -+static struct class *chip_class; -+const char *LOG_FLAG = "LT8912B"; -+ -+u8 I2CADR; -+u8 addr_1_value = 0x00; -+u8 addr_2_value = 0x00; -+ -+ -+static int chip_open(struct inode *inode, struct file *filp) -+{ -+ printk("chip open\n"); -+ return 0; -+} -+ -+ -+static int chip_close (struct inode *node, struct file *file) -+{ -+ printk("chip close\n"); -+ return 0; -+} -+ -+ -+static ssize_t chip_read(struct file *filp, char __user *buf, size_t cnt, loff_t *offt) -+{ -+ Chip_Control_Args parameter; -+ -+ if (copy_from_user(¶meter, buf, sizeof(parameter))) { -+ return -EFAULT; -+ } -+ -+ parameter.value = HDMI_ReadI2C_Byte(parameter.address); -+ -+ if (copy_to_user(buf, ¶meter, sizeof(parameter))) { -+ return -EFAULT; -+ } -+ -+ return sizeof(parameter); -+ -+} -+ -+static ssize_t chip_write(struct file *filp, const char __user *buf, size_t cnt, loff_t *offt) -+{ -+ Chip_Control_Args parameter; -+ -+ if (copy_from_user(¶meter, buf, sizeof(parameter))) { -+ return -EFAULT; -+ } -+ -+ HDMI_WriteI2C_Byte(parameter.address, parameter.value); -+ -+ return sizeof(parameter); -+ -+} -+ -+ -+ -+ -+static struct file_operations chip_drv = { -+ .owner = THIS_MODULE, -+ .open = chip_open, -+ .release = chip_close, -+ .read = chip_read, -+ .write = chip_write, -+}; -+ -+ -+ -+static int chip_dev_init(void) -+{ -+ int ret; -+ dev_t devid; -+ -+ ret = alloc_chrdev_region(&devid, 0, 1, ChipName); -+ if (ret < 0) { -+ return ret; -+ } -+ -+ major = MAJOR(devid); -+ cdev_init(&chip_cdev, &chip_drv); -+ cdev_add(&chip_cdev, devid, 1); -+ chip_class = class_create(THIS_MODULE, "chip_class"); -+ if (IS_ERR(chip_class)) { -+ unregister_chrdev(major, ChipName); -+ return -1; -+ } -+ -+ device_create(chip_class, NULL, MKDEV(major, 0), NULL, ChipName); /* /dev/ChipName */ -+ -+ return 0; -+} -+ -+ -+static void chip_dev_exit(void) -+{ -+ device_destroy(chip_class, MKDEV(major, 0)); -+ class_destroy(chip_class); -+ cdev_del(&chip_cdev); -+ unregister_chrdev_region(MKDEV(major,0), 1); -+} -+ -+ -+ -+static const struct regmap_range chip_ranges[] = { -+ { .range_min = 0, .range_max = 0xffff }, -+}; -+ -+static const struct regmap_access_table chip_table = { -+ .yes_ranges = chip_ranges, -+ .n_yes_ranges = ARRAY_SIZE(chip_ranges), -+}; -+ -+static const struct regmap_config chip_regmap_config = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ .volatile_table = &chip_table, -+ .cache_type = REGCACHE_NONE, -+}; -+ -+ -+ -+static int chip_parse_dts(struct device *dev) -+{ -+ -+ /* -+ * devm_gpiod_get_optional - If this fails, NULL is returned and no error pointer. -+ * -+ * devm_gpiod_get - If this fails, an error pointer is returned, usually ERR_PTR(-ENOENT). -+ * -+ * The devm_gpiod_get function is recommended for practical use. -+ */ -+ -+ -+ //Gets the handle to power gpio in dts -+ -+#if 1 -+ lt8912b->power_gpio=devm_gpiod_get_optional(dev, "power", GPIOD_OUT_HIGH); -+ if (IS_ERR(lt8912b->power_gpio)) { -+ dev_err(dev, "Failed to get power GPIO\n"); -+ return PTR_ERR(lt8912b->power_gpio); -+ } -+#endif -+ -+ //Gets the handle to reset gpio in dts -+ -+ lt8912b->reset_gpio=devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); -+ if (IS_ERR(lt8912b->reset_gpio)) { -+ dev_err(dev, "Failed to get reset GPIO\n"); -+ return PTR_ERR(lt8912b->reset_gpio); -+ } -+ -+ -+ // Additional GPIO pins can be added here if needed -+ -+ return 0; -+} -+ -+ -+static int chip_probe(struct i2c_client *client, const struct i2c_device_id *id) -+{ -+ struct i2c_board_info addr_1_board_info = { -+ I2C_BOARD_INFO("lt8912b_addr_1", addr_1_value), -+ }; -+ struct i2c_board_info addr_2_board_info = { -+ I2C_BOARD_INFO("lt8912b_addr_2", addr_2_value), -+ }; -+ struct device_node *np = client->dev.of_node; -+ struct device_node *addr_1_node; -+ struct device_node *addr_2_node; -+ int ret; -+ -+ if (!np) { -+ dev_err(&client->dev, "Device tree node missing"); -+ return -EINVAL; -+ } -+ -+ chip_dev_init(); -+ -+ lt8912b = devm_kzalloc(&client->dev, sizeof(*lt8912b), GFP_KERNEL); -+ if (lt8912b == NULL) -+ return -ENOMEM; -+ -+ lt8912b->i2c_stu = client; -+ -+ lt8912b->dev = &client->dev; -+ -+ //////////////////////////////////////////////// -+ //addr_0 -+ -+ lt8912b->chip_regmap = devm_regmap_init_i2c(client, &chip_regmap_config); -+ if (IS_ERR(lt8912b->chip_regmap)) { -+ dev_err(&client->dev, "Failed to initialize regmap\n"); -+ return PTR_ERR(lt8912b->chip_regmap); -+ } -+ -+ //////////////////////////////////////////////// -+ -+ ///////////////////////////////////////////////// -+ //addr_1 -+ -+ addr_1_node = of_get_child_by_name(np, "lt8912b_addr_1"); -+ if (!addr_1_node) { -+ dev_err(&client->dev, "Failed to find lt8912b_addr_1 node"); -+ return -EINVAL; -+ } -+ -+ lt8912b->addr_1 = devm_kzalloc(&client->dev, sizeof(struct addr_1), GFP_KERNEL); -+ if (!lt8912b->addr_1) -+ return -ENOMEM; -+ -+ if (of_property_read_u8(addr_1_node, "addr_1_reg", &addr_1_value)) { -+ dev_err(&client->dev, "Failed to get addr_1_reg address"); -+ return -EINVAL; -+ } -+ addr_1_board_info.addr =addr_1_value; -+ -+ lt8912b->addr_1->i2c_stu = i2c_new_device(client->adapter, &addr_1_board_info); -+ if (!lt8912b->addr_1->i2c_stu) { -+ dev_err(&client->dev, "Failed to create I2C client for addr_1"); -+ return -ENODEV; -+ } -+ -+ lt8912b->addr_1->regmap = devm_regmap_init_i2c(lt8912b->addr_1->i2c_stu, &chip_regmap_config); -+ if (IS_ERR(lt8912b->addr_1->regmap)) { -+ dev_err(&client->dev, "Failed to initialize addr_1 regmap"); -+ i2c_unregister_device(lt8912b->addr_1->i2c_stu); -+ return PTR_ERR(lt8912b->addr_1->regmap); -+ } -+ -+ /////////////////////////////////////////////////// -+ -+ ///////////////////////////////////////////////// -+ //addr_2 -+ -+ addr_2_node = of_get_child_by_name(np, "lt8912b_addr_2"); -+ if (!addr_2_node) { -+ dev_err(&client->dev, "Failed to find lt8912b_addr_2 node"); -+ return -EINVAL; -+ } -+ -+ lt8912b->addr_2 = devm_kzalloc(&client->dev, sizeof(struct addr_2), GFP_KERNEL); -+ if (!lt8912b->addr_2) -+ return -ENOMEM; -+ -+ if (of_property_read_u8(addr_2_node, "addr_2_reg", &addr_2_value)) { -+ dev_err(&client->dev, "Failed to get addr_2_reg address"); -+ return -EINVAL; -+ } -+ addr_2_board_info.addr =addr_2_value; -+ -+ lt8912b->addr_2->i2c_stu = i2c_new_device(client->adapter, &addr_2_board_info); -+ if (!lt8912b->addr_2->i2c_stu) { -+ dev_err(&client->dev, "Failed to create I2C client for addr_2"); -+ return -ENODEV; -+ } -+ -+ lt8912b->addr_2->regmap = devm_regmap_init_i2c(lt8912b->addr_2->i2c_stu, &chip_regmap_config); -+ if (IS_ERR(lt8912b->addr_2->regmap)) { -+ dev_err(&client->dev, "Failed to initialize addr_2 regmap"); -+ i2c_unregister_device(lt8912b->addr_2->i2c_stu); -+ return PTR_ERR(lt8912b->addr_2->regmap); -+ } -+ /////////////////////////////////////////////////// -+ -+ mutex_init(<8912b->ocm_lock); -+ -+ ret = chip_parse_dts(lt8912b->dev); -+ if (ret<0){ -+ dev_err(&client->dev, "Failed to parse device tree\n"); -+ return ret; -+ } -+ -+ i2c_set_clientdata(client, lt8912b); -+ -+ -+ kthread_obj = kthread_run(LT8912B_Main, NULL, "LT8912B_kthread"); -+ if (IS_ERR(kthread_obj)) { -+ dev_err(&client->dev, "Failed to create kernel thread\n"); -+ return PTR_ERR(kthread_obj); -+ } -+ -+ return 0; -+ -+} -+ -+static int chip_remove(struct i2c_client *client) -+{ -+ -+ Main_Loop = false; -+ msleep(500); -+ -+ mutex_destroy(<8912b->ocm_lock); -+ -+ i2c_unregister_device(lt8912b->addr_1->i2c_stu); -+ -+ i2c_unregister_device(lt8912b->addr_2->i2c_stu); -+ -+ chip_dev_exit(); -+ -+ printk("driver removed\n"); -+ return 0; -+} -+ -+ -+static int chip_suspend(struct device *dev) -+{ -+ -+ printk(KERN_INFO "%s Suspend.\n",LOG_FLAG); -+ -+ gpiod_set_value(lt8912b->reset_gpio,0); -+ msleep(10); -+ -+ Main_Loop =false; -+ -+ return 0; -+} -+ -+ -+ -+static int chip_resume(struct device *dev) -+{ -+ -+ printk(KERN_INFO "%s Resume.\n",LOG_FLAG); -+ -+ -+ gpiod_set_value(lt8912b->reset_gpio,1); -+ msleep(5); -+ -+ Main_Loop = true; -+ msleep(5); -+ -+ kthread_obj = kthread_run(LT8912B_Main, NULL, "LT8912B_kthread"); -+ -+ return 0; -+} -+ -+ -+static const struct dev_pm_ops chip_pm_ops = { -+ .suspend = chip_suspend, -+ .resume = chip_resume, -+}; -+ -+ -+ -+ -+static const struct i2c_device_id chip_ids[] = { -+ {"lt8912b", 0}, -+ { } -+}; -+MODULE_DEVICE_TABLE(i2c, chip_ids); -+ -+ -+static const struct of_device_id chip_id_table[] = { -+ {.compatible = "lontium,lt8912b"}, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, chip_id_table); -+ -+ -+static struct i2c_driver chip_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "lt8912b", -+ .pm = &chip_pm_ops, -+ .of_match_table = chip_id_table, -+ -+ }, -+ .probe = chip_probe, -+ .remove = chip_remove, -+ .id_table = chip_ids, -+}; -+ -+ -+module_i2c_driver(chip_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("LT8912B driver"); -+MODULE_AUTHOR("Tony Yang"); -diff --git a/source/kernel/kernel5.4/drivers/video/LT8912B/src/OcmI2cMaster.c b/source/kernel/kernel5.4/drivers/video/LT8912B/src/OcmI2cMaster.c -new file mode 100644 ---- a/source/kernel/kernel5.4/drivers/video/LT8912B/src/OcmI2cMaster.c -+++ b/source/kernel/kernel5.4/drivers/video/LT8912B/src/OcmI2cMaster.c -@@ -0,0 +1,91 @@ -+#include "../include/include.h" -+ -+ -+ -+ -+ -+int HDMI_WriteI2C_Byte(u8 addr,u8 data) -+{ -+ int ret = 0; -+ mutex_lock(<8912b->ocm_lock); -+ -+ if(I2CADR==0x90) -+ { -+ ret = regmap_write(lt8912b->chip_regmap, addr, data); -+ if (ret < 0) { -+ printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d", -+ lt8912b->i2c_stu->addr, addr, data, ret); -+ mutex_unlock(<8912b->ocm_lock); -+ return ret; -+ } -+ }else if(I2CADR==0x92){ -+ ret = regmap_write(lt8912b->addr_1->regmap, addr, data); -+ if (ret < 0) { -+ printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d", -+ lt8912b->addr_1->i2c_stu->addr, addr, data, ret); -+ mutex_unlock(<8912b->ocm_lock); -+ return ret; -+ } -+ -+ }else if(I2CADR==0x94){ -+ ret = regmap_write(lt8912b->addr_2->regmap, addr, data); -+ if (ret < 0) { -+ printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d", -+ lt8912b->addr_2->i2c_stu->addr, addr, data, ret); -+ mutex_unlock(<8912b->ocm_lock); -+ return ret; -+ } -+ } -+ -+ mutex_unlock(<8912b->ocm_lock); -+ return 0; -+} -+ -+ -+ -+ -+ -+int HDMI_ReadI2C_Byte(u8 addr) -+{ -+ int ret = 0; -+ unsigned int val = 0; -+ mutex_lock(<8912b->ocm_lock); -+ -+ if(I2CADR==0x90){ -+ -+ ret = regmap_read(lt8912b->chip_regmap, addr, &val); -+ if (ret < 0) { -+ printk("regmap_read error: (0x%02x 0x%02x) %d", -+ lt8912b->i2c_stu->addr, addr, ret); -+ mutex_unlock(<8912b->ocm_lock); -+ return ret; -+ } -+ }else if(I2CADR==0x92){ -+ -+ ret = regmap_read(lt8912b->addr_1->regmap, addr, &val); -+ if (ret < 0) { -+ printk("regmap_read error: (0x%02x 0x%02x) %d", -+ lt8912b->addr_1->i2c_stu->addr, addr, ret); -+ mutex_unlock(<8912b->ocm_lock); -+ return ret; -+ } -+ -+ }else if(I2CADR==0x94){ -+ -+ ret = regmap_read(lt8912b->addr_2->regmap, addr, &val); -+ if (ret < 0) { -+ printk("regmap_read error: (0x%02x 0x%02x) %d", -+ lt8912b->addr_2->i2c_stu->addr, addr, ret); -+ mutex_unlock(<8912b->ocm_lock); -+ return ret; -+ } -+ -+ } -+ -+ mutex_unlock(<8912b->ocm_lock); -+ return (u8)val; -+} -+ -+ -+EXPORT_SYMBOL(HDMI_WriteI2C_Byte); -+EXPORT_SYMBOL(HDMI_ReadI2C_Byte); -diff --git a/source/bsp/u-boot22/arch/arm/dts/uis7885_2h10.dts b/source/bsp/u-boot22/arch/arm/dts/uis7885_2h10.dts -index 38a049e987..311964869c 100644 ---- a/source/bsp/u-boot22/arch/arm/dts/uis7885_2h10.dts -+++ b/source/bsp/u-boot22/arch/arm/dts/uis7885_2h10.dts -@@ -9,7 +9,7 @@ - #include "lcd/lcd_g40396_truly_mipi_fhd.dtsi" - #include "lcd/lcd_nt36672e_truly_mipi_fhd_nodsc.dtsi" - #include "lcd/lcd_ili7806s_truly_mipi_hdplus.dtsi" --#include "lcd/lcd_dummy_mipi.dtsi" -+#include "lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi" - #include - #include - -@@ -72,7 +72,7 @@ - reg = <0x0 0x92200000 0x0 0x00200000>; - }; - -- pre_log_buffer: pre_log_buffer@92300000{ -+ pre_log_buffer: pre_log_buffer@b4000000{ - reg = <0x0 0xb4000000 0x0 0x00002000>; - }; - -@@ -89,8 +89,8 @@ - reg = <0x0 0xbd060000 0x0 0x01fa0000>; - }; - -- tos_shm_reserved: sh-mem@96000000{ -- reg = <0x0 0x96000000 0x0 0x00100000>; -+ tos_shm_reserved: sh-mem@C3000000{ -+ reg = <0x0 0xC3000000 0x0 0x00100000>; - }; - - secboot_arg_reserved: secboot-arg-mem@98100000{ -diff --git a/source/bsp/u-boot22/board/sprd/uis7885_2h10/pinmap-ums9620.c b/source/bsp/u-boot22/board/sprd/uis7885_2h10/pinmap-ums9620.c -index 28addeca94..933d4f4024 100644 ---- a/source/bsp/u-boot22/board/sprd/uis7885_2h10/pinmap-ums9620.c -+++ b/source/bsp/u-boot22/board/sprd/uis7885_2h10/pinmap-ums9620.c -@@ -35,13 +35,13 @@ static struct pinmap_t pinmap[] = { - //{REG_PIN_PWR_PAD_CTL_RESERVED,0x00000000},// - {REG_PIN_SIM_MATRIX_MTX_CFG, 0x00000002},//SIM0->PSCP_SIM0;SIM1->PSCP_SIM1; - {REG_PIN_DMIC_MATRIX_MTX_CFG, 0x00000000},//DMIC0->AUDCP_AUD_DMIC0;DMIC1->AUDCP_AUD_DMIC1;DMIC2->AUDCP_PDM_DMIC2 --{REG_PIN_UART_MATRIX_MTX_CFG, 0x5B97081A},//UART0->CM4_UART1;UART1->AP_UART1;UART2->AP_UART2;UART3->PHYCP_WCI2;UART4->CM4_UART0;UART5->CM4_UART2;UART6->PSCP_UART1; --{REG_PIN_UART_MATRIX_MTX_CFG1, 0x00000086},//UART7->PHYCP_UART0;UART8->AUDDSP_UART0; -+{REG_PIN_UART_MATRIX_MTX_CFG, 0x3B97081A},//UART0->CM4_UART1;UART1->AP_UART1;UART2->AP_UART2;UART3->PHYCP_WCI2;UART4->CM4_UART0;UART5->CM4_UART2;UART6->AP_UART3; -+{REG_PIN_UART_MATRIX_MTX_CFG1, 0x00000080},//UART7->AP_UART0;UART8->AUDDSP_UART0; - {REG_PIN_IIS_MATRIX_MTX_CFG, 0x02904080},//IIS0->AP_IIS0;IIS1->AP_IIS1;IIS2->AP_IIS2;IIS3->AUDCP_IIS0;IIS4->AUDCP_IIS1; - {REG_PIN_IIS_MATRIX_MTX_CFG1, 0x00000006},//IIS5->AUDCP_IIS2;IIS6->vbc_IIS2; - {REG_PIN_SPI_MATRIX_MTX_CFG, 0x00000040},//SPI0->AP_SPI0;SPI1->AP_SPI1;SPI2->AP_SPI2;SPI3->CM4_SPI0; --{REG_PIN_IIC_MATRIX_MTX_CFG, 0x76D23C10},//IIC0->AP_IIC0;IIC1->AP_IIC1;IIC2->CM4_I2C0;IIC3->AP_IIC3;IIC4->AP_IIC2;IIC5->CM4_I2C1;IIC6->AP_IIC6;IIC7->AP_IIC7 --{REG_PIN_IIC_MATRIX_MTX_CFG1, 0x0000054},//IIC8->AP_IIC4;IIC9->AP_IIC5 -+{REG_PIN_IIC_MATRIX_MTX_CFG, 0x76523C10},//IIC0->AP_IIC0;IIC1->AP_IIC1;IIC2->CM4_I2C0;IIC3->AP_IIC3;IIC4->AP_IIC2;IIC5->AP_I2C5;IIC6->AP_IIC6;IIC7->AP_IIC7 -+{REG_PIN_IIC_MATRIX_MTX_CFG1, 0x000000D4},//IIC8->AP_IIC4;IIC9->CM4_IIC1 - {REG_PIN_HOT_PLUG_DET_MATRIX_MTX_CFG, 0x00000000},//HOTPLUG0->SIM0;HOTPLUG1->SIM1;HOTPLUG2->AP_SDIO0 - - //REG_PIN_xx Function select -@@ -86,10 +86,10 @@ static struct pinmap_t pinmap[] = { - {REG_MISC_PIN_EXTINT0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//CTP_INT - {REG_PIN_EXTINT1, BITS_PIN_AF(3)}, - {REG_MISC_PIN_EXTINT1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CTP_RST --{REG_PIN_SDA3, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SDA3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC --{REG_PIN_SCL3, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SCL3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_PIN_SDA3, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SDA3, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//HDMI conn I2C -+{REG_PIN_SCL3, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SCL3, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//HDMI conn I2C - {REG_PIN_DCDC_ARM1_EN, BITS_PIN_AF(0)}, - {REG_MISC_PIN_DCDC_ARM1_EN, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//VDDCPU1_EN - {REG_PIN_PTEST, BITS_PIN_AF(0)}, -@@ -144,20 +144,20 @@ static struct pinmap_t pinmap[] = { - {REG_MISC_PIN_TF_DET, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//TF_DET - {REG_PIN_BAT_DET, BITS_PIN_AF(0)}, - {REG_MISC_PIN_BAT_DET, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//BAT_DET --{REG_PIN_SCL4, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SCL4, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC --{REG_PIN_SDA4, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SDA4, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_PIN_SCL4, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SCL4, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//HDMI/CTP I2C -+{REG_PIN_SDA4, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SDA4, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//HDMI/CTP I2C - {REG_PIN_CLK_AUX1, BITS_PIN_AF(0)}, - {REG_MISC_PIN_CLK_AUX1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CLK_AUX1 --{REG_PIN_IIS1DI, BITS_PIN_AF(2)}, --{REG_MISC_PIN_IIS1DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//FTID_INT --{REG_PIN_IIS1DO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS1DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//FTID_RSTN --{REG_PIN_IIS1CLK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS1CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAMERA_FLASH_EN --{REG_PIN_IIS1LRCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS1LRCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//camera_torch_en -+{REG_PIN_IIS1DI, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS1DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//40PIN PCM_DI -+{REG_PIN_IIS1DO, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS1DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//40PIN PCM_DO -+{REG_PIN_IIS1CLK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS1CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_OE},//40PIN PCM_CLK -+{REG_PIN_IIS1LRCK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS1LRCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//40PIN PCM_SYNC - {REG_PIN_SIMCLK0, BITS_PIN_AF(0)}, - {REG_MISC_PIN_SIMCLK0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_NONE | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//SIM0_CLK - {REG_PIN_SIMDA0, BITS_PIN_AF(0)}, -@@ -171,39 +171,39 @@ static struct pinmap_t pinmap[] = { - {REG_PIN_SIMRST1, BITS_PIN_AF(0)}, - {REG_MISC_PIN_SIMRST1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_NONE | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//SIM1_RST - {REG_PIN_SD0_CMD, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD0_CMD, BITS_PIN_DS(7) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_CMD -+{REG_MISC_PIN_SD0_CMD, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_CMD - {REG_PIN_SD0_D_0, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD0_D_0, BITS_PIN_DS(7) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D0 -+{REG_MISC_PIN_SD0_D_0, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D0 - {REG_PIN_SD0_D_1, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD0_D_1, BITS_PIN_DS(7) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D1 -+{REG_MISC_PIN_SD0_D_1, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D1 - {REG_PIN_SD0_CLK, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD0_CLK, BITS_PIN_DS(7) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_CLK0 -+{REG_MISC_PIN_SD0_CLK, BITS_PIN_DS(6) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_CLK0 - {REG_PIN_SD0_D_2, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD0_D_2, BITS_PIN_DS(7) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D2 -+{REG_MISC_PIN_SD0_D_2, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D2 - {REG_PIN_SD0_D_3, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD0_D_3, BITS_PIN_DS(7) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D3 --{REG_PIN_SD2_CMD, BITS_PIN_AF(1)}, --{REG_MISC_PIN_SD2_CMD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//LCM_SPI_MISO --{REG_PIN_SD2_D0, BITS_PIN_AF(1)}, --{REG_MISC_PIN_SD2_D0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//LCM_SPI_MOSI --{REG_PIN_SD2_D1, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SD2_D1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAMERA_FLASH_CHIPEN --{REG_PIN_SD2_CLK, BITS_PIN_AF(1)}, --{REG_MISC_PIN_SD2_CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//LCM_SPI_CLK --{REG_PIN_SD2_D2, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SD2_D2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//UCP1301_RSTN --{REG_PIN_SD2_D3, BITS_PIN_AF(1)}, --{REG_MISC_PIN_SD2_D3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_SPI_CS -+{REG_MISC_PIN_SD0_D_3, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TF_SD0_D3 -+{REG_PIN_SD2_CMD, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SD2_CMD, BITS_PIN_DS(4) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD2_CMD -+{REG_PIN_SD2_D0, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SD2_D0, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF__SD2_D0 -+{REG_PIN_SD2_D1, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SD2_D1, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD2_D1 -+{REG_PIN_SD2_CLK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SD2_CLK, BITS_PIN_DS(4) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD2_CLK -+{REG_PIN_SD2_D2, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SD2_D2, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD2_D2 -+{REG_PIN_SD2_D3, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_SD2_D3, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD2_D3 - {REG_PIN_IIS3DI, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS3DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_SOURCE_AVEEEN -+{REG_MISC_PIN_IIS3DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC - {REG_PIN_IIS3DO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS3DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_SOURCE_AVDDEN --{REG_PIN_IIS3LRCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS3LRCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//BQ25970_INTacticelow --{REG_PIN_IIS3CLK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS3CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//TOF_XSHUT -+{REG_MISC_PIN_IIS3DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//SPI1_CS1 ? -+{REG_PIN_IIS3LRCK, BITS_PIN_AF(1)}, -+{REG_MISC_PIN_IIS3LRCK, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C7 -+{REG_PIN_IIS3CLK, BITS_PIN_AF(1)}, -+{REG_MISC_PIN_IIS3CLK, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C7 - {REG_PIN_CLK_AUX2, BITS_PIN_AF(0)}, --{REG_MISC_PIN_CLK_AUX2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CLK_AUX2 -+{REG_MISC_PIN_CLK_AUX2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//clk AUX2 test point - {REG_PIN_RFCTL_0, BITS_PIN_AF(0)}, - {REG_MISC_PIN_RFCTL_0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//RFCTL_0 - {REG_PIN_RFCTL_1, BITS_PIN_AF(0)}, -@@ -222,20 +222,20 @@ static struct pinmap_t pinmap[] = { - {REG_MISC_PIN_RFCTL_7, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//RFCTL_7 - {REG_PIN_RFCTL_8, BITS_PIN_AF(0)}, - {REG_MISC_PIN_RFCTL_8, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//RFCTL_8 --{REG_PIN_RFCTL_9, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFCTL_9, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//VDDCAMMOT_EN --{REG_PIN_RFCTL_10, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFCTL_10, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//VDDCAMA1_EN -+{REG_PIN_RFCTL_9, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFCTL_9, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//RFCTL_9 -+{REG_PIN_RFCTL_10, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFCTL_10, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//RFCTL_10 - {REG_PIN_RFCTL_11, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFCTL_11, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//VDDCAMA0_EN --{REG_PIN_RFCTL_12, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFCTL_12, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//VDDCAMCORE_EN -+{REG_MISC_PIN_RFCTL_11, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_PIN_RFCTL_12, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFCTL_12, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//RFCTL_12 - {REG_PIN_RFCTL_13, BITS_PIN_AF(0)}, - {REG_MISC_PIN_RFCTL_13, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//GNSS_COEXIST - {REG_PIN_RFCTL_14, BITS_PIN_AF(1)}, - {REG_MISC_PIN_RFCTL_14, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//WB_WCI_2_RXD - {REG_PIN_RFCTL_15, BITS_PIN_AF(1)}, --{REG_MISC_PIN_RFCTL_15, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//WB_WCI_2_RXD -+{REG_MISC_PIN_RFCTL_15, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//WB_WCI_2_TXD - {REG_PIN_RFFE0_SCK, BITS_PIN_AF(0)}, - {REG_MISC_PIN_RFFE0_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SCK0 - {REG_PIN_RFFE0_SDA, BITS_PIN_AF(0)}, -@@ -256,16 +256,16 @@ static struct pinmap_t pinmap[] = { - {REG_MISC_PIN_RFFE4_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SCK4 - {REG_PIN_RFFE4_SDA, BITS_PIN_AF(0)}, - {REG_MISC_PIN_RFFE4_SDA, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SDA4 --{REG_PIN_RFFE5_SCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFFE5_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC --{REG_PIN_RFFE5_SDA, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFFE5_SDA, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC --{REG_PIN_RFFE6_SCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFFE6_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC --{REG_PIN_RFFE6_SDA, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFFE6_SDA, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_PIN_RFFE5_SCK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFFE5_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SCK5 -+{REG_PIN_RFFE5_SDA, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFFE5_SDA, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SDA5 -+{REG_PIN_RFFE6_SCK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFFE6_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SCK6 -+{REG_PIN_RFFE6_SDA, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_RFFE6_SDA, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_ALL_CP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//RFFE_SDA6 - {REG_PIN_RFFE7_SCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_RFFE7_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_RFFE7_SCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//HDMI_PWR_5V - {REG_PIN_RFFE7_SDA, BITS_PIN_AF(3)}, - {REG_MISC_PIN_RFFE7_SDA, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC - {REG_PIN_LVDSRF_ADDAC0_ON, BITS_PIN_AF(0)}, -@@ -293,31 +293,31 @@ static struct pinmap_t pinmap[] = { - {REG_PIN_SDA6, BITS_PIN_AF(0)}, - {REG_MISC_PIN_SDA6, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C6_SDA - {REG_PIN_VDSP_TDO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_VDSP_TDO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_VDSP_TDO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//LCM_INT1 - {REG_PIN_VDSP_TDI, BITS_PIN_AF(3)}, --{REG_MISC_PIN_VDSP_TDI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_VDSP_TDI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//LCM_INT/LT8912B - {REG_PIN_VDSP_TMS, BITS_PIN_AF(3)}, - {REG_MISC_PIN_VDSP_TMS, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_Z},//BOARD_ID0 - {REG_PIN_VDSP_TCK, BITS_PIN_AF(3)}, - {REG_MISC_PIN_VDSP_TCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_Z},//BOARD_ID1 - {REG_PIN_VDSP_RTCK, BITS_PIN_AF(3)}, - {REG_MISC_PIN_VDSP_RTCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_Z},//BOARD_ID2 --{REG_PIN_DMIC_CLK2, BITS_PIN_AF(0)}, --{REG_MISC_PIN_DMIC_CLK2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//PDM_CLK2 --{REG_PIN_DMIC_DATA2, BITS_PIN_AF(0)}, --{REG_MISC_PIN_DMIC_DATA2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//PDM_DATA2 -+{REG_PIN_DMIC_CLK2, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_DMIC_CLK2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_PIN_DMIC_DATA2, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_DMIC_DATA2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC - {REG_PIN_DMIC_CLK0, BITS_PIN_AF(3)}, - {REG_MISC_PIN_DMIC_CLK0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//CHG_INT - {REG_PIN_DMIC_DATA0, BITS_PIN_AF(3)}, --{REG_MISC_PIN_DMIC_DATA0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_DMIC_DATA0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//HUB_LDO_EN - {REG_PIN_DMIC_CLK1, BITS_PIN_AF(3)}, --{REG_MISC_PIN_DMIC_CLK1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CHG_EN_N -+{REG_MISC_PIN_DMIC_CLK1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//HDMI_5V_EN - {REG_PIN_DMIC_DATA1, BITS_PIN_AF(3)}, --{REG_MISC_PIN_DMIC_DATA1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CHG_FLAG_N --{REG_PIN_U2TXD, BITS_PIN_AF(0)}, --{REG_MISC_PIN_U2TXD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//BB_U2TXD --{REG_PIN_U2RXD, BITS_PIN_AF(0)}, --{REG_MISC_PIN_U2RXD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//BB_U2RXD -+{REG_MISC_PIN_DMIC_DATA1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//USB_HOST_SW1 -+{REG_PIN_U2TXD, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_U2TXD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//EXT_LEVLESHIFT_EN -+{REG_PIN_U2RXD, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_U2RXD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//POE_PWR_OFF - {REG_PIN_U1TXD, BITS_PIN_AF(0)}, - {REG_MISC_PIN_U1TXD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//BB_U1TXD - {REG_PIN_U1RXD, BITS_PIN_AF(0)}, -@@ -335,45 +335,45 @@ static struct pinmap_t pinmap[] = { - {REG_PIN_MTMS_ARM, BITS_PIN_AF(0)}, - {REG_MISC_PIN_MTMS_ARM, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_NONE | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//MTMS - {REG_PIN_AUD_DSP_TDO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_AUD_DSP_TDO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_AUD_DSP_TDO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//USBA_5V_EN - {REG_PIN_AUD_DSP_RTCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_AUD_DSP_RTCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_AUD_DSP_RTCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LAN_PWR_EN - {REG_PIN_AUD_DSP_TDI, BITS_PIN_AF(3)}, --{REG_MISC_PIN_AUD_DSP_TDI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_AUD_DSP_TDI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO148 - {REG_PIN_AUD_DSP_TCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_AUD_DSP_TCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//TOF_GPIO -+{REG_MISC_PIN_AUD_DSP_TCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC - {REG_PIN_AUD_DSP_TMS, BITS_PIN_AF(3)}, --{REG_MISC_PIN_AUD_DSP_TMS, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_AUD_DSP_TMS, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO150 - {REG_PIN_CMMCLK0, BITS_PIN_AF(0)}, --{REG_MISC_PIN_CMMCLK0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_MCLK0 -+{REG_MISC_PIN_CMMCLK0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_CMMCLK1, BITS_PIN_AF(0)}, - {REG_MISC_PIN_CMMCLK1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_MCLK1 - {REG_PIN_CMMCLK2, BITS_PIN_AF(0)}, - {REG_MISC_PIN_CMMCLK2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_MCLK2 - {REG_PIN_CMMCLK3, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMMCLK3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_CMMCLK3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_CMRST0, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMRST0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_RST0 -+{REG_MISC_PIN_CMRST0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_CMRST1, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMRST1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_RST1 -+{REG_MISC_PIN_CMRST1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_CMRST2, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMRST2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_RST2 -+{REG_MISC_PIN_CMRST2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//HUB_LDO_EN - {REG_PIN_CMRST3, BITS_PIN_AF(3)}, - {REG_MISC_PIN_CMRST3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_RST3 - {REG_PIN_CMRST4, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMRST4, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_CMRST4, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG5 - {REG_PIN_CMRST5, BITS_PIN_AF(3)}, - {REG_MISC_PIN_CMRST5, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_RST5 - {REG_PIN_CMPD0, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMPD0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_PWDN0 -+{REG_MISC_PIN_CMPD0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_CMPD1, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMPD1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_PWDN1 -+{REG_MISC_PIN_CMPD1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_CMPD2, BITS_PIN_AF(3)}, - {REG_MISC_PIN_CMPD2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_PWDN2 - {REG_PIN_CMPD3, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMPD3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_CMPD3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG4 - {REG_PIN_CMPD4, BITS_PIN_AF(3)}, --{REG_MISC_PIN_CMPD4, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_CMPD4, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG3 - {REG_PIN_CMPD5, BITS_PIN_AF(3)}, - {REG_MISC_PIN_CMPD5, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//CAM_PWDN5 - {REG_PIN_SCL0, BITS_PIN_AF(0)}, -@@ -389,17 +389,17 @@ static struct pinmap_t pinmap[] = { - {REG_PIN_SDA8, BITS_PIN_AF(0)}, - {REG_MISC_PIN_SDA8, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C8_SDA - {REG_PIN_SCL9, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SCL9, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C9_SCL -+{REG_MISC_PIN_SCL9, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C9_SCL - {REG_PIN_SDA9, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SDA9, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C9_SDA -+{REG_MISC_PIN_SDA9, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C9_SDA - {REG_PIN_SPI3_CSN, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI3_CSN, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//CAMERA_FLASH_SYNC -+{REG_MISC_PIN_SPI3_CSN, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG3 - {REG_PIN_SPI3_CLK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI3_CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//COLOR_SENSOR_INT -+{REG_MISC_PIN_SPI3_CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG2 - {REG_PIN_SPI3_DI, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI3_DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//EAR_CTL1 -+{REG_MISC_PIN_SPI3_DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG1 - {REG_PIN_SPI3_DO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI3_DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//EAR_CTL2 -+{REG_MISC_PIN_SPI3_DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG0 - {REG_PIN_SPI0_CSN, BITS_PIN_AF(0)}, - {REG_MISC_PIN_SPI0_CSN, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//FTID_SPI_CS - {REG_PIN_SPI0_DO, BITS_PIN_AF(0)}, -@@ -412,46 +412,46 @@ static struct pinmap_t pinmap[] = { - {REG_MISC_PIN_SCL2, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C2_SCL - {REG_PIN_SDA2, BITS_PIN_AF(0)}, - {REG_MISC_PIN_SDA2, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C2_SDA --{REG_PIN_KEYOUT1, BITS_PIN_AF(2)}, --{REG_MISC_PIN_KEYOUT1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//PROX_INT --{REG_PIN_KEYOUT0, BITS_PIN_AF(2)}, --{REG_MISC_PIN_KEYOUT0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//AG_INT0 --{REG_PIN_KEYOUT2, BITS_PIN_AF(2)}, --{REG_MISC_PIN_KEYOUT2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//AG_INT1 -+{REG_PIN_KEYOUT1, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_KEYOUT1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINGT -+{REG_PIN_KEYOUT0, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_KEYOUT0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//USBA_CL_EN -+{REG_PIN_KEYOUT2, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_KEYOUT2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//EXT_XTL_EN4 - {REG_PIN_EXTINT9, BITS_PIN_AF(3)}, --{REG_MISC_PIN_EXTINT9, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//FS_EIS -+{REG_MISC_PIN_EXTINT9, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_Z},//LAN_PWR_EN - {REG_PIN_EXTINT10, BITS_PIN_AF(3)}, --{REG_MISC_PIN_EXTINT10, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//WCHG_INT -+{REG_MISC_PIN_EXTINT10, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//WB_TX_REQ - {REG_PIN_KEYIN0, BITS_PIN_AF(3)}, - {REG_MISC_PIN_KEYIN0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//KEYIN0 - {REG_PIN_KEYIN1, BITS_PIN_AF(3)}, - {REG_MISC_PIN_KEYIN1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//KETIN1 - {REG_PIN_KEYIN2, BITS_PIN_AF(3)}, --{REG_MISC_PIN_KEYIN2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//LCM_ID -+{REG_MISC_PIN_KEYIN2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//TEST POINT - {REG_PIN_SPI2_CSN, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI2_CSN, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_SPI2_CSN, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//WB_INT - {REG_PIN_SPI2_DO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI2_DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_SPI2_DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_SOURCE_AVDDEN - {REG_PIN_SPI2_DI, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI2_DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC -+{REG_MISC_PIN_SPI2_DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//GPIO - {REG_PIN_SPI2_CLK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_SPI2_CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC --{REG_PIN_SD1_CMD, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD1_CMD, BITS_PIN_DS(4) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD1_CMD --{REG_PIN_SD1_D0, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD1_D0, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD1_D0 --{REG_PIN_SD1_D1, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD1_D1, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD1_D1 --{REG_PIN_SD1_CLK, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD1_CLK, BITS_PIN_DS(4) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD1_CLK --{REG_PIN_SD1_D2, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD1_D2, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD1_D2 --{REG_PIN_SD1_D3, BITS_PIN_AF(0)}, --{REG_MISC_PIN_SD1_D3, BITS_PIN_DS(3) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//WF_SD1_D3 -+{REG_MISC_PIN_SPI2_CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//EXT_GPIO_PG4 -+{REG_PIN_SD1_CMD, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_SD1_CMD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL| BIT_PIN_SLP_OE},//WCN_CHIP_EN -+{REG_PIN_SD1_D0, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_SD1_D0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM1_RSTN -+{REG_PIN_SD1_D1, BITS_PIN_AF(3)}, -+{REG_MISC_PIN_SD1_D1, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM1_FMARK -+{REG_PIN_SD1_CLK, BITS_PIN_AF(1)}, -+{REG_MISC_PIN_SD1_CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//PERST0_N -+{REG_PIN_SD1_D2, BITS_PIN_AF(1)}, -+{REG_MISC_PIN_SD1_D2, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//PCIE3_CLKREQ -+{REG_PIN_SD1_D3, BITS_PIN_AF(1)}, -+{REG_MISC_PIN_SD1_D3, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_IE},//PCIE3_WAKE - {REG_PIN_U5TXD, BITS_PIN_AF(1)}, --{REG_MISC_PIN_U5TXD, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C5_SCL -+{REG_MISC_PIN_U5TXD, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C5_SCL - {REG_PIN_U5RXD, BITS_PIN_AF(1)}, --{REG_MISC_PIN_U5RXD, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C5_SDA -+{REG_MISC_PIN_U5RXD, BITS_PIN_DS(1) | BIT_PIN_WPUS | BIT_PIN_WPU | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPU | BIT_PIN_SLP_Z},//I2C5_SDA - {REG_PIN_CLK_AUX0, BITS_PIN_AF(0)}, - {REG_MISC_PIN_CLK_AUX0, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//WCN_32K_IN - {REG_PIN_U0TXD, BITS_PIN_AF(0)}, -@@ -470,18 +470,18 @@ static struct pinmap_t pinmap[] = { - {REG_MISC_PIN_IIS0CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//BT_PCM_CLK - {REG_PIN_IIS0LRCK, BITS_PIN_AF(0)}, - {REG_MISC_PIN_IIS0LRCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//BT_PCM_SYNC --{REG_PIN_PWMC, BITS_PIN_AF(3)}, --{REG_MISC_PIN_PWMC, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//WF_HOST_WAKE --{REG_PIN_IIS4DO, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS4DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//WB_CHIP_EN -+{REG_PIN_PWMC, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_PWMC, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//EXT_PWM -+{REG_PIN_IIS4DO, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS4DO, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_I2S_SDO /HDMI - {REG_PIN_IIS4DI, BITS_PIN_AF(3)}, - {REG_MISC_PIN_IIS4DI, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//WB_RST --{REG_PIN_IIS4CLK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS4CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//WB_INT --{REG_PIN_IIS4LRCK, BITS_PIN_AF(3)}, --{REG_MISC_PIN_IIS4LRCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_IE},//WF_WAKE_HOST -+{REG_PIN_IIS4CLK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS4CLK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_I2S_CLK -+{REG_PIN_IIS4LRCK, BITS_PIN_AF(0)}, -+{REG_MISC_PIN_IIS4LRCK, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_AP | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//LCM_I2S_WS - {REG_PIN_ESE_GPIO_N, BITS_PIN_AF(0)}, --{REG_MISC_PIN_ESE_GPIO_N, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NFC_CLK_REQ -+{REG_MISC_PIN_ESE_GPIO_N, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_WPD | BIT_PIN_SLP_AP | BIT_PIN_SLP_WPD | BIT_PIN_SLP_Z},//NC - {REG_PIN_U4TXD, BITS_PIN_AF(0)}, - {REG_MISC_PIN_U4TXD, BITS_PIN_DS(1) | BIT_PIN_NULL | BIT_PIN_NUL | BIT_PIN_SLP_CM4 | BIT_PIN_SLP_NUL | BIT_PIN_SLP_OE},//GPS_U1RXD - {REG_PIN_U4RXD, BITS_PIN_AF(0)}, -diff --git a/source/bsp/u-boot22/drivers/video/sprd/dsi/mipi_dsi_api.c b/source/bsp/u-boot22/drivers/video/sprd/dsi/mipi_dsi_api.c -index cb361e6b9b..c27d96f707 100644 ---- a/source/bsp/u-boot22/drivers/video/sprd/dsi/mipi_dsi_api.c -+++ b/source/bsp/u-boot22/drivers/video/sprd/dsi/mipi_dsi_api.c -@@ -231,7 +231,8 @@ int mipi_dsi_dpi_video(struct sprd_dsi *dsi, struct dpi_video_param *param) - dsi_hal_vblk_cmd_trans_limit(dsi, 0x80); - if (!dsi->panel->hporch_lp_disable) - dsi_hal_dpi_hporch_lp_en(dsi, 1); -- dsi_hal_dpi_vporch_lp_en(dsi, 1); -+ dsi_hal_dpi_hporch_lp_en(dsi, 0); -+ dsi_hal_dpi_vporch_lp_en(dsi, 0); - dsi_hal_dpi_hsync_pol(dsi, param->hsync_pol); - dsi_hal_dpi_vsync_pol(dsi, param->vsync_pol); - dsi_hal_dpi_data_en_pol(dsi, param->de_pol); -diff --git a/source/bsp/u-boot22/drivers/video/sprd/sprd_panel.c b/source/bsp/u-boot22/drivers/video/sprd/sprd_panel.c -index a73c23999e..3383794042 100644 ---- a/source/bsp/u-boot22/drivers/video/sprd/sprd_panel.c -+++ b/source/bsp/u-boot22/drivers/video/sprd/sprd_panel.c -@@ -68,6 +68,11 @@ uint32_t load_lcd_id_to_kernel(void) - /* WORKAROUND: to keep the same order with sprdfb_panel.c */ - uint32_t load_lcd_width_to_kernel(void) - { -+ if (panel_drv && panel_drv->info && -+ panel_drv->info->lcd_name && -+ !strcmp(panel_drv->info->lcd_name, "lcd_dummy_mipi_hd")) -+ return panel_drv->info->width; -+ - if (panel_drv && panel_drv->info) - return panel_drv->info->height; - else -@@ -77,6 +82,11 @@ uint32_t load_lcd_width_to_kernel(void) - /* WORKAROUND: to keep the same order with sprdfb_panel.c */ - uint32_t load_lcd_hight_to_kernel(void) - { -+ if (panel_drv && panel_drv->info && -+ panel_drv->info->lcd_name && -+ !strcmp(panel_drv->info->lcd_name, "lcd_dummy_mipi_hd")) -+ return panel_drv->info->height; -+ - if (panel_drv && panel_drv->info) - return panel_drv->info->width; - else -diff --git a/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi b/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -new file mode 100644 ---- a/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -+++ b/source/bsp/u-boot22/arch/arm/dts/lcd/lcd_lt8912b_mipi_hdmi_1080p.dtsi -@@ -0,0 +1,57 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR MIT -+/* -+ * LT8912B MIPI-DSI to HDMI 1080p dummy panel config. -+ */ -+ -+/ { -+ lcds { -+ lcd_dummy_mipi_hd: lcd_dummy_mipi_hd { -+ sprd,dsi-work-mode = <2>; /* video pulse mode */ -+ sprd,dsi-lane-number = <4>; -+ sprd,dsi-color-format = "rgb888"; -+ -+ sprd,phy-bit-clock = <1200000>; /* kbps 921600 1200000 */ -+ sprd,phy-escape-clock = <20000>; /* kHz */ -+ sprd,video-lp-cmd-enable = <0>; -+ sprd,hporch-lp-disable = <1>; -+ sprd,width-mm = <121>; -+ sprd,height-mm = <68>; -+ sprd,esd-check-enable = <0>; -+ sprd,esd-check-mode = <1>; -+ sprd,esd-check-period = <1000>; -+ -+ /* panel interface type: 2:MIPI; 3:SPI */ -+ sprd,panel-if-type = <2>; -+ sprd,power-gpio-delay = <20>; -+ sprd,dsi-switch = <1>; -+ -+ /* -+ * LT8912B is a bridge and has no DCS LCD ID register. -+ * Use a dummy panel id so U-Boot passes this panel to kernel. -+ */ -+ sprd,lcd-id-tokernel = <0xffff>; -+ sprd,reset-on-sequence = <1 5>, <0 5>, <1 5>, <0 5>, <1 20>; -+ sprd,reset-off-sequence = <0 20>; -+ sprd,initial-command = [ -+ ]; -+ sprd,sleep-in-command = [ -+ ]; -+ sprd,sleep-out-command = [ -+ ]; -+ -+ display-timings { -+ timing0 { -+ clock-frequency = <153600000>; -+ hactive = <1920>; -+ vactive = <1080>; -+ hfront-porch = <88>; -+ hsync-len = <44>; -+ hback-porch = <148>; -+ vfront-porch = <56>; -+ vsync-len = <6>; -+ vback-porch = <60>; -+ }; -+ }; -+ }; -+ }; -+}; diff --git a/HDMI/LT8912B/LT8912B Ap note.pdf b/HDMI/LT8912B/LT8912B Ap note.pdf deleted file mode 100644 index a37e3b68d..000000000 Binary files a/HDMI/LT8912B/LT8912B Ap note.pdf and /dev/null differ diff --git a/HDMI/LT8912B/LT8912B PCB layout 建议.txt b/HDMI/LT8912B/LT8912B PCB layout 建议.txt deleted file mode 100644 index c771e47a9..000000000 --- a/HDMI/LT8912B/LT8912B PCB layout 建议.txt +++ /dev/null @@ -1,5 +0,0 @@ - -LT8912B PCB layout建议: -1ã€å·®åˆ†ï¼ˆMIPIã€HDMIã€LVDS）周围40mil的范围ä¸è¦æœ‰åœ°æˆ–ä¿¡å·çº¿ã€æ•·é“œï¼ŒæŽ§åˆ¶å¥½100æ¬§å§†é˜»æŠ—åŒ¹é… -2ã€å·®åˆ†ä¿¡å·å¯¹ï¼ˆMIPIã€HDMIã€LVDS）之间控制三å€çº¿å®½é—´è·ï¼Œä¼´éšGND离差分3å€çº¿å®½é—´è·ï¼Œå¹¶ä¸”在GND线上多打些孔，若空间ä¸å¤Ÿå¯ä»¥ä¸åŠ ä¼´éš -3ã€æ™¶æŒ¯å¸ƒçº¿å°½é‡çŸ­ï¼Œå¯ä»¥å°†å馈电阻放在晶振与IC之间 \ No newline at end of file diff --git a/HDMI/LT8912B/LT8912B 差分走线å‚考.png b/HDMI/LT8912B/LT8912B 差分走线å‚考.png deleted file mode 100644 index 8f049f5a1..000000000 Binary files a/HDMI/LT8912B/LT8912B 差分走线å‚考.png and /dev/null differ diff --git a/HDMI/LT8912B/LT8912B 输入MIPI ä¿¡å·çš„è¦æ±‚.pdf b/HDMI/LT8912B/LT8912B 输入MIPI ä¿¡å·çš„è¦æ±‚.pdf deleted file mode 100644 index aedd6e431..000000000 Binary files a/HDMI/LT8912B/LT8912B 输入MIPI ä¿¡å·çš„è¦æ±‚.pdf and /dev/null differ diff --git a/HDMI/LT8912B/LT8912B_Datasheet_R1.2(1).pdf b/HDMI/LT8912B/LT8912B_Datasheet_R1.2(1).pdf deleted file mode 100644 index 90c988fca..000000000 Binary files a/HDMI/LT8912B/LT8912B_Datasheet_R1.2(1).pdf and /dev/null differ diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0.zip b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0.zip deleted file mode 100644 index b8eb52632..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0.zip +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:7924fbf626c681a754907e7c6393c4823e71aed12b9117d14d01b5838be5092a -size 1062626 diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/Kconfig b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/Kconfig deleted file mode 100755 index 1898ac5c6..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ - -config LT8912B - tristate "LT8912B Driver" - default m - help - Control LT8912B Chip - Select m:build as a separate module; - Select y:Build into the kernel - Select n:Not build diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/Makefile b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/Makefile deleted file mode 100755 index 37fc98c97..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/Makefile +++ /dev/null @@ -1,5 +0,0 @@ - -lt8912b-y := src/LontiumDrv.o src/LT8912B_Main.o src/LT8912B.o src/OcmI2cMaster.o \ - -obj-$(CONFIG_LT8912B) += lt8912b.o - diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/doc/LT8912B Linux Driver Introduction document (English).docx b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/doc/LT8912B Linux Driver Introduction document (English).docx deleted file mode 100755 index b0c4dc6ea..000000000 Binary files a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/doc/LT8912B Linux Driver Introduction document (English).docx and /dev/null differ diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/doc/Makefile b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/doc/Makefile deleted file mode 100755 index 78a24c1c4..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/doc/Makefile +++ /dev/null @@ -1,27 +0,0 @@ - -# 1. Be sure to change KERN_DIR when using a different board kernel -# 2. The kernel in KERN_DIR must be configured and compiled in advance, and the following environment variables must be set in order to compile the kernel: -# 2.1 ARCH, For example: export ARCH=arm64 -# 2.2 CROSS_COMPILE, For example: export CROSS_COMPILE=aarch64-linux-gnu- -# 2.3 PATH, For example: export PATH=$PATH:/home/book/100ask_roc-rk3399-pc/ToolChain-6.3.1/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin -# Note: The above three environment variables may not be the same for different development boards and different compilers. -# For details, see the Advanced user manual of each development board - - -KERN_DIR = /home/ysy/workspace/imx6ull_pro/Imx6ull_source_code/Linux-4.9.88 - -all: - make -C $(KERN_DIR) M=`pwd` modules - -clean: - make -C $(KERN_DIR) M=`pwd` modules clean - rm -rf modules.order - - - -lt8912b-y := src/LontiumDrv.o src/LT8912B_Main.o src/LT8912B.o src/OcmI2cMaster.o \ - - - -obj-m += lt8912b.o - diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/LT8912B.h b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/LT8912B.h deleted file mode 100755 index 8f425d4b6..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/LT8912B.h +++ /dev/null @@ -1,72 +0,0 @@ - -#ifndef _LT8912B_H -#define _LT8912B_H - -#define _1080P_60Hz - -/* output mode */ -#define _hdmi_output -#define _lvds_bypass - -//#define _pattern_test_ - -#define _lane_swap_ //mipi input 3210 -//#define _pn_swap_ //mipi input lane pn swap - -#define dds_debug - -/* lanes */ -#define lane_cnt 0 /*0: 4lane; 1: 1lane; 2: 2lane; 3: 3lane;*/ - - -typedef struct video_timing{ -u16 hfp; -u16 hs; -u16 hbp; -u16 hact; -u16 htotal; -u16 vfp; -u16 vs; -u16 vbp; -u16 vact; -u16 vtotal; -bool h_polarity; -bool v_polarity; -u16 vic; -u8 aspact_ratio; // 0=no data, 1=4:3, 2=16:9, 3=no data. -u32 pclk_khz; -}_video_timing; - -typedef enum -{ - I2S_2CH, - I2S_8CH, - SPDIF -}_Audio_Input_Mode; - -#define Audio_Input_Mode I2S_2CH - -#define AR_ND 0x00 -#define AR_4_3 0x01 -#define AR_16_9 0x02 - -typedef struct panel_parameter -{ - u16 hfp; - u16 hs; - u16 hbp; - u16 hact; - u16 htotal; - u16 vfp; - u16 vs; - u16 vbp; - u16 vact; - u16 vtotal; - u32 pclk_khz; -}_panel_parameter; - -extern void LT8912B_Config(void); - -extern u8 Tx_HPD; - -#endif diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/LT8912B_Main.h b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/LT8912B_Main.h deleted file mode 100755 index dcf87006a..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/LT8912B_Main.h +++ /dev/null @@ -1,5 +0,0 @@ -#ifndef _LT8912B_MAIN_H_ -#define _LT8912B_MAIN_H_ - -extern int LT8912B_Main(void *data); -#endif \ No newline at end of file diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/LontiumDrv.h b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/LontiumDrv.h deleted file mode 100755 index eb74f6147..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/LontiumDrv.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef _LONTIUMDRV_H_ -#define _LONTIUMDRV_H_ - - -struct _lt8912b{ - struct device *dev; - struct mutex ocm_lock; - struct gpio_desc *reset_gpio; - struct gpio_desc *power_gpio; - struct i2c_client *i2c_stu; - struct regmap *chip_regmap; - struct addr_1{ - struct i2c_client *i2c_stu; - struct regmap *regmap; - }*addr_1; - struct addr_2{ - struct i2c_client *i2c_stu; - struct regmap *regmap; - }*addr_2; - -}; - - - -typedef struct -{ - u8 address; - u8 value; -} Chip_Control_Args; - - -extern struct _lt8912b *lt8912b; -extern volatile bool Main_Loop; -extern const char *LOG_FLAG; - -extern u8 addr_1; -extern u8 addr_2; - -#endif diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/OcmI2cMaster.h b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/OcmI2cMaster.h deleted file mode 100755 index 75b0ac612..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/OcmI2cMaster.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _OCMI2CMASTER_H_ -#define _OCMI2CMASTER_H_ - - -extern int HDMI_WriteI2C_Byte(u8 addr,u8 data); -extern int HDMI_ReadI2C_Byte(u8 addr); - -extern u8 I2CADR; - -#endif diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/include.h b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/include.h deleted file mode 100755 index 690f500db..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/include/include.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _INCLUDE_H_ -#define _INCLUDE_H_ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - - -#include "LontiumDrv.h" - -#include "LT8912B_Main.h" -#include "LT8912B.h" - - -#include "OcmI2cMaster.h" - - - - -#endif diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/LT8912B.c b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/LT8912B.c deleted file mode 100755 index abcb9c439..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/LT8912B.c +++ /dev/null @@ -1,749 +0,0 @@ - -#include "../include/include.h" - -u8 Hsync_H_last = 0x00; -u8 Hsync_L_last = 0x00; -u8 Vsync_H_last = 0x00; -u8 Vsync_L_last = 0x00; - -u8 Hsync_L, Hsync_H, Vsync_L, Vsync_H; - - -bool suspend_on = 0; - -u8 Tx_HPD=0; - -// hfp, hs, hbp, hact, htotal, vfp, vs, vbp, vact, vtotal, hfp, hs, hbp, hact, htotal, vfp, vs, vbp, vact, vtotal, h_polary, v_polary, vic, aspact_ratio, pclk_khz -struct video_timing video_640x480_60Hz = {16, 96, 48, 640, 800, 10, 2, 33, 480, 525, 0,0, 1, AR_4_3, 25000}; -struct video_timing video_720x480_60Hz = {16, 62, 60, 720, 858, 9, 6, 30, 480, 525, 0,0, 2, AR_4_3, 27000}; -struct video_timing video_720x576_50Hz = {12, 64, 68, 720, 864, 5, 5, 39, 576, 625, 0,0,17, AR_4_3, 27000}; -struct video_timing video_800x600_60Hz = {48, 128, 88, 800, 1056, 1, 4, 23, 600, 628, 1,1, 0, AR_16_9, 40000}; -struct video_timing video_1024x768_60Hz = {24, 136, 160, 1024, 1344, 3, 6, 29, 768, 806, 0,0, 0, AR_16_9, 65000}; -struct video_timing video_1280x720_60Hz = {110, 40, 220, 1280, 1650, 5, 5, 20, 720, 750, 1,1, 4, AR_16_9, 74250}; -struct video_timing video_1280x800_60Hz = {28, 32, 100, 1280, 1440, 2, 6, 15, 800, 823, 0,0, 0, AR_16_9, 71000}; -struct video_timing video_1920x1080_60Hz = {88, 44, 148, 1920, 2200, 4, 5, 36, 1080, 1125, 1,1,16, AR_16_9, 148500}; - -struct video_timing *video; - - -void DigitalClockEn(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x02,0xf7); - HDMI_WriteI2C_Byte(0x08,0xff); - HDMI_WriteI2C_Byte(0x09,0xff); - HDMI_WriteI2C_Byte(0x0a,0xff); - HDMI_WriteI2C_Byte(0x0b,0x7c); - HDMI_WriteI2C_Byte(0x0c,0xff); -} -void TxAnalog(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x31,0xE1); - HDMI_WriteI2C_Byte(0x32,0xE1); - HDMI_WriteI2C_Byte(0x33,0x0c); //en/disable hdmid output - HDMI_WriteI2C_Byte(0x37,0x00); - HDMI_WriteI2C_Byte(0x38,0x22); - HDMI_WriteI2C_Byte(0x60,0x82); -} - -void CbusAnalog(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x39,0x45); - HDMI_WriteI2C_Byte(0x3a,0x00); //20180719 - HDMI_WriteI2C_Byte(0x3b,0x00); -} - -void HDMIPllAnalog(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x44,0x31); - HDMI_WriteI2C_Byte(0x55,0x44); - HDMI_WriteI2C_Byte(0x57,0x01); - HDMI_WriteI2C_Byte(0x5a,0x02); -} - -void AviInfoframe(struct video_timing *video_format) -{ - u8 VIC = video_format->vic; - u8 AR = video_format->aspact_ratio; - u8 pb0,pb2,pb4,Sync_Polarity; - - I2CADR = 0x94; - HDMI_WriteI2C_Byte(0x3c,0x41); //enable null package - - Sync_Polarity = (video_format->h_polarity*0x02) + (video_format->v_polarity*0x01); - pb2 = (AR<<4) + 0x08; - pb4 = VIC; - pb0 = (((pb2 + pb4) <= 0x5f)?(0x5f - pb2 - pb4):(0x15f - pb2 - pb4)); - - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0xab,Sync_Polarity); //sync polarity - - I2CADR = 0x94; - HDMI_WriteI2C_Byte(0x43,pb0); //PB0:check sum - HDMI_WriteI2C_Byte(0x44,0x10); //PB1:RGB888 - HDMI_WriteI2C_Byte(0x45,pb2); //PB2 - HDMI_WriteI2C_Byte(0x46,0x00); //PB3 - HDMI_WriteI2C_Byte(0x47,pb4); //PB4:vic -} - -void MipiAnalog(void) -{ - I2CADR = 0x90; - #ifdef _pn_swap_ - HDMI_WriteI2C_Byte(0x3e,0xf6); //P/N swap - #else - HDMI_WriteI2C_Byte(0x3e,0xd6); //if mipi pin map follow reference design, no need swap P/N. - #endif - - HDMI_WriteI2C_Byte(0x3f,0xd4);//EQ - HDMI_WriteI2C_Byte(0x41,0x3c);//EQ -} - -void MipiBasicSet(void) -{ - I2CADR = 0x92; - HDMI_WriteI2C_Byte(0x10,0x01); // term en - HDMI_WriteI2C_Byte(0x11,0x10); // settle - //HDMI_WriteI2C_Byte(0x12,0x08); // trail - HDMI_WriteI2C_Byte(0x13,lane_cnt); //00 4 lane //01 1 lane //02 2 lane //03 3lane - HDMI_WriteI2C_Byte(0x14,0x00); //debug mux - - #ifdef _lane_swap_ //for EVB only, if mipi pin map follow reference design, no need swap lane. - HDMI_WriteI2C_Byte(0x15,0xa8); //lane swap:3210 - printk("%s nmipi basic set: lane swap 3210, %d\n",LOG_FLAG,lane_cnt); - #else - HDMI_WriteI2C_Byte(0x15,0x00); //lane swap:0123 - #endif - - HDMI_WriteI2C_Byte(0x1a,0x03); // hshift 3 - HDMI_WriteI2C_Byte(0x1b,0x03); // vshift 3 -} - -void MIPI_Video_Setup(struct video_timing *video_format) -{ - I2CADR = 0x92; - HDMI_WriteI2C_Byte(0x18,(u8)(video_format->hs%256)); // hwidth - HDMI_WriteI2C_Byte(0x19,(u8)(video_format->vs%256)); // vwidth - HDMI_WriteI2C_Byte(0x1c,(u8)(video_format->hact%256)); // H_active[7:0] - HDMI_WriteI2C_Byte(0x1d,(u8)(video_format->hact/256)); // H_active[15:8] - HDMI_WriteI2C_Byte(0x2f,0x0c); // fifo_buff_length 12 - HDMI_WriteI2C_Byte(0x34,(u8)(video_format->htotal%256)); // H_total[7:0] - HDMI_WriteI2C_Byte(0x35,(u8)(video_format->htotal/256)); // H_total[15:8] - HDMI_WriteI2C_Byte(0x36,(u8)(video_format->vtotal%256)); // V_total[7:0] - HDMI_WriteI2C_Byte(0x37,(u8)(video_format->vtotal/256)); // V_total[15:8] - HDMI_WriteI2C_Byte(0x38,(u8)(video_format->vbp%256)); // VBP[7:0] - HDMI_WriteI2C_Byte(0x39,(u8)(video_format->vbp/256)); // VBP[15:8] - HDMI_WriteI2C_Byte(0x3a,(u8)(video_format->vfp%256)); // VFP[7:0] - HDMI_WriteI2C_Byte(0x3b,(u8)(video_format->vfp/256)); // VFP[15:8] - HDMI_WriteI2C_Byte(0x3c,(u8)(video_format->hbp%256)); // HBP[7:0] - HDMI_WriteI2C_Byte(0x3d,(u8)(video_format->hbp/256)); // HBP[15:8] - HDMI_WriteI2C_Byte(0x3e,(u8)(video_format->hfp%256)); // HFP[7:0] - HDMI_WriteI2C_Byte(0x3f,(u8)(video_format->hfp/256)); // HFP[15:8] - video = video_format; -} - -void MIPIRxLogicRes(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x03,0x7f); //mipi rx reset - msleep(10); - HDMI_WriteI2C_Byte(0x03,0xff); - - HDMI_WriteI2C_Byte(0x05,0xfb); //dds reset - msleep(10); - HDMI_WriteI2C_Byte(0x05,0xff); -} - -void DDSConfig(void) -{ - I2CADR = 0x92; - HDMI_WriteI2C_Byte(0x4e,0x93);//strm_sw_freq_word[ 7: 0] - HDMI_WriteI2C_Byte(0x4f,0x3E);//strm_sw_freq_word[15: 8] - HDMI_WriteI2C_Byte(0x50,0x29);//strm_sw_freq_word[23:16] - HDMI_WriteI2C_Byte(0x51,0x80);//[0]=strm_sw_freq_word[24] - HDMI_WriteI2C_Byte(0x1e,0x4f); - HDMI_WriteI2C_Byte(0x1f,0x5e);//full_value 464 - HDMI_WriteI2C_Byte(0x20,0x01); - HDMI_WriteI2C_Byte(0x21,0x2c);//full_value1 416 - HDMI_WriteI2C_Byte(0x22,0x01); - HDMI_WriteI2C_Byte(0x23,0xfa);//full_value2 400 - HDMI_WriteI2C_Byte(0x24,0x00); - HDMI_WriteI2C_Byte(0x25,0xc8);//full_value3 384 - HDMI_WriteI2C_Byte(0x26,0x00); - HDMI_WriteI2C_Byte(0x27,0x5e);//empty_value 464 - HDMI_WriteI2C_Byte(0x28,0x01); - HDMI_WriteI2C_Byte(0x29,0x2c);//empty_value1 416 - HDMI_WriteI2C_Byte(0x2a,0x01); - HDMI_WriteI2C_Byte(0x2b,0xfa);//empty_value2 400 - HDMI_WriteI2C_Byte(0x2c,0x00); - HDMI_WriteI2C_Byte(0x2d,0xc8);//empty_value3 384 - HDMI_WriteI2C_Byte(0x2e,0x00); - HDMI_WriteI2C_Byte(0x42,0x64);//tmr_set[ 7:0]:100us - HDMI_WriteI2C_Byte(0x43,0x00);//tmr_set[15:8]:100us - HDMI_WriteI2C_Byte(0x44,0x04);//timer step - HDMI_WriteI2C_Byte(0x45,0x00); - HDMI_WriteI2C_Byte(0x46,0x59); - HDMI_WriteI2C_Byte(0x47,0x00); - HDMI_WriteI2C_Byte(0x48,0xf2); - HDMI_WriteI2C_Byte(0x49,0x06); - HDMI_WriteI2C_Byte(0x4a,0x00); - HDMI_WriteI2C_Byte(0x4b,0x72); - HDMI_WriteI2C_Byte(0x4c,0x45); - HDMI_WriteI2C_Byte(0x4d,0x00); - HDMI_WriteI2C_Byte(0x52,0x08);// trend step - HDMI_WriteI2C_Byte(0x53,0x00); - HDMI_WriteI2C_Byte(0x54,0xb2); - HDMI_WriteI2C_Byte(0x55,0x00); - HDMI_WriteI2C_Byte(0x56,0xe4); - HDMI_WriteI2C_Byte(0x57,0x0d); - HDMI_WriteI2C_Byte(0x58,0x00); - HDMI_WriteI2C_Byte(0x59,0xe4); - HDMI_WriteI2C_Byte(0x5a,0x8a); - HDMI_WriteI2C_Byte(0x5b,0x00); - HDMI_WriteI2C_Byte(0x5c,0x34); - HDMI_WriteI2C_Byte(0x51,0x00); -} - -void AudioIIsEn(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0xB2,0x01);//DVI mode:0x00; HDMI mode:0x01; - I2CADR = 0x94; - HDMI_WriteI2C_Byte(0x06,0x08); - HDMI_WriteI2C_Byte(0x07,0xF0); - HDMI_WriteI2C_Byte(0x34,0xD2);//0xE2:32FS; 0xD2:64FS - HDMI_WriteI2C_Byte(0x0F,0x2B); -} - -void AudioSpdifEn(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0xB2,0x01); - I2CADR = 0x94; - HDMI_WriteI2C_Byte(0x06,0x0e); - HDMI_WriteI2C_Byte(0x07,0x00); - HDMI_WriteI2C_Byte(0x34,0xD2);//0xE2:32FS; 0xD2:64FS -} - -void Core_Pll_setup(struct panel_parameter *panel) -{ - u8 cpll_m, cpll_k1,cpll_k2; //cpll_k3; - u32 temp; - - temp=(panel->pclk_khz*7)/25; - cpll_m=temp/1000; - - temp=(panel->pclk_khz*7)/25; - temp=temp%1000; - //temp=temp*16.384; - temp=temp*16384/1000; - - cpll_k1=temp%256; - cpll_k2=temp/256; - - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x50,0x24);//cp=50uA - HDMI_WriteI2C_Byte(0x51,0x05);//xtal_clk as reference,second order passive LPF PLL - HDMI_WriteI2C_Byte(0x52,0x14);//use second-order PLL - HDMI_WriteI2C_Byte(0x69,cpll_m);//CP_PRESET_DIV_RATIO - HDMI_WriteI2C_Byte(0x69,(cpll_m|0x80)); - HDMI_WriteI2C_Byte(0x6c,(cpll_k2|0x80));//RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8] - HDMI_WriteI2C_Byte(0x6b,cpll_k1); - - HDMI_WriteI2C_Byte(0x04,0xfb);//core pll reset - HDMI_WriteI2C_Byte(0x04,0xff); -} - -void Core_Pll_bypass(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x50,0x24); //cp=50uA - HDMI_WriteI2C_Byte(0x51,0x2d); //Pix_clk as reference,second order passive LPF PLL - HDMI_WriteI2C_Byte(0x52,0x04); //loopdiv=0;use second-order PLL - HDMI_WriteI2C_Byte(0x69,0x0e); //CP_PRESET_DIV_RATIO - HDMI_WriteI2C_Byte(0x69,0x8e); - HDMI_WriteI2C_Byte(0x6a,0x00); - HDMI_WriteI2C_Byte(0x6c,0xb8); //RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8] - HDMI_WriteI2C_Byte(0x6b,0x51); - - HDMI_WriteI2C_Byte(0x04,0xfb); //core pll reset - HDMI_WriteI2C_Byte(0x04,0xff); -} - -void Lvds_Pll_Reset(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x02,0xf7); //lvds pll reset - HDMI_WriteI2C_Byte(0x02,0xff); -} - - -void Scaler_bypass(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x7f,0x00);//disable scaler - HDMI_WriteI2C_Byte(0xa8,0x13); -} - -void Scaler_setup(struct video_timing *input_video,struct panel_parameter *panel) -{ - //for example: 720P to 1280x800 - //These register base on MIPI resolution and LVDS panel resolution. - u32 h_ratio,v_ratio; - u8 i; - u32 htotal; -// h_ratio = input_video->hact*4096.00/panel->hact; -// v_ratio = input_video->vact*4096.00/panel->vact; - h_ratio = input_video->hact*4096/panel->hact; - v_ratio = input_video->vact*4096/panel->vact; - - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x80,0x00); - HDMI_WriteI2C_Byte(0x81,0xff); - HDMI_WriteI2C_Byte(0x82,0x03); - HDMI_WriteI2C_Byte(0x83,(u8)(input_video->hact%256)); - HDMI_WriteI2C_Byte(0x84,(u8)(input_video->hact/256)); - HDMI_WriteI2C_Byte(0x85,0x80); - HDMI_WriteI2C_Byte(0x86,0x10); - HDMI_WriteI2C_Byte(0x87,(u8)(panel->htotal%256)); - HDMI_WriteI2C_Byte(0x88,(u8)(panel->htotal/256)); - HDMI_WriteI2C_Byte(0x89,(u8)(panel->hs%256)); - HDMI_WriteI2C_Byte(0x8a,(u8)(panel->hbp%256)); - HDMI_WriteI2C_Byte(0x8b,(u8)(panel->vs%256)); - HDMI_WriteI2C_Byte(0x8c,(u8)(panel->hact%256)); - HDMI_WriteI2C_Byte(0x8d,(u8)(panel->vact%256)); - HDMI_WriteI2C_Byte(0x8e,(u8)(panel->vact/256)*16+(panel->hact/256)); - HDMI_WriteI2C_Byte(0x8f,(u8)(h_ratio%256)); - HDMI_WriteI2C_Byte(0x90,(u8)(h_ratio/256)); - HDMI_WriteI2C_Byte(0x91,(u8)(v_ratio%256)); - HDMI_WriteI2C_Byte(0x92,(u8)(v_ratio/256)); - HDMI_WriteI2C_Byte(0x7f,0x96); - //HDMI_WriteI2C_Byte(0x7f,0xb0); - //HDMI_WriteI2C_Byte(0xa8,0x3b); - HDMI_WriteI2C_Byte(0xa8,0x13); - - HDMI_WriteI2C_Byte(0x02,0xf7);//lvds pll reset - HDMI_WriteI2C_Byte(0x02,0xff); - - HDMI_WriteI2C_Byte(0x03,0xcf);//scaler reset - HDMI_WriteI2C_Byte(0x03,0xff); - - HDMI_WriteI2C_Byte(0x7f,0xb0); - - for(i = 0; i < 300; i++) - { - if(HDMI_ReadI2C_Byte(0xa7)&0x20) - { - htotal = (HDMI_ReadI2C_Byte(0xa7)&0x0f)*0x100 + HDMI_ReadI2C_Byte(0xa6); - printk("%s scaler setup htotal = %d.\n",LOG_FLAG,htotal); - - break; - //please set "htotal" to panel_parameter's htotal. - } - printk("%s scaler loop = %d\n",LOG_FLAG, i); - msleep(100); - } -} -void LvdsPowerUp(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x44,0x30); - HDMI_WriteI2C_Byte(0x51,0x05); -} -void LvdsPowerDown(void) -{ - I2CADR = 0x90; - //HDMI_WriteI2C_Byte(0x44,0x31); - HDMI_WriteI2C_Byte(0x51,0x15); // - //HDMI_WriteI2C_Byte(0x03,0xfb); -} - -void LvdsBypass(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x50,0x24); //cp=50uA - HDMI_WriteI2C_Byte(0x51,0x2d); //Pix_clk as reference,second order passive LPF PLL - HDMI_WriteI2C_Byte(0x52,0x04); //loopdiv=0;use second-order PLL - HDMI_WriteI2C_Byte(0x69,0x0e); //CP_PRESET_DIV_RATIO - HDMI_WriteI2C_Byte(0x69,0x8e); - HDMI_WriteI2C_Byte(0x6a,0x00); - HDMI_WriteI2C_Byte(0x6c,0xb8); //RGD_CP_SOFT_K_EN,RGD_CP_SOFT_K[13:8] - HDMI_WriteI2C_Byte(0x6b,0x51); - - HDMI_WriteI2C_Byte(0x04,0xfb); //core pll reset - HDMI_WriteI2C_Byte(0x04,0xff); - - HDMI_WriteI2C_Byte(0x7f,0x00); //disable scaler - HDMI_WriteI2C_Byte(0xa8,0x13); //0x13:VSEA ; 0x33:JEIDA; -} - -void LvdsOutput(bool on) -{ - if(on) - { - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x02,0xf7); //lvds pll reset - HDMI_WriteI2C_Byte(0x02,0xff); //scaler module reset - HDMI_WriteI2C_Byte(0x03,0xcb); //lvds tx module reset - HDMI_WriteI2C_Byte(0x03,0xfb); - HDMI_WriteI2C_Byte(0x03,0xff); - HDMI_WriteI2C_Byte(0x44,0x30); //enbale lvds output - printk("%s LT8912_lvds_output_enable!\n",LOG_FLAG); - - }else{ - - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x44,0x31); - } -} - - -void HdmiOutput(bool on) -{ - if(on) - { - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x33,0x0e); //enable hdmi output - printk("%s HDMI output Enable.\n",LOG_FLAG); - } - else - { - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x33,0x0c); //disable hdmi output - printk("%s HDMI output Disable.\n",LOG_FLAG); - } -} - - -void LvdsScalerResult(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x7f,0xb0); -} - - -void ScalerReset(void) -{ - I2CADR = 0x90; - HDMI_WriteI2C_Byte(0x03,0xcf); - HDMI_WriteI2C_Byte(0x03,0xff); -} - - -void lt8912_check_dds(void) -{ - u8 reg_920c, reg_920d, reg_920e, reg_920f; - u8 i; - for(i = 0; i < 10; i++) - { - I2CADR = 0x92; - reg_920c = HDMI_ReadI2C_Byte(0x0c); - reg_920d = HDMI_ReadI2C_Byte(0x0d); - reg_920e = HDMI_ReadI2C_Byte(0x0e); - reg_920f = HDMI_ReadI2C_Byte(0x0f); - printk("%s 0x0c~0f = %02x, %02x, %02x\n",LOG_FLAG,reg_920c, reg_920d, reg_920e); -// if((reg_920e == 0xd2)&&(reg_920d < 0xff)&&(reg_920d > 0xd0)) //shall update threshold here base on actual dds result. -// { -// printk("%s lvds_check_dds: stable!\n",LOG_FLAG); -// break; -// } - - msleep(500); - } -} - -void lvds_output_cfg(void) -{ - LvdsPowerUp(); - #ifdef _lvds_bypass - LvdsBypass(); - #else - //Core_Pll_setup(&AA070M0C1); - Core_Pll_setup(&KD101FM_1_C001A); - Scaler_setup(&video_1280x720_60Hz,&KD101FM_1_C001A); - #endif -} - -void MIPI_Input_det(void) -{ - I2CADR = 0x90; - Hsync_L = HDMI_ReadI2C_Byte(0x9c); - Hsync_H = HDMI_ReadI2C_Byte(0x9d); - Vsync_L = HDMI_ReadI2C_Byte(0x9e); - Vsync_H = HDMI_ReadI2C_Byte(0x9f); - - if((Hsync_H!=Hsync_H_last)||(Vsync_H!=Vsync_H_last)) /*hiht byte changed*/ - { - printk("%s 0x9c~9f = %x, %x, %x, %x.\n", LOG_FLAG,Hsync_H, Hsync_L,Vsync_H, Vsync_L); - - if(Vsync_H==0x02 && Vsync_L <= 0xef&&Vsync_L >= 0xec)//0x2EE - { - video = &video_1280x720_60Hz; - printk("%s videoformat = VESA_1280x720_60\n",LOG_FLAG); - } - else if(Vsync_H == 0x03 && Vsync_L <= 0x3a &&Vsync_L >= 0x34)//0x337 - { - video = &video_1280x800_60Hz; - printk("%s videoformat = VESA_1280x800_60\n",LOG_FLAG); - } - else if(Vsync_H == 0x04 && Vsync_L <= 0x67&&Vsync_L >= 0x63)//0x465 - { - video = &video_1920x1080_60Hz; - printk("%s videoformat = VESA_1920x1080_60\n",LOG_FLAG); - } - else - { - printk("%s videoformat = video_none\n",LOG_FLAG); - } - - Hsync_L_last = Hsync_L; - Hsync_H_last = Hsync_H; - Vsync_L_last = Vsync_L; - Vsync_H_last = Vsync_H; - - MIPI_Video_Setup(video); - AviInfoframe(video); - MIPIRxLogicRes(); - } - -} - - -//void dds_clock_debug(void) -//{ -// #ifdef dds_debug -// u8 reg_920c, reg_920d, reg_920e, reg_920f; -// -// while(1) -// { -// I2CADR = 0x92; -// reg_920c = HDMI_ReadI2C_Byte(0x0c); -// reg_920d = HDMI_ReadI2C_Byte(0x0d); -// reg_920e = HDMI_ReadI2C_Byte(0x0e); -// reg_920f = HDMI_ReadI2C_Byte(0x0f); -// -// printk("\r\n0x0c~0e = %02x, %02x, %02x",reg_920c, reg_920d, reg_920e); -// printk("\r\nEnter the dds_clock_debug cycle"); -// -// msleep(1000); -// } -// #endif -//} - -void pattern_test(void) -{ - u32 DDS_initial_value; - u8 pclk_Mhz; - -// video = &video_640x480_60Hz; -// video = &video_720x480_60Hz; -// video = &video_800x600_60Hz; -// video = &video_1280x720_60Hz; -// video = &video_1280x800_60Hz; - video = &video_1920x1080_60Hz; - - DigitalClockEn(); - TxAnalog(); - CbusAnalog(); - HDMIPllAnalog(); - AudioIIsEn(); - AviInfoframe(video); - lvds_output_cfg(); - - I2CADR = 0x92; - //////////////////Pattern resolution set//////////////////// - HDMI_WriteI2C_Byte(0x72,0x12); - HDMI_WriteI2C_Byte(0x73,(u8)((video->hs+video->hbp)%256)); //RGD_PTN_DE_DLY[7:0] - HDMI_WriteI2C_Byte(0x74,(u8)((video->hs+video->hbp)/256)); //RGD_PTN_DE_DLY[11:8] - HDMI_WriteI2C_Byte(0x75,(u8)((video->vs+video->vbp)%256)); //RGD_PTN_DE_TOP[6:0] - HDMI_WriteI2C_Byte(0x76,(u8)(video->hact%256)); //RGD_PTN_DE_CNT[7:0] - HDMI_WriteI2C_Byte(0x77,(u8)(video->vact%256)); //RGD_PTN_DE_LIN[7:0] - HDMI_WriteI2C_Byte(0x78,((((u8)(video->vact/256))<<4)+((u8)(video->hact/256)))); //RGD_PTN_DE_LIN[10:8],RGD_PTN_DE_CNT[11:8] - HDMI_WriteI2C_Byte(0x79,(u8)(video->htotal%256)); //RGD_PTN_H_TOTAL[7:0] - HDMI_WriteI2C_Byte(0x7a,(u8)(video->vtotal%256)); //RGD_PTN_V_TOTAL[7:0] - HDMI_WriteI2C_Byte(0x7b,((((u8)(video->vtotal/256))<<4)+((u8)(video->htotal/256)))); //RGD_PTN_V_TOTAL[10:8],RGD_PTN_H_TOTAL[11:8] - HDMI_WriteI2C_Byte(0x7c,(u8)(video->hs%256)); //RGD_PTN_HWIDTH[7:0] - HDMI_WriteI2C_Byte(0x7d,((((u8)(video->hs/256))<<6)+((u8)(video->vs%256)))); //RGD_PTN_HWIDTH[9:8],RGD_PTN_VWIDTH[5:0] - HDMI_WriteI2C_Byte(0x70,0x80); //pattern enable - HDMI_WriteI2C_Byte(0x71,0x51); - HDMI_WriteI2C_Byte(0x42,0x12); - /////////////////////////////////////////////////////////// - - HDMI_WriteI2C_Byte(0x1e,0x67); //h v d pol hdmi sel pll sel - - //////////////////pattern pixl clock set/////////////////// - pclk_Mhz = (u8)(video->pclk_khz/1000); - DDS_initial_value = (u32)(pclk_Mhz*0x16C16); - HDMI_WriteI2C_Byte(0x4e,(u8)(DDS_initial_value&0x000000ff)); //strm_sw_freq_word[ 7: 0] - HDMI_WriteI2C_Byte(0x4f,(u8)((DDS_initial_value&0x0000ff00)>>8)); //strm_sw_freq_word[15: 8] - HDMI_WriteI2C_Byte(0x50,(u8)((DDS_initial_value&0x00ff0000)>>16)); //strm_sw_freq_word[23:16] - HDMI_WriteI2C_Byte(0x51,0x80); - -// HDMI_WriteI2C_Byte(0x4e,0x3E); //strm_sw_freq_word[ 7: 0] -// HDMI_WriteI2C_Byte(0x4f,0xE9); //strm_sw_freq_word[15: 8] -// HDMI_WriteI2C_Byte(0x50,0xD3); //strm_sw_freq_word[23:16] -// HDMI_WriteI2C_Byte(0x51,0x80); //pattern en - /////////////////////////////////////////////////////////// - - HdmiOutput(1); - LvdsOutput(1); -} - - -u8 LT8912_Get_HPD(void) -{ - //(0x90)0xc1[bit7] description HPD is High or Low - I2CADR = 0x90; - if((HDMI_ReadI2C_Byte(0xc1)&0x80)==0x80) - { - printk("%s LT8912_Get_HPD: high\n",LOG_FLAG); - return 1; - } - else - { - printk("%s LT8912_Get_HPD: low\n",LOG_FLAG); - return 0; - } -} - -void LT8912B_chip_ID(void) -{ - I2CADR=0x90; - printk("%s chip ID: 0x%x, 0x%x\n",LOG_FLAG,HDMI_ReadI2C_Byte(0x00), HDMI_ReadI2C_Byte(0x01)); -} - - -void LT8912B_Suspend(bool on) -{ - //9mA,HPD detect is normal. - if(on) - { - if(!suspend_on) - { - // enter suspend mode - I2CADR = 0x90; - HDMI_WriteI2C_Byte( 0x54, 0x1d ); - HDMI_WriteI2C_Byte( 0x51, 0x15 ); - HDMI_WriteI2C_Byte( 0x44, 0x31 ); - HDMI_WriteI2C_Byte( 0x41, 0xbd ); - HDMI_WriteI2C_Byte( 0x5c, 0x11 ); - suspend_on = 1; - printk("%s suspend on.\n",LOG_FLAG); - } - - }else{ - - if(suspend_on) - { - //exist suspend mode - I2CADR = 0x90; - HDMI_WriteI2C_Byte( 0x5c, 0x10 ); - HDMI_WriteI2C_Byte( 0x54, 0x1c ); - HDMI_WriteI2C_Byte( 0x51, 0x2d ); - HDMI_WriteI2C_Byte( 0x44, 0x30 ); - HDMI_WriteI2C_Byte( 0x41, 0xbc ); - - msleep(10); - HDMI_WriteI2C_Byte(0x03,0x7f); - msleep(10); - HDMI_WriteI2C_Byte(0x03,0xff); - - HDMI_WriteI2C_Byte(0x05,0xfb); - msleep(10); - HDMI_WriteI2C_Byte(0x05,0xff); - suspend_on = 0; - printk("%s suspend off.\n",LOG_FLAG); - } - } -} - - -void LT8912B_Config(void) -{ - LT8912B_chip_ID(); - - #ifdef _pattern_test_ - pattern_test(); - while(Main_Loop); - #else - DigitalClockEn(); - TxAnalog(); - CbusAnalog(); - HDMIPllAnalog(); - MipiAnalog(); - MipiBasicSet(); - DDSConfig(); - MIPI_Video_Setup(&video_1920x1080_60Hz); - MIPI_Input_det(); - AudioIIsEn(); - - - #ifdef dds_debug - lt8912_check_dds(); // can be removed when debug stage. - #endif - - #ifdef _lvds_bypass - lvds_output_cfg(); - LvdsOutput(1); - #endif - -///////////////////////////////////////////////////////////// test use -// HdmiOutput(1); -// while(1); -///////////////////////////////////////////////////////////// - - #ifdef _hdmi_output - if(LT8912_Get_HPD()) - { - if(!Tx_HPD) - { - HdmiOutput(1); - Tx_HPD = 1; - printk("%s LT8912_Get_HPD: high\n",LOG_FLAG); - } - - }else{ - - if(Tx_HPD) - { - LT8912B_Suspend(1); - printk("%s LT8912 Suspend!\n",LOG_FLAG); - HdmiOutput(0); - Tx_HPD = 0; - printk("%s LT8912_Get_HPD: low\n",LOG_FLAG); - } - } - #endif - - #endif - - while(Main_Loop) - { - MIPI_Input_det(); - msleep(300); - - #ifdef _hdmi_output - if(LT8912_Get_HPD()) - { - if(!Tx_HPD) - { - LT8912B_Suspend(0); - HdmiOutput(1); - Tx_HPD = 1; - } - - }else{ - - if(Tx_HPD) - { - LT8912B_Suspend(1); - HdmiOutput(0); - Tx_HPD = 0; - } - } - #endif - } -} diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/LT8912B_Main.c b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/LT8912B_Main.c deleted file mode 100755 index 53a85b125..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/LT8912B_Main.c +++ /dev/null @@ -1,35 +0,0 @@ -#include "../include/include.h" - - -void LT8912B_Power_On(void) -{ - gpiod_set_value(lt8912b->power_gpio,1); - msleep(5); - printk("%s Set power High level.\n ",LOG_FLAG); - -} - -void LT8912B_Reset(void) -{ - //complete chip reset logic - gpiod_set_value(lt8912b->reset_gpio,1); - msleep(5); - gpiod_set_value(lt8912b->reset_gpio,0); - msleep(5); - gpiod_set_value(lt8912b->reset_gpio,1); - msleep(100); - printk("%s Reset chip.\n",LOG_FLAG); -} - - -int LT8912B_Main(void *data) -{ - printk("%s Init Start!\n",LOG_FLAG); - LT8912B_Power_On(); - LT8912B_Reset(); - LT8912B_Config(); - - Tx_HPD = 0; - - return 0; -} diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/LontiumDrv.c b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/LontiumDrv.c deleted file mode 100755 index dabd39db0..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/LontiumDrv.c +++ /dev/null @@ -1,385 +0,0 @@ -#include "../include/include.h" - - -struct _lt8912b *lt8912b; -static struct task_struct *kthread_obj; -volatile bool Main_Loop=true; -char *ChipName = "lt8912b"; //Define Lontium Chip Name -static int major = 0; -static struct cdev chip_cdev; -static struct class *chip_class; -const char *LOG_FLAG = "LT8912B"; - -u8 I2CADR; -u8 addr_1_value = 0x00; -u8 addr_2_value = 0x00; - - -static int chip_open(struct inode *inode, struct file *filp) -{ - printk("chip open\n"); - return 0; -} - - -static int chip_close (struct inode *node, struct file *file) -{ - printk("chip close\n"); - return 0; -} - - -static ssize_t chip_read(struct file *filp, char __user *buf, size_t cnt, loff_t *offt) -{ - Chip_Control_Args parameter; - - if (copy_from_user(¶meter, buf, sizeof(parameter))) { - return -EFAULT; - } - - parameter.value = HDMI_ReadI2C_Byte(parameter.address); - - if (copy_to_user(buf, ¶meter, sizeof(parameter))) { - return -EFAULT; - } - - return sizeof(parameter); - -} - -static ssize_t chip_write(struct file *filp, const char __user *buf, size_t cnt, loff_t *offt) -{ - Chip_Control_Args parameter; - - if (copy_from_user(¶meter, buf, sizeof(parameter))) { - return -EFAULT; - } - - HDMI_WriteI2C_Byte(parameter.address, parameter.value); - - return sizeof(parameter); - -} - - - - -static struct file_operations chip_drv = { - .owner = THIS_MODULE, - .open = chip_open, - .release = chip_close, - .read = chip_read, - .write = chip_write, -}; - - - -static int chip_dev_init(void) -{ - int ret; - dev_t devid; - - ret = alloc_chrdev_region(&devid, 0, 1, ChipName); - if (ret < 0) { - return ret; - } - - major = MAJOR(devid); - cdev_init(&chip_cdev, &chip_drv); - cdev_add(&chip_cdev, devid, 1); - chip_class = class_create(THIS_MODULE, "chip_class"); - if (IS_ERR(chip_class)) { - unregister_chrdev(major, ChipName); - return -1; - } - - device_create(chip_class, NULL, MKDEV(major, 0), NULL, ChipName); /* /dev/ChipName */ - - return 0; -} - - -static void chip_dev_exit(void) -{ - device_destroy(chip_class, MKDEV(major, 0)); - class_destroy(chip_class); - cdev_del(&chip_cdev); - unregister_chrdev_region(MKDEV(major,0), 1); -} - - - -static const struct regmap_range chip_ranges[] = { - { .range_min = 0, .range_max = 0xffff }, -}; - -static const struct regmap_access_table chip_table = { - .yes_ranges = chip_ranges, - .n_yes_ranges = ARRAY_SIZE(chip_ranges), -}; - -static const struct regmap_config chip_regmap_config = { - .reg_bits = 8, - .val_bits = 8, - .volatile_table = &chip_table, - .cache_type = REGCACHE_NONE, -}; - - - -static int chip_parse_dts(struct device *dev) -{ - - /* - * devm_gpiod_get_optional - If this fails, NULL is returned and no error pointer. - * - * devm_gpiod_get - If this fails, an error pointer is returned, usually ERR_PTR(-ENOENT). - * - * The devm_gpiod_get function is recommended for practical use. - */ - - - //Gets the handle to power gpio in dts - - lt8912b->power_gpio=devm_gpiod_get_optional(dev, "power", GPIOD_OUT_HIGH); - if (IS_ERR(lt8912b->power_gpio)) { - dev_err(dev, "Failed to get power GPIO\n"); - return PTR_ERR(lt8912b->power_gpio); - } - - - //Gets the handle to reset gpio in dts - - lt8912b->reset_gpio=devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); - if (IS_ERR(lt8912b->reset_gpio)) { - dev_err(dev, "Failed to get reset GPIO\n"); - return PTR_ERR(lt8912b->reset_gpio); - } - - - // Additional GPIO pins can be added here if needed - - return 0; -} - - -static int chip_probe(struct i2c_client *client, const struct i2c_device_id *id) -{ - struct i2c_board_info addr_1_board_info = { - I2C_BOARD_INFO("lt8912b_addr_1", addr_1_value), - }; - struct i2c_board_info addr_2_board_info = { - I2C_BOARD_INFO("lt8912b_addr_2", addr_2_value), - }; - struct device_node *np = client->dev.of_node; - struct device_node *addr_1_node; - struct device_node *addr_2_node; - int ret; - - if (!np) { - dev_err(&client->dev, "Device tree node missing"); - return -EINVAL; - } - - chip_dev_init(); - - lt8912b = devm_kzalloc(&client->dev, sizeof(*lt8912b), GFP_KERNEL); - if (lt8912b == NULL) - return -ENOMEM; - - lt8912b->i2c_stu = client; - - lt8912b->dev = &client->dev; - - //////////////////////////////////////////////// - //addr_0 - - lt8912b->chip_regmap = devm_regmap_init_i2c(client, &chip_regmap_config); - if (IS_ERR(lt8912b->chip_regmap)) { - dev_err(&client->dev, "Failed to initialize regmap\n"); - return PTR_ERR(lt8912b->chip_regmap); - } - - //////////////////////////////////////////////// - - ///////////////////////////////////////////////// - //addr_1 - - addr_1_node = of_get_child_by_name(np, "lt8912b_addr_1"); - if (!addr_1_node) { - dev_err(&client->dev, "Failed to find lt8912b_addr_1 node"); - return -EINVAL; - } - - lt8912b->addr_1 = devm_kzalloc(&client->dev, sizeof(struct addr_1), GFP_KERNEL); - if (!lt8912b->addr_1) - return -ENOMEM; - - if (of_property_read_u8(addr_1_node, "addr_1_reg", &addr_1_value)) { - dev_err(&client->dev, "Failed to get addr_1_reg address"); - return -EINVAL; - } - addr_1_board_info.addr =addr_1_value; - - lt8912b->addr_1->i2c_stu = i2c_new_device(client->adapter, &addr_1_board_info); - if (!lt8912b->addr_1->i2c_stu) { - dev_err(&client->dev, "Failed to create I2C client for addr_1"); - return -ENODEV; - } - - lt8912b->addr_1->regmap = devm_regmap_init_i2c(lt8912b->addr_1->i2c_stu, &chip_regmap_config); - if (IS_ERR(lt8912b->addr_1->regmap)) { - dev_err(&client->dev, "Failed to initialize addr_1 regmap"); - i2c_unregister_device(lt8912b->addr_1->i2c_stu); - return PTR_ERR(lt8912b->addr_1->regmap); - } - - /////////////////////////////////////////////////// - - ///////////////////////////////////////////////// - //addr_2 - - addr_2_node = of_get_child_by_name(np, "lt8912b_addr_2"); - if (!addr_2_node) { - dev_err(&client->dev, "Failed to find lt8912b_addr_2 node"); - return -EINVAL; - } - - lt8912b->addr_2 = devm_kzalloc(&client->dev, sizeof(struct addr_2), GFP_KERNEL); - if (!lt8912b->addr_2) - return -ENOMEM; - - if (of_property_read_u8(addr_2_node, "addr_2_reg", &addr_2_value)) { - dev_err(&client->dev, "Failed to get addr_2_reg address"); - return -EINVAL; - } - addr_2_board_info.addr =addr_2_value; - - lt8912b->addr_2->i2c_stu = i2c_new_device(client->adapter, &addr_2_board_info); - if (!lt8912b->addr_2->i2c_stu) { - dev_err(&client->dev, "Failed to create I2C client for addr_2"); - return -ENODEV; - } - - lt8912b->addr_2->regmap = devm_regmap_init_i2c(lt8912b->addr_2->i2c_stu, &chip_regmap_config); - if (IS_ERR(lt8912b->addr_2->regmap)) { - dev_err(&client->dev, "Failed to initialize addr_2 regmap"); - i2c_unregister_device(lt8912b->addr_2->i2c_stu); - return PTR_ERR(lt8912b->addr_2->regmap); - } - /////////////////////////////////////////////////// - - mutex_init(<8912b->ocm_lock); - - ret = chip_parse_dts(lt8912b->dev); - if (ret<0){ - dev_err(&client->dev, "Failed to parse device tree\n"); - return ret; - } - - i2c_set_clientdata(client, lt8912b); - - - kthread_obj = kthread_run(LT8912B_Main, NULL, "LT8912B_kthread"); - if (IS_ERR(kthread_obj)) { - dev_err(&client->dev, "Failed to create kernel thread\n"); - return PTR_ERR(kthread_obj); - } - - return 0; - -} - -static int chip_remove(struct i2c_client *client) -{ - - Main_Loop = false; - msleep(500); - - mutex_destroy(<8912b->ocm_lock); - - i2c_unregister_device(lt8912b->addr_1->i2c_stu); - - i2c_unregister_device(lt8912b->addr_2->i2c_stu); - - chip_dev_exit(); - - printk("driver removed\n"); - return 0; -} - - -static int chip_suspend(struct device *dev) -{ - - printk(KERN_INFO "%s Suspend.\n",LOG_FLAG); - - gpiod_set_value(lt8912b->reset_gpio,0); - msleep(10); - - Main_Loop =false; - - return 0; -} - - - -static int chip_resume(struct device *dev) -{ - - printk(KERN_INFO "%s Resume.\n",LOG_FLAG); - - - gpiod_set_value(lt8912b->reset_gpio,1); - msleep(5); - - Main_Loop = true; - msleep(5); - - kthread_obj = kthread_run(LT8912B_Main, NULL, "LT8912B_kthread"); - - return 0; -} - - -static const struct dev_pm_ops chip_pm_ops = { - .suspend = chip_suspend, - .resume = chip_resume, -}; - - - - -static const struct i2c_device_id chip_ids[] = { - {"lt8912b", 0}, - { } -}; -MODULE_DEVICE_TABLE(i2c, chip_ids); - - -static const struct of_device_id chip_id_table[] = { - {.compatible = "lontium,lt8912b"}, - { } -}; -MODULE_DEVICE_TABLE(of, chip_id_table); - - -static struct i2c_driver chip_driver = { - .driver = { - .owner = THIS_MODULE, - .name = "lt8912b", - .pm = &chip_pm_ops, - .of_match_table = chip_id_table, - - }, - .probe = chip_probe, - .remove = chip_remove, - .id_table = chip_ids, -}; - - -module_i2c_driver(chip_driver); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("LT8912B driver"); -MODULE_AUTHOR("Tony Yang"); diff --git a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/OcmI2cMaster.c b/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/OcmI2cMaster.c deleted file mode 100755 index 22ff41e60..000000000 --- a/HDMI/LT8912B/LT8912B_Linux_Driver_v1.0/src/OcmI2cMaster.c +++ /dev/null @@ -1,91 +0,0 @@ -#include "../include/include.h" - - - - - -int HDMI_WriteI2C_Byte(u8 addr,u8 data) -{ - int ret = 0; - mutex_lock(<8912b->ocm_lock); - - if(I2CADR==0x90) - { - ret = regmap_write(lt8912b->chip_regmap, addr, data); - if (ret < 0) { - printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d", - lt8912b->i2c_stu->addr, addr, data, ret); - mutex_unlock(<8912b->ocm_lock); - return ret; - } - }else if(I2CADR==0x92){ - ret = regmap_write(lt8912b->addr_1->regmap, addr, data); - if (ret < 0) { - printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d", - lt8912b->addr_1->i2c_stu->addr, addr, data, ret); - mutex_unlock(<8912b->ocm_lock); - return ret; - } - - }else if(I2CADR==0x94){ - ret = regmap_write(lt8912b->addr_2->regmap, addr, data); - if (ret < 0) { - printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d", - lt8912b->addr_2->i2c_stu->addr, addr, data, ret); - mutex_unlock(<8912b->ocm_lock); - return ret; - } - } - - mutex_unlock(<8912b->ocm_lock); - return 0; -} - - - - - -int HDMI_ReadI2C_Byte(u8 addr) -{ - int ret = 0; - unsigned int val = 0; - mutex_lock(<8912b->ocm_lock); - - if(I2CADR==0x90){ - - ret = regmap_read(lt8912b->chip_regmap, addr, &val); - if (ret < 0) { - printk("regmap_read error: (0x%02x 0x%02x) %d", - lt8912b->i2c_stu->addr, addr, ret); - mutex_unlock(<8912b->ocm_lock); - return ret; - } - }else if(I2CADR==0x92){ - - ret = regmap_read(lt8912b->addr_1->regmap, addr, &val); - if (ret < 0) { - printk("regmap_read error: (0x%02x 0x%02x) %d", - lt8912b->addr_1->i2c_stu->addr, addr, ret); - mutex_unlock(<8912b->ocm_lock); - return ret; - } - - }else if(I2CADR==0x94){ - - ret = regmap_read(lt8912b->addr_2->regmap, addr, &val); - if (ret < 0) { - printk("regmap_read error: (0x%02x 0x%02x) %d", - lt8912b->addr_2->i2c_stu->addr, addr, ret); - mutex_unlock(<8912b->ocm_lock); - return ret; - } - - } - - mutex_unlock(<8912b->ocm_lock); - return (u8)val; -} - - -EXPORT_SYMBOL(HDMI_WriteI2C_Byte); -EXPORT_SYMBOL(HDMI_ReadI2C_Byte); diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003.rar b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003.rar deleted file mode 100644 index 353894317..000000000 Binary files a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003.rar and /dev/null differ diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/Backup of Backup of Backup of LT8912B.CF3 b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/Backup of Backup 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a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/LT8912B.SearchResults b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/LT8912B.SearchResults deleted file mode 100644 index ea1f8d062..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/LT8912B.SearchResults +++ /dev/null @@ -1,4 +0,0 @@ ----- _LVDS_Bypass_ Matches (3 in 3 files) ---- -LT8912B.c (src):#ifdef _LVDS_Bypass_ -Main.c:#ifdef _LVDS_Bypass_ -Main.h (inc)://#define _LVDS_Bypass_ diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/LT8912B.WK3 b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/LT8912B.WK3 deleted file mode 100644 index e21ec18b6..000000000 Binary files a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/LT8912B.WK3 and /dev/null differ diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/TAGS.txt b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/TAGS.txt deleted file mode 100644 index fc6083ce2..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/TAGS.txt +++ /dev/null @@ -1,2013 +0,0 @@ -!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ -!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ -!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/ -!_TAG_PROGRAM_NAME Exuberant Ctags // -!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ -!_TAG_PROGRAM_VERSION 5.8 // -ADC1 inc\stm8s.h 2389;" macro -ADC1_AWCRH_RESET_VALUE inc\stm8s.h 191;" macro -ADC1_AWCRL_RESET_VALUE inc\stm8s.h 192;" macro -ADC1_BaseAddress inc\stm8s.h 2371;" macro -ADC1_CR1_ADON inc\stm8s.h 210;" macro -ADC1_CR1_CONT inc\stm8s.h 209;" macro -ADC1_CR1_RESET_VALUE inc\stm8s.h 182;" macro -ADC1_CR1_SPSEL inc\stm8s.h 208;" macro -ADC1_CR2_ALIGN inc\stm8s.h 214;" macro -ADC1_CR2_EXTSEL inc\stm8s.h 213;" macro -ADC1_CR2_EXTTRIG inc\stm8s.h 212;" macro -ADC1_CR2_RESET_VALUE inc\stm8s.h 183;" macro -ADC1_CR2_SCAN inc\stm8s.h 215;" macro -ADC1_CR3_DBUF inc\stm8s.h 217;" macro -ADC1_CR3_OVR inc\stm8s.h 218;" macro -ADC1_CR3_RESET_VALUE inc\stm8s.h 184;" macro -ADC1_CSR_AWD inc\stm8s.h 203;" macro -ADC1_CSR_AWDIE inc\stm8s.h 205;" macro -ADC1_CSR_CH inc\stm8s.h 206;" macro -ADC1_CSR_EOC inc\stm8s.h 202;" macro -ADC1_CSR_EOCIE inc\stm8s.h 204;" macro -ADC1_CSR_RESET_VALUE inc\stm8s.h 181;" macro -ADC1_HTRH_RESET_VALUE inc\stm8s.h 188;" macro -ADC1_HTRL_RESET_VALUE inc\stm8s.h 187;" macro -ADC1_IRQHandler inc\stm8s_it.h 37;" prototype signature:(void) -ADC1_LTRH_RESET_VALUE inc\stm8s.h 189;" macro -ADC1_LTRL_RESET_VALUE inc\stm8s.h 190;" macro -ADC1_TDRH_RESET_VALUE inc\stm8s.h 186;" macro -ADC1_TDRL_RESET_VALUE inc\stm8s.h 185;" macro -ADC1_TypeDef inc\stm8s.h 175;" typedef typeref:struct:ADC1_struct -ADC1_struct inc\stm8s.h 135;" struct -ADC2 inc\stm8s.h 2393;" macro -ADC2_BaseAddress inc\stm8s.h 2372;" macro -ADC2_CR1_ADON inc\stm8s.h 267;" macro -ADC2_CR1_CONT inc\stm8s.h 266;" macro -ADC2_CR1_RESET_VALUE inc\stm8s.h 248;" macro -ADC2_CR1_SPSEL inc\stm8s.h 265;" macro -ADC2_CR2_ALIGN inc\stm8s.h 271;" macro -ADC2_CR2_EXTSEL inc\stm8s.h 270;" macro -ADC2_CR2_EXTTRIG inc\stm8s.h 269;" macro -ADC2_CR2_RESET_VALUE inc\stm8s.h 249;" macro -ADC2_CSR_CH inc\stm8s.h 263;" macro -ADC2_CSR_EOC inc\stm8s.h 261;" macro -ADC2_CSR_EOCIE inc\stm8s.h 262;" macro -ADC2_CSR_RESET_VALUE inc\stm8s.h 247;" macro -ADC2_IRQHandler inc\stm8s_it.h 38;" prototype signature:(void) -ADC2_TDRH_RESET_VALUE inc\stm8s.h 251;" macro -ADC2_TDRL_RESET_VALUE inc\stm8s.h 250;" macro -ADC2_TypeDef inc\stm8s.h 241;" typedef typeref:struct:ADC2_struct -ADC2_struct inc\stm8s.h 230;" struct -APR inc\stm8s.h 285;" member struct:AWU_struct -AREA inc\stm8s.h 2553;" macro -AREA inc\stm8s_macro.h 109;" macro -ARR inc\stm8s.h 1129;" member struct:TIM6_struct -ARR inc\stm8s.h 925;" member struct:TIM4_struct -ARRH inc\stm8s.h 485;" member struct:TIM1_struct -ARRH inc\stm8s.h 697;" member struct:TIM2_struct -ARRH inc\stm8s.h 819;" member struct:TIM3_struct -ARRH inc\stm8s.h 993;" member struct:TIM5_struct -ARRL inc\stm8s.h 486;" member struct:TIM1_struct -ARRL inc\stm8s.h 698;" member struct:TIM2_struct -ARRL inc\stm8s.h 820;" member struct:TIM3_struct -ARRL inc\stm8s.h 994;" member struct:TIM5_struct -AWCRH inc\stm8s.h 172;" member struct:ADC1_struct -AWCRL inc\stm8s.h 173;" member struct:ADC1_struct -AWSRH inc\stm8s.h 170;" member struct:ADC1_struct -AWSRL inc\stm8s.h 171;" member struct:ADC1_struct -AWU inc\stm8s.h 2396;" macro -AWU_APR_APR inc\stm8s.h 311;" macro -AWU_APR_RESET_VALUE inc\stm8s.h 295;" macro -AWU_BaseAddress inc\stm8s.h 2357;" macro -AWU_CSR_AWUEN inc\stm8s.h 307;" macro -AWU_CSR_AWUF inc\stm8s.h 306;" macro -AWU_CSR_MR inc\stm8s.h 308;" macro -AWU_CSR_MSR inc\stm8s.h 309;" macro -AWU_CSR_RESET_VALUE inc\stm8s.h 294;" macro -AWU_IRQHandler inc\stm8s_it.h 61;" prototype signature:(void) -AWU_TBR_AWUTB inc\stm8s.h 313;" macro -AWU_TBR_RESET_VALUE inc\stm8s.h 296;" macro -AWU_TypeDef inc\stm8s.h 288;" typedef typeref:struct:AWU_struct -AWU_struct inc\stm8s.h 282;" struct -Ack_I2c src\i2c_master.c 136;" function signature:(bool a) -AffBit inc\stm8s.h 2527;" macro -AffBit inc\stm8s_macro.h 82;" macro -Audioconfig main.c 174;" function signature:(void) -Authen main.c 249;" function signature:(void) -Auto_load main.c 206;" function signature:(void) -BEEP inc\stm8s.h 2398;" macro -BEEP_BaseAddress inc\stm8s.h 2358;" macro -BEEP_CSR_BEEPDIV inc\stm8s.h 346;" macro -BEEP_CSR_BEEPEN inc\stm8s.h 345;" macro -BEEP_CSR_BEEPSEL inc\stm8s.h 344;" macro -BEEP_CSR_RESET_VALUE inc\stm8s.h 334;" macro -BEEP_TypeDef inc\stm8s.h 328;" typedef typeref:struct:BEEP_struct -BEEP_struct inc\stm8s.h 324;" struct -BKR inc\stm8s.h 496;" member struct:TIM1_struct -BRR1 inc\stm8s.h 1645;" member struct:UART1_struct -BRR1 inc\stm8s.h 1743;" member struct:UART2_struct -BRR1 inc\stm8s.h 1851;" member struct:UART3_struct -BRR2 inc\stm8s.h 1646;" member struct:UART1_struct -BRR2 inc\stm8s.h 1744;" member struct:UART2_struct -BRR2 inc\stm8s.h 1852;" member struct:UART3_struct -BT656_480P main.c 313;" function signature:(void) -BTR1 inc\stm8s.h 2069;" member struct:__anon1::__anon2::__anon8 -BTR2 inc\stm8s.h 2070;" member struct:__anon1::__anon2::__anon8 -BYTE_0 inc\stm8s.h 2534;" macro -BYTE_0 inc\stm8s_macro.h 89;" macro -BYTE_1 inc\stm8s.h 2535;" macro -BYTE_1 inc\stm8s_macro.h 90;" macro -BYTE_2 inc\stm8s.h 2536;" macro -BYTE_2 inc\stm8s_macro.h 91;" macro -BYTE_3 inc\stm8s.h 2537;" macro -BYTE_3 inc\stm8s_macro.h 92;" macro -BitClr inc\stm8s.h 2555;" macro -BitClr inc\stm8s_macro.h 111;" macro -BitSet inc\stm8s.h 2556;" macro -BitSet inc\stm8s_macro.h 112;" macro -BitStatus inc\stm8s_type.h 85;" typedef typeref:enum:__anon28 -BitVal inc\stm8s.h 2557;" macro -BitVal inc\stm8s_macro.h 113;" macro -CAN inc\stm8s.h 2401;" macro -CANCCR inc\stm8s.h 370;" member struct:CLK_struct -CAN_BTR1_RESET_VALUE inc\stm8s.h 2283;" macro -CAN_BTR2_CLKS inc\stm8s.h 2222;" macro -CAN_BTR2_RESET_VALUE inc\stm8s.h 2284;" macro -CAN_BaseAddress inc\stm8s.h 2373;" macro -CAN_DGR_LBKM inc\stm8s.h 2156;" macro -CAN_DGR_RESET_VALUE inc\stm8s.h 2276;" macro -CAN_DGR_RX inc\stm8s.h 2159;" macro -CAN_DGR_SAMP inc\stm8s.h 2158;" macro -CAN_DGR_SLIM inc\stm8s.h 2157;" macro -CAN_DGR_TXM2E inc\stm8s.h 2160;" macro -CAN_EIER_BOFIE inc\stm8s.h 2197;" macro -CAN_EIER_EPVIE inc\stm8s.h 2196;" macro -CAN_EIER_ERRIE inc\stm8s.h 2199;" macro -CAN_EIER_EWGIE inc\stm8s.h 2195;" macro -CAN_EIER_LECIE inc\stm8s.h 2198;" macro -CAN_EIER_RESET_VALUE inc\stm8s.h 2280;" macro -CAN_ESR_BOFF inc\stm8s.h 2188;" macro -CAN_ESR_EPVF inc\stm8s.h 2187;" macro -CAN_ESR_EWGF inc\stm8s.h 2186;" macro -CAN_ESR_LEC inc\stm8s.h 2192;" macro -CAN_ESR_LEC0 inc\stm8s.h 2189;" macro -CAN_ESR_LEC1 inc\stm8s.h 2190;" macro -CAN_ESR_LEC2 inc\stm8s.h 2191;" macro -CAN_ESR_RESET_VALUE inc\stm8s.h 2279;" macro -CAN_FCR1_FACT0 inc\stm8s.h 2240;" macro -CAN_FCR1_FACT1 inc\stm8s.h 2241;" macro -CAN_FCR1_FSC00 inc\stm8s.h 2247;" macro -CAN_FCR1_FSC01 inc\stm8s.h 2248;" macro -CAN_FCR1_FSC10 inc\stm8s.h 2249;" macro -CAN_FCR1_FSC11 inc\stm8s.h 2250;" macro -CAN_FCR2_FACT2 inc\stm8s.h 2242;" macro -CAN_FCR2_FACT3 inc\stm8s.h 2243;" macro -CAN_FCR2_FSC20 inc\stm8s.h 2251;" macro -CAN_FCR2_FSC21 inc\stm8s.h 2252;" macro -CAN_FCR2_FSC30 inc\stm8s.h 2253;" macro -CAN_FCR2_FSC31 inc\stm8s.h 2254;" macro -CAN_FCR3_FACT4 inc\stm8s.h 2244;" macro -CAN_FCR3_FACT5 inc\stm8s.h 2245;" macro -CAN_FCR3_FSC40 inc\stm8s.h 2255;" macro -CAN_FCR3_FSC41 inc\stm8s.h 2256;" macro -CAN_FCR3_FSC50 inc\stm8s.h 2257;" macro -CAN_FCR3_FSC51 inc\stm8s.h 2258;" macro -CAN_FCR_RESET_VALUE inc\stm8s.h 2287;" macro -CAN_FMR1_FMH0 inc\stm8s.h 2226;" macro -CAN_FMR1_FMH1 inc\stm8s.h 2228;" macro -CAN_FMR1_FMH2 inc\stm8s.h 2230;" macro -CAN_FMR1_FMH3 inc\stm8s.h 2232;" macro -CAN_FMR1_FML0 inc\stm8s.h 2225;" macro -CAN_FMR1_FML1 inc\stm8s.h 2227;" macro -CAN_FMR1_FML2 inc\stm8s.h 2229;" macro -CAN_FMR1_FML3 inc\stm8s.h 2231;" macro -CAN_FMR1_RESET_VALUE inc\stm8s.h 2285;" macro -CAN_FMR2_FMH4 inc\stm8s.h 2235;" macro -CAN_FMR2_FMH5 inc\stm8s.h 2237;" macro -CAN_FMR2_FML4 inc\stm8s.h 2234;" macro -CAN_FMR2_FML5 inc\stm8s.h 2236;" macro -CAN_FMR2_RESET_VALUE inc\stm8s.h 2286;" macro -CAN_IER_FFIE inc\stm8s.h 2150;" macro -CAN_IER_FMPIE inc\stm8s.h 2149;" macro -CAN_IER_FOVIE inc\stm8s.h 2151;" macro -CAN_IER_RESET_VALUE inc\stm8s.h 2275;" macro -CAN_IER_TMEIE inc\stm8s.h 2148;" macro -CAN_IER_WKUIE inc\stm8s.h 2152;" macro -CAN_MCR_ABOM inc\stm8s.h 2114;" macro -CAN_MCR_AWUM inc\stm8s.h 2113;" macro -CAN_MCR_INRQ inc\stm8s.h 2108;" macro -CAN_MCR_NART inc\stm8s.h 2112;" macro -CAN_MCR_RESET_VALUE inc\stm8s.h 2270;" macro -CAN_MCR_RFLM inc\stm8s.h 2111;" macro -CAN_MCR_SLEEP inc\stm8s.h 2109;" macro -CAN_MCR_TTCM inc\stm8s.h 2115;" macro -CAN_MCR_TXFP inc\stm8s.h 2110;" macro -CAN_MCSR_ABRQ inc\stm8s.h 2170;" macro -CAN_MCSR_ALST inc\stm8s.h 2173;" macro -CAN_MCSR_RESET_VALUE inc\stm8s.h 2291;" macro -CAN_MCSR_RQCP inc\stm8s.h 2171;" macro -CAN_MCSR_TERR inc\stm8s.h 2174;" macro -CAN_MCSR_TXOK inc\stm8s.h 2172;" macro -CAN_MCSR_TXRQ inc\stm8s.h 2169;" macro -CAN_MDLCR_DLC inc\stm8s.h 2176;" macro -CAN_MDLCR_TGT inc\stm8s.h 2177;" macro -CAN_MDLC_RESET_VALUE inc\stm8s.h 2290;" macro -CAN_MFMI_RESET_VALUE inc\stm8s.h 2289;" macro -CAN_MIDR1_IDE inc\stm8s.h 2180;" macro -CAN_MIDR1_RTR inc\stm8s.h 2179;" macro -CAN_MSR_ERRI inc\stm8s.h 2120;" macro -CAN_MSR_INAK inc\stm8s.h 2118;" macro -CAN_MSR_RESET_VALUE inc\stm8s.h 2271;" macro -CAN_MSR_RX inc\stm8s.h 2123;" macro -CAN_MSR_SLAK inc\stm8s.h 2119;" macro -CAN_MSR_TX inc\stm8s.h 2122;" macro -CAN_MSR_WKUI inc\stm8s.h 2121;" macro -CAN_PSR_PS0 inc\stm8s.h 2164;" macro -CAN_PSR_PS1 inc\stm8s.h 2165;" macro -CAN_PSR_PS2 inc\stm8s.h 2166;" macro -CAN_PSR_RESET_VALUE inc\stm8s.h 2277;" macro -CAN_RECR_REC0 inc\stm8s.h 2212;" macro -CAN_RECR_REC1 inc\stm8s.h 2213;" macro -CAN_RECR_REC2 inc\stm8s.h 2214;" macro -CAN_RECR_REC3 inc\stm8s.h 2215;" macro -CAN_RECR_REC4 inc\stm8s.h 2216;" macro -CAN_RECR_REC5 inc\stm8s.h 2217;" macro -CAN_RECR_REC6 inc\stm8s.h 2218;" macro -CAN_RECR_REC7 inc\stm8s.h 2219;" macro -CAN_RECR_RESET_VALUE inc\stm8s.h 2282;" macro -CAN_RFR_FMP01 inc\stm8s.h 2142;" macro -CAN_RFR_FOVR inc\stm8s.h 2144;" macro -CAN_RFR_FULL inc\stm8s.h 2143;" macro -CAN_RFR_RESET_VALUE inc\stm8s.h 2274;" macro -CAN_RFR_RFOM inc\stm8s.h 2145;" macro -CAN_RX_IRQHandler inc\stm8s_it.h 54;" prototype signature:(void) -CAN_TECR_RESET_VALUE inc\stm8s.h 2281;" macro -CAN_TECR_TEC0 inc\stm8s.h 2202;" macro -CAN_TECR_TEC1 inc\stm8s.h 2203;" macro -CAN_TECR_TEC2 inc\stm8s.h 2204;" macro -CAN_TECR_TEC3 inc\stm8s.h 2205;" macro -CAN_TECR_TEC4 inc\stm8s.h 2206;" macro -CAN_TECR_TEC5 inc\stm8s.h 2207;" macro -CAN_TECR_TEC6 inc\stm8s.h 2208;" macro -CAN_TECR_TEC7 inc\stm8s.h 2209;" macro -CAN_TPR_CODE0 inc\stm8s.h 2134;" macro -CAN_TPR_LOW0 inc\stm8s.h 2138;" macro -CAN_TPR_LOW1 inc\stm8s.h 2139;" macro -CAN_TPR_LOW2 inc\stm8s.h 2140;" macro -CAN_TPR_RESET_VALUE inc\stm8s.h 2273;" macro -CAN_TPR_TME0 inc\stm8s.h 2135;" macro -CAN_TPR_TME1 inc\stm8s.h 2136;" macro -CAN_TPR_TME2 inc\stm8s.h 2137;" macro -CAN_TSR_RESET_VALUE inc\stm8s.h 2272;" macro -CAN_TSR_RQCP0 inc\stm8s.h 2126;" macro -CAN_TSR_RQCP012 inc\stm8s.h 2129;" macro -CAN_TSR_RQCP1 inc\stm8s.h 2127;" macro -CAN_TSR_RQCP2 inc\stm8s.h 2128;" macro -CAN_TSR_TXOK0 inc\stm8s.h 2130;" macro -CAN_TSR_TXOK1 inc\stm8s.h 2131;" macro -CAN_TSR_TXOK2 inc\stm8s.h 2132;" macro -CAN_TX_IRQHandler inc\stm8s_it.h 53;" prototype signature:(void) -CAN_TypeDef inc\stm8s.h 2102;" typedef typeref:struct:__anon1 -CCER1 inc\stm8s.h 479;" member struct:TIM1_struct -CCER1 inc\stm8s.h 692;" member struct:TIM2_struct -CCER1 inc\stm8s.h 815;" member struct:TIM3_struct -CCER1 inc\stm8s.h 988;" member struct:TIM5_struct -CCER2 inc\stm8s.h 480;" member struct:TIM1_struct -CCER2 inc\stm8s.h 693;" member struct:TIM2_struct -CCER2 inc\stm8s.h 989;" member struct:TIM5_struct -CCMR1 inc\stm8s.h 475;" member struct:TIM1_struct -CCMR1 inc\stm8s.h 689;" member struct:TIM2_struct -CCMR1 inc\stm8s.h 813;" member struct:TIM3_struct -CCMR1 inc\stm8s.h 985;" member struct:TIM5_struct -CCMR2 inc\stm8s.h 476;" member struct:TIM1_struct -CCMR2 inc\stm8s.h 690;" member struct:TIM2_struct -CCMR2 inc\stm8s.h 814;" member struct:TIM3_struct -CCMR2 inc\stm8s.h 986;" member struct:TIM5_struct -CCMR3 inc\stm8s.h 477;" member struct:TIM1_struct -CCMR3 inc\stm8s.h 691;" member struct:TIM2_struct -CCMR3 inc\stm8s.h 987;" member struct:TIM5_struct -CCMR4 inc\stm8s.h 478;" member struct:TIM1_struct -CCMR_TIxDirect_Set inc\stm8s.h 608;" macro -CCOR inc\stm8s.h 368;" member struct:CLK_struct -CCR1H inc\stm8s.h 488;" member struct:TIM1_struct -CCR1H inc\stm8s.h 699;" member struct:TIM2_struct -CCR1H inc\stm8s.h 821;" member struct:TIM3_struct -CCR1H inc\stm8s.h 995;" member struct:TIM5_struct -CCR1L inc\stm8s.h 489;" member struct:TIM1_struct -CCR1L inc\stm8s.h 700;" member struct:TIM2_struct -CCR1L inc\stm8s.h 822;" member struct:TIM3_struct -CCR1L inc\stm8s.h 996;" member struct:TIM5_struct -CCR2H inc\stm8s.h 490;" member struct:TIM1_struct -CCR2H inc\stm8s.h 701;" member struct:TIM2_struct -CCR2H inc\stm8s.h 823;" member struct:TIM3_struct -CCR2H inc\stm8s.h 997;" member struct:TIM5_struct -CCR2L inc\stm8s.h 491;" member struct:TIM1_struct -CCR2L inc\stm8s.h 702;" member struct:TIM2_struct -CCR2L inc\stm8s.h 824;" member struct:TIM3_struct -CCR2L inc\stm8s.h 998;" member struct:TIM5_struct -CCR3H inc\stm8s.h 492;" member struct:TIM1_struct -CCR3H inc\stm8s.h 703;" member struct:TIM2_struct -CCR3H inc\stm8s.h 999;" member struct:TIM5_struct -CCR3L inc\stm8s.h 1000;" member struct:TIM5_struct -CCR3L inc\stm8s.h 493;" member struct:TIM1_struct -CCR3L inc\stm8s.h 704;" member struct:TIM2_struct -CCR4H inc\stm8s.h 494;" member struct:TIM1_struct -CCR4L inc\stm8s.h 495;" member struct:TIM1_struct -CCRH inc\stm8s.h 1205;" member struct:I2C_struct -CCRL inc\stm8s.h 1204;" member struct:I2C_struct -CFG inc\stm8s.h 2474;" macro -CFG_BaseAddress inc\stm8s.h 2375;" macro -CFG_GCR_AL inc\stm8s.h 2322;" macro -CFG_GCR_RESET_VALUE inc\stm8s.h 2311;" macro -CFG_GCR_SWD inc\stm8s.h 2321;" macro -CFG_TypeDef inc\stm8s.h 2305;" typedef typeref:struct:CFG_struct -CFG_struct inc\stm8s.h 2301;" struct -CKDIVR inc\stm8s.h 365;" member struct:CLK_struct -CLK inc\stm8s.h 2404;" macro -CLKPrescTable src\stm8s_clk.c 40;" variable -CLK_AdjustHSICalibrationValue inc\stm8s_clk.h 392;" prototype signature:(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue) -CLK_AdjustHSICalibrationValue src\stm8s_clk.c 275;" function signature:(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue) -CLK_BaseAddress inc\stm8s.h 2354;" macro -CLK_CANCCR_CANDIV inc\stm8s.h 450;" macro -CLK_CANCCR_RESET_VALUE inc\stm8s.h 390;" macro -CLK_CANConfig inc\stm8s_clk.h 389;" prototype signature:(CLK_CANDivider_TypeDef CLK_CANDivider) -CLK_CANDIVIDER_1 inc\stm8s_clk.h 201;" enumerator enum:__anon21 -CLK_CANDIVIDER_2 inc\stm8s_clk.h 202;" enumerator enum:__anon21 -CLK_CANDIVIDER_3 inc\stm8s_clk.h 203;" enumerator enum:__anon21 -CLK_CANDIVIDER_4 inc\stm8s_clk.h 204;" enumerator enum:__anon21 -CLK_CANDIVIDER_5 inc\stm8s_clk.h 205;" enumerator enum:__anon21 -CLK_CANDIVIDER_6 inc\stm8s_clk.h 206;" enumerator enum:__anon21 -CLK_CANDIVIDER_7 inc\stm8s_clk.h 207;" enumerator enum:__anon21 -CLK_CANDIVIDER_8 inc\stm8s_clk.h 208;" enumerator enum:__anon21 -CLK_CANDivider_TypeDef inc\stm8s_clk.h 209;" typedef typeref:enum:__anon21 -CLK_CCOCmd inc\stm8s_clk.h 378;" prototype signature:(FunctionalState NewState) -CLK_CCOConfig inc\stm8s_clk.h 385;" prototype signature:(CLK_Output_TypeDef CLK_CCO) -CLK_CCOR_CCOBSY inc\stm8s.h 445;" macro -CLK_CCOR_CCOEN inc\stm8s.h 448;" macro -CLK_CCOR_CCORDY inc\stm8s.h 446;" macro -CLK_CCOR_CCOSEL inc\stm8s.h 447;" macro -CLK_CCOR_RESET_VALUE inc\stm8s.h 389;" macro -CLK_CKDIVR_CPUDIV inc\stm8s.h 422;" macro -CLK_CKDIVR_HSIDIV inc\stm8s.h 421;" macro -CLK_CKDIVR_RESET_VALUE inc\stm8s.h 385;" macro -CLK_CMSR_CKM inc\stm8s.h 412;" macro -CLK_CMSR_RESET_VALUE inc\stm8s.h 382;" macro -CLK_CSSCONFIG_DISABLE inc\stm8s_clk.h 58;" enumerator enum:__anon12 -CLK_CSSCONFIG_ENABLE inc\stm8s_clk.h 57;" enumerator enum:__anon12 -CLK_CSSCONFIG_ENABLEWITHIT inc\stm8s_clk.h 56;" enumerator enum:__anon12 -CLK_CSSConfig_TypeDef inc\stm8s_clk.h 59;" typedef typeref:enum:__anon12 -CLK_CSSR_AUX inc\stm8s.h 442;" macro -CLK_CSSR_CSSD inc\stm8s.h 440;" macro -CLK_CSSR_CSSDIE inc\stm8s.h 441;" macro -CLK_CSSR_CSSEN inc\stm8s.h 443;" macro -CLK_CSSR_RESET_VALUE inc\stm8s.h 388;" macro -CLK_CURRENTCLOCKSTATE_DISABLE inc\stm8s_clk.h 48;" enumerator enum:__anon11 -CLK_CURRENTCLOCKSTATE_ENABLE inc\stm8s_clk.h 49;" enumerator enum:__anon11 -CLK_ClearITPendingBit inc\stm8s_clk.h 397;" prototype signature:(CLK_IT_TypeDef CLK_IT) -CLK_ClearITPendingBit src\stm8s_clk.c 352;" function signature:(CLK_IT_TypeDef CLK_IT) -CLK_ClockSecuritySystemEnable inc\stm8s_clk.h 390;" prototype signature:(void) -CLK_ClockSecuritySystemEnable src\stm8s_clk.c 241;" function signature:(void) -CLK_ClockSwitchCmd inc\stm8s_clk.h 379;" prototype signature:(FunctionalState NewState) -CLK_ClockSwitchCmd src\stm8s_clk.c 93;" function signature:(FunctionalState NewState) -CLK_ClockSwitchConfig inc\stm8s_clk.h 383;" prototype signature:(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState) -CLK_Configuration inc\main.h 13;" prototype signature:(void) -CLK_Configuration main.c 50;" function signature:(void) -CLK_CurrentClockState_TypeDef inc\stm8s_clk.h 50;" typedef typeref:enum:__anon11 -CLK_DeInit inc\stm8s_clk.h 374;" prototype signature:(void) -CLK_DeInit src\stm8s_clk.c 64;" function signature:(void) -CLK_ECKR_HSEEN inc\stm8s.h 410;" macro -CLK_ECKR_HSERDY inc\stm8s.h 409;" macro -CLK_ECKR_RESET_VALUE inc\stm8s.h 381;" macro -CLK_FLAG_AUX inc\stm8s_clk.h 152;" enumerator enum:__anon17 -CLK_FLAG_CCOBSY inc\stm8s_clk.h 153;" enumerator enum:__anon17 -CLK_FLAG_CCORDY inc\stm8s_clk.h 154;" enumerator enum:__anon17 -CLK_FLAG_CSSD inc\stm8s_clk.h 151;" enumerator enum:__anon17 -CLK_FLAG_HSERDY inc\stm8s_clk.h 148;" enumerator enum:__anon17 -CLK_FLAG_HSIRDY inc\stm8s_clk.h 147;" enumerator enum:__anon17 -CLK_FLAG_LSIRDY inc\stm8s_clk.h 146;" enumerator enum:__anon17 -CLK_FLAG_SWBSY inc\stm8s_clk.h 150;" enumerator enum:__anon17 -CLK_FLAG_SWIF inc\stm8s_clk.h 149;" enumerator enum:__anon17 -CLK_FastHaltWakeUpCmd inc\stm8s_clk.h 380;" prototype signature:(FunctionalState NewState) -CLK_Flag_TypeDef inc\stm8s_clk.h 156;" typedef typeref:enum:__anon17 -CLK_GetClockFreq inc\stm8s_clk.h 393;" prototype signature:(void) -CLK_GetFlagStatus inc\stm8s_clk.h 395;" prototype signature:(CLK_Flag_TypeDef CLK_FLAG) -CLK_GetITStatus inc\stm8s_clk.h 396;" prototype signature:(CLK_IT_TypeDef CLK_IT) -CLK_GetITStatus src\stm8s_clk.c 308;" function signature:(CLK_IT_TypeDef CLK_IT) -CLK_GetSYSCLKSource inc\stm8s_clk.h 394;" prototype signature:(void) -CLK_GetSYSCLKSource src\stm8s_clk.c 254;" function signature:(void) -CLK_HSECmd inc\stm8s_clk.h 375;" prototype signature:(FunctionalState NewState) -CLK_HSICmd inc\stm8s_clk.h 376;" prototype signature:(FunctionalState NewState) -CLK_HSIPrescalerConfig inc\stm8s_clk.h 384;" prototype signature:(CLK_Prescaler_TypeDef HSIPrescaler) -CLK_HSIPrescalerConfig src\stm8s_clk.c 146;" function signature:(CLK_Prescaler_TypeDef HSIPrescaler) -CLK_HSITRIMR_HSITRIM inc\stm8s.h 452;" macro -CLK_HSITRIMR_RESET_VALUE inc\stm8s.h 391;" macro -CLK_HSITRIMVALUE_0 inc\stm8s_clk.h 74;" enumerator enum:__anon14 -CLK_HSITRIMVALUE_1 inc\stm8s_clk.h 75;" enumerator enum:__anon14 -CLK_HSITRIMVALUE_2 inc\stm8s_clk.h 76;" enumerator enum:__anon14 -CLK_HSITRIMVALUE_3 inc\stm8s_clk.h 77;" enumerator enum:__anon14 -CLK_HSITRIMVALUE_4 inc\stm8s_clk.h 78;" enumerator enum:__anon14 -CLK_HSITRIMVALUE_5 inc\stm8s_clk.h 79;" enumerator enum:__anon14 -CLK_HSITRIMVALUE_6 inc\stm8s_clk.h 80;" enumerator enum:__anon14 -CLK_HSITRIMVALUE_7 inc\stm8s_clk.h 81;" enumerator enum:__anon14 -CLK_HSITrimValue_TypeDef inc\stm8s_clk.h 82;" typedef typeref:enum:__anon14 -CLK_ICKR_FHWU inc\stm8s.h 405;" macro -CLK_ICKR_HSIEN inc\stm8s.h 407;" macro -CLK_ICKR_HSIRDY inc\stm8s.h 406;" macro -CLK_ICKR_LSIEN inc\stm8s.h 404;" macro -CLK_ICKR_LSIRDY inc\stm8s.h 403;" macro -CLK_ICKR_RESET_VALUE inc\stm8s.h 380;" macro -CLK_ICKR_SWUAH inc\stm8s.h 402;" macro -CLK_IRQHandler inc\stm8s_it.h 60;" prototype signature:(void) -CLK_ITConfig inc\stm8s_clk.h 386;" prototype signature:(CLK_IT_TypeDef CLK_IT, FunctionalState NewState) -CLK_ITConfig src\stm8s_clk.c 170;" function signature:(CLK_IT_TypeDef CLK_IT, FunctionalState NewState) -CLK_IT_CSSD inc\stm8s_clk.h 162;" enumerator enum:__anon18 -CLK_IT_SWIF inc\stm8s_clk.h 163;" enumerator enum:__anon18 -CLK_IT_TypeDef inc\stm8s_clk.h 164;" typedef typeref:enum:__anon18 -CLK_LSICmd inc\stm8s_clk.h 377;" prototype signature:(FunctionalState NewState) -CLK_OUTPUT_CPU inc\stm8s_clk.h 91;" enumerator enum:__anon15 -CLK_OUTPUT_CPUDIV16 inc\stm8s_clk.h 95;" enumerator enum:__anon15 -CLK_OUTPUT_CPUDIV2 inc\stm8s_clk.h 92;" enumerator enum:__anon15 -CLK_OUTPUT_CPUDIV32 inc\stm8s_clk.h 96;" enumerator enum:__anon15 -CLK_OUTPUT_CPUDIV4 inc\stm8s_clk.h 93;" enumerator enum:__anon15 -CLK_OUTPUT_CPUDIV64 inc\stm8s_clk.h 97;" enumerator enum:__anon15 -CLK_OUTPUT_CPUDIV8 inc\stm8s_clk.h 94;" enumerator enum:__anon15 -CLK_OUTPUT_HSE inc\stm8s_clk.h 90;" enumerator enum:__anon15 -CLK_OUTPUT_HSI inc\stm8s_clk.h 88;" enumerator enum:__anon15 -CLK_OUTPUT_HSIRC inc\stm8s_clk.h 98;" enumerator enum:__anon15 -CLK_OUTPUT_LSI inc\stm8s_clk.h 89;" enumerator enum:__anon15 -CLK_OUTPUT_MASTER inc\stm8s_clk.h 99;" enumerator enum:__anon15 -CLK_OUTPUT_OTHERS inc\stm8s_clk.h 100;" enumerator enum:__anon15 -CLK_Output_TypeDef inc\stm8s_clk.h 101;" typedef typeref:enum:__anon15 -CLK_PCKENR1_I2C inc\stm8s.h 434;" macro -CLK_PCKENR1_RESET_VALUE inc\stm8s.h 386;" macro -CLK_PCKENR1_SPI inc\stm8s.h 433;" macro -CLK_PCKENR1_TIM1 inc\stm8s.h 424;" macro -CLK_PCKENR1_TIM2 inc\stm8s.h 426;" macro -CLK_PCKENR1_TIM3 inc\stm8s.h 425;" macro -CLK_PCKENR1_TIM4 inc\stm8s.h 428;" macro -CLK_PCKENR1_TIM5 inc\stm8s.h 427;" macro -CLK_PCKENR1_TIM6 inc\stm8s.h 429;" macro -CLK_PCKENR1_UART1 inc\stm8s.h 432;" macro -CLK_PCKENR1_UART2 inc\stm8s.h 431;" macro -CLK_PCKENR1_UART3 inc\stm8s.h 430;" macro -CLK_PCKENR2_ADC inc\stm8s.h 437;" macro -CLK_PCKENR2_AWU inc\stm8s.h 438;" macro -CLK_PCKENR2_CAN inc\stm8s.h 436;" macro -CLK_PCKENR2_RESET_VALUE inc\stm8s.h 387;" macro -CLK_PERIPHERAL_ADC inc\stm8s_clk.h 129;" enumerator enum:__anon16 -CLK_PERIPHERAL_AWU inc\stm8s_clk.h 128;" enumerator enum:__anon16 -CLK_PERIPHERAL_CAN inc\stm8s_clk.h 130;" enumerator enum:__anon16 -CLK_PERIPHERAL_I2C inc\stm8s_clk.h 113;" enumerator enum:__anon16 -CLK_PERIPHERAL_SPI inc\stm8s_clk.h 114;" enumerator enum:__anon16 -CLK_PERIPHERAL_TIMER1 inc\stm8s_clk.h 127;" enumerator enum:__anon16 -CLK_PERIPHERAL_TIMER2 inc\stm8s_clk.h 125;" enumerator enum:__anon16 -CLK_PERIPHERAL_TIMER3 inc\stm8s_clk.h 126;" enumerator enum:__anon16 -CLK_PERIPHERAL_TIMER4 inc\stm8s_clk.h 123;" enumerator enum:__anon16 -CLK_PERIPHERAL_TIMER5 inc\stm8s_clk.h 124;" enumerator enum:__anon16 -CLK_PERIPHERAL_TIMER6 inc\stm8s_clk.h 122;" enumerator enum:__anon16 -CLK_PERIPHERAL_UART1 inc\stm8s_clk.h 116;" enumerator enum:__anon16 -CLK_PERIPHERAL_UART2 inc\stm8s_clk.h 120;" enumerator enum:__anon16 -CLK_PERIPHERAL_UART3 inc\stm8s_clk.h 121;" enumerator enum:__anon16 -CLK_PRESCALER_CPUDIV1 inc\stm8s_clk.h 179;" enumerator enum:__anon19 -CLK_PRESCALER_CPUDIV128 inc\stm8s_clk.h 186;" enumerator enum:__anon19 -CLK_PRESCALER_CPUDIV16 inc\stm8s_clk.h 183;" enumerator enum:__anon19 -CLK_PRESCALER_CPUDIV2 inc\stm8s_clk.h 180;" enumerator enum:__anon19 -CLK_PRESCALER_CPUDIV32 inc\stm8s_clk.h 184;" enumerator enum:__anon19 -CLK_PRESCALER_CPUDIV4 inc\stm8s_clk.h 181;" enumerator enum:__anon19 -CLK_PRESCALER_CPUDIV64 inc\stm8s_clk.h 185;" enumerator enum:__anon19 -CLK_PRESCALER_CPUDIV8 inc\stm8s_clk.h 182;" enumerator enum:__anon19 -CLK_PRESCALER_HSIDIV1 inc\stm8s_clk.h 175;" enumerator enum:__anon19 -CLK_PRESCALER_HSIDIV2 inc\stm8s_clk.h 176;" enumerator enum:__anon19 -CLK_PRESCALER_HSIDIV4 inc\stm8s_clk.h 177;" enumerator enum:__anon19 -CLK_PRESCALER_HSIDIV8 inc\stm8s_clk.h 178;" enumerator enum:__anon19 -CLK_PeripheralClockConfig inc\stm8s_clk.h 382;" prototype signature:(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState) -CLK_Peripheral_TypeDef inc\stm8s_clk.h 131;" typedef typeref:enum:__anon16 -CLK_Prescaler_TypeDef inc\stm8s_clk.h 187;" typedef typeref:enum:__anon19 -CLK_SOURCE_HSE inc\stm8s_clk.h 67;" enumerator enum:__anon13 -CLK_SOURCE_HSI inc\stm8s_clk.h 65;" enumerator enum:__anon13 -CLK_SOURCE_LSI inc\stm8s_clk.h 66;" enumerator enum:__anon13 -CLK_SWCR_RESET_VALUE inc\stm8s.h 384;" macro -CLK_SWCR_SWBSY inc\stm8s.h 419;" macro -CLK_SWCR_SWEN inc\stm8s.h 418;" macro -CLK_SWCR_SWIEN inc\stm8s.h 417;" macro -CLK_SWCR_SWIF inc\stm8s.h 416;" macro -CLK_SWIMCCR_RESET_VALUE inc\stm8s.h 392;" macro -CLK_SWIMCCR_SWIMDIV inc\stm8s.h 454;" macro -CLK_SWIMConfig inc\stm8s_clk.h 388;" prototype signature:(CLK_SWIMDivider_TypeDef CLK_SWIMDivider) -CLK_SWIMDIVIDER_2 inc\stm8s_clk.h 193;" enumerator enum:__anon20 -CLK_SWIMDIVIDER_OTHER inc\stm8s_clk.h 194;" enumerator enum:__anon20 -CLK_SWIMDivider_TypeDef inc\stm8s_clk.h 195;" typedef typeref:enum:__anon20 -CLK_SWITCHMODE_AUTO inc\stm8s_clk.h 41;" enumerator enum:__anon10 -CLK_SWITCHMODE_MANUAL inc\stm8s_clk.h 40;" enumerator enum:__anon10 -CLK_SWR_RESET_VALUE inc\stm8s.h 383;" macro -CLK_SWR_SWI inc\stm8s.h 414;" macro -CLK_SYSCLKConfig inc\stm8s_clk.h 387;" prototype signature:(CLK_Prescaler_TypeDef CLK_Prescaler) -CLK_SYSCLKConfig src\stm8s_clk.c 213;" function signature:(CLK_Prescaler_TypeDef ClockPrescaler) -CLK_SYSCLKEmergencyClear inc\stm8s_clk.h 391;" prototype signature:(void) -CLK_SYSCLKEmergencyClear src\stm8s_clk.c 296;" function signature:(void) -CLK_SlowActiveHaltWakeUpCmd inc\stm8s_clk.h 381;" prototype signature:(FunctionalState NewState) -CLK_SlowActiveHaltWakeUpCmd src\stm8s_clk.c 120;" function signature:(FunctionalState NewState) -CLK_Source_TypeDef inc\stm8s_clk.h 68;" typedef typeref:enum:__anon13 -CLK_SwitchMode_TypeDef inc\stm8s_clk.h 42;" typedef typeref:enum:__anon10 -CLK_TIMEOUT inc\stm8s_clk.h 223;" macro -CLK_TypeDef inc\stm8s.h 374;" typedef typeref:struct:CLK_struct -CLK_struct inc\stm8s.h 357;" struct -CMSR inc\stm8s.h 362;" member struct:CLK_struct -CNTR inc\stm8s.h 1127;" member struct:TIM6_struct -CNTR inc\stm8s.h 923;" member struct:TIM4_struct -CNTRH inc\stm8s.h 481;" member struct:TIM1_struct -CNTRH inc\stm8s.h 694;" member struct:TIM2_struct -CNTRH inc\stm8s.h 816;" member struct:TIM3_struct -CNTRH inc\stm8s.h 990;" member struct:TIM5_struct -CNTRL inc\stm8s.h 482;" member struct:TIM1_struct -CNTRL inc\stm8s.h 695;" member struct:TIM2_struct -CNTRL inc\stm8s.h 817;" member struct:TIM3_struct -CNTRL inc\stm8s.h 991;" member struct:TIM5_struct -CPU_CC_I1I0 inc\stm8s.h 1325;" macro -CPU_SOFT_INT_DISABLED inc\stm8s_itc.h 119;" macro -CR inc\stm8s.h 1498;" member struct:WWDG_struct -CR1 inc\stm8s.h 1121;" member struct:TIM6_struct -CR1 inc\stm8s.h 112;" member struct:GPIO_struct -CR1 inc\stm8s.h 1193;" member struct:I2C_struct -CR1 inc\stm8s.h 1338;" member struct:EXTI_struct -CR1 inc\stm8s.h 1379;" member struct:FLASH_struct -CR1 inc\stm8s.h 1561;" member struct:SPI_struct -CR1 inc\stm8s.h 159;" member struct:ADC1_struct -CR1 inc\stm8s.h 1647;" member struct:UART1_struct -CR1 inc\stm8s.h 1745;" member struct:UART2_struct -CR1 inc\stm8s.h 1853;" member struct:UART3_struct -CR1 inc\stm8s.h 233;" member struct:ADC2_struct -CR1 inc\stm8s.h 467;" member struct:TIM1_struct -CR1 inc\stm8s.h 680;" member struct:TIM2_struct -CR1 inc\stm8s.h 808;" member struct:TIM3_struct -CR1 inc\stm8s.h 915;" member struct:TIM4_struct -CR1 inc\stm8s.h 978;" member struct:TIM5_struct -CR2 inc\stm8s.h 1122;" member struct:TIM6_struct -CR2 inc\stm8s.h 113;" member struct:GPIO_struct -CR2 inc\stm8s.h 1194;" member struct:I2C_struct -CR2 inc\stm8s.h 1339;" member struct:EXTI_struct -CR2 inc\stm8s.h 1380;" member struct:FLASH_struct -CR2 inc\stm8s.h 1562;" member struct:SPI_struct -CR2 inc\stm8s.h 160;" member struct:ADC1_struct -CR2 inc\stm8s.h 1648;" member struct:UART1_struct -CR2 inc\stm8s.h 1746;" member struct:UART2_struct -CR2 inc\stm8s.h 1854;" member struct:UART3_struct -CR2 inc\stm8s.h 234;" member struct:ADC2_struct -CR2 inc\stm8s.h 468;" member struct:TIM1_struct -CR2 inc\stm8s.h 979;" member struct:TIM5_struct -CR3 inc\stm8s.h 161;" member struct:ADC1_struct -CR3 inc\stm8s.h 1649;" member struct:UART1_struct -CR3 inc\stm8s.h 1747;" member struct:UART2_struct -CR3 inc\stm8s.h 1855;" member struct:UART3_struct -CR4 inc\stm8s.h 1650;" member struct:UART1_struct -CR4 inc\stm8s.h 1748;" member struct:UART2_struct -CR4 inc\stm8s.h 1856;" member struct:UART3_struct -CR5 inc\stm8s.h 1651;" member struct:UART1_struct -CR5 inc\stm8s.h 1749;" member struct:UART2_struct -CR6 inc\stm8s.h 1750;" member struct:UART2_struct -CR6 inc\stm8s.h 1858;" member struct:UART3_struct -CRCPR inc\stm8s.h 1566;" member struct:SPI_struct -CSR inc\stm8s.h 158;" member struct:ADC1_struct -CSR inc\stm8s.h 1631;" member struct:SWIM_struct -CSR inc\stm8s.h 232;" member struct:ADC2_struct -CSR inc\stm8s.h 284;" member struct:AWU_struct -CSR inc\stm8s.h 326;" member struct:BEEP_struct -CSSR inc\stm8s.h 367;" member struct:CLK_struct -Check_RGB888 main.c 11;" macro file: -Check_Ycbcr444 main.c 10;" macro file: -ChgBit inc\stm8s.h 2526;" macro -ChgBit inc\stm8s_macro.h 81;" macro -ChipInit main.c 132;" function signature:(void) -CloseAudio main.c 112;" function signature:(void) -CloseVideo main.c 122;" function signature:(void) -ClrBit inc\stm8s.h 2524;" macro -ClrBit inc\stm8s_macro.h 79;" macro -Color_RGB888 main.c 15;" macro file: -Color_Ycbcr422 main.c 16;" macro file: -Color_Ycbcr444 main.c 14;" macro file: -Colorspace main.c 189;" function signature:(u8 color) -Config inc\stm8s.h 2079;" member union:__anon1::__anon2 typeref:struct:__anon1::__anon2::__anon8 -DB0RH inc\stm8s.h 137;" member struct:ADC1_struct -DB0RL inc\stm8s.h 138;" member struct:ADC1_struct -DB1RH inc\stm8s.h 139;" member struct:ADC1_struct -DB1RL inc\stm8s.h 140;" member struct:ADC1_struct -DB2RH inc\stm8s.h 141;" member struct:ADC1_struct -DB2RL inc\stm8s.h 142;" member struct:ADC1_struct -DB3RH inc\stm8s.h 143;" member struct:ADC1_struct -DB3RL inc\stm8s.h 144;" member struct:ADC1_struct -DB4RH inc\stm8s.h 145;" member struct:ADC1_struct -DB4RL inc\stm8s.h 146;" member struct:ADC1_struct -DB5RH inc\stm8s.h 147;" member struct:ADC1_struct -DB5RL inc\stm8s.h 148;" member struct:ADC1_struct -DB6RH inc\stm8s.h 149;" member struct:ADC1_struct -DB6RL inc\stm8s.h 150;" member struct:ADC1_struct -DB7RH inc\stm8s.h 151;" member struct:ADC1_struct -DB7RL inc\stm8s.h 152;" member struct:ADC1_struct -DB8RH inc\stm8s.h 153;" member struct:ADC1_struct -DB8RL inc\stm8s.h 154;" member struct:ADC1_struct -DB9RH inc\stm8s.h 155;" member struct:ADC1_struct -DB9RL inc\stm8s.h 156;" member struct:ADC1_struct -DDR inc\stm8s.h 111;" member struct:GPIO_struct -DGR inc\stm8s.h 1948;" member struct:__anon1 -DISABLE inc\stm8s_type.h 88;" enumerator enum:__anon29 -DM inc\stm8s.h 2478;" macro -DM_BaseAddress inc\stm8s.h 2378;" macro -DR inc\stm8s.h 1199;" member struct:I2C_struct -DR inc\stm8s.h 1565;" member struct:SPI_struct -DR inc\stm8s.h 1632;" member struct:SWIM_struct -DR inc\stm8s.h 1644;" member struct:UART1_struct -DR inc\stm8s.h 1742;" member struct:UART2_struct -DR inc\stm8s.h 1850;" member struct:UART3_struct -DRH inc\stm8s.h 162;" member struct:ADC1_struct -DRH inc\stm8s.h 236;" member struct:ADC2_struct -DRL inc\stm8s.h 163;" member struct:ADC1_struct -DRL inc\stm8s.h 237;" member struct:ADC2_struct -DTR inc\stm8s.h 497;" member struct:TIM1_struct -DUKR inc\stm8s.h 1389;" member struct:FLASH_struct -Delay_ms inc\i2c_master.h 24;" prototype signature:(u16 mscount) -Delay_ms src\i2c_master.c 25;" function signature:(u16 mscount) -ECKR inc\stm8s.h 360;" member struct:CLK_struct -EDID_BLOCK_SIZE inc\edid.h 15;" macro -EEPROM_EEC_IRQHandler inc\stm8s_it.h 35;" prototype signature:(void) -EGR inc\stm8s.h 1126;" member struct:TIM6_struct -EGR inc\stm8s.h 474;" member struct:TIM1_struct -EGR inc\stm8s.h 688;" member struct:TIM2_struct -EGR inc\stm8s.h 812;" member struct:TIM3_struct -EGR inc\stm8s.h 922;" member struct:TIM4_struct -EGR inc\stm8s.h 984;" member struct:TIM5_struct -EIER inc\stm8s.h 2066;" member struct:__anon1::__anon2::__anon8 -ENABLE inc\stm8s_type.h 89;" enumerator enum:__anon29 -ERROR inc\stm8s_type.h 96;" enumerator enum:__anon30 -ESR inc\stm8s.h 2065;" member struct:__anon1::__anon2::__anon8 -ETR inc\stm8s.h 470;" member struct:TIM1_struct -EXTI inc\stm8s.h 2406;" macro -EXTI_BaseAddress inc\stm8s.h 2352;" macro -EXTI_CR1_PAIS inc\stm8s.h 1361;" macro -EXTI_CR1_PBIS inc\stm8s.h 1360;" macro -EXTI_CR1_PCIS inc\stm8s.h 1359;" macro -EXTI_CR1_PDIS inc\stm8s.h 1358;" macro -EXTI_CR1_RESET_VALUE inc\stm8s.h 1347;" macro -EXTI_CR2_PEIS inc\stm8s.h 1364;" macro -EXTI_CR2_RESET_VALUE inc\stm8s.h 1348;" macro -EXTI_CR2_TLIS inc\stm8s.h 1363;" macro -EXTI_DeInit inc\stm8s_exti.h 115;" prototype signature:(void) -EXTI_DeInit src\stm8s_exti.c 45;" function signature:(void) -EXTI_GetExtIntSensitivity inc\stm8s_exti.h 118;" prototype signature:(EXTI_Port_TypeDef Port) -EXTI_GetExtIntSensitivity src\stm8s_exti.c 75;" function signature:(EXTI_Port_TypeDef Port) -EXTI_GetTLISensitivity inc\stm8s_exti.h 119;" prototype signature:(void) -EXTI_GetTLISensitivity src\stm8s_exti.c 114;" function signature:(void) -EXTI_PORTA_IRQHandler inc\stm8s_it.h 59;" prototype signature:(void) -EXTI_PORTB_IRQHandler inc\stm8s_it.h 58;" prototype signature:(void) -EXTI_PORTC_IRQHandler inc\stm8s_it.h 57;" prototype signature:(void) -EXTI_PORTD_IRQHandler inc\stm8s_it.h 56;" prototype signature:(void) -EXTI_PORTE_IRQHandler inc\stm8s_it.h 55;" prototype signature:(void) -EXTI_PORT_GPIOA inc\stm8s_exti.h 57;" enumerator enum:__anon24 -EXTI_PORT_GPIOB inc\stm8s_exti.h 58;" enumerator enum:__anon24 -EXTI_PORT_GPIOC inc\stm8s_exti.h 59;" enumerator enum:__anon24 -EXTI_PORT_GPIOD inc\stm8s_exti.h 60;" enumerator enum:__anon24 -EXTI_PORT_GPIOE inc\stm8s_exti.h 61;" enumerator enum:__anon24 -EXTI_Port_TypeDef inc\stm8s_exti.h 62;" typedef typeref:enum:__anon24 -EXTI_SENSITIVITY_FALL_LOW inc\stm8s_exti.h 39;" enumerator enum:__anon22 -EXTI_SENSITIVITY_FALL_ONLY inc\stm8s_exti.h 41;" enumerator enum:__anon22 -EXTI_SENSITIVITY_RISE_FALL inc\stm8s_exti.h 42;" enumerator enum:__anon22 -EXTI_SENSITIVITY_RISE_ONLY inc\stm8s_exti.h 40;" enumerator enum:__anon22 -EXTI_Sensitivity_TypeDef inc\stm8s_exti.h 43;" typedef typeref:enum:__anon22 -EXTI_SetExtIntSensitivity inc\stm8s_exti.h 116;" prototype signature:(EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue) -EXTI_SetTLISensitivity inc\stm8s_exti.h 117;" prototype signature:(EXTI_TLISensitivity_TypeDef SensitivityValue) -EXTI_SetTLISensitivity src\stm8s_exti.c 58;" function signature:(EXTI_TLISensitivity_TypeDef SensitivityValue) -EXTI_TLISENSITIVITY_FALL_ONLY inc\stm8s_exti.h 49;" enumerator enum:__anon23 -EXTI_TLISENSITIVITY_RISE_ONLY inc\stm8s_exti.h 50;" enumerator enum:__anon23 -EXTI_TLISensitivity_TypeDef inc\stm8s_exti.h 51;" typedef typeref:enum:__anon23 -EXTI_TypeDef inc\stm8s.h 1341;" typedef typeref:struct:EXTI_struct -EXTI_struct inc\stm8s.h 1336;" struct -ErrorStatus inc\stm8s_type.h 99;" typedef typeref:enum:__anon30 -F0R1 inc\stm8s.h 1999;" member struct:__anon1::__anon2::__anon5 -F0R2 inc\stm8s.h 2000;" member struct:__anon1::__anon2::__anon5 -F0R3 inc\stm8s.h 2001;" member struct:__anon1::__anon2::__anon5 -F0R4 inc\stm8s.h 2002;" member struct:__anon1::__anon2::__anon5 -F0R5 inc\stm8s.h 2003;" member struct:__anon1::__anon2::__anon5 -F0R6 inc\stm8s.h 2004;" member struct:__anon1::__anon2::__anon5 -F0R7 inc\stm8s.h 2005;" member struct:__anon1::__anon2::__anon5 -F0R8 inc\stm8s.h 2006;" member struct:__anon1::__anon2::__anon5 -F1R1 inc\stm8s.h 2008;" member struct:__anon1::__anon2::__anon5 -F1R2 inc\stm8s.h 2009;" member struct:__anon1::__anon2::__anon5 -F1R3 inc\stm8s.h 2010;" member struct:__anon1::__anon2::__anon5 -F1R4 inc\stm8s.h 2011;" member struct:__anon1::__anon2::__anon5 -F1R5 inc\stm8s.h 2012;" member struct:__anon1::__anon2::__anon5 -F1R6 inc\stm8s.h 2013;" member struct:__anon1::__anon2::__anon5 -F1R7 inc\stm8s.h 2014;" member struct:__anon1::__anon2::__anon5 -F1R8 inc\stm8s.h 2015;" member struct:__anon1::__anon2::__anon5 -F2R1 inc\stm8s.h 2021;" member struct:__anon1::__anon2::__anon6 -F2R2 inc\stm8s.h 2022;" member struct:__anon1::__anon2::__anon6 -F2R3 inc\stm8s.h 2023;" member struct:__anon1::__anon2::__anon6 -F2R4 inc\stm8s.h 2024;" member struct:__anon1::__anon2::__anon6 -F2R5 inc\stm8s.h 2025;" member struct:__anon1::__anon2::__anon6 -F2R6 inc\stm8s.h 2026;" member struct:__anon1::__anon2::__anon6 -F2R7 inc\stm8s.h 2027;" member struct:__anon1::__anon2::__anon6 -F2R8 inc\stm8s.h 2028;" member struct:__anon1::__anon2::__anon6 -F3R1 inc\stm8s.h 2030;" member struct:__anon1::__anon2::__anon6 -F3R2 inc\stm8s.h 2031;" member struct:__anon1::__anon2::__anon6 -F3R3 inc\stm8s.h 2032;" member struct:__anon1::__anon2::__anon6 -F3R4 inc\stm8s.h 2033;" member struct:__anon1::__anon2::__anon6 -F3R5 inc\stm8s.h 2034;" member struct:__anon1::__anon2::__anon6 -F3R6 inc\stm8s.h 2035;" member struct:__anon1::__anon2::__anon6 -F3R7 inc\stm8s.h 2036;" member struct:__anon1::__anon2::__anon6 -F3R8 inc\stm8s.h 2037;" member struct:__anon1::__anon2::__anon6 -F4R1 inc\stm8s.h 2043;" member struct:__anon1::__anon2::__anon7 -F4R2 inc\stm8s.h 2044;" member struct:__anon1::__anon2::__anon7 -F4R3 inc\stm8s.h 2045;" member struct:__anon1::__anon2::__anon7 -F4R4 inc\stm8s.h 2046;" member struct:__anon1::__anon2::__anon7 -F4R5 inc\stm8s.h 2047;" member struct:__anon1::__anon2::__anon7 -F4R6 inc\stm8s.h 2048;" member struct:__anon1::__anon2::__anon7 -F4R7 inc\stm8s.h 2049;" member struct:__anon1::__anon2::__anon7 -F4R8 inc\stm8s.h 2050;" member struct:__anon1::__anon2::__anon7 -F5R1 inc\stm8s.h 2052;" member struct:__anon1::__anon2::__anon7 -F5R2 inc\stm8s.h 2053;" member struct:__anon1::__anon2::__anon7 -F5R3 inc\stm8s.h 2054;" member struct:__anon1::__anon2::__anon7 -F5R4 inc\stm8s.h 2055;" member struct:__anon1::__anon2::__anon7 -F5R5 inc\stm8s.h 2056;" member struct:__anon1::__anon2::__anon7 -F5R6 inc\stm8s.h 2057;" member struct:__anon1::__anon2::__anon7 -F5R7 inc\stm8s.h 2058;" member struct:__anon1::__anon2::__anon7 -F5R8 inc\stm8s.h 2059;" member struct:__anon1::__anon2::__anon7 -FALSE inc\stm8s_type.h 62;" enumerator enum:__anon25 -FAR inc\stm8s.h 66;" macro -FAR inc\stm8s.h 71;" macro -FCR1 inc\stm8s.h 2074;" member struct:__anon1::__anon2::__anon8 -FCR2 inc\stm8s.h 2075;" member struct:__anon1::__anon2::__anon8 -FCR3 inc\stm8s.h 2076;" member struct:__anon1::__anon2::__anon8 -FLAG_I2C_ERROR src\i2c_master.c 11;" variable -FLAG_RX_Mode main.c 17;" variable -FLASH inc\stm8s.h 2408;" macro -FLASH_BaseAddress inc\stm8s.h 2350;" macro -FLASH_CR1_AHALT inc\stm8s.h 1413;" macro -FLASH_CR1_FIX inc\stm8s.h 1415;" macro -FLASH_CR1_HALT inc\stm8s.h 1412;" macro -FLASH_CR1_IE inc\stm8s.h 1414;" macro -FLASH_CR1_RESET_VALUE inc\stm8s.h 1397;" macro -FLASH_CR2_ERASE inc\stm8s.h 1419;" macro -FLASH_CR2_FPRG inc\stm8s.h 1420;" macro -FLASH_CR2_OPT inc\stm8s.h 1417;" macro -FLASH_CR2_PRG inc\stm8s.h 1421;" macro -FLASH_CR2_RESET_VALUE inc\stm8s.h 1398;" macro -FLASH_CR2_WPRG inc\stm8s.h 1418;" macro -FLASH_DUKR_DUK inc\stm8s.h 1437;" macro -FLASH_DUKR_RESET_VALUE inc\stm8s.h 1402;" macro -FLASH_IAPSR_DUL inc\stm8s.h 1430;" macro -FLASH_IAPSR_EOP inc\stm8s.h 1431;" macro -FLASH_IAPSR_HVOFF inc\stm8s.h 1429;" macro -FLASH_IAPSR_PUL inc\stm8s.h 1432;" macro -FLASH_IAPSR_RESET_VALUE inc\stm8s.h 1400;" macro -FLASH_IAPSR_WR_PG_DIS inc\stm8s.h 1433;" macro -FLASH_NCR2_NERASE inc\stm8s.h 1425;" macro -FLASH_NCR2_NFPRG inc\stm8s.h 1426;" macro -FLASH_NCR2_NOPT inc\stm8s.h 1423;" macro -FLASH_NCR2_NPRG inc\stm8s.h 1427;" macro -FLASH_NCR2_NWPRG inc\stm8s.h 1424;" macro -FLASH_NCR2_RESET_VALUE inc\stm8s.h 1399;" macro -FLASH_PUKR_PUK inc\stm8s.h 1435;" macro -FLASH_PUKR_RESET_VALUE inc\stm8s.h 1401;" macro -FLASH_TypeDef inc\stm8s.h 1391;" typedef typeref:struct:FLASH_struct -FLASH_struct inc\stm8s.h 1377;" struct -FMR1 inc\stm8s.h 2072;" member struct:__anon1::__anon2::__anon8 -FMR2 inc\stm8s.h 2073;" member struct:__anon1::__anon2::__anon8 -FPR inc\stm8s.h 1382;" member struct:FLASH_struct -FR01 inc\stm8s.h 1976;" member struct:__anon1::__anon2::__anon4 -FR02 inc\stm8s.h 1977;" member struct:__anon1::__anon2::__anon4 -FR03 inc\stm8s.h 1978;" member struct:__anon1::__anon2::__anon4 -FR04 inc\stm8s.h 1979;" member struct:__anon1::__anon2::__anon4 -FR05 inc\stm8s.h 1980;" member struct:__anon1::__anon2::__anon4 -FR06 inc\stm8s.h 1981;" member struct:__anon1::__anon2::__anon4 -FR07 inc\stm8s.h 1982;" member struct:__anon1::__anon2::__anon4 -FR08 inc\stm8s.h 1983;" member struct:__anon1::__anon2::__anon4 -FR09 inc\stm8s.h 1985;" member struct:__anon1::__anon2::__anon4 -FR10 inc\stm8s.h 1986;" member struct:__anon1::__anon2::__anon4 -FR11 inc\stm8s.h 1987;" member struct:__anon1::__anon2::__anon4 -FR12 inc\stm8s.h 1988;" member struct:__anon1::__anon2::__anon4 -FR13 inc\stm8s.h 1989;" member struct:__anon1::__anon2::__anon4 -FR14 inc\stm8s.h 1990;" member struct:__anon1::__anon2::__anon4 -FR15 inc\stm8s.h 1991;" member struct:__anon1::__anon2::__anon4 -FR16 inc\stm8s.h 1992;" member struct:__anon1::__anon2::__anon4 -FREQR inc\stm8s.h 1195;" member struct:I2C_struct -Filter inc\stm8s.h 1994;" member union:__anon1::__anon2 typeref:struct:__anon1::__anon2::__anon4 -Filter01 inc\stm8s.h 2017;" member union:__anon1::__anon2 typeref:struct:__anon1::__anon2::__anon5 -Filter23 inc\stm8s.h 2039;" member union:__anon1::__anon2 typeref:struct:__anon1::__anon2::__anon6 -Filter45 inc\stm8s.h 2061;" member union:__anon1::__anon2 typeref:struct:__anon1::__anon2::__anon7 -FlagStatus inc\stm8s_type.h 85;" typedef typeref:enum:__anon28 -Format main.c 320;" function signature:(void) -Fun_Status inc\stm8s_type.h 72;" typedef typeref:enum:__anon26 -FunctionalState inc\stm8s_type.h 91;" typedef typeref:enum:__anon29 -GCR inc\stm8s.h 2303;" member struct:CFG_struct -GET_GPIO_InputPin inc\i2c_master.h 22;" prototype signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin) -GET_MASTER_SDA src\i2c_master.c 23;" macro file: -GPIOA inc\stm8s.h 2412;" macro -GPIOA_BaseAddress inc\stm8s.h 2340;" macro -GPIOB inc\stm8s.h 2414;" macro -GPIOB_BaseAddress inc\stm8s.h 2341;" macro -GPIOC inc\stm8s.h 2416;" macro -GPIOC_BaseAddress inc\stm8s.h 2342;" macro -GPIOD inc\stm8s.h 2418;" macro -GPIOD_BaseAddress inc\stm8s.h 2343;" macro -GPIOE inc\stm8s.h 2420;" macro -GPIOE_BaseAddress inc\stm8s.h 2344;" macro -GPIOF inc\stm8s.h 2422;" macro -GPIOF_BaseAddress inc\stm8s.h 2345;" macro -GPIOG inc\stm8s.h 2425;" macro -GPIOG_BaseAddress inc\stm8s.h 2346;" macro -GPIOH inc\stm8s.h 2429;" macro -GPIOH_BaseAddress inc\stm8s.h 2347;" macro -GPIOI inc\stm8s.h 2430;" macro -GPIOI_BaseAddress inc\stm8s.h 2348;" macro -GPIO_CR1_RESET_VALUE inc\stm8s.h 123;" macro -GPIO_CR2_RESET_VALUE inc\stm8s.h 124;" macro -GPIO_DDR_RESET_VALUE inc\stm8s.h 122;" macro -GPIO_DeInit inc\stm8s_gpio.h 133;" prototype signature:(GPIO_TypeDef* GPIOx) -GPIO_DeInit src\stm8s_gpio.c 45;" function signature:(GPIO_TypeDef* GPIOx) -GPIO_ExternalPullUpConfig inc\stm8s_gpio.h 142;" prototype signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState) -GPIO_ExternalPullUpConfig src\stm8s_gpio.c 223;" function signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState) -GPIO_Init inc\stm8s_gpio.h 134;" prototype signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode) -GPIO_Init src\stm8s_gpio.c 62;" function signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode) -GPIO_Initial inc\main.h 12;" prototype signature:(void) -GPIO_Initial main.c 56;" function signature:(void) -GPIO_MODE_IN_FL_IT inc\stm8s_gpio.h 52;" enumerator enum:__anon31 -GPIO_MODE_IN_FL_NO_IT inc\stm8s_gpio.h 50;" enumerator enum:__anon31 -GPIO_MODE_IN_PU_IT inc\stm8s_gpio.h 53;" enumerator enum:__anon31 -GPIO_MODE_IN_PU_NO_IT inc\stm8s_gpio.h 51;" enumerator enum:__anon31 -GPIO_MODE_OUT_OD_HIZ_FAST inc\stm8s_gpio.h 58;" enumerator enum:__anon31 -GPIO_MODE_OUT_OD_HIZ_SLOW inc\stm8s_gpio.h 60;" enumerator enum:__anon31 -GPIO_MODE_OUT_OD_LOW_FAST inc\stm8s_gpio.h 54;" enumerator enum:__anon31 -GPIO_MODE_OUT_OD_LOW_SLOW inc\stm8s_gpio.h 56;" enumerator enum:__anon31 -GPIO_MODE_OUT_PP_HIGH_FAST inc\stm8s_gpio.h 59;" enumerator enum:__anon31 -GPIO_MODE_OUT_PP_HIGH_SLOW inc\stm8s_gpio.h 61;" enumerator enum:__anon31 -GPIO_MODE_OUT_PP_LOW_FAST inc\stm8s_gpio.h 55;" enumerator enum:__anon31 -GPIO_MODE_OUT_PP_LOW_SLOW inc\stm8s_gpio.h 57;" enumerator enum:__anon31 -GPIO_Mode_TypeDef inc\stm8s_gpio.h 62;" typedef typeref:enum:__anon31 -GPIO_ODR_RESET_VALUE inc\stm8s.h 121;" macro -GPIO_PIN_0 inc\stm8s_gpio.h 71;" enumerator enum:__anon32 -GPIO_PIN_1 inc\stm8s_gpio.h 72;" enumerator enum:__anon32 -GPIO_PIN_2 inc\stm8s_gpio.h 73;" enumerator enum:__anon32 -GPIO_PIN_3 inc\stm8s_gpio.h 74;" enumerator enum:__anon32 -GPIO_PIN_4 inc\stm8s_gpio.h 75;" enumerator enum:__anon32 -GPIO_PIN_5 inc\stm8s_gpio.h 76;" enumerator enum:__anon32 -GPIO_PIN_6 inc\stm8s_gpio.h 77;" enumerator enum:__anon32 -GPIO_PIN_7 inc\stm8s_gpio.h 78;" enumerator enum:__anon32 -GPIO_PIN_ALL inc\stm8s_gpio.h 81;" enumerator enum:__anon32 -GPIO_PIN_HNIB inc\stm8s_gpio.h 80;" enumerator enum:__anon32 -GPIO_PIN_LNIB inc\stm8s_gpio.h 79;" enumerator enum:__anon32 -GPIO_Pin_TypeDef inc\stm8s_gpio.h 82;" typedef typeref:enum:__anon32 -GPIO_ReadInputData inc\stm8s_gpio.h 139;" prototype signature:(GPIO_TypeDef* GPIOx) -GPIO_ReadInputData src\stm8s_gpio.c 195;" function signature:(GPIO_TypeDef* GPIOx) -GPIO_ReadInputPin inc\stm8s_gpio.h 141;" prototype signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin) -GPIO_ReadInputPin src\stm8s_gpio.c 210;" function signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin) -GPIO_ReadOutputData inc\stm8s_gpio.h 140;" prototype signature:(GPIO_TypeDef* GPIOx) -GPIO_ReadOutputData src\stm8s_gpio.c 183;" function signature:(GPIO_TypeDef* GPIOx) -GPIO_TypeDef inc\stm8s.h 115;" typedef typeref:struct:GPIO_struct -GPIO_Write inc\stm8s_gpio.h 135;" prototype signature:(GPIO_TypeDef* GPIOx, u8 PortVal) -GPIO_Write src\stm8s_gpio.c 129;" function signature:(GPIO_TypeDef* GPIOx, u8 PortVal) -GPIO_WriteHigh inc\stm8s_gpio.h 136;" prototype signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins) -GPIO_WriteHigh src\stm8s_gpio.c 143;" function signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins) -GPIO_WriteLow inc\stm8s_gpio.h 137;" prototype signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins) -GPIO_WriteLow src\stm8s_gpio.c 157;" function signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins) -GPIO_WriteReverse inc\stm8s_gpio.h 138;" prototype signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins) -GPIO_WriteReverse src\stm8s_gpio.c 171;" function signature:(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins) -GPIO_struct inc\stm8s.h 107;" struct -GTR inc\stm8s.h 1652;" member struct:UART1_struct -GTR inc\stm8s.h 1751;" member struct:UART2_struct -HDMI_ReadI2C_Byte inc\i2c_master.h 25;" prototype signature:(u8 RegAddr) -HDMI_ReadI2C_Byte src\i2c_master.c 228;" function signature:(u8 RegAddr) -HDMI_ReadI2C_ByteN inc\i2c_master.h 26;" prototype signature:(u8 RegAddr,u8 *p_data,u8 N) -HDMI_ReadI2C_ByteN src\i2c_master.c 239;" function signature:(u8 RegAddr,u8 *p_data,u8 N) -HDMI_WriteI2C_Byte inc\i2c_master.h 27;" prototype signature:(u8 RegAddr, u8 d) -HDMI_WriteI2C_Byte src\i2c_master.c 248;" function signature:(u8 RegAddr, u8 d) -HDMI_WriteI2C_ByteN inc\i2c_master.h 28;" prototype signature:(u8 RegAddr, u8 *d,u8 N) -HDMI_WriteI2C_ByteN src\i2c_master.c 257;" function signature:(u8 RegAddr, u8 *d,u8 N) -HIGH inc\stm8s_type.h 77;" enumerator enum:__anon27 -HSE_VALUE inc\stm8s_conf.h 40;" macro -HSE_VALUE inc\stm8s_conf.h 42;" macro -HSIDivFactor src\stm8s_clk.c 39;" variable -HSITRIMR inc\stm8s.h 371;" member struct:CLK_struct -HSI_VALUE inc\stm8s_clk.h 221;" macro -HTRH inc\stm8s.h 166;" member struct:ADC1_struct -HTRL inc\stm8s.h 167;" member struct:ADC1_struct -Hdcpmode main.c 144;" function signature:(void) -Hdmimodepol main.c 170;" function signature:(void) -I2C inc\stm8s.h 2439;" macro -I2CADR src\i2c_master.c 13;" variable -I2C_BaseAddress inc\stm8s.h 2360;" macro -I2C_CCRH_CCR inc\stm8s.h 1285;" macro -I2C_CCRH_DUTY inc\stm8s.h 1284;" macro -I2C_CCRH_FS inc\stm8s.h 1283;" macro -I2C_CCRH_RESET_VALUE inc\stm8s.h 1226;" macro -I2C_CCRL_CCR inc\stm8s.h 1281;" macro -I2C_CCRL_RESET_VALUE inc\stm8s.h 1225;" macro -I2C_CR1_ENGC inc\stm8s.h 1238;" macro -I2C_CR1_NOSTRETCH inc\stm8s.h 1237;" macro -I2C_CR1_PE inc\stm8s.h 1239;" macro -I2C_CR1_RESET_VALUE inc\stm8s.h 1215;" macro -I2C_CR2_ACK inc\stm8s.h 1243;" macro -I2C_CR2_POS inc\stm8s.h 1242;" macro -I2C_CR2_RESET_VALUE inc\stm8s.h 1216;" macro -I2C_CR2_START inc\stm8s.h 1245;" macro -I2C_CR2_STOP inc\stm8s.h 1244;" macro -I2C_CR2_SWRST inc\stm8s.h 1241;" macro -I2C_DR_DR inc\stm8s.h 1256;" macro -I2C_DR_RESET_VALUE inc\stm8s.h 1220;" macro -I2C_FREQR_FREQ inc\stm8s.h 1247;" macro -I2C_FREQR_RESET_VALUE inc\stm8s.h 1217;" macro -I2C_IRQHandler inc\stm8s_it.h 43;" prototype signature:(void) -I2C_ITR_ITBUFEN inc\stm8s.h 1277;" macro -I2C_ITR_ITERREN inc\stm8s.h 1279;" macro -I2C_ITR_ITEVTEN inc\stm8s.h 1278;" macro -I2C_ITR_RESET_VALUE inc\stm8s.h 1224;" macro -I2C_OARH_ADD inc\stm8s.h 1254;" macro -I2C_OARH_ADDCONF inc\stm8s.h 1253;" macro -I2C_OARH_ADDMODE inc\stm8s.h 1252;" macro -I2C_OARH_RESET_VALUE inc\stm8s.h 1219;" macro -I2C_OARL_ADD inc\stm8s.h 1249;" macro -I2C_OARL_ADD0 inc\stm8s.h 1250;" macro -I2C_OARL_RESET_VALUE inc\stm8s.h 1218;" macro -I2C_SR1_ADD10 inc\stm8s.h 1261;" macro -I2C_SR1_ADDR inc\stm8s.h 1263;" macro -I2C_SR1_BTF inc\stm8s.h 1262;" macro -I2C_SR1_RESET_VALUE inc\stm8s.h 1221;" macro -I2C_SR1_RXNE inc\stm8s.h 1259;" macro -I2C_SR1_SB inc\stm8s.h 1264;" macro -I2C_SR1_STOPF inc\stm8s.h 1260;" macro -I2C_SR1_TXE inc\stm8s.h 1258;" macro -I2C_SR2_AF inc\stm8s.h 1268;" macro -I2C_SR2_ARLO inc\stm8s.h 1269;" macro -I2C_SR2_BERR inc\stm8s.h 1270;" macro -I2C_SR2_OVR inc\stm8s.h 1267;" macro -I2C_SR2_RESET_VALUE inc\stm8s.h 1222;" macro -I2C_SR2_WUFH inc\stm8s.h 1266;" macro -I2C_SR3_BUSY inc\stm8s.h 1274;" macro -I2C_SR3_GENCALL inc\stm8s.h 1272;" macro -I2C_SR3_MSL inc\stm8s.h 1275;" macro -I2C_SR3_RESET_VALUE inc\stm8s.h 1223;" macro -I2C_SR3_TRA inc\stm8s.h 1273;" macro -I2C_SendByte src\i2c_master.c 71;" function signature:(u8 c) -I2C_TRISER_RESET_VALUE inc\stm8s.h 1227;" macro -I2C_TRISER_TRISE inc\stm8s.h 1287;" macro -I2C_TypeDef inc\stm8s.h 1209;" typedef typeref:struct:I2C_struct -I2C_master_Port src\i2c_master.c 15;" variable -I2C_master_SCL src\i2c_master.c 17;" variable -I2C_master_SDA src\i2c_master.c 16;" variable -I2C_struct inc\stm8s.h 1191;" struct -IAPSR inc\stm8s.h 1384;" member struct:FLASH_struct -ICKR inc\stm8s.h 359;" member struct:CLK_struct -ICR inc\stm8s.h 1563;" member struct:SPI_struct -IDR inc\stm8s.h 110;" member struct:GPIO_struct -IER inc\stm8s.h 1124;" member struct:TIM6_struct -IER inc\stm8s.h 1947;" member struct:__anon1 -IER inc\stm8s.h 471;" member struct:TIM1_struct -IER inc\stm8s.h 685;" member struct:TIM2_struct -IER inc\stm8s.h 809;" member struct:TIM3_struct -IER inc\stm8s.h 920;" member struct:TIM4_struct -IER inc\stm8s.h 981;" member struct:TIM5_struct -ISPR1 inc\stm8s.h 1300;" member struct:ITC_struct -ISPR2 inc\stm8s.h 1301;" member struct:ITC_struct -ISPR3 inc\stm8s.h 1302;" member struct:ITC_struct -ISPR4 inc\stm8s.h 1303;" member struct:ITC_struct -ISPR5 inc\stm8s.h 1304;" member struct:ITC_struct -ISPR6 inc\stm8s.h 1305;" member struct:ITC_struct -ISPR7 inc\stm8s.h 1306;" member struct:ITC_struct -ISPR8 inc\stm8s.h 1307;" member struct:ITC_struct -IS_CLK_CANDIVIDER_OK inc\stm8s_clk.h 358;" macro -IS_CLK_CSSCONFIG_OK inc\stm8s_clk.h 250;" macro -IS_CLK_CURRENTCLOCKSTATE_OK inc\stm8s_clk.h 245;" macro -IS_CLK_FLAG_OK inc\stm8s_clk.h 311;" macro -IS_CLK_HSIPRESCALER_OK inc\stm8s_clk.h 329;" macro -IS_CLK_HSITRIMVALUE_OK inc\stm8s_clk.h 264;" macro -IS_CLK_IT_OK inc\stm8s_clk.h 324;" macro -IS_CLK_OUTPUT_OK inc\stm8s_clk.h 276;" macro -IS_CLK_PERIPHERAL_OK inc\stm8s_clk.h 293;" macro -IS_CLK_PRESCALER_OK inc\stm8s_clk.h 337;" macro -IS_CLK_SOURCE_OK inc\stm8s_clk.h 257;" macro -IS_CLK_SWIMDIVIDER_OK inc\stm8s_clk.h 353;" macro -IS_CLK_SWITCHMODE_OK inc\stm8s_clk.h 240;" macro -IS_EXTI_PINMASK_OK inc\stm8s_exti.h 103;" macro -IS_EXTI_PORT_OK inc\stm8s_exti.h 93;" macro -IS_EXTI_SENSITIVITY_OK inc\stm8s_exti.h 77;" macro -IS_EXTI_TLISENSITIVITY_OK inc\stm8s_exti.h 86;" macro -IS_FUNCTIONALSTATE_OK inc\stm8s_type.h 93;" macro -IS_GPIO_MODE_OK inc\stm8s_gpio.h 104;" macro -IS_GPIO_PIN_OK inc\stm8s_gpio.h 122;" macro -IS_ITC_INTERRUPTS_DISABLED inc\stm8s_itc.h 144;" macro -IS_ITC_IRQ_OK inc\stm8s_itc.h 134;" macro -IS_ITC_PRIORITY_OK inc\stm8s_itc.h 137;" macro -IS_IWDG_PRESCALER_OK inc\stm8s_iwdg.h 61;" macro -IS_IWDG_WRITEACCESS_MODE_OK inc\stm8s_iwdg.h 73;" macro -IS_STATE_VALUE_OK inc\stm8s.h 2540;" macro -IS_STATE_VALUE_OK inc\stm8s_macro.h 96;" macro -ITC inc\stm8s.h 2472;" macro -ITC_BaseAddress inc\stm8s.h 2376;" macro -ITC_DeInit inc\stm8s_itc.h 157;" prototype signature:(void) -ITC_DeInit src\stm8s_itc.c 71;" function signature:(void) -ITC_GetCPUCC inc\stm8s_itc.h 156;" prototype signature:(void) -ITC_GetCPUCC src\stm8s_itc.c 42;" function signature:(void) -ITC_GetSoftIntStatus inc\stm8s_itc.h 158;" prototype signature:(void) -ITC_GetSoftIntStatus src\stm8s_itc.c 89;" function signature:(void) -ITC_GetSoftwarePriority inc\stm8s_itc.h 160;" prototype signature:(ITC_Irq_TypeDef IrqNum) -ITC_GetSoftwarePriority src\stm8s_itc.c 99;" function signature:(ITC_Irq_TypeDef IrqNum) -ITC_IRQ_ADC1 inc\stm8s_itc.h 87;" enumerator enum:__anon33 -ITC_IRQ_ADC2 inc\stm8s_itc.h 83;" enumerator enum:__anon33 -ITC_IRQ_AWU inc\stm8s_itc.h 40;" enumerator enum:__anon33 -ITC_IRQ_CAN_RX inc\stm8s_itc.h 49;" enumerator enum:__anon33 -ITC_IRQ_CAN_TX inc\stm8s_itc.h 50;" enumerator enum:__anon33 -ITC_IRQ_CLK inc\stm8s_itc.h 41;" enumerator enum:__anon33 -ITC_IRQ_EEPROM_EEC inc\stm8s_itc.h 96;" enumerator enum:__anon33 -ITC_IRQ_I2C inc\stm8s_itc.h 73;" enumerator enum:__anon33 -ITC_IRQ_PORTA inc\stm8s_itc.h 42;" enumerator enum:__anon33 -ITC_IRQ_PORTB inc\stm8s_itc.h 43;" enumerator enum:__anon33 -ITC_IRQ_PORTC inc\stm8s_itc.h 44;" enumerator enum:__anon33 -ITC_IRQ_PORTD inc\stm8s_itc.h 45;" enumerator enum:__anon33 -ITC_IRQ_PORTE inc\stm8s_itc.h 46;" enumerator enum:__anon33 -ITC_IRQ_PORTF inc\stm8s_itc.h 54;" enumerator enum:__anon33 -ITC_IRQ_SPI inc\stm8s_itc.h 57;" enumerator enum:__anon33 -ITC_IRQ_TIM1_CAPCOM inc\stm8s_itc.h 59;" enumerator enum:__anon33 -ITC_IRQ_TIM1_OVF inc\stm8s_itc.h 58;" enumerator enum:__anon33 -ITC_IRQ_TIM3_CAPCOM inc\stm8s_itc.h 70;" enumerator enum:__anon33 -ITC_IRQ_TIM3_OVF inc\stm8s_itc.h 69;" enumerator enum:__anon33 -ITC_IRQ_TIM5_CAPCOM inc\stm8s_itc.h 63;" enumerator enum:__anon33 -ITC_IRQ_TIM5_OVFTRI inc\stm8s_itc.h 62;" enumerator enum:__anon33 -ITC_IRQ_TIM6_OVFTRI inc\stm8s_itc.h 91;" enumerator enum:__anon33 -ITC_IRQ_TLI inc\stm8s_itc.h 39;" enumerator enum:__anon33 -ITC_IRQ_UART1_RX inc\stm8s_itc.h 72;" enumerator enum:__anon33 -ITC_IRQ_UART1_TX inc\stm8s_itc.h 71;" enumerator enum:__anon33 -ITC_IRQ_UART2_RX inc\stm8s_itc.h 77;" enumerator enum:__anon33 -ITC_IRQ_UART2_TX inc\stm8s_itc.h 76;" enumerator enum:__anon33 -ITC_IRQ_UART3_RX inc\stm8s_itc.h 82;" enumerator enum:__anon33 -ITC_IRQ_UART3_TX inc\stm8s_itc.h 81;" enumerator enum:__anon33 -ITC_Irq_TypeDef inc\stm8s_itc.h 97;" typedef typeref:enum:__anon33 -ITC_PRIORITYLEVEL_0 inc\stm8s_itc.h 103;" enumerator enum:__anon34 -ITC_PRIORITYLEVEL_1 inc\stm8s_itc.h 104;" enumerator enum:__anon34 -ITC_PRIORITYLEVEL_2 inc\stm8s_itc.h 105;" enumerator enum:__anon34 -ITC_PRIORITYLEVEL_3 inc\stm8s_itc.h 106;" enumerator enum:__anon34 -ITC_PriorityLevel_TypeDef inc\stm8s_itc.h 107;" typedef typeref:enum:__anon34 -ITC_SPRX_RESET_VALUE inc\stm8s.h 1315;" macro -ITC_SetSoftwarePriority inc\stm8s_itc.h 159;" prototype signature:(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue) -ITC_SetSoftwarePriority src\stm8s_itc.c 201;" function signature:(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue) -ITC_TypeDef inc\stm8s.h 1309;" typedef typeref:struct:ITC_struct -ITC_struct inc\stm8s.h 1298;" struct -ITR inc\stm8s.h 1203;" member struct:I2C_struct -ITStatus inc\stm8s_type.h 85;" typedef typeref:enum:__anon28 -IWDG inc\stm8s.h 2436;" macro -IWDG_BaseAddress inc\stm8s.h 2356;" macro -IWDG_Enable inc\stm8s_iwdg.h 118;" prototype signature:(void) -IWDG_KEY_ENABLE inc\stm8s_iwdg.h 45;" macro -IWDG_KEY_REFRESH inc\stm8s_iwdg.h 40;" macro -IWDG_PR_RESET_VALUE inc\stm8s.h 1484;" macro -IWDG_Prescaler_128 inc\stm8s_iwdg.h 100;" enumerator enum:__anon36 -IWDG_Prescaler_16 inc\stm8s_iwdg.h 97;" enumerator enum:__anon36 -IWDG_Prescaler_256 inc\stm8s_iwdg.h 101;" enumerator enum:__anon36 -IWDG_Prescaler_32 inc\stm8s_iwdg.h 98;" enumerator enum:__anon36 -IWDG_Prescaler_4 inc\stm8s_iwdg.h 95;" enumerator enum:__anon36 -IWDG_Prescaler_64 inc\stm8s_iwdg.h 99;" enumerator enum:__anon36 -IWDG_Prescaler_8 inc\stm8s_iwdg.h 96;" enumerator enum:__anon36 -IWDG_Prescaler_TypeDef inc\stm8s_iwdg.h 102;" typedef typeref:enum:__anon36 -IWDG_RLR_RESET_VALUE inc\stm8s.h 1485;" macro -IWDG_ReloadCounter inc\stm8s_iwdg.h 117;" prototype signature:(void) -IWDG_SetPrescaler inc\stm8s_iwdg.h 115;" prototype signature:(IWDG_Prescaler_TypeDef IWDG_Prescaler) -IWDG_SetReload inc\stm8s_iwdg.h 116;" prototype signature:(u8 Reload) -IWDG_TypeDef inc\stm8s.h 1478;" typedef typeref:struct:IWDG_struct -IWDG_WriteAccessCmd inc\stm8s_iwdg.h 114;" prototype signature:(IWDG_WriteAccess_TypeDef IWDG_WriteAccess) -IWDG_WriteAccess_Disable inc\stm8s_iwdg.h 89;" enumerator enum:__anon35 -IWDG_WriteAccess_Enable inc\stm8s_iwdg.h 88;" enumerator enum:__anon35 -IWDG_WriteAccess_TypeDef inc\stm8s_iwdg.h 90;" typedef typeref:enum:__anon35 -IWDG_struct inc\stm8s.h 1472;" struct -Initstate main.c 92;" function signature:(void) -Initstate_LT8619C main.c 102;" function signature:(void) -InterruptInit main.c 151;" function signature:(void) -KR inc\stm8s.h 1474;" member struct:IWDG_struct -LOW inc\stm8s_type.h 76;" enumerator enum:__anon27 -LSI_VALUE inc\stm8s_clk.h 222;" macro -LT8618EX_ADR inc\lt8522ex.h 13;" macro -LT8618EX_ADR_last inc\lt8522ex.h 14;" macro -LTRH inc\stm8s.h 168;" member struct:ADC1_struct -LTRL inc\stm8s.h 169;" member struct:ADC1_struct -MCR inc\stm8s.h 1942;" member struct:__anon1 -MCSR inc\stm8s.h 1955;" member struct:__anon1::__anon2::__anon3 -MDAR1 inc\stm8s.h 1961;" member struct:__anon1::__anon2::__anon3 -MDAR1 inc\stm8s.h 2089;" member struct:__anon1::__anon2::__anon9 -MDAR2 inc\stm8s.h 1962;" member struct:__anon1::__anon2::__anon3 -MDAR2 inc\stm8s.h 2090;" member struct:__anon1::__anon2::__anon9 -MDAR3 inc\stm8s.h 1963;" member struct:__anon1::__anon2::__anon3 -MDAR3 inc\stm8s.h 2091;" member struct:__anon1::__anon2::__anon9 -MDAR4 inc\stm8s.h 1964;" member struct:__anon1::__anon2::__anon3 -MDAR4 inc\stm8s.h 2092;" member struct:__anon1::__anon2::__anon9 -MDAR5 inc\stm8s.h 1965;" member struct:__anon1::__anon2::__anon3 -MDAR5 inc\stm8s.h 2093;" member struct:__anon1::__anon2::__anon9 -MDAR6 inc\stm8s.h 1966;" member struct:__anon1::__anon2::__anon3 -MDAR6 inc\stm8s.h 2094;" member struct:__anon1::__anon2::__anon9 -MDAR7 inc\stm8s.h 1967;" member struct:__anon1::__anon2::__anon3 -MDAR7 inc\stm8s.h 2095;" member struct:__anon1::__anon2::__anon9 -MDAR8 inc\stm8s.h 1968;" member struct:__anon1::__anon2::__anon3 -MDAR8 inc\stm8s.h 2096;" member struct:__anon1::__anon2::__anon9 -MDLCR inc\stm8s.h 1956;" member struct:__anon1::__anon2::__anon3 -MDLCR inc\stm8s.h 2084;" member struct:__anon1::__anon2::__anon9 -MFMI inc\stm8s.h 2083;" member struct:__anon1::__anon2::__anon9 -MIDR1 inc\stm8s.h 1957;" member struct:__anon1::__anon2::__anon3 -MIDR1 inc\stm8s.h 2085;" member struct:__anon1::__anon2::__anon9 -MIDR2 inc\stm8s.h 1958;" member struct:__anon1::__anon2::__anon3 -MIDR2 inc\stm8s.h 2086;" member struct:__anon1::__anon2::__anon9 -MIDR3 inc\stm8s.h 1959;" member struct:__anon1::__anon2::__anon3 -MIDR3 inc\stm8s.h 2087;" member struct:__anon1::__anon2::__anon9 -MIDR4 inc\stm8s.h 1960;" member struct:__anon1::__anon2::__anon3 -MIDR4 inc\stm8s.h 2088;" member struct:__anon1::__anon2::__anon9 -MSR inc\stm8s.h 1943;" member struct:__anon1 -MTSRH inc\stm8s.h 1970;" member struct:__anon1::__anon2::__anon3 -MTSRH inc\stm8s.h 2098;" member struct:__anon1::__anon2::__anon9 -MTSRL inc\stm8s.h 1969;" member struct:__anon1::__anon2::__anon3 -MTSRL inc\stm8s.h 2097;" member struct:__anon1::__anon2::__anon9 -Manual_load main.c 215;" function signature:(void) -MskBit inc\stm8s.h 2530;" macro -MskBit inc\stm8s_macro.h 85;" macro -NCR2 inc\stm8s.h 1381;" member struct:FLASH_struct -NEAR inc\stm8s.h 67;" macro -NEAR inc\stm8s.h 72;" macro -NFPR inc\stm8s.h 1383;" member struct:FLASH_struct -NOPT1 inc\stm8s.h 1451;" member struct:OPT_struct -NOPT2 inc\stm8s.h 1453;" member struct:OPT_struct -NOPT3 inc\stm8s.h 1455;" member struct:OPT_struct -NOPT4 inc\stm8s.h 1457;" member struct:OPT_struct -NOPT5 inc\stm8s.h 1459;" member struct:OPT_struct -NOPT7 inc\stm8s.h 1463;" member struct:OPT_struct -NonHandledInterrupt inc\stm8s_it.h 34;" prototype signature:(void) -NonHandledInterrupt stm8_interrupt_vector.c 12;" function signature:(void) -OARH inc\stm8s.h 1197;" member struct:I2C_struct -OARL inc\stm8s.h 1196;" member struct:I2C_struct -ODR inc\stm8s.h 109;" member struct:GPIO_struct -OFF inc\stm8s_type.h 69;" enumerator enum:__anon26 -OISR inc\stm8s.h 498;" member struct:TIM1_struct -ON inc\stm8s_type.h 70;" enumerator enum:__anon26 -ONCHIP_EDID main.c 26;" variable -OPT inc\stm8s.h 2410;" macro -OPT0 inc\stm8s.h 1449;" member struct:OPT_struct -OPT1 inc\stm8s.h 1450;" member struct:OPT_struct -OPT2 inc\stm8s.h 1452;" member struct:OPT_struct -OPT3 inc\stm8s.h 1454;" member struct:OPT_struct -OPT4 inc\stm8s.h 1456;" member struct:OPT_struct -OPT5 inc\stm8s.h 1458;" member struct:OPT_struct -OPT7 inc\stm8s.h 1462;" member struct:OPT_struct -OPT_BaseAddress inc\stm8s.h 2339;" macro -OPT_TypeDef inc\stm8s.h 1465;" typedef typeref:struct:OPT_struct -OPT_struct inc\stm8s.h 1447;" struct -OpenAudio main.c 117;" function signature:(void) -OpenVideo main.c 127;" function signature:(void) -Out_Ycbcr444 main.c 12;" macro file: -PCKENR1 inc\stm8s.h 366;" member struct:CLK_struct -PCKENR2 inc\stm8s.h 369;" member struct:CLK_struct -PR inc\stm8s.h 1475;" member struct:IWDG_struct -PSCR inc\stm8s.h 1128;" member struct:TIM6_struct -PSCR inc\stm8s.h 1653;" member struct:UART1_struct -PSCR inc\stm8s.h 1752;" member struct:UART2_struct -PSCR inc\stm8s.h 696;" member struct:TIM2_struct -PSCR inc\stm8s.h 818;" member struct:TIM3_struct -PSCR inc\stm8s.h 924;" member struct:TIM4_struct -PSCR inc\stm8s.h 992;" member struct:TIM5_struct -PSCRH inc\stm8s.h 483;" member struct:TIM1_struct -PSCRL inc\stm8s.h 484;" member struct:TIM1_struct -PSR inc\stm8s.h 1949;" member struct:__anon1 -PUKR inc\stm8s.h 1387;" member struct:FLASH_struct -Packetconfig main.c 181;" function signature:(u8 checksum,u8 output) -Page inc\stm8s.h 2101;" member struct:__anon1 typeref:union:__anon1::__anon2 -Pin_Status inc\stm8s_type.h 79;" typedef typeref:enum:__anon27 -PointerAttr inc\stm8s.h 78;" macro -PointerAttr inc\stm8s.h 80;" macro -PointerAttr_Far inc\stm8s.h 63;" macro -RCR inc\stm8s.h 487;" member struct:TIM1_struct -RECR inc\stm8s.h 2068;" member struct:__anon1::__anon2::__anon8 -RESERVED inc\stm8s.h 157;" member struct:ADC1_struct -RESERVED inc\stm8s.h 1857;" member struct:UART3_struct -RESERVED inc\stm8s.h 235;" member struct:ADC2_struct -RESERVED inc\stm8s.h 361;" member struct:CLK_struct -RESERVED1 inc\stm8s.h 1198;" member struct:I2C_struct -RESERVED1 inc\stm8s.h 1385;" member struct:FLASH_struct -RESERVED1 inc\stm8s.h 1460;" member struct:OPT_struct -RESERVED1 inc\stm8s.h 682;" member struct:TIM2_struct -RESERVED1 inc\stm8s.h 917;" member struct:TIM4_struct -RESERVED2 inc\stm8s.h 1207;" member struct:I2C_struct -RESERVED2 inc\stm8s.h 1386;" member struct:FLASH_struct -RESERVED2 inc\stm8s.h 1461;" member struct:OPT_struct -RESERVED2 inc\stm8s.h 683;" member struct:TIM2_struct -RESERVED2 inc\stm8s.h 918;" member struct:TIM4_struct -RESERVED3 inc\stm8s.h 1388;" member struct:FLASH_struct -RESET inc\stm8s_type.h 82;" enumerator enum:__anon28 -RESET_Lt8618EX main.c 85;" function signature:(void) -RFR inc\stm8s.h 1946;" member struct:__anon1 -RGB888_24bit main.c 290;" function signature:(void) -RLR inc\stm8s.h 1476;" member struct:IWDG_struct -RST inc\stm8s.h 2433;" macro -RST_BaseAddress inc\stm8s.h 2353;" macro -RST_SR_EMCF inc\stm8s.h 1544;" macro -RST_SR_ILLOPF inc\stm8s.h 1546;" macro -RST_SR_IWDGF inc\stm8s.h 1547;" macro -RST_SR_SWIMF inc\stm8s.h 1545;" macro -RST_SR_WWDGF inc\stm8s.h 1548;" macro -RST_TypeDef inc\stm8s.h 1538;" typedef typeref:struct:RST_struct -RST_struct inc\stm8s.h 1534;" struct -RXCRCR inc\stm8s.h 1567;" member struct:SPI_struct -RcvByte src\i2c_master.c 110;" function signature:(void) -ReadEdid_1 main.c 260;" function signature:(void) -ReadEdid_2 main.c 275;" function signature:(void) -Reserved1 inc\stm8s.h 2071;" member struct:__anon1::__anon2::__anon8 -Reserved2 inc\stm8s.h 2077;" member struct:__anon1::__anon2::__anon8 -RxFIFO inc\stm8s.h 2100;" member union:__anon1::__anon2 typeref:struct:__anon1::__anon2::__anon9 -S16_MAX inc\stm8s_type.h 115;" macro -S16_MIN inc\stm8s_type.h 116;" macro -S32_MAX inc\stm8s_type.h 118;" macro -S32_MIN inc\stm8s_type.h 119;" macro -S8_MAX inc\stm8s_type.h 112;" macro -S8_MIN inc\stm8s_type.h 113;" macro -SET inc\stm8s_type.h 83;" enumerator enum:__anon28 -SET_LT8522EX_RESET main.c 9;" macro file: -SET_MASTER_SCL src\i2c_master.c 21;" macro file: -SET_MASTER_SDA src\i2c_master.c 20;" macro file: -SMCR inc\stm8s.h 1123;" member struct:TIM6_struct -SMCR inc\stm8s.h 469;" member struct:TIM1_struct -SMCR inc\stm8s.h 980;" member struct:TIM5_struct -SPI inc\stm8s.h 2438;" macro -SPI_BaseAddress inc\stm8s.h 2359;" macro -SPI_CR1_BR inc\stm8s.h 1595;" macro -SPI_CR1_CPHA inc\stm8s.h 1598;" macro -SPI_CR1_CPOL inc\stm8s.h 1597;" macro -SPI_CR1_LSBFIRST inc\stm8s.h 1593;" macro -SPI_CR1_MSTR inc\stm8s.h 1596;" macro -SPI_CR1_RESET_VALUE inc\stm8s.h 1576;" macro -SPI_CR1_SPE inc\stm8s.h 1594;" macro -SPI_CR2_BDM inc\stm8s.h 1600;" macro -SPI_CR2_BDOE inc\stm8s.h 1601;" macro -SPI_CR2_CRCEN inc\stm8s.h 1602;" macro -SPI_CR2_CRCNEXT inc\stm8s.h 1603;" macro -SPI_CR2_RESET_VALUE inc\stm8s.h 1577;" macro -SPI_CR2_RXONLY inc\stm8s.h 1604;" macro -SPI_CR2_SSI inc\stm8s.h 1606;" macro -SPI_CR2_SSM inc\stm8s.h 1605;" macro -SPI_CRCPR_RESET_VALUE inc\stm8s.h 1581;" macro -SPI_DR_RESET_VALUE inc\stm8s.h 1580;" macro -SPI_ICR_ERRIE inc\stm8s.h 1610;" macro -SPI_ICR_RESET_VALUE inc\stm8s.h 1578;" macro -SPI_ICR_RXEI inc\stm8s.h 1609;" macro -SPI_ICR_TXEI inc\stm8s.h 1608;" macro -SPI_ICR_WKIE inc\stm8s.h 1611;" macro -SPI_IRQHandler inc\stm8s_it.h 52;" prototype signature:(void) -SPI_RXCRCR_RESET_VALUE inc\stm8s.h 1582;" macro -SPI_SR_BSY inc\stm8s.h 1613;" macro -SPI_SR_CRCERR inc\stm8s.h 1616;" macro -SPI_SR_MODF inc\stm8s.h 1615;" macro -SPI_SR_OVR inc\stm8s.h 1614;" macro -SPI_SR_RESET_VALUE inc\stm8s.h 1579;" macro -SPI_SR_RXNE inc\stm8s.h 1619;" macro -SPI_SR_TXE inc\stm8s.h 1618;" macro -SPI_SR_WKUP inc\stm8s.h 1617;" macro -SPI_TXCRCR_RESET_VALUE inc\stm8s.h 1583;" macro -SPI_TypeDef inc\stm8s.h 1570;" typedef typeref:struct:SPI_struct -SPI_struct inc\stm8s.h 1559;" struct -SR inc\stm8s.h 1536;" member struct:RST_struct -SR inc\stm8s.h 1564;" member struct:SPI_struct -SR inc\stm8s.h 1643;" member struct:UART1_struct -SR inc\stm8s.h 1741;" member struct:UART2_struct -SR inc\stm8s.h 1849;" member struct:UART3_struct -SR1 inc\stm8s.h 1125;" member struct:TIM6_struct -SR1 inc\stm8s.h 1200;" member struct:I2C_struct -SR1 inc\stm8s.h 472;" member struct:TIM1_struct -SR1 inc\stm8s.h 686;" member struct:TIM2_struct -SR1 inc\stm8s.h 810;" member struct:TIM3_struct -SR1 inc\stm8s.h 921;" member struct:TIM4_struct -SR1 inc\stm8s.h 982;" member struct:TIM5_struct -SR2 inc\stm8s.h 1201;" member struct:I2C_struct -SR2 inc\stm8s.h 473;" member struct:TIM1_struct -SR2 inc\stm8s.h 687;" member struct:TIM2_struct -SR2 inc\stm8s.h 811;" member struct:TIM3_struct -SR2 inc\stm8s.h 983;" member struct:TIM5_struct -SR3 inc\stm8s.h 1202;" member struct:I2C_struct -STM8S103 inc\stm8s.h 48;" macro -SUCCESS inc\stm8s_type.h 97;" enumerator enum:__anon30 -SWCR inc\stm8s.h 364;" member struct:CLK_struct -SWIM inc\stm8s.h 2476;" macro -SWIMCCR inc\stm8s.h 372;" member struct:CLK_struct -SWIM_BaseAddress inc\stm8s.h 2377;" macro -SWIM_TypeDef inc\stm8s.h 1634;" typedef typeref:struct:SWIM_struct -SWIM_struct inc\stm8s.h 1629;" struct -SWR inc\stm8s.h 363;" member struct:CLK_struct -SetBit inc\stm8s.h 2523;" macro -SetBit inc\stm8s_macro.h 78;" macro -Sourceselect main.c 156;" function signature:(void) -Start_I2c src\i2c_master.c 47;" function signature:(void) -Stop_I2c src\i2c_master.c 60;" function signature:(void) -Swingset main.c 160;" function signature:(void) -Systeminit main.c 194;" function signature:(void) -TBR inc\stm8s.h 286;" member struct:AWU_struct -TDRH inc\stm8s.h 164;" member struct:ADC1_struct -TDRH inc\stm8s.h 238;" member struct:ADC2_struct -TDRL inc\stm8s.h 165;" member struct:ADC1_struct -TDRL inc\stm8s.h 239;" member struct:ADC2_struct -TECR inc\stm8s.h 2067;" member struct:__anon1::__anon2::__anon8 -TIM1 inc\stm8s.h 2453;" macro -TIM1_ARRH_ARR inc\stm8s.h 634;" macro -TIM1_ARRH_RESET_VALUE inc\stm8s.h 524;" macro -TIM1_ARRL_ARR inc\stm8s.h 635;" macro -TIM1_ARRL_RESET_VALUE inc\stm8s.h 525;" macro -TIM1_BKR_AOE inc\stm8s.h 652;" macro -TIM1_BKR_BKE inc\stm8s.h 654;" macro -TIM1_BKR_BKP inc\stm8s.h 653;" macro -TIM1_BKR_LOCK inc\stm8s.h 657;" macro -TIM1_BKR_MOE inc\stm8s.h 651;" macro -TIM1_BKR_OSSI inc\stm8s.h 656;" macro -TIM1_BKR_OSSR inc\stm8s.h 655;" macro -TIM1_BKR_RESET_VALUE inc\stm8s.h 535;" macro -TIM1_BaseAddress inc\stm8s.h 2364;" macro -TIM1_CAP_COM_IRQHandler inc\stm8s_it.h 50;" prototype signature:(void) -TIM1_CCER1_CC1E inc\stm8s.h 617;" macro -TIM1_CCER1_CC1NE inc\stm8s.h 615;" macro -TIM1_CCER1_CC1NP inc\stm8s.h 614;" macro -TIM1_CCER1_CC1P inc\stm8s.h 616;" macro -TIM1_CCER1_CC2E inc\stm8s.h 613;" macro -TIM1_CCER1_CC2NE inc\stm8s.h 611;" macro -TIM1_CCER1_CC2NP inc\stm8s.h 610;" macro -TIM1_CCER1_CC2P inc\stm8s.h 612;" macro -TIM1_CCER1_RESET_VALUE inc\stm8s.h 518;" macro -TIM1_CCER2_CC3E inc\stm8s.h 624;" macro -TIM1_CCER2_CC3NE inc\stm8s.h 622;" macro -TIM1_CCER2_CC3NP inc\stm8s.h 621;" macro -TIM1_CCER2_CC3P inc\stm8s.h 623;" macro -TIM1_CCER2_CC4E inc\stm8s.h 620;" macro -TIM1_CCER2_CC4P inc\stm8s.h 619;" macro -TIM1_CCER2_RESET_VALUE inc\stm8s.h 519;" macro -TIM1_CCMR1_RESET_VALUE inc\stm8s.h 514;" macro -TIM1_CCMR2_RESET_VALUE inc\stm8s.h 515;" macro -TIM1_CCMR3_RESET_VALUE inc\stm8s.h 516;" macro -TIM1_CCMR4_RESET_VALUE inc\stm8s.h 517;" macro -TIM1_CCMR_CCxS inc\stm8s.h 606;" macro -TIM1_CCMR_ICxF inc\stm8s.h 602;" macro -TIM1_CCMR_ICxPSC inc\stm8s.h 601;" macro -TIM1_CCMR_OCM inc\stm8s.h 603;" macro -TIM1_CCMR_OCxFE inc\stm8s.h 605;" macro -TIM1_CCMR_OCxPE inc\stm8s.h 604;" macro -TIM1_CCR1H_CCR1 inc\stm8s.h 639;" macro -TIM1_CCR1H_RESET_VALUE inc\stm8s.h 527;" macro -TIM1_CCR1L_CCR1 inc\stm8s.h 640;" macro -TIM1_CCR1L_RESET_VALUE inc\stm8s.h 528;" macro -TIM1_CCR2H_CCR2 inc\stm8s.h 642;" macro -TIM1_CCR2H_RESET_VALUE inc\stm8s.h 529;" macro -TIM1_CCR2L_CCR2 inc\stm8s.h 643;" macro -TIM1_CCR2L_RESET_VALUE inc\stm8s.h 530;" macro -TIM1_CCR3H_CCR3 inc\stm8s.h 645;" macro -TIM1_CCR3H_RESET_VALUE inc\stm8s.h 531;" macro -TIM1_CCR3L_CCR3 inc\stm8s.h 646;" macro -TIM1_CCR3L_RESET_VALUE inc\stm8s.h 532;" macro -TIM1_CCR4H_CCR4 inc\stm8s.h 648;" macro -TIM1_CCR4H_RESET_VALUE inc\stm8s.h 533;" macro -TIM1_CCR4L_CCR4 inc\stm8s.h 649;" macro -TIM1_CCR4L_RESET_VALUE inc\stm8s.h 534;" macro -TIM1_CNTRH_CNT inc\stm8s.h 626;" macro -TIM1_CNTRH_RESET_VALUE inc\stm8s.h 520;" macro -TIM1_CNTRL_CNT inc\stm8s.h 628;" macro -TIM1_CNTRL_RESET_VALUE inc\stm8s.h 521;" macro -TIM1_CR1_ARPE inc\stm8s.h 547;" macro -TIM1_CR1_CEN inc\stm8s.h 553;" macro -TIM1_CR1_CMS inc\stm8s.h 548;" macro -TIM1_CR1_DIR inc\stm8s.h 549;" macro -TIM1_CR1_OPM inc\stm8s.h 550;" macro -TIM1_CR1_RESET_VALUE inc\stm8s.h 506;" macro -TIM1_CR1_UDIS inc\stm8s.h 552;" macro -TIM1_CR1_URS inc\stm8s.h 551;" macro -TIM1_CR2_CCPC inc\stm8s.h 558;" macro -TIM1_CR2_COMS inc\stm8s.h 557;" macro -TIM1_CR2_MMS inc\stm8s.h 556;" macro -TIM1_CR2_RESET_VALUE inc\stm8s.h 507;" macro -TIM1_CR2_TI1S inc\stm8s.h 555;" macro -TIM1_DTR_DTG inc\stm8s.h 659;" macro -TIM1_DTR_RESET_VALUE inc\stm8s.h 536;" macro -TIM1_EGR_BG inc\stm8s.h 592;" macro -TIM1_EGR_CC1G inc\stm8s.h 598;" macro -TIM1_EGR_CC2G inc\stm8s.h 597;" macro -TIM1_EGR_CC3G inc\stm8s.h 596;" macro -TIM1_EGR_CC4G inc\stm8s.h 595;" macro -TIM1_EGR_COMG inc\stm8s.h 594;" macro -TIM1_EGR_RESET_VALUE inc\stm8s.h 513;" macro -TIM1_EGR_TG inc\stm8s.h 593;" macro -TIM1_EGR_UG inc\stm8s.h 599;" macro -TIM1_ETR_ECE inc\stm8s.h 565;" macro -TIM1_ETR_ETF inc\stm8s.h 567;" macro -TIM1_ETR_ETP inc\stm8s.h 564;" macro -TIM1_ETR_ETPS inc\stm8s.h 566;" macro -TIM1_ETR_RESET_VALUE inc\stm8s.h 509;" macro -TIM1_IER_BIE inc\stm8s.h 569;" macro -TIM1_IER_CC1IE inc\stm8s.h 575;" macro -TIM1_IER_CC2IE inc\stm8s.h 574;" macro -TIM1_IER_CC3IE inc\stm8s.h 573;" macro -TIM1_IER_CC4IE inc\stm8s.h 572;" macro -TIM1_IER_COMIE inc\stm8s.h 571;" macro -TIM1_IER_RESET_VALUE inc\stm8s.h 510;" macro -TIM1_IER_TIE inc\stm8s.h 570;" macro -TIM1_IER_UIE inc\stm8s.h 576;" macro -TIM1_OISR_OIS1 inc\stm8s.h 667;" macro -TIM1_OISR_OIS1N inc\stm8s.h 666;" macro -TIM1_OISR_OIS2 inc\stm8s.h 665;" macro -TIM1_OISR_OIS2N inc\stm8s.h 664;" macro -TIM1_OISR_OIS3 inc\stm8s.h 663;" macro -TIM1_OISR_OIS3N inc\stm8s.h 662;" macro -TIM1_OISR_OIS4 inc\stm8s.h 661;" macro -TIM1_OISR_RESET_VALUE inc\stm8s.h 537;" macro -TIM1_PSCH_PSC inc\stm8s.h 630;" macro -TIM1_PSCL_PSC inc\stm8s.h 632;" macro -TIM1_PSCRH_RESET_VALUE inc\stm8s.h 522;" macro -TIM1_PSCRL_RESET_VALUE inc\stm8s.h 523;" macro -TIM1_RCR_REP inc\stm8s.h 637;" macro -TIM1_RCR_RESET_VALUE inc\stm8s.h 526;" macro -TIM1_SMCR_MSM inc\stm8s.h 560;" macro -TIM1_SMCR_RESET_VALUE inc\stm8s.h 508;" macro -TIM1_SMCR_SMS inc\stm8s.h 562;" macro -TIM1_SMCR_TS inc\stm8s.h 561;" macro -TIM1_SR1_BIF inc\stm8s.h 578;" macro -TIM1_SR1_CC1IF inc\stm8s.h 584;" macro -TIM1_SR1_CC2IF inc\stm8s.h 583;" macro -TIM1_SR1_CC3IF inc\stm8s.h 582;" macro -TIM1_SR1_CC4IF inc\stm8s.h 581;" macro -TIM1_SR1_COMIF inc\stm8s.h 580;" macro -TIM1_SR1_RESET_VALUE inc\stm8s.h 511;" macro -TIM1_SR1_TIF inc\stm8s.h 579;" macro -TIM1_SR1_UIF inc\stm8s.h 585;" macro -TIM1_SR2_CC1OF inc\stm8s.h 590;" macro -TIM1_SR2_CC2OF inc\stm8s.h 589;" macro -TIM1_SR2_CC3OF inc\stm8s.h 588;" macro -TIM1_SR2_CC4OF inc\stm8s.h 587;" macro -TIM1_SR2_RESET_VALUE inc\stm8s.h 512;" macro -TIM1_TypeDef inc\stm8s.h 500;" typedef typeref:struct:TIM1_struct -TIM1_UPD_OVF_TRG_BRK_IRQHandler inc\stm8s_it.h 51;" prototype signature:(void) -TIM1_struct inc\stm8s.h 465;" struct -TIM2 inc\stm8s.h 2456;" macro -TIM2_ARRH_ARR inc\stm8s.h 786;" macro -TIM2_ARRH_RESET_VALUE inc\stm8s.h 725;" macro -TIM2_ARRL_ARR inc\stm8s.h 787;" macro -TIM2_ARRL_RESET_VALUE inc\stm8s.h 726;" macro -TIM2_BaseAddress inc\stm8s.h 2365;" macro -TIM2_CAP_COM_IRQHandler inc\stm8s_it.h 48;" prototype signature:(void) -TIM2_CCER1_CC1E inc\stm8s.h 776;" macro -TIM2_CCER1_CC1P inc\stm8s.h 775;" macro -TIM2_CCER1_CC2E inc\stm8s.h 774;" macro -TIM2_CCER1_CC2P inc\stm8s.h 773;" macro -TIM2_CCER1_RESET_VALUE inc\stm8s.h 720;" macro -TIM2_CCER2_CC3E inc\stm8s.h 779;" macro -TIM2_CCER2_CC3P inc\stm8s.h 778;" macro -TIM2_CCER2_RESET_VALUE inc\stm8s.h 721;" macro -TIM2_CCMR1_RESET_VALUE inc\stm8s.h 717;" macro -TIM2_CCMR2_RESET_VALUE inc\stm8s.h 718;" macro -TIM2_CCMR3_RESET_VALUE inc\stm8s.h 719;" macro -TIM2_CCMR_CCxS inc\stm8s.h 771;" macro -TIM2_CCMR_ICxF inc\stm8s.h 768;" macro -TIM2_CCMR_ICxPSC inc\stm8s.h 767;" macro -TIM2_CCMR_OCM inc\stm8s.h 769;" macro -TIM2_CCMR_OCxPE inc\stm8s.h 770;" macro -TIM2_CCR1H_CCR1 inc\stm8s.h 789;" macro -TIM2_CCR1H_RESET_VALUE inc\stm8s.h 727;" macro -TIM2_CCR1L_CCR1 inc\stm8s.h 790;" macro -TIM2_CCR1L_RESET_VALUE inc\stm8s.h 728;" macro -TIM2_CCR2H_CCR2 inc\stm8s.h 792;" macro -TIM2_CCR2H_RESET_VALUE inc\stm8s.h 729;" macro -TIM2_CCR2L_CCR2 inc\stm8s.h 793;" macro -TIM2_CCR2L_RESET_VALUE inc\stm8s.h 730;" macro -TIM2_CCR3H_CCR3 inc\stm8s.h 795;" macro -TIM2_CCR3H_RESET_VALUE inc\stm8s.h 731;" macro -TIM2_CCR3L_CCR3 inc\stm8s.h 796;" macro -TIM2_CCR3L_RESET_VALUE inc\stm8s.h 732;" macro -TIM2_CNTRH_CNT inc\stm8s.h 781;" macro -TIM2_CNTRH_RESET_VALUE inc\stm8s.h 722;" macro -TIM2_CNTRL_CNT inc\stm8s.h 782;" macro -TIM2_CNTRL_RESET_VALUE inc\stm8s.h 723;" macro -TIM2_CR1_ARPE inc\stm8s.h 742;" macro -TIM2_CR1_CEN inc\stm8s.h 746;" macro -TIM2_CR1_OPM inc\stm8s.h 743;" macro -TIM2_CR1_RESET_VALUE inc\stm8s.h 712;" macro -TIM2_CR1_UDIS inc\stm8s.h 745;" macro -TIM2_CR1_URS inc\stm8s.h 744;" macro -TIM2_EGR_CC1G inc\stm8s.h 764;" macro -TIM2_EGR_CC2G inc\stm8s.h 763;" macro -TIM2_EGR_CC3G inc\stm8s.h 762;" macro -TIM2_EGR_RESET_VALUE inc\stm8s.h 716;" macro -TIM2_EGR_UG inc\stm8s.h 765;" macro -TIM2_IER_CC1IE inc\stm8s.h 750;" macro -TIM2_IER_CC2IE inc\stm8s.h 749;" macro -TIM2_IER_CC3IE inc\stm8s.h 748;" macro -TIM2_IER_RESET_VALUE inc\stm8s.h 713;" macro -TIM2_IER_UIE inc\stm8s.h 751;" macro -TIM2_PSCR_PSC inc\stm8s.h 784;" macro -TIM2_PSCR_RESET_VALUE inc\stm8s.h 724;" macro -TIM2_SR1_CC1IF inc\stm8s.h 755;" macro -TIM2_SR1_CC2IF inc\stm8s.h 754;" macro -TIM2_SR1_CC3IF inc\stm8s.h 753;" macro -TIM2_SR1_RESET_VALUE inc\stm8s.h 714;" macro -TIM2_SR1_UIF inc\stm8s.h 756;" macro -TIM2_SR2_CC1OF inc\stm8s.h 760;" macro -TIM2_SR2_CC2OF inc\stm8s.h 759;" macro -TIM2_SR2_CC3OF inc\stm8s.h 758;" macro -TIM2_SR2_RESET_VALUE inc\stm8s.h 715;" macro -TIM2_TypeDef inc\stm8s.h 706;" typedef typeref:struct:TIM2_struct -TIM2_UPD_OVF_BRK_IRQHandler inc\stm8s_it.h 49;" prototype signature:(void) -TIM2_struct inc\stm8s.h 678;" struct -TIM3 inc\stm8s.h 2460;" macro -TIM3_ARRH_ARR inc\stm8s.h 895;" macro -TIM3_ARRH_RESET_VALUE inc\stm8s.h 843;" macro -TIM3_ARRL_ARR inc\stm8s.h 896;" macro -TIM3_ARRL_RESET_VALUE inc\stm8s.h 844;" macro -TIM3_BaseAddress inc\stm8s.h 2366;" macro -TIM3_CAP_COM_IRQHandler inc\stm8s_it.h 46;" prototype signature:(void) -TIM3_CCER1_CC1E inc\stm8s.h 888;" macro -TIM3_CCER1_CC1P inc\stm8s.h 887;" macro -TIM3_CCER1_CC2E inc\stm8s.h 886;" macro -TIM3_CCER1_CC2P inc\stm8s.h 885;" macro -TIM3_CCER1_RESET_VALUE inc\stm8s.h 839;" macro -TIM3_CCMR1_RESET_VALUE inc\stm8s.h 837;" macro -TIM3_CCMR2_RESET_VALUE inc\stm8s.h 838;" macro -TIM3_CCMR_CCxS inc\stm8s.h 883;" macro -TIM3_CCMR_ICxF inc\stm8s.h 880;" macro -TIM3_CCMR_ICxPSC inc\stm8s.h 879;" macro -TIM3_CCMR_OCM inc\stm8s.h 881;" macro -TIM3_CCMR_OCxPE inc\stm8s.h 882;" macro -TIM3_CCR1H_CCR1 inc\stm8s.h 898;" macro -TIM3_CCR1H_RESET_VALUE inc\stm8s.h 845;" macro -TIM3_CCR1L_CCR1 inc\stm8s.h 899;" macro -TIM3_CCR1L_RESET_VALUE inc\stm8s.h 846;" macro -TIM3_CCR2H_CCR2 inc\stm8s.h 901;" macro -TIM3_CCR2H_RESET_VALUE inc\stm8s.h 847;" macro -TIM3_CCR2L_CCR2 inc\stm8s.h 902;" macro -TIM3_CCR2L_RESET_VALUE inc\stm8s.h 848;" macro -TIM3_CNTRH_CNT inc\stm8s.h 890;" macro -TIM3_CNTRH_RESET_VALUE inc\stm8s.h 840;" macro -TIM3_CNTRL_CNT inc\stm8s.h 891;" macro -TIM3_CNTRL_RESET_VALUE inc\stm8s.h 841;" macro -TIM3_CR1_ARPE inc\stm8s.h 858;" macro -TIM3_CR1_CEN inc\stm8s.h 862;" macro -TIM3_CR1_OPM inc\stm8s.h 859;" macro -TIM3_CR1_RESET_VALUE inc\stm8s.h 832;" macro -TIM3_CR1_UDIS inc\stm8s.h 861;" macro -TIM3_CR1_URS inc\stm8s.h 860;" macro -TIM3_EGR_CC1G inc\stm8s.h 876;" macro -TIM3_EGR_CC2G inc\stm8s.h 875;" macro -TIM3_EGR_RESET_VALUE inc\stm8s.h 836;" macro -TIM3_EGR_UG inc\stm8s.h 877;" macro -TIM3_IER_CC1IE inc\stm8s.h 865;" macro -TIM3_IER_CC2IE inc\stm8s.h 864;" macro -TIM3_IER_RESET_VALUE inc\stm8s.h 833;" macro -TIM3_IER_UIE inc\stm8s.h 866;" macro -TIM3_PSCR_PSC inc\stm8s.h 893;" macro -TIM3_PSCR_RESET_VALUE inc\stm8s.h 842;" macro -TIM3_SR1_CC1IF inc\stm8s.h 869;" macro -TIM3_SR1_CC2IF inc\stm8s.h 868;" macro -TIM3_SR1_RESET_VALUE inc\stm8s.h 834;" macro -TIM3_SR1_UIF inc\stm8s.h 870;" macro -TIM3_SR2_CC1OF inc\stm8s.h 873;" macro -TIM3_SR2_CC2OF inc\stm8s.h 872;" macro -TIM3_SR2_RESET_VALUE inc\stm8s.h 835;" macro -TIM3_TypeDef inc\stm8s.h 826;" typedef typeref:struct:TIM3_struct -TIM3_UPD_OVF_BRK_IRQHandler inc\stm8s_it.h 47;" prototype signature:(void) -TIM3_struct inc\stm8s.h 806;" struct -TIM4 inc\stm8s.h 2464;" macro -TIM4_ARR_ARR inc\stm8s.h 965;" macro -TIM4_ARR_RESET_VALUE inc\stm8s.h 939;" macro -TIM4_BaseAddress inc\stm8s.h 2367;" macro -TIM4_CNTR_CNT inc\stm8s.h 961;" macro -TIM4_CNTR_RESET_VALUE inc\stm8s.h 937;" macro -TIM4_CR1_ARPE inc\stm8s.h 949;" macro -TIM4_CR1_CEN inc\stm8s.h 953;" macro -TIM4_CR1_OPM inc\stm8s.h 950;" macro -TIM4_CR1_RESET_VALUE inc\stm8s.h 933;" macro -TIM4_CR1_UDIS inc\stm8s.h 952;" macro -TIM4_CR1_URS inc\stm8s.h 951;" macro -TIM4_EGR_RESET_VALUE inc\stm8s.h 936;" macro -TIM4_EGR_UG inc\stm8s.h 959;" macro -TIM4_IER_RESET_VALUE inc\stm8s.h 934;" macro -TIM4_IER_UIE inc\stm8s.h 955;" macro -TIM4_PSCR_PSC inc\stm8s.h 963;" macro -TIM4_PSCR_RESET_VALUE inc\stm8s.h 938;" macro -TIM4_SR1_RESET_VALUE inc\stm8s.h 935;" macro -TIM4_SR1_UIF inc\stm8s.h 957;" macro -TIM4_TypeDef inc\stm8s.h 927;" typedef typeref:struct:TIM4_struct -TIM4_UPD_OVF_IRQHandler inc\stm8s_it.h 36;" prototype signature:(void) -TIM4_struct inc\stm8s.h 913;" struct -TIM5 inc\stm8s.h 2468;" macro -TIM5_ARRH_ARR inc\stm8s.h 1097;" macro -TIM5_ARRH_RESET_VALUE inc\stm8s.h 1022;" macro -TIM5_ARRL_ARR inc\stm8s.h 1098;" macro -TIM5_ARRL_RESET_VALUE inc\stm8s.h 1023;" macro -TIM5_BaseAddress inc\stm8s.h 2368;" macro -TIM5_CCER1_CC1E inc\stm8s.h 1087;" macro -TIM5_CCER1_CC1P inc\stm8s.h 1086;" macro -TIM5_CCER1_CC2E inc\stm8s.h 1085;" macro -TIM5_CCER1_CC2P inc\stm8s.h 1084;" macro -TIM5_CCER1_RESET_VALUE inc\stm8s.h 1017;" macro -TIM5_CCER2_CC3E inc\stm8s.h 1090;" macro -TIM5_CCER2_CC3P inc\stm8s.h 1089;" macro -TIM5_CCER2_RESET_VALUE inc\stm8s.h 1018;" macro -TIM5_CCMR1_RESET_VALUE inc\stm8s.h 1014;" macro -TIM5_CCMR2_RESET_VALUE inc\stm8s.h 1015;" macro -TIM5_CCMR3_RESET_VALUE inc\stm8s.h 1016;" macro -TIM5_CCMR_CCxS inc\stm8s.h 1082;" macro -TIM5_CCMR_ICxF inc\stm8s.h 1079;" macro -TIM5_CCMR_ICxPSC inc\stm8s.h 1078;" macro -TIM5_CCMR_OCM inc\stm8s.h 1080;" macro -TIM5_CCMR_OCxPE inc\stm8s.h 1081;" macro -TIM5_CCMR_TIxDirect_Set inc\stm8s.h 1109;" macro -TIM5_CCR1H_CCR1 inc\stm8s.h 1100;" macro -TIM5_CCR1H_RESET_VALUE inc\stm8s.h 1024;" macro -TIM5_CCR1L_CCR1 inc\stm8s.h 1101;" macro -TIM5_CCR1L_RESET_VALUE inc\stm8s.h 1025;" macro -TIM5_CCR2H_CCR2 inc\stm8s.h 1103;" macro -TIM5_CCR2H_RESET_VALUE inc\stm8s.h 1026;" macro -TIM5_CCR2L_CCR2 inc\stm8s.h 1104;" macro -TIM5_CCR2L_RESET_VALUE inc\stm8s.h 1027;" macro -TIM5_CCR3H_CCR3 inc\stm8s.h 1106;" macro -TIM5_CCR3H_RESET_VALUE inc\stm8s.h 1028;" macro -TIM5_CCR3L_CCR3 inc\stm8s.h 1107;" macro -TIM5_CCR3L_RESET_VALUE inc\stm8s.h 1029;" macro -TIM5_CNTRH_CNT inc\stm8s.h 1092;" macro -TIM5_CNTRH_RESET_VALUE inc\stm8s.h 1019;" macro -TIM5_CNTRL_CNT inc\stm8s.h 1093;" macro -TIM5_CNTRL_RESET_VALUE inc\stm8s.h 1020;" macro -TIM5_CR1_ARPE inc\stm8s.h 1039;" macro -TIM5_CR1_CEN inc\stm8s.h 1043;" macro -TIM5_CR1_OPM inc\stm8s.h 1040;" macro -TIM5_CR1_RESET_VALUE inc\stm8s.h 1007;" macro -TIM5_CR1_UDIS inc\stm8s.h 1042;" macro -TIM5_CR1_URS inc\stm8s.h 1041;" macro -TIM5_CR2_MMS inc\stm8s.h 1047;" macro -TIM5_CR2_RESET_VALUE inc\stm8s.h 1008;" macro -TIM5_CR2_TI1S inc\stm8s.h 1046;" macro -TIM5_EGR_CC1G inc\stm8s.h 1075;" macro -TIM5_EGR_CC2G inc\stm8s.h 1074;" macro -TIM5_EGR_CC3G inc\stm8s.h 1073;" macro -TIM5_EGR_RESET_VALUE inc\stm8s.h 1013;" macro -TIM5_EGR_TG inc\stm8s.h 1072;" macro -TIM5_EGR_UG inc\stm8s.h 1076;" macro -TIM5_IER_CC1IE inc\stm8s.h 1059;" macro -TIM5_IER_CC2IE inc\stm8s.h 1058;" macro -TIM5_IER_CC3IE inc\stm8s.h 1057;" macro -TIM5_IER_RESET_VALUE inc\stm8s.h 1010;" macro -TIM5_IER_TIE inc\stm8s.h 1056;" macro -TIM5_IER_UIE inc\stm8s.h 1060;" macro -TIM5_PSCR_PSC inc\stm8s.h 1095;" macro -TIM5_PSCR_RESET_VALUE inc\stm8s.h 1021;" macro -TIM5_SMCR_MSM inc\stm8s.h 1050;" macro -TIM5_SMCR_RESET_VALUE inc\stm8s.h 1009;" macro -TIM5_SMCR_SMS inc\stm8s.h 1052;" macro -TIM5_SMCR_TS inc\stm8s.h 1051;" macro -TIM5_SR1_CC1IF inc\stm8s.h 1065;" macro -TIM5_SR1_CC2IF inc\stm8s.h 1064;" macro -TIM5_SR1_CC3IF inc\stm8s.h 1063;" macro -TIM5_SR1_RESET_VALUE inc\stm8s.h 1011;" macro -TIM5_SR1_TIF inc\stm8s.h 1062;" macro -TIM5_SR1_UIF inc\stm8s.h 1066;" macro -TIM5_SR2_CC1OF inc\stm8s.h 1070;" macro -TIM5_SR2_CC2OF inc\stm8s.h 1069;" macro -TIM5_SR2_CC3OF inc\stm8s.h 1068;" macro -TIM5_SR2_RESET_VALUE inc\stm8s.h 1012;" macro -TIM5_TypeDef inc\stm8s.h 1001;" typedef typeref:struct:TIM5_struct -TIM5_struct inc\stm8s.h 976;" struct -TIM6 inc\stm8s.h 2469;" macro -TIM6_ARR_ARR inc\stm8s.h 1182;" macro -TIM6_ARR_RESET_VALUE inc\stm8s.h 1143;" macro -TIM6_BaseAddress inc\stm8s.h 2369;" macro -TIM6_CNTR_CNT inc\stm8s.h 1178;" macro -TIM6_CNTR_RESET_VALUE inc\stm8s.h 1141;" macro -TIM6_CR1_ARPE inc\stm8s.h 1153;" macro -TIM6_CR1_CEN inc\stm8s.h 1157;" macro -TIM6_CR1_OPM inc\stm8s.h 1154;" macro -TIM6_CR1_RESET_VALUE inc\stm8s.h 1135;" macro -TIM6_CR1_UDIS inc\stm8s.h 1156;" macro -TIM6_CR1_URS inc\stm8s.h 1155;" macro -TIM6_CR2_MMS inc\stm8s.h 1161;" macro -TIM6_CR2_RESET_VALUE inc\stm8s.h 1136;" macro -TIM6_EGR_RESET_VALUE inc\stm8s.h 1140;" macro -TIM6_EGR_TG inc\stm8s.h 1175;" macro -TIM6_EGR_UG inc\stm8s.h 1176;" macro -TIM6_IER_RESET_VALUE inc\stm8s.h 1138;" macro -TIM6_IER_TIE inc\stm8s.h 1169;" macro -TIM6_IER_UIE inc\stm8s.h 1170;" macro -TIM6_PSCR_PSC inc\stm8s.h 1180;" macro -TIM6_PSCR_RESET_VALUE inc\stm8s.h 1142;" macro -TIM6_SMCR_MSM inc\stm8s.h 1164;" macro -TIM6_SMCR_RESET_VALUE inc\stm8s.h 1137;" macro -TIM6_SMCR_SMS inc\stm8s.h 1166;" macro -TIM6_SMCR_TS inc\stm8s.h 1165;" macro -TIM6_SR1_RESET_VALUE inc\stm8s.h 1139;" macro -TIM6_SR1_TIF inc\stm8s.h 1172;" macro -TIM6_SR1_UIF inc\stm8s.h 1173;" macro -TIM6_TypeDef inc\stm8s.h 1131;" typedef typeref:struct:TIM6_struct -TIM6_struct inc\stm8s.h 1119;" struct -TINY inc\stm8s.h 68;" macro -TINY inc\stm8s.h 73;" macro -TLI_IRQHandler inc\stm8s_it.h 62;" prototype signature:(void) -TPR inc\stm8s.h 1945;" member struct:__anon1 -TRAP_IRQHandler inc\stm8s_it.h 63;" prototype signature:(void) -TRISER inc\stm8s.h 1206;" member struct:I2C_struct -TRUE inc\stm8s_type.h 63;" enumerator enum:__anon25 -TSR inc\stm8s.h 1944;" member struct:__anon1 -TXCRCR inc\stm8s.h 1568;" member struct:SPI_struct -TxMailbox inc\stm8s.h 1972;" member union:__anon1::__anon2 typeref:struct:__anon1::__anon2::__anon3 -TxPllconfig main.c 165;" function signature:(void) -U16_MAX inc\stm8s_type.h 114;" macro -U32_MAX inc\stm8s_type.h 117;" macro -U8_MAX inc\stm8s_type.h 111;" macro -UART1 inc\stm8s.h 2442;" macro -UART1_BRR1_DIVM inc\stm8s.h 1689;" macro -UART1_BRR1_RESET_VALUE inc\stm8s.h 1662;" macro -UART1_BRR2_DIVF inc\stm8s.h 1692;" macro -UART1_BRR2_DIVM inc\stm8s.h 1691;" macro -UART1_BRR2_RESET_VALUE inc\stm8s.h 1663;" macro -UART1_BaseAddress inc\stm8s.h 2361;" macro -UART1_CR1_M inc\stm8s.h 1697;" macro -UART1_CR1_PCEN inc\stm8s.h 1699;" macro -UART1_CR1_PIEN inc\stm8s.h 1701;" macro -UART1_CR1_PS inc\stm8s.h 1700;" macro -UART1_CR1_R8 inc\stm8s.h 1694;" macro -UART1_CR1_RESET_VALUE inc\stm8s.h 1664;" macro -UART1_CR1_T8 inc\stm8s.h 1695;" macro -UART1_CR1_UARTD inc\stm8s.h 1696;" macro -UART1_CR1_WAKE inc\stm8s.h 1698;" macro -UART1_CR2_ILIEN inc\stm8s.h 1706;" macro -UART1_CR2_REN inc\stm8s.h 1708;" macro -UART1_CR2_RESET_VALUE inc\stm8s.h 1665;" macro -UART1_CR2_RIEN inc\stm8s.h 1705;" macro -UART1_CR2_RWU inc\stm8s.h 1709;" macro -UART1_CR2_SBK inc\stm8s.h 1710;" macro -UART1_CR2_TCIEN inc\stm8s.h 1704;" macro -UART1_CR2_TEN inc\stm8s.h 1707;" macro -UART1_CR2_TIEN inc\stm8s.h 1703;" macro -UART1_CR3_CKEN inc\stm8s.h 1714;" macro -UART1_CR3_CPHA inc\stm8s.h 1716;" macro -UART1_CR3_CPOL inc\stm8s.h 1715;" macro -UART1_CR3_LBCL inc\stm8s.h 1717;" macro -UART1_CR3_LINEN inc\stm8s.h 1712;" macro -UART1_CR3_RESET_VALUE inc\stm8s.h 1666;" macro -UART1_CR3_STOP inc\stm8s.h 1713;" macro -UART1_CR4_ADD inc\stm8s.h 1722;" macro -UART1_CR4_LBDF inc\stm8s.h 1721;" macro -UART1_CR4_LBDIEN inc\stm8s.h 1719;" macro -UART1_CR4_LBDL inc\stm8s.h 1720;" macro -UART1_CR4_RESET_VALUE inc\stm8s.h 1667;" macro -UART1_CR5_HDSEL inc\stm8s.h 1726;" macro -UART1_CR5_IREN inc\stm8s.h 1728;" macro -UART1_CR5_IRLP inc\stm8s.h 1727;" macro -UART1_CR5_NACK inc\stm8s.h 1725;" macro -UART1_CR5_RESET_VALUE inc\stm8s.h 1668;" macro -UART1_CR5_SCEN inc\stm8s.h 1724;" macro -UART1_GTR_RESET_VALUE inc\stm8s.h 1669;" macro -UART1_PSCR_RESET_VALUE inc\stm8s.h 1670;" macro -UART1_RX_IRQHandler inc\stm8s_it.h 44;" prototype signature:(void) -UART1_SR_FE inc\stm8s.h 1686;" macro -UART1_SR_IDLE inc\stm8s.h 1683;" macro -UART1_SR_NF inc\stm8s.h 1685;" macro -UART1_SR_OR inc\stm8s.h 1684;" macro -UART1_SR_PE inc\stm8s.h 1687;" macro -UART1_SR_RESET_VALUE inc\stm8s.h 1661;" macro -UART1_SR_RXNE inc\stm8s.h 1682;" macro -UART1_SR_TC inc\stm8s.h 1681;" macro -UART1_SR_TXE inc\stm8s.h 1680;" macro -UART1_TX_IRQHandler inc\stm8s_it.h 45;" prototype signature:(void) -UART1_TypeDef inc\stm8s.h 1655;" typedef typeref:struct:UART1_struct -UART1_struct inc\stm8s.h 1641;" struct -UART2 inc\stm8s.h 2446;" macro -UART2_BRR1_DIVM inc\stm8s.h 1789;" macro -UART2_BRR1_RESET_VALUE inc\stm8s.h 1761;" macro -UART2_BRR2_DIVF inc\stm8s.h 1792;" macro -UART2_BRR2_DIVM inc\stm8s.h 1791;" macro -UART2_BRR2_RESET_VALUE inc\stm8s.h 1762;" macro -UART2_BaseAddress inc\stm8s.h 2362;" macro -UART2_CR1_M inc\stm8s.h 1797;" macro -UART2_CR1_PCEN inc\stm8s.h 1799;" macro -UART2_CR1_PIEN inc\stm8s.h 1801;" macro -UART2_CR1_PS inc\stm8s.h 1800;" macro -UART2_CR1_R8 inc\stm8s.h 1794;" macro -UART2_CR1_RESET_VALUE inc\stm8s.h 1763;" macro -UART2_CR1_T8 inc\stm8s.h 1795;" macro -UART2_CR1_UARTD inc\stm8s.h 1796;" macro -UART2_CR1_WAKE inc\stm8s.h 1798;" macro -UART2_CR2_ILIEN inc\stm8s.h 1806;" macro -UART2_CR2_REN inc\stm8s.h 1808;" macro -UART2_CR2_RESET_VALUE inc\stm8s.h 1764;" macro -UART2_CR2_RIEN inc\stm8s.h 1805;" macro -UART2_CR2_RWU inc\stm8s.h 1809;" macro -UART2_CR2_SBK inc\stm8s.h 1810;" macro -UART2_CR2_TCIEN inc\stm8s.h 1804;" macro -UART2_CR2_TEN inc\stm8s.h 1807;" macro -UART2_CR2_TIEN inc\stm8s.h 1803;" macro -UART2_CR3_CKEN inc\stm8s.h 1814;" macro -UART2_CR3_CPHA inc\stm8s.h 1816;" macro -UART2_CR3_CPOL inc\stm8s.h 1815;" macro -UART2_CR3_LBCL inc\stm8s.h 1817;" macro -UART2_CR3_LINEN inc\stm8s.h 1812;" macro -UART2_CR3_RESET_VALUE inc\stm8s.h 1765;" macro -UART2_CR3_STOP inc\stm8s.h 1813;" macro -UART2_CR4_ADD inc\stm8s.h 1822;" macro -UART2_CR4_LBDF inc\stm8s.h 1821;" macro -UART2_CR4_LBDIEN inc\stm8s.h 1819;" macro -UART2_CR4_LBDL inc\stm8s.h 1820;" macro -UART2_CR4_RESET_VALUE inc\stm8s.h 1766;" macro -UART2_CR5_HDSEL inc\stm8s.h 1826;" macro -UART2_CR5_IREN inc\stm8s.h 1828;" macro -UART2_CR5_IRLP inc\stm8s.h 1827;" macro -UART2_CR5_NACK inc\stm8s.h 1825;" macro -UART2_CR5_RESET_VALUE inc\stm8s.h 1767;" macro -UART2_CR5_SCEN inc\stm8s.h 1824;" macro -UART2_CR6_LASE inc\stm8s.h 1832;" macro -UART2_CR6_LDUM inc\stm8s.h 1830;" macro -UART2_CR6_LHDF inc\stm8s.h 1834;" macro -UART2_CR6_LHDIEN inc\stm8s.h 1833;" macro -UART2_CR6_LSF inc\stm8s.h 1835;" macro -UART2_CR6_LSLV inc\stm8s.h 1831;" macro -UART2_CR6_RESET_VALUE inc\stm8s.h 1768;" macro -UART2_GTR_RESET_VALUE inc\stm8s.h 1769;" macro -UART2_PSCR_RESET_VALUE inc\stm8s.h 1770;" macro -UART2_RX_IRQHandler inc\stm8s_it.h 41;" prototype signature:(void) -UART2_SR_FE inc\stm8s.h 1786;" macro -UART2_SR_IDLE inc\stm8s.h 1783;" macro -UART2_SR_NF inc\stm8s.h 1785;" macro -UART2_SR_OR inc\stm8s.h 1784;" macro -UART2_SR_PE inc\stm8s.h 1787;" macro -UART2_SR_RESET_VALUE inc\stm8s.h 1760;" macro -UART2_SR_RXNE inc\stm8s.h 1782;" macro -UART2_SR_TC inc\stm8s.h 1781;" macro -UART2_SR_TXE inc\stm8s.h 1780;" macro -UART2_TX_IRQHandler inc\stm8s_it.h 42;" prototype signature:(void) -UART2_TypeDef inc\stm8s.h 1754;" typedef typeref:struct:UART2_struct -UART2_struct inc\stm8s.h 1739;" struct -UART3 inc\stm8s.h 2450;" macro -UART3_BRR1_DIVM inc\stm8s.h 1892;" macro -UART3_BRR1_RESET_VALUE inc\stm8s.h 1867;" macro -UART3_BRR2_DIVF inc\stm8s.h 1895;" macro -UART3_BRR2_DIVM inc\stm8s.h 1894;" macro -UART3_BRR2_RESET_VALUE inc\stm8s.h 1868;" macro -UART3_BaseAddress inc\stm8s.h 2363;" macro -UART3_CR1_M inc\stm8s.h 1900;" macro -UART3_CR1_PCEN inc\stm8s.h 1902;" macro -UART3_CR1_PIEN inc\stm8s.h 1904;" macro -UART3_CR1_PS inc\stm8s.h 1903;" macro -UART3_CR1_R8 inc\stm8s.h 1897;" macro -UART3_CR1_RESET_VALUE inc\stm8s.h 1869;" macro -UART3_CR1_T8 inc\stm8s.h 1898;" macro -UART3_CR1_UARTD inc\stm8s.h 1899;" macro -UART3_CR1_WAKE inc\stm8s.h 1901;" macro -UART3_CR2_ILIEN inc\stm8s.h 1909;" macro -UART3_CR2_REN inc\stm8s.h 1911;" macro -UART3_CR2_RESET_VALUE inc\stm8s.h 1870;" macro -UART3_CR2_RIEN inc\stm8s.h 1908;" macro -UART3_CR2_RWU inc\stm8s.h 1912;" macro -UART3_CR2_SBK inc\stm8s.h 1913;" macro -UART3_CR2_TCIEN inc\stm8s.h 1907;" macro -UART3_CR2_TEN inc\stm8s.h 1910;" macro -UART3_CR2_TIEN inc\stm8s.h 1906;" macro -UART3_CR3_LINEN inc\stm8s.h 1915;" macro -UART3_CR3_RESET_VALUE inc\stm8s.h 1871;" macro -UART3_CR3_STOP inc\stm8s.h 1916;" macro -UART3_CR4_ADD inc\stm8s.h 1921;" macro -UART3_CR4_LBDF inc\stm8s.h 1920;" macro -UART3_CR4_LBDIEN inc\stm8s.h 1918;" macro -UART3_CR4_LBDL inc\stm8s.h 1919;" macro -UART3_CR4_RESET_VALUE inc\stm8s.h 1872;" macro -UART3_CR6_LASE inc\stm8s.h 1925;" macro -UART3_CR6_LDUM inc\stm8s.h 1923;" macro -UART3_CR6_LHDF inc\stm8s.h 1927;" macro -UART3_CR6_LHDIEN inc\stm8s.h 1926;" macro -UART3_CR6_LSF inc\stm8s.h 1928;" macro -UART3_CR6_LSLV inc\stm8s.h 1924;" macro -UART3_CR6_RESET_VALUE inc\stm8s.h 1873;" macro -UART3_RX_IRQHandler inc\stm8s_it.h 39;" prototype signature:(void) -UART3_SR_FE inc\stm8s.h 1889;" macro -UART3_SR_IDLE inc\stm8s.h 1886;" macro -UART3_SR_NF inc\stm8s.h 1888;" macro -UART3_SR_OR inc\stm8s.h 1887;" macro -UART3_SR_PE inc\stm8s.h 1890;" macro -UART3_SR_RESET_VALUE inc\stm8s.h 1866;" macro -UART3_SR_RXNE inc\stm8s.h 1885;" macro -UART3_SR_TC inc\stm8s.h 1884;" macro -UART3_SR_TXE inc\stm8s.h 1883;" macro -UART3_TX_IRQHandler inc\stm8s_it.h 40;" prototype signature:(void) -UART3_TypeDef inc\stm8s.h 1860;" typedef typeref:struct:UART3_struct -UART3_struct inc\stm8s.h 1847;" struct -USE_STDPERIPH_DRIVER inc\stm8s.h 57;" macro -ValBit inc\stm8s.h 2532;" macro -ValBit inc\stm8s_macro.h 87;" macro -Video_mode1080i60 main.c 25;" variable -Video_mode480P60 main.c 20;" variable -Video_mode576P50 main.c 22;" variable -Video_mode576i60 main.c 24;" variable -Video_mode720P60 main.c 23;" variable -WR inc\stm8s.h 1499;" member struct:WWDG_struct -WWDG inc\stm8s.h 2435;" macro -WWDG_BaseAddress inc\stm8s.h 2355;" macro -WWDG_CR_RESET_VALUE inc\stm8s.h 1507;" macro -WWDG_CR_T inc\stm8s.h 1520;" macro -WWDG_CR_T6 inc\stm8s.h 1519;" macro -WWDG_CR_WDGA inc\stm8s.h 1518;" macro -WWDG_TypeDef inc\stm8s.h 1501;" typedef typeref:struct:WWDG_struct -WWDG_WR_MSB inc\stm8s.h 1522;" macro -WWDG_WR_RESET_VALUE inc\stm8s.h 1508;" macro -WWDG_WR_W inc\stm8s.h 1523;" macro -WWDG_struct inc\stm8s.h 1496;" struct -Write_EDID2HDMI_Shadow main.c 34;" function signature:(void) -YCbCr422_162024bit main.c 300;" function signature:(void) -YCbCr422_8bit_YC_mux main.c 305;" function signature:(void) -Ycbcr444_24bit main.c 295;" function signature:(void) -_CLK inc\stm8s_conf.h 68;" macro -_COSMIC_ inc\stm8s.h 32;" macro -_COSMIC_ inc\stm8s.h 34;" macro -_COSMIC_ inc\stm8s_macro.h 29;" macro -_COSMIC_ inc\stm8s_macro.h 31;" macro -_EDID_H inc\edid.h 12;" macro -_EXTI inc\stm8s_conf.h 71;" macro -_GPIO inc\stm8s_conf.h 80;" macro -_I2C_MASTER_H inc\i2c_master.h 12;" macro -_INCLUDE_H inc\include.h 10;" macro -_ITC inc\stm8s_conf.h 86;" macro -_IWDG inc\stm8s_conf.h 89;" macro -_LT8522EX_H inc\lt8522ex.h 10;" macro -_MAIN_H inc\main.h 10;" macro -_RAISONANCE_ inc\stm8s.h 31;" macro -_RAISONANCE_ inc\stm8s.h 35;" macro -_RAISONANCE_ inc\stm8s_macro.h 28;" macro -_RAISONANCE_ inc\stm8s_macro.h 32;" macro -__CONST inc\stm8s.h 69;" macro -__CONST inc\stm8s.h 74;" macro -__STM8S_CLK_H inc\stm8s_clk.h 25;" macro -__STM8S_CONF_H inc\stm8s_conf.h 24;" macro -__STM8S_EXTI_H__ inc\stm8s_exti.h 24;" macro -__STM8S_GPIO_H inc\stm8s_gpio.h 24;" macro -__STM8S_H inc\stm8s.h 24;" macro -__STM8S_ITC_H__ inc\stm8s_itc.h 24;" macro -__STM8S_IT_H inc\stm8s_it.h 24;" macro -__STM8S_IWDG_H inc\stm8s_iwdg.h 24;" macro -__STM8S_MACRO_H inc\stm8s_macro.h 24;" macro -__STM8S_TYPE_H inc\stm8s_type.h 24;" macro -_stext inc\stm8s_it.h 64;" prototype signature:(void) -_stext stm8_interrupt_vector.c 20;" prototype file: -_vectab stm8_interrupt_vector.c 22;" variable -ack src\i2c_master.c 12;" variable -assert_failed inc\stm8s_conf.h 150;" prototype signature:(u8* file, u32 line) -assert_param inc\stm8s_conf.h 148;" macro -assert_param inc\stm8s_conf.h 152;" macro -bool inc\stm8s_type.h 65;" typedef typeref:enum:__anon25 -delay_us src\i2c_master.c 38;" function signature:(u8 uscount) -disableInterrupts inc\stm8s.h 2491;" macro -disableInterrupts inc\stm8s.h 2500;" macro -disableInterrupts inc\stm8s_macro.h 46;" macro -disableInterrupts inc\stm8s_macro.h 55;" macro -edid_buff_1 main.c 18;" variable -edid_buff_2 main.c 19;" variable -enableInterrupts inc\stm8s.h 2490;" macro -enableInterrupts inc\stm8s.h 2499;" macro -enableInterrupts inc\stm8s_macro.h 45;" macro -enableInterrupts inc\stm8s_macro.h 54;" macro -halt inc\stm8s.h 2497;" macro -halt inc\stm8s.h 2506;" macro -halt inc\stm8s_macro.h 52;" macro -halt inc\stm8s_macro.h 61;" macro -i2c_read_byte src\i2c_master.c 189;" function signature:(u8 sla,u8 suba,u8 *s,u8 no) -i2c_write_byte src\i2c_master.c 155;" function signature:(u8 sla,u8 suba,u8 *s,u8 no) -interrupt_handler stm8_interrupt_vector.c 9;" member struct:interrupt_vector file: -interrupt_handler_t stm8_interrupt_vector.c 5;" typedef file: -interrupt_instruction stm8_interrupt_vector.c 8;" member struct:interrupt_vector file: -interrupt_vector stm8_interrupt_vector.c 7;" struct file: -main main.c 327;" function -max inc\stm8s_type.h 107;" macro -min inc\stm8s_type.h 103;" macro -nop inc\stm8s.h 2494;" macro -nop inc\stm8s.h 2503;" macro -nop inc\stm8s_macro.h 49;" macro -nop inc\stm8s_macro.h 58;" macro -out_RGB888 main.c 13;" macro file: -rim inc\stm8s.h 2492;" macro -rim inc\stm8s.h 2501;" macro -rim inc\stm8s_macro.h 47;" macro -rim inc\stm8s_macro.h 56;" macro -s16 inc\stm8s_type.h 29;" typedef -s32 inc\stm8s_type.h 28;" typedef -s8 inc\stm8s_type.h 30;" typedef -sc16 inc\stm8s_type.h 33;" typedef -sc32 inc\stm8s_type.h 32;" typedef -sc8 inc\stm8s_type.h 34;" typedef -sim inc\stm8s.h 2493;" macro -sim inc\stm8s.h 2502;" macro -sim inc\stm8s_macro.h 48;" macro -sim inc\stm8s_macro.h 57;" macro -trap inc\stm8s.h 2495;" macro -trap inc\stm8s.h 2504;" macro -trap inc\stm8s_macro.h 50;" macro -trap inc\stm8s_macro.h 59;" macro -u16 inc\stm8s_type.h 45;" typedef -u32 inc\stm8s_type.h 44;" typedef -u8 inc\stm8s_type.h 46;" typedef -uc16 inc\stm8s_type.h 49;" typedef -uc32 inc\stm8s_type.h 48;" typedef -uc8 inc\stm8s_type.h 50;" typedef -vs16 inc\stm8s_type.h 37;" typedef -vs32 inc\stm8s_type.h 36;" typedef -vs8 inc\stm8s_type.h 38;" typedef -vsc16 inc\stm8s_type.h 41;" typedef -vsc32 inc\stm8s_type.h 40;" typedef -vsc8 inc\stm8s_type.h 42;" typedef -vu16 inc\stm8s_type.h 53;" typedef -vu32 inc\stm8s_type.h 52;" typedef -vu8 inc\stm8s_type.h 54;" typedef -vuc16 inc\stm8s_type.h 57;" typedef -vuc32 inc\stm8s_type.h 56;" typedef -vuc8 inc\stm8s_type.h 58;" typedef -wfi inc\stm8s.h 2496;" macro -wfi inc\stm8s.h 2505;" macro -wfi inc\stm8s_macro.h 51;" macro -wfi inc\stm8s_macro.h 60;" macro diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/TAGS_Filelist.txt b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/TAGS_Filelist.txt deleted file mode 100644 index 7574f71e9..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/TAGS_Filelist.txt +++ /dev/null @@ -1,25 +0,0 @@ -main.c -src\i2c_master.c -src\interrupt.c -src\stm8s_clk.c -src\stm8s_exti.c -src\stm8s_gpio.c -src\stm8s_itc.c -stm8_interrupt_vector.c -inc\i2c_master.h -inc\include.h -inc\lt8522ex.h -inc\stm8s.h -inc\stm8s_clk.h -inc\stm8s_conf.h -inc\stm8s_exti.h -inc\stm8s_it.h -inc\stm8s_macro.h -inc\stm8s_type.h -..\..\..\..\..\..\..\..\program files (x86)\cosmic\cxstm8_32k\hstm8\mods0.h -..\..\..\..\..\..\..\..\program files (x86)\cosmic\cxstm8_32k\hstm8\string.h -inc\edid.h -inc\main.h -inc\stm8s_gpio.h -inc\stm8s_itc.h -inc\stm8s_iwdg.h diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/checkres.spy b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/checkres.spy deleted file mode 100644 index 80e01b45b..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/checkres.spy +++ /dev/null @@ -1,9 +0,0 @@ -; -; ** Welcome to ST Visual Debug SPY System ** -; ** Copyright STMicroelectronics (c) 1999, all rights reserved ** -; Level 1 -; Date 04/12/14 -; Time 11:09:57 -; -<.\confmenu.cpp:170-11:09:57> -Error: resource handle has not been restored in .\mainfrm.cpp:3205 diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/Delay.h b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/Delay.h deleted file mode 100644 index 9d1c038a3..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/Delay.h +++ /dev/null @@ -1,16 +0,0 @@ - -#ifndef _Delay_H -#define _Delay_H - -extern void Timer0_Delay100us(UINT32 u32CNT); -extern void Timer0_Delay1ms(UINT32 u32CNT); -extern void Timer1_Delay10ms(UINT32 u32CNT); -extern void Timer2_Delay500us(UINT32 u32CNT); -extern void Timer3_Delay100ms(UINT32 u32CNT); - -extern void Timer0_Delay40ms(UINT32 u32CNT); -extern void Timer3_Delay10us(UINT32 u32CNT); - -extern bit BIT_TMP; -#endif - diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/Function_Define.h b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/Function_Define.h deleted file mode 100644 index 73e1cf1d4..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/Function_Define.h +++ /dev/null @@ -1,539 +0,0 @@ - -/*-------------------------------------------------------------------------- - N76E003 Function_define.h V1.02 - - All function define inital setting file for Nuvoton N76E003 - --------------------------------------------------------------------------*/ - -#include -#include - -#define nop _nop_( ); - -//16 --> 8 x 2 -#define HIBYTE( v1 ) ( (UINT8)( ( v1 ) >> 8 ) ) //v1 is UINT16 -#define LOBYTE( v1 ) ( (UINT8)( ( v1 ) & 0xFF ) ) -//8 x 2 --> 16 -#define MAKEWORD( v1, v2 ) ( ( ( (UINT16)( v1 ) ) << 8 ) + (UINT16)( v2 ) ) //v1,v2 is UINT8 -//8 x 4 --> 32 -#define MAKELONG( v1, v2, v3, v4 ) (UINT32)( ( v1 << 32 ) + ( v2 << 16 ) + ( v3 << 8 ) + v4 ) //v1,v2,v3,v4 is UINT8 -//32 --> 16 x 2 -#define YBYTE1( v1 ) ( (UINT16)( ( v1 ) >> 16 ) ) //v1 is UINT32 -#define YBYTE0( v1 ) ( (UINT16)( ( v1 ) & 0xFFFF ) ) -//32 --> 8 x 4 -#define TBYTE3( v1 ) ( (UINT8)( ( v1 ) >> 24 ) ) //v1 is UINT32 -#define TBYTE2( v1 ) ( (UINT8)( ( v1 ) >> 16 ) ) -#define TBYTE1( v1 ) ( (UINT8)( ( v1 ) >> 8 ) ) -#define TBYTE0( v1 ) ( (UINT8)( ( v1 ) & 0xFF ) ) - -#define SET_BIT0 0x01 -#define SET_BIT1 0x02 -#define SET_BIT2 0x04 -#define SET_BIT3 0x08 -#define SET_BIT4 0x10 -#define SET_BIT5 0x20 -#define SET_BIT6 0x40 -#define SET_BIT7 0x80 -#define SET_BIT8 0x0100 -#define SET_BIT9 0x0200 -#define SET_BIT10 0x0400 -#define SET_BIT11 0x0800 -#define SET_BIT12 0x1000 -#define SET_BIT13 0x2000 -#define SET_BIT14 0x4000 -#define SET_BIT15 0x8000 - -#define CLR_BIT0 0xFE -#define CLR_BIT1 0xFD -#define CLR_BIT2 0xFB -#define CLR_BIT3 0xF7 -#define CLR_BIT4 0xEF -#define CLR_BIT5 0xDF -#define CLR_BIT6 0xBF -#define CLR_BIT7 0x7F - -#define CLR_BIT8 0xFEFF -#define CLR_BIT9 0xFDFF -#define CLR_BIT10 0xFBFF -#define CLR_BIT11 0xF7FF -#define CLR_BIT12 0xEFFF -#define CLR_BIT13 0xDFFF -#define CLR_BIT14 0xBFFF -#define CLR_BIT15 0x7FFF - -#define FAIL 1 -#define PASS 0 - - -/***************************************************************************************** -* For GPIO INIT setting -*****************************************************************************************/ -//------------------- Define Port as Quasi mode ------------------- -#define P00_Quasi_Mode P0M1 &= ~SET_BIT0; P0M2 &= ~SET_BIT0 -#define P01_Quasi_Mode P0M1 &= ~SET_BIT1; P0M2 &= ~SET_BIT1 -#define P02_Quasi_Mode P0M1 &= ~SET_BIT2; P0M2 &= ~SET_BIT2 -#define P03_Quasi_Mode P0M1 &= ~SET_BIT3; P0M2 &= ~SET_BIT3 -#define P04_Quasi_Mode P0M1 &= ~SET_BIT4; P0M2 &= ~SET_BIT4 -#define P05_Quasi_Mode P0M1 &= ~SET_BIT5; P0M2 &= ~SET_BIT5 -#define P06_Quasi_Mode P0M1 &= ~SET_BIT6; P0M2 &= ~SET_BIT6 -#define P07_Quasi_Mode P0M1 &= ~SET_BIT7; P0M2 &= ~SET_BIT7 -#define P10_Quasi_Mode P1M1 &= ~SET_BIT0; P1M2 &= ~SET_BIT0 -#define P11_Quasi_Mode P1M1 &= ~SET_BIT1; P1M2 &= ~SET_BIT1 -#define P12_Quasi_Mode P1M1 &= ~SET_BIT2; P1M2 &= ~SET_BIT2 -#define P13_Quasi_Mode P1M1 &= ~SET_BIT3; P1M2 &= ~SET_BIT3 -#define P14_Quasi_Mode P1M1 &= ~SET_BIT4; P1M2 &= ~SET_BIT4 -#define P15_Quasi_Mode P1M1 &= ~SET_BIT5; P1M2 &= ~SET_BIT5 -#define P16_Quasi_Mode P1M1 &= ~SET_BIT6; P1M2 &= ~SET_BIT6 -#define P17_Quasi_Mode P1M1 &= ~SET_BIT7; P1M2 &= ~SET_BIT7 -#define P30_Quasi_Mode P3M1 &= ~SET_BIT0; P3M2 &= ~SET_BIT0 -//------------------- Define Port as Push Pull mode ------------------- -#define P00_PushPull_Mode P0M1 &= ~SET_BIT0; P0M2 |= SET_BIT0 -#define P01_PushPull_Mode P0M1 &= ~SET_BIT1; P0M2 |= SET_BIT1 -#define P02_PushPull_Mode P0M1 &= ~SET_BIT2; P0M2 |= SET_BIT2 -#define P03_PushPull_Mode P0M1 &= ~SET_BIT3; P0M2 |= SET_BIT3 -#define P04_PushPull_Mode P0M1 &= ~SET_BIT4; P0M2 |= SET_BIT4 -#define P05_PushPull_Mode P0M1 &= ~SET_BIT5; P0M2 |= SET_BIT5 -#define P06_PushPull_Mode P0M1 &= ~SET_BIT6; P0M2 |= SET_BIT6 -#define P07_PushPull_Mode P0M1 &= ~SET_BIT7; P0M2 |= SET_BIT7 -#define P10_PushPull_Mode P1M1 &= ~SET_BIT0; P1M2 |= SET_BIT0 -#define P11_PushPull_Mode P1M1 &= ~SET_BIT1; P1M2 |= SET_BIT1 -#define P12_PushPull_Mode P1M1 &= ~SET_BIT2; P1M2 |= SET_BIT2 -#define P13_PushPull_Mode P1M1 &= ~SET_BIT3; P1M2 |= SET_BIT3 -#define P14_PushPull_Mode P1M1 &= ~SET_BIT4; P1M2 |= SET_BIT4 -#define P15_PushPull_Mode P1M1 &= ~SET_BIT5; P1M2 |= SET_BIT5 -#define P16_PushPull_Mode P1M1 &= ~SET_BIT6; P1M2 |= SET_BIT6 -#define P17_PushPull_Mode P1M1 &= ~SET_BIT7; P1M2 |= SET_BIT7 -#define P30_PushPull_Mode P3M1 &= ~SET_BIT0; P3M2 |= SET_BIT0 -#define GPIO1_PushPull_Mode P1M1 &= ~SET_BIT0; P1M2 |= SET_BIT0 -//------------------- Define Port as Input Only mode ------------------- -#define P00_Input_Mode P0M1 |= SET_BIT0; P0M2 &= ~SET_BIT0 -#define P01_Input_Mode P0M1 |= SET_BIT1; P0M2 &= ~SET_BIT1 -#define P02_Input_Mode P0M1 |= SET_BIT2; P0M2 &= ~SET_BIT2 -#define P03_Input_Mode P0M1 |= SET_BIT3; P0M2 &= ~SET_BIT3 -#define P04_Input_Mode P0M1 |= SET_BIT4; P0M2 &= ~SET_BIT4 -#define P05_Input_Mode P0M1 |= SET_BIT5; P0M2 &= ~SET_BIT5 -#define P06_Input_Mode P0M1 |= SET_BIT6; P0M2 &= ~SET_BIT6 -#define P07_Input_Mode P0M1 |= SET_BIT7; P0M2 &= ~SET_BIT7 -#define P10_Input_Mode P1M1 |= SET_BIT0; P1M2 &= ~SET_BIT0 -#define P11_Input_Mode P1M1 |= SET_BIT1; P1M2 &= ~SET_BIT1 -#define P12_Input_Mode P1M1 |= SET_BIT2; P1M2 &= ~SET_BIT2 -#define P13_Input_Mode P1M1 |= SET_BIT3; P1M2 &= ~SET_BIT3 -#define P14_Input_Mode P1M1 |= SET_BIT4; P1M2 &= ~SET_BIT4 -#define P15_Input_Mode P1M1 |= SET_BIT5; P1M2 &= ~SET_BIT5 -#define P16_Input_Mode P1M1 |= SET_BIT6; P1M2 &= ~SET_BIT6 -#define P17_Input_Mode P1M1 |= SET_BIT7; P1M2 &= ~SET_BIT7 -#define P30_Input_Mode P3M1 |= SET_BIT0; P3M2 &= ~SET_BIT0 -//-------------------Define Port as Open Drain mode ------------------- -#define P00_OpenDrain_Mode P0M1 |= SET_BIT0; P0M2 |= SET_BIT0 -#define P01_OpenDrain_Mode P0M1 |= SET_BIT1; P0M2 |= SET_BIT1 -#define P02_OpenDrain_Mode P0M1 |= SET_BIT2; P0M2 |= SET_BIT2 -#define P03_OpenDrain_Mode P0M1 |= SET_BIT3; P0M2 |= SET_BIT3 -#define P04_OpenDrain_Mode P0M1 |= SET_BIT4; P0M2 |= SET_BIT4 -#define P05_OpenDrain_Mode P0M1 |= SET_BIT5; P0M2 |= SET_BIT5 -#define P06_OpenDrain_Mode P0M1 |= SET_BIT6; P0M2 |= SET_BIT6 -#define P07_OpenDrain_Mode P0M1 |= SET_BIT7; P0M2 |= SET_BIT7 -#define P10_OpenDrain_Mode P1M1 |= SET_BIT0; P1M2 |= SET_BIT0 -#define P11_OpenDrain_Mode P1M1 |= SET_BIT1; P1M2 |= SET_BIT1 -#define P12_OpenDrain_Mode P1M1 |= SET_BIT2; P1M2 |= SET_BIT2 -#define P13_OpenDrain_Mode P1M1 |= SET_BIT3; P1M2 |= SET_BIT3 -#define P14_OpenDrain_Mode P1M1 |= SET_BIT4; P1M2 |= SET_BIT4 -#define P15_OpenDrain_Mode P1M1 |= SET_BIT5; P1M2 |= SET_BIT5 -#define P16_OpenDrain_Mode P1M1 |= SET_BIT6; P1M2 |= SET_BIT6 -#define P17_OpenDrain_Mode P1M1 |= SET_BIT7; P1M2 |= SET_BIT7 -#define P30_OpenDrain_Mode P3M1 |= SET_BIT0; P3M2 |= SET_BIT0 -//--------- Define all port as quasi mode --------- -#define Set_All_GPIO_Quasi_Mode P0M1 = 0; P0M2 = 0; P1M1 = 0; P1M2 = 0; P3M1 = 0; P3M2 = 0 - -#define set_GPIO1 P12 = 1 -#define clr_GPIO1 P12 = 0 - - -/**************************************************************************** - Enable INT port 0~3 - ***************************************************************************/ -#define Enable_INT_Port0 PICON &= 0xFB; -#define Enable_INT_Port1 PICON |= 0x01; -#define Enable_INT_Port2 PICON |= 0x02; -#define Enable_INT_Port3 PICON |= 0x03; - - -/***************************************************************************** - Enable each bit low level trig mode -*****************************************************************************/ -#define Enable_BIT7_LowLevel_Trig PICON &= 0x7F; PINEN |= 0x80; PIPEN &= 0x7F -#define Enable_BIT6_LowLevel_Trig PICON &= 0x7F; PINEN |= 0x40; PIPEN &= 0xBF -#define Enable_BIT5_LowLevel_Trig PICON &= 0xBF; PINEN |= 0x20; PIPEN &= 0xDF -#define Enable_BIT4_LowLevel_Trig PICON &= 0xBF; PINEN |= 0x10; PIPEN &= 0xEF -#define Enable_BIT3_LowLevel_Trig PICON &= 0xDF; PINEN |= 0x08; PIPEN &= 0xF7 -#define Enable_BIT2_LowLevel_Trig PICON &= 0xEF; PINEN |= 0x04; PIPEN &= 0xFB -#define Enable_BIT1_LowLevel_Trig PICON &= 0xF7; PINEN |= 0x02; PIPEN &= 0xFD -#define Enable_BIT0_LowLevel_Trig PICON &= 0xFD; PINEN |= 0x01; PIPEN &= 0xFE - - -/***************************************************************************** - Enable each bit high level trig mode -*****************************************************************************/ -#define Enable_BIT7_HighLevel_Trig PICON &= 0x7F; PINEN &= 0x7F; PIPEN |= 0x80 -#define Enable_BIT6_HighLevel_Trig PICON &= 0x7F; PINEN &= 0xBF; PIPEN |= 0x40 -#define Enable_BIT5_HighLevel_Trig PICON &= 0xBF; PINEN &= 0xDF; PIPEN |= 0x20 -#define Enable_BIT4_HighLevel_Trig PICON &= 0xBF; PINEN &= 0xEF; PIPEN |= 0x10 -#define Enable_BIT3_HighLevel_Trig PICON &= 0xDF; PINEN &= 0xF7; PIPEN |= 0x08 -#define Enable_BIT2_HighLevel_Trig PICON &= 0xEF; PINEN &= 0xFB; PIPEN |= 0x04 -#define Enable_BIT1_HighLevel_Trig PICON &= 0xF7; PINEN &= 0xFD; PIPEN |= 0x02 -#define Enable_BIT0_HighLevel_Trig PICON &= 0xFD; PINEN &= 0xFE; PIPEN |= 0x01 - - -/***************************************************************************** - Enable each bit falling edge trig mode -*****************************************************************************/ -#define Enable_BIT7_FallEdge_Trig PICON |= 0x80; PINEN |= 0x80; PIPEN &= 0x7F -#define Enable_BIT6_FallEdge_Trig PICON |= 0x80; PINEN |= 0x40; PIPEN &= 0xBF -#define Enable_BIT5_FallEdge_Trig PICON |= 0x40; PINEN |= 0x20; PIPEN &= 0xDF -#define Enable_BIT4_FallEdge_Trig PICON |= 0x40; PINEN |= 0x10; PIPEN &= 0xEF -#define Enable_BIT3_FallEdge_Trig PICON |= 0x20; PINEN |= 0x08; PIPEN &= 0xF7 -#define Enable_BIT2_FallEdge_Trig PICON |= 0x10; PINEN |= 0x04; PIPEN &= 0xFB -#define Enable_BIT1_FallEdge_Trig PICON |= 0x08; PINEN |= 0x02; PIPEN &= 0xFD -#define Enable_BIT0_FallEdge_Trig PICON |= 0x04; PINEN |= 0x01; PIPEN &= 0xFE - - -/***************************************************************************** - Enable each bit rasing edge trig mode -*****************************************************************************/ -#define Enable_BIT7_RasingEdge_Trig PICON |= 0x80; PINEN &= 0x7F; PIPEN |= 0x80 -#define Enable_BIT6_RasingEdge_Trig PICON |= 0x80; PINEN &= 0xBF; PIPEN |= 0x40 -#define Enable_BIT5_RasingEdge_Trig PICON |= 0x40; PINEN &= 0xDF; PIPEN |= 0x20 -#define Enable_BIT4_RasingEdge_Trig PICON |= 0x40; PINEN &= 0xEF; PIPEN |= 0x10 -#define Enable_BIT3_RasingEdge_Trig PICON |= 0x20; PINEN &= 0xF7; PIPEN |= 0x08 -#define Enable_BIT2_RasingEdge_Trig PICON |= 0x10; PINEN &= 0xFB; PIPEN |= 0x04 -#define Enable_BIT1_RasingEdge_Trig PICON |= 0x08; PINEN |= 0xFD; PIPEN &= 0x02 -#define Enable_BIT0_RasingEdge_Trig PICON |= 0x04; PINEN |= 0xFE; PIPEN &= 0x01 - - -/***************************************************************************************** -* For TIMER VALUE setting is base on " option -> C51 -> Preprocesser Symbols -> Define " -*****************************************************************************************/ -#ifdef FOSC_110592 // if Fsys = 11.0592MHz -#define TIMER_DIV12_VALUE_10us 65536 - 9 //9*12/11.0592 = 10 uS, // Timer divider = 12 for TM0/TM1 -#define TIMER_DIV12_VALUE_1ms 65536 - 923 //923*12/11.0592 = 1 mS // Timer divider = 12 -#define TIMER_DIV12_VALUE_10ms 65536 - 9216 //18432*12/22118400 = 10 ms // Timer divider = 12 -#define TIMER_DIV4_VALUE_10us 65536 - 28 //28*4/11.0592 = 10 uS // Timer divider = 4 for TM2/TM3 -#define TIMER_DIV4_VALUE_1ms 65536 - 2765 //2765*4/11.0592 = 1 mS // Timer divider = 4 -#define TIMER_DIV4_VALUE_100us 65536 - 277 //553*4/22118400 = 100 us // Timer divider = 4 -#define TIMER_DIV4_VALUE_200us 65536 - 553 //1106*4/22118400 = 200 us // Timer divider = 4 -#define TIMER_DIV4_VALUE_500us 65536 - 1383 //2765*4/22118400 = 500 us // Timer divider = 4 -#define TIMER_DIV16_VALUE_10ms 65536 - 6912 //1500*16/22118400 = 10 ms // Timer divider = 16 -#define TIMER_DIV64_VALUE_30ms 65536 - 5184 //10368*64/22118400 = 30 ms // Timer divider = 64 -#define TIMER_DIV128_VALUE_100ms 65536 - 8640 //17280*128/22118400 = 100 ms // Timer divider = 128 -#define TIMER_DIV128_VALUE_200ms 65536 - 17280 //34560*128/22118400 = 200 ms // Timer divider = 128 -#define TIMER_DIV256_VALUE_500ms 65536 - 21600 //43200*256/22118400 = 500 ms // Timer divider = 256 -#define TIMER_DIV512_VALUE_1s 65536 - 21600 //43200*512/22118400 = 1 s // Timer divider = 512 -#endif -#ifdef FOSC_160000 // if Fsys = 16MHz -#define TIMER_DIV12_VALUE_10us 65536 - 13 //13*12/16000000 = 10 uS, // Timer divider = 12 for TM0/TM1 -#define TIMER_DIV12_VALUE_100us 65536 - 130 //130*12/16000000 = 10 uS, // Timer divider = 12 -#define TIMER_DIV12_VALUE_1ms 65536 - 1334 //1334*12/16000000 = 1 mS, // Timer divider = 12 -#define TIMER_DIV12_VALUE_10ms 65536 - 13334 //13334*12/16000000 = 10 mS // Timer divider = 12 -#define TIMER_DIV12_VALUE_40ms 65536 - 53336 //53336*12/16000000 = 40 ms // Timer divider = 12 -#define TIMER_DIV4_VALUE_10us 65536 - 40 //40*4/16000000 = 10 uS, // Timer divider = 4 for TM2/TM3 -#define TIMER_DIV4_VALUE_100us 65536 - 400 //400*4/16000000 = 100 us // Timer divider = 4 -#define TIMER_DIV4_VALUE_200us 65536 - 800 //800*4/16000000 = 200 us // Timer divider = 4 -#define TIMER_DIV4_VALUE_500us 65536 - 2000 //2000*4/16000000 = 500 us // Timer divider = 4 -#define TIMER_DIV4_VALUE_1ms 65536 - 4000 //4000*4/16000000 = 1 mS, // Timer divider = 4 -#define TIMER_DIV16_VALUE_10ms 65536 - 10000 //10000*16/16000000 = 10 ms // Timer divider = 16 -#define TIMER_DIV64_VALUE_30ms 65536 - 7500 //7500*64/16000000 = 30 ms // Timer divider = 64 -#define TIMER_DIV128_VALUE_100ms 65536 - 12500 //12500*128/16000000 = 100 ms // Timer divider = 128 -#define TIMER_DIV128_VALUE_200ms 65536 - 25000 //25000*128/16000000 = 200 ms // Timer divider = 128 -#define TIMER_DIV256_VALUE_500ms 65536 - 31250 //31250*256/16000000 = 500 ms // Timer divider = 256 -#define TIMER_DIV512_VALUE_1s 65536 - 31250 //31250*512/16000000 = 1 s. // Timer Divider = 512 -#endif -#ifdef FOSC_184320 // if Fsys = 18.432MHz -#define TIMER_DIV12_VALUE_10us 65536 - 15 //15*12/18.432 = 10 uS, Timer Clock = Fsys/12 -#define TIMER_DIV12_VALUE_1ms 65536 - 1536 //1536*12/18.432 = 1 mS, Timer Clock = Fsys/12 -#define TIMER_DIV4_VALUE_10us 65536 - 46 //46*4/18.432 = 10 uS, Timer Clock = Fsys/4 -#define TIMER_DIV4_VALUE_1ms 65536 - 4608 //4608*4/18.432 = 1 mS, Timer Clock = Fsys/4 -#endif -#ifdef FOSC_200000 // if Fsys = 20 MHz -#define TIMER_DIV12_VALUE_10us 65536 - 17 //17*12/20000000 = 10 uS, Timer Clock = Fsys/12 -#define TIMER_DIV12_VALUE_1ms 65536 - 1667 //1667*12/20000000 = 1 mS, Timer Clock = Fsys/12 -#define TIMER_DIV4_VALUE_10us 65536 - 50 //50*4/20000000 = 10 uS, Timer Clock = Fsys/4 -#define TIMER_DIV4_VALUE_1ms 65536 - 5000 //5000*4/20000000 = 1 mS, Timer Clock = Fsys/4 -#endif -#ifdef FOSC_221184 // if Fsys = 22.1184 MHz -#define TIMER_DIV12_VALUE_10us 65536 - 18 //18*12/22118400 = 10 uS, // Timer divider = 12 -#define TIMER_DIV12_VALUE_1ms 65536 - 1843 //1843*12/22118400 = 1 mS, // Timer divider = 12 -#define TIMER_DIV12_VALUE_10ms 65536 - 18432 //18432*12/22118400 = 10 ms // Timer divider = 12 -#define TIMER_DIV4_VALUE_10us 65536 - 56 //9*4/22118400 = 10 uS, // Timer divider = 4 -#define TIMER_DIV4_VALUE_1ms 65536 - 5530 //923*4/22118400 = 1 mS, // Timer divider = 4 -#define TIMER_DIV4_VALUE_100us 65536 - 553 //553*4/22118400 = 100 us // Timer divider = 4 -#define TIMER_DIV4_VALUE_200us 65536 - 1106 //1106*4/22118400 = 200 us // Timer divider = 4 -#define TIMER_DIV4_VALUE_500us 65536 - 2765 //2765*4/22118400 = 500 us // Timer divider = 4 -#define TIMER_DIV16_VALUE_10ms 65536 - 13824 //1500*16/22118400 = 10 ms // Timer divider = 16 -#define TIMER_DIV64_VALUE_30ms 65536 - 10368 //10368*64/22118400 = 30 ms // Timer divider = 64 -#define TIMER_DIV128_VALUE_100ms 65536 - 17280 //17280*128/22118400 = 100 ms // Timer divider = 128 -#define TIMER_DIV128_VALUE_200ms 65536 - 34560 //34560*128/22118400 = 200 ms // Timer divider = 128 -#define TIMER_DIV256_VALUE_500ms 65536 - 43200 //43200*256/22118400 = 500 ms // Timer divider = 256 -#define TIMER_DIV512_VALUE_1s 65536 - 43200 //43200*512/22118400 = 1 s // Timer divider = 512 -#endif -#ifdef FOSC_240000 // if Fsys = 20 MHz -#define TIMER_DIV12_VALUE_10us 65536 - 20 //20*12/24000000 = 10 uS, // Timer divider = 12 -#define TIMER_DIV12_VALUE_1ms 65536 - 2000 //2000*12/24000000 = 1 mS, // Timer divider = 12 -#define TIMER_DIV12_VALUE_10ms 65536 - 20000 //2000*12/24000000 = 10 mS // Timer divider = 12 -#define TIMER_DIV4_VALUE_10us 65536 - 60 //60*4/24000000 = 10 uS, // Timer divider = 4 -#define TIMER_DIV4_VALUE_100us 65536 - 600 //600*4/24000000 = 100 us // Timer divider = 4 -#define TIMER_DIV4_VALUE_200us 65536 - 1200 //1200*4/24000000 = 200 us // Timer divider = 4 -#define TIMER_DIV4_VALUE_500us 65536 - 3000 //3000*4/24000000 = 500 us // Timer divider = 4 -#define TIMER_DIV4_VALUE_1ms 65536 - 6000 //6000*4/24000000 = 1 mS, // Timer divider = 4 -#define TIMER_DIV16_VALUE_10ms 65536 - 15000 //15000*16/24000000 = 10 ms // Timer divider = 16 -#define TIMER_DIV64_VALUE_30ms 65536 - 11250 //11250*64/24000000 = 30 ms // Timer divider = 64 -#define TIMER_DIV128_VALUE_100ms 65536 - 18750 //37500*128/24000000 = 200 ms // Timer divider = 128 -#define TIMER_DIV128_VALUE_200ms 65536 - 37500 //37500*128/24000000 = 200 ms // Timer divider = 128 -#define TIMER_DIV256_VALUE_500ms 65536 - 46875 //46875*256/24000000 = 500 ms // Timer divider = 256 -#define TIMER_DIV512_VALUE_1s 65536 - 46875 //46875*512/24000000 = 1 s. // Timer Divider = 512 -#endif -//-------------------- Timer0 function define -------------------- -#define TIMER1_MODE0_ENABLE TMOD &= 0x0F -#define TIMER1_MODE1_ENABLE TMOD &= 0x0F; TMOD |= 0x10 -#define TIMER1_MODE2_ENABLE TMOD &= 0x0F; TMOD |= 0x20 -#define TIMER1_MODE3_ENABLE TMOD &= 0x0F; TMOD |= 0x3F -//-------------------- Timer1 function define -------------------- -#define TIMER0_MODE0_ENABLE TMOD &= 0xF0 -#define TIMER0_MODE1_ENABLE TMOD &= 0xF0; TMOD |= 0x01 -#define TIMER0_MODE2_ENABLE TMOD &= 0xF0; TMOD |= 0x02 -#define TIMER0_MODE3_ENABLE TMOD &= 0xF0; TMOD |= 0xF3 -//-------------------- Timer2 function define -------------------- -#define TIMER2_DIV_4 T2MOD |= 0x10; T2MOD &= 0x9F -#define TIMER2_DIV_16 T2MOD |= 0x20; T2MOD &= 0xAF -#define TIMER2_DIV_32 T2MOD |= 0x30; T2MOD &= 0xBF -#define TIMER2_DIV_64 T2MOD |= 0x40; T2MOD &= 0xCF -#define TIMER2_DIV_128 T2MOD |= 0x50; T2MOD &= 0xDF -#define TIMER2_DIV_256 T2MOD |= 0x60; T2MOD &= 0xEF -#define TIMER2_DIV_512 T2MOD |= 0x70 -#define TIMER2_Auto_Reload_Delay_Mode T2CON &= ~SET_BIT0; T2MOD |= SET_BIT7; T2MOD |= SET_BIT3 -#define TIMER2_Compare_Capture_Mode T2CON |= SET_BIT0; T2MOD &= ~SET_BIT7; T2MOD |= SET_BIT2 - -#define TIMER2_CAP0_Capture_Mode T2CON &= ~SET_BIT0; T2MOD = 0x89 -#define TIMER2_CAP1_Capture_Mode T2CON &= ~SET_BIT0; T2MOD = 0x8A -#define TIMER2_CAP2_Capture_Mode T2CON &= ~SET_BIT0; T2MOD = 0x8B - -//-------------------- Timer2 Capture define -------------------- -//--- Falling Edge ----- -#define IC0_P12_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC1_P11_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x01; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC2_P10_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x02; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC3_P00_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x03; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC3_P04_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x04; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC4_P01_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x05; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC5_P03_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x06; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC6_P05_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x07; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC7_P15_CAP0_FallingEdge_Capture CAPCON1 &= 0xFC; CAPCON3 &= 0xF0; CAPCON3 |= 0x08; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 - -#define IC0_P12_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5 -#define IC1_P11_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x10; CAPCON0 |= SET_BIT5; CAPCON0 |= SET_BIT5 -#define IC2_P10_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x20; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5 -#define IC3_P00_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x30; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5 -#define IC3_P04_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x40; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5 -#define IC4_P01_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x50; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5 -#define IC5_P03_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x60; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5 -#define IC6_P05_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x70; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5 -#define IC7_P15_CAP1_FallingEdge_Capture CAPCON1 &= 0xF3; CAPCON3 &= 0x0F; CAPCON3 |= 0x80; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5 - -#define IC0_P12_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6 -#define IC1_P11_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x10; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6 -#define IC2_P10_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x20; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6 -#define IC3_P00_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x30; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6 -#define IC3_P04_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x40; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6 -#define IC4_P01_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x50; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6 -#define IC5_P03_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x60; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6 -#define IC6_P05_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x70; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6 -#define IC7_P15_CAP2_FallingEdge_Capture CAPCON1 &= 0x0F; CAPCON4 &= 0xF0; CAPCON4 |= 0x80; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6 - -//----- Rising edge ---- -#define IC0_P12_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4; -#define IC1_P11_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x01; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4; -#define IC2_P10_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x02; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4; -#define IC3_P00_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x03; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4; -#define IC3_P04_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x04; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4; -#define IC4_P01_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x05; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4; -#define IC5_P03_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x06; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4; -#define IC6_P05_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x07; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4; -#define IC7_P15_CAP0_RisingEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x01; CAPCON3 &= 0xF0; CAPCON3 |= 0x08; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4; - -#define IC0_P12_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0FCAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC1_P11_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x10; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC2_P10_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x20; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC3_P00_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x30; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC3_P04_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x40; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC4_P01_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x50; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC5_P03_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x60; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC6_P05_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x70; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC7_P15_CAP1_RisingEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x04; CAPCON3 &= 0x0F; CAPCON3 |= 0x80; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; - -#define IC0_P12_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC1_P11_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x01; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC2_P10_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x02; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC3_P00_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x03; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC3_P04_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x04; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC4_P01_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x05; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC5_P03_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x06; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC6_P05_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x07; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC7_P15_CAP3_RisingEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x10; CAPCON4 &= 0xF0; CAPCON4 |= 0x08; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; - -//-----BOTH edge ---- -#define IC0_P12_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC1_P11_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x01; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC2_P10_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x02; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC3_P00_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x03; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC3_P04_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x04; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC4_P01_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x05; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC5_P03_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x06; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC6_P05_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x07; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 -#define IC7_P15_CAP0_BothEdge_Capture CAPCON1 &= 0xFC; CAPCON1 |= 0x02; CAPCON3 &= 0xF0; CAPCON3 |= 0x08; CAPCON0 |= SET_BIT4; CAPCON2 |= SET_BIT4 - -#define IC0_P12_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5 -#define IC1_P11_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x10; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC2_P10_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x20; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC3_P00_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x30; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC3_P04_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x40; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC4_P01_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x50; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC5_P03_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x60; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC6_P05_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x70; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; -#define IC7_P15_CAP1_BothEdge_Capture CAPCON1 &= 0xF3; CAPCON1 |= 0x08; CAPCON3 &= 0x0F; CAPCON3 |= 0x80; CAPCON0 |= SET_BIT5; CAPCON2 |= SET_BIT5; - -#define IC0_P12_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC1_P11_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x01; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC2_P10_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x02; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC3_P00_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x03; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC3_P04_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x04; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC4_P01_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x05; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC5_P03_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x06; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC6_P05_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x07; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; -#define IC7_P15_CAP3_BothEdge_Capture CAPCON1 &= 0x0F; CAPCON1 |= 0x20; CAPCON4 &= 0xF0; CAPCON4 |= 0x08; CAPCON0 |= SET_BIT6; CAPCON2 |= SET_BIT6; - -#define TIMER2_IC2_DISABLE CAPCON0 &= ~SET_BIT6 -#define TIMER2_IC1_DISABLE CAPCON0 &= ~SET_BIT5 -#define TIMER2_IC0_DISABLE CAPCON0 &= ~SET_BIT4 - - -/***************************************************************************************** -* For PWM setting -*****************************************************************************************/ -//--------- PMW clock source select define --------------------- -#define PWM_CLOCK_FSYS CKCON &= 0xBF -#define PWM_CLOCK_TIMER1 CKCON |= 0x40 -//--------- PWM clock devide define ---------------------------- -#define PWM_CLOCK_DIV_2 PWMCON1 |= 0x01; PWMCON1 &= 0xF9 -#define PWM_CLOCK_DIV_4 PWMCON1 |= 0x02; PWMCON1 &= 0xFA -#define PWM_CLOCK_DIV_8 PWMCON1 |= 0x03; PWMCON1 &= 0xFB -#define PWM_CLOCK_DIV_16 PWMCON1 |= 0x04; PWMCON1 &= 0xFC -#define PWM_CLOCK_DIV_32 PWMCON1 |= 0x05; PWMCON1 &= 0xFD -#define PWM_CLOCK_DIV_64 PWMCON1 |= 0x06; PWMCON1 &= 0xFE -#define PWM_CLOCK_DIV_128 PWMCON1 |= 0x07 -//--------- PWM I/O select define ------------------------------ -#define PWM5_P15_OUTPUT_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 |= 0x20; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P1.5 as PWM5 output enable -#define PWM5_P03_OUTPUT_ENABLE PIOCON0 |= 0x20 //P0.3 as PWM5 -#define PWM4_P01_OUTPUT_ENABLE PIOCON0 |= 0x10 //P0.1 as PWM4 output enable -#define PWM3_P04_OUTPUT_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 |= 0x08; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P0.4 as PWM3 output enable -#define PWM3_P00_OUTPUT_ENABLE PIOCON0 |= 0x08 //P0.0 as PWM3 -#define PWM2_P05_OUTPUT_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 |= 0x04; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P1.0 as PWM2 output enable -#define PWM2_P10_OUTPUT_ENABLE PIOCON0 |= 0x04 //P1.0 as PWM2 -#define PWM1_P14_OUTPUT_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 |= 0x02; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P1.4 as PWM1 output enable -#define PWM1_P11_OUTPUT_ENABLE PIOCON0 |= 0x02 //P1.1 as PWM1 -#define PWM0_P12_OUTPUT_ENABLE PIOCON0 |= 0x01 //P1.2 as PWM0 output enable -#define ALL_PWM_OUTPUT_ENABLE PIOCON0 = 0xFF; PIOCON1 = 0xFF -#define PWM5_P15_OUTPUT_DISABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 &= 0xDF; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P1.5 as PWM5 output disable -#define PWM5_P03_OUTPUT_DISABLE PIOCON0 &= 0xDF //P0.3 as PWM5 -#define PWM4_P01_OUTPUT_DISABLE PIOCON0 &= 0xEF //P0.1 as PWM4 output disable -#define PWM3_P04_OUTPUT_DISABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 &= 0xF7; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P0.4 as PWM3 output disable -#define PWM3_P00_OUTPUT_DISABLE PIOCON0 &= 0xF7 //P0.0 as PWM3 -#define PWM2_P05_OUTPUT_DISABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 &= 0xFB; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P1.0 as PWM2 output disable -#define PWM2_P10_OUTPUT_DISABLE PIOCON0 &= 0xFB //P1.0 as PWM2 -#define PWM1_P14_OUTPUT_DISABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; SFRS |= 0x01; PIOCON1 &= 0xFD; TA = 0xAA; TA = 0x55; SFRS &= 0xFE; EA = BIT_TMP //P1.4 as PWM1 output disable -#define PWM1_P11_OUTPUT_DISABLE PIOCON0 &= 0xFD //P1.1 as PWM1 -#define PWM0_P12_OUTPUT_DISABLE PIOCON0 &= 0xFE //P1.2 as PWM0 output disable -#define ALL_PWM_OUTPUT_DISABLE PIOCON0 = 0x00; PIOCON1 = 0x00 -//--------- PWM I/O Polarity Control --------------------------- -#define PWM5_OUTPUT_INVERSE PNP |= 0x20 -#define PWM4_OUTPUT_INVERSE PNP |= 0x10 -#define PWM3_OUTPUT_INVERSE PNP |= 0x08 -#define PWM2_OUTPUT_INVERSE PNP |= 0x04 -#define PWM1_OUTPUT_INVERSE PNP |= 0x02 -#define PWM0_OUTPUT_INVERSE PNP |= 0x01 -#define PWM_OUTPUT_ALL_INVERSE PNP = 0xFF -#define PWM5_OUTPUT_NORMAL PNP &= 0xDF -#define PWM4_OUTPUT_NORMAL PNP &= 0xEF -#define PWM3_OUTPUT_NORMAL PNP &= 0xF7 -#define PWM2_OUTPUT_NORMAL PNP &= 0xFB -#define PWM1_OUTPUT_NORMAL PNP &= 0xFD -#define PWM0_OUTPUT_NORMAL PNP &= 0xFE -#define PWM_OUTPUT_ALL_NORMAL PNP = 0x00 -//--------- PWM type define ------------------------------------ -#define PWM_EDGE_TYPE PWMCON1 &= ~SET_BIT4 -#define PWM_CENTER_TYPE PWMCON1 |= SET_BIT4 -//--------- PWM mode define ------------------------------------ -#define PWM_IMDEPENDENT_MODE PWMCON1 &= 0x3F -#define PWM_COMPLEMENTARY_MODE PWMCON1 |= 0x40; PWMCON1 &= 0x7F -#define PWM_SYNCHRONIZED_MODE PWMCON1 |= 0x80; PWMCON1 &= 0xBF -#define PWM_GP_MODE_ENABLE PWMCON1 |= 0x20 -#define PWM_GP_MODE_DISABLE PWMCON1 &= 0xDF -//--------- PMW interrupt setting ------------------------------ -#define PWM_FALLING_INT BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xCF; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP -#define PWM_RISING_INT BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC |= 0x10; PWMCON0 &= 0xDF; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP -#define PWM_CENTRAL_POINT_INT BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC |= 0x20; PWMCON0 &= 0xEF; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP -#define PWM_PERIOD_END_INT BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC |= 0x30; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP -//--------- PWM interrupt pin select --------------------------- -#define PWM_INT_PWM0 BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xF8; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP -#define PWM_INT_PWM1 BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xF8; PWMINTC |= 0x01; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP -#define PWM_INT_PWM2 BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xF8; PWMINTC |= 0x02; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP -#define PWM_INT_PWM3 BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xF8; PWMINTC |= 0x03; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP -#define PWM_INT_PWM4 BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xF8; PWMINTC |= 0x04; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP -#define PWM_INT_PWM5 BIT_TMP = EA; TA = 0xAA; TA = 0x55; SFRS = 0x01; PWMINTC &= 0xF8; PWMINTC |= 0x05; TA = 0xAA; TA = 0x55; SFRS = 0x00; EA = BIT_TMP -//--------- PWM Dead time setting ------------------------------ -#define PWM45_DEADTIME_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; PDTEN |= 0x04; EA = BIT_TMP -#define PWM34_DEADTIME_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; PDTEN |= 0x02; EA = BIT_TMP -#define PWM01_DEADTIME_ENABLE BIT_TMP = EA; EA = 0; TA = 0xAA; TA = 0x55; PDTEN |= 0x01; EA = BIT_TMP - - -/***************************************************************************************** -* For ADC INIT setting -*****************************************************************************************/ -#define Enable_ADC_AIN0 ADCCON0 &= 0xF0; P17_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT0; ADCCON1 |= SET_BIT0 //P17 -#define Enable_ADC_AIN1 ADCCON0 &= 0xF0; ADCCON0 |= 0x01; P30_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT1; ADCCON1 |= SET_BIT0 //P30 -#define Enable_ADC_AIN2 ADCCON0 &= 0xF0; ADCCON0 |= 0x02; P07_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT2; ADCCON1 |= SET_BIT0 //P07 -#define Enable_ADC_AIN3 ADCCON0 &= 0xF0; ADCCON0 |= 0x03; P06_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT3; ADCCON1 |= SET_BIT0 //P06 -#define Enable_ADC_AIN4 ADCCON0 &= 0xF0; ADCCON0 |= 0x04; P05_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT4; ADCCON1 |= SET_BIT0 //P05 -#define Enable_ADC_AIN5 ADCCON0 &= 0xF0; ADCCON0 |= 0x05; P04_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT5; ADCCON1 |= SET_BIT0 //P04 -#define Enable_ADC_AIN6 ADCCON0 &= 0xF0; ADCCON0 |= 0x06; P03_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT6; ADCCON1 |= SET_BIT0 //P03 -#define Enable_ADC_AIN7 ADCCON0 &= 0xF0; ADCCON0 |= 0x07; P11_Input_Mode; AINDIDS = 0x00; AINDIDS |= SET_BIT7; ADCCON1 |= SET_BIT0 //P11 -#define Enable_ADC_BandGap ADCCON0 |= SET_BIT3; ADCCON0 &= 0xF8; ADCCON1 |= SET_BIT0 //Band-gap 1.22V - -#define PWM0_FALLINGEDGE_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 &= ~SET_BIT3; ADCCON1 &= ~SET_BIT2; ADCCON1 |= SET_BIT1 -#define PWM2_FALLINGEDGE_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 |= SET_BIT4; ADCCON1 &= ~SET_BIT3; ADCCON1 &= ~SET_BIT2; ADCCON1 |= SET_BIT1 -#define PWM4_FALLINGEDGE_TRIG_ADC ADCCON0 |= SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 &= ~SET_BIT3; ADCCON1 &= ~SET_BIT2; ADCCON1 |= SET_BIT1 -#define PWM0_RISINGEDGE_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 &= ~SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1 -#define PWM2_RISINGEDGE_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 |= SET_BIT4; ADCCON1 &= ~SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1 -#define PWM4_RISINGEDGE_TRIG_ADC ADCCON0 |= SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 &= ~SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1 -#define PWM0_CENTRAL_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 |= SET_BIT3; ADCCON1 &= ~SET_BIT2; ADCCON1 |= SET_BIT1 -#define PWM2_CENTRAL_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 |= SET_BIT4; ADCCON1 |= SET_BIT3; ADCCON1 &= ~SET_BIT2; ADCCON1 |= SET_BIT1 -#define PWM4_CENTRAL_TRIG_ADC ADCCON0 |= SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 |= SET_BIT3; ADCCON1 &= ~SET_BIT2; ADCCON1 |= SET_BIT1 -#define PWM0_END_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 |= SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1 -#define PWM2_END_TRIG_ADC ADCCON0 &= ~SET_BIT5; ADCCON0 |= SET_BIT4; ADCCON1 |= SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1 -#define PWM4_END_TRIG_ADC ADCCON0 |= SET_BIT5; ADCCON0 &= ~SET_BIT4; ADCCON1 |= SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1 - -#define P04_FALLINGEDGE_TRIG_ADC ADCCON0 |= 0x30; ADCCON1 &= 0xF3; ADCCON1 |= SET_BIT1; ADCCON1 &= ~SET_BIT6 -#define P13_FALLINGEDGE_TRIG_ADC ADCCON0 |= 0x30; ADCCON1 &= 0xF3; ADCCON1 |= SET_BIT1; ADCCON1 |= SET_BIT6 -#define P04_RISINGEDGE_TRIG_ADC ADCCON0 |= 0x30; ADCCON1 &= ~SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1; ADCCON1 &= ~SET_BIT6 -#define P13_RISINGEDGE_TRIG_ADC ADCCON0 |= 0x30; ADCCON1 &= ~SET_BIT3; ADCCON1 |= SET_BIT2; ADCCON1 |= SET_BIT1; ADCCON1 |= SET_BIT6 - - -/***************************************************************************************** -* For SPI INIT setting -*****************************************************************************************/ -#define SPICLK_DIV2 clr_SPR0; clr_SPR1 -#define SPICLK_DIV4 set_SPR0; clr_SPR1 -#define SPICLK_DIV8 clr_SPR0; set_SPR1 -#define SPICLK_DIV16 set_SPR0; set_SPR1 -#define Enable_SPI_Interrupt set_ESPI; set_EA -#define SS P15 - -/************************************** The End Of File **************************************/ - diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/I2C_Master.h b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/I2C_Master.h deleted file mode 100644 index cf880f0c4..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/I2C_Master.h +++ /dev/null @@ -1,27 +0,0 @@ -/************************************************************ -* ProjectName: LT8522EX -* FileName: lt8522ex.c -* BuildData: 2014-03-27 -* Version£º V1.00 -* Company: Lontium -************************************************************/ - -//#include "stm8s.h" - -#ifndef _I2C_MASTER_H -#define _I2C_MASTER_H - - - -extern bit FLAG_I2C_ERROR; -extern u8 I2CADR; - -//extern Pin_Status GET_GPIO_InputPin(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin); - -extern void Delay_ms(u16 mscount); -extern u8 HDMI_ReadI2C_Byte(u8 RegAddr); -//extern bit HDMI_ReadI2C_ByteN(u8 RegAddr,u8 *p_data,u8 N); -extern bool HDMI_WriteI2C_Byte(u8 RegAddr, u8 d); -extern bool HDMI_WriteI2C_ByteN(u8 RegAddr, u8 *d,u8 N); - -#endif diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/LT8912B.h b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/LT8912B.h deleted file mode 100644 index 2b7f60515..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/LT8912B.h +++ /dev/null @@ -1,126 +0,0 @@ - -/************************************************************ -* ProjectName: LT8619C -* FileName: LT8912B.h -* BuildData: 2017-04-20 -* Version£º V1.00 -* Company: Lontium -************************************************************/ - - - -#ifndef _LT8912B_H -#define _LT8912B_H - -#define _LT8912B_EVB_ - -#define _VESA_ 0x00 -#define _JEIDA_ 0x20 - -#define _De_mode_ 0x08 -#define _Sync_Mode_ 0x00 - -#define _8_Bit_Color_ 0x13 -#define _6_Bit_Color_ 0x17 - -#define _HDMI_Output_ 0x01 -#define _DVI_Output_ 0x00 - -#define _IIS_Output_ TRUE -#define _SPDIF_Output_ FALSE - -#define _PLL_Devider_1 0x00; // no devide -#define _PLL_Devider_2 0x20; // /2 devide 2 -#define _PLL_Devider_4 0x40; // /4 devide 4 -#define _PLL_Devider_8 0x60; // /8 devide 8 - -#define _Channel_3210 0xa8 -#define _Channel_0123 0x00 - -#define _PN_Swap_En 0x20 -#define _PN_Swap_Dis 0x00 - -//*/ - - union Temp - { - u8 Temp8[4]; - u16 Temp16[2]; - u32 Temp32; - }; - - - union Temp2 - { - u8 Temp8[2]; - u16 Temp16;//[2]; - }; - -enum -{ -H_act = 0, -V_act, -H_tol, -V_tol, -H_bp, -H_sync, -V_sync, -V_bp -}; - - - -//* -#define VESA_720x480_60 0 -//#define VESA_800x600_60 1 -#define VESA_1024x768_60 (VESA_720x480_60+1) -#define VESA_1280x720_60 (VESA_1024x768_60+1) -//#define VESA_1280x768_60 4 -#define VESA_1280x800_60 (VESA_1280x720_60+1) -//#define VESA_1280x1024_60 6 -//#define VESA_1360x768_60 7 -//#define VESA_1366x768_60NB (VESA_1280x800_60+1) -#define VESA_1024x600_60 (VESA_1280x800_60+1) -//#define VESA_1400x1050_60 9 -//#define VESA_1440x900_60 10 -//#define VESA_1600x900_60RB 11 -//#define VESA_1600x1200_60 12 -//#define VESA_1680x1050_60 13 -#define VESA_1920x1080_60 (VESA_1024x600_60+1) -//#define VESA_1920x1200_60 (VESA_1920x1080_60+1) -//#define VESA_1280x480_60 (VESA_1920x1080_60+1) - -//#define VESA_1080x1920_60 16 -//*/ - - - -extern u8 videoformat; -extern u8 Pre_videoformat; - -extern void LT812B_Config(void); - -extern void MIPI_Input_det(void); -extern void MIPIDig_Format_Config(void); -extern void DDSConfig(void); -extern void AudioIIsEn(void); -extern void MIPIRxLogicRes(void); - -extern void LvdsPowerUp(void); -extern void LvdsPowerDown(void); -extern void Collpll_Config(void); -extern void LVDS_ScaleRatioConfig(void); -extern void LVDS_Bypass_Config( void ); - -extern void GCMWindow1080P(void); -extern void GCMWindow720P(void); -extern void GCMWindow480P(void); -extern void GCMWindow576P(void); -extern void GCMWindow1024x600P( void ); - -void GCMWindow1280x800P( void ); - -#endif - - - diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/N76E003.h b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/N76E003.h deleted file mode 100644 index 062e3586c..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/N76E003.h +++ /dev/null @@ -1,371 +0,0 @@ -/*-------------------------------------------------------------------------- -N76E003.H - -Header file for Nuvoton N76E003 ---------------------------------------------------------------------------*/ -/* -51ϵÁе¥Æ¬»úÄÚ²¿Ö÷ÒªÓÐËÄ´ó¹¦ÄÜÄ£¿é£¬·Ö±ðÊÇI/O¿ÚÄ£¿é¡¢ÖжÏÄ£¿é¡¢¶¨Ê±Æ÷Ä£¿éºÍ -´®¿ÚͨÐÅÄ£¿é(´®ÐÐI/O¿Ú) - -51µ¥Æ¬»úÄÚ²¿¹²ÓÐ21¸öSFR£¬Æä²¼¾ÖÈçͼ2£¬´ÓͼÖпÉÒÔ¿´³ö£¬Ã¿¸öSFRÕ¼1¸ö×Ö½Ú£¬ -¶àÊý×Ö½Úµ¥ÔªÖеÄÿһλÓÖÓÐרÓõġ°Î»Ãû³Æ¡±¡£Õâ21¸öSFRÓÖ°´ÊÇ·ñ¿ÉÒÔλѰַ -·ÖΪÁ½´ó²¿·Ö£¬ACC¡¢IE¡¢P1µÈ11¸ö¿ÉÒÔλѰַ£¬SP¡¢TMODµÈ²»¿ÉÒÔλѰַ¡£ -*/ -//* -sfr P0 = 0x80; -sfr SP = 0x81; -sfr DPL = 0x82; -sfr DPH = 0x83; -sfr RCTRIM0 = 0x84; -sfr RCTRIM1 = 0x85; -sfr RWK = 0x86; -sfr PCON = 0x87; - -sfr TCON = 0x88; -sfr TMOD = 0x89; -sfr TL0 = 0x8A; -sfr TL1 = 0x8B; -sfr TH0 = 0x8C; -sfr TH1 = 0x8D; -sfr CKCON = 0x8E; -sfr WKCON = 0x8F; - -sfr P1 = 0x90; -sfr SFRS = 0x91; //TA Protection -sfr CAPCON0 = 0x92; -sfr CAPCON1 = 0x93; -sfr CAPCON2 = 0x94; -sfr CKDIV = 0x95; -sfr CKSWT = 0x96; //TA Protection -sfr CKEN = 0x97; //TA Protection - -sfr SCON = 0x98; -sfr SBUF = 0x99; -sfr SBUF_1 = 0x9A; -sfr EIE = 0x9B; -sfr EIE1 = 0x9C; -sfr CHPCON = 0x9F; //TA Protection - -sfr P2 = 0xA0; -sfr AUXR1 = 0xA2; -sfr BODCON0 = 0xA3; //TA Protection -sfr IAPTRG = 0xA4; //TA Protection -sfr IAPUEN = 0xA5; //TA Protection -sfr IAPAL = 0xA6; -sfr IAPAH = 0xA7; - -sfr IE = 0xA8; -sfr SADDR = 0xA9; -sfr WDCON = 0xAA; //TA Protection -sfr BODCON1 = 0xAB; //TA Protection -sfr P3M1 = 0xAC; -sfr P3S = 0xAC; //Page1 -sfr P3M2 = 0xAD; -sfr P3SR = 0xAD; //Page1 -sfr IAPFD = 0xAE; -sfr IAPCN = 0xAF; - -sfr P3 = 0xB0; -sfr P0M1 = 0xB1; -sfr P0S = 0xB1; //Page1 -sfr P0M2 = 0xB2; -sfr P0SR = 0xB2; //Page1 -sfr P1M1 = 0xB3; -sfr P1S = 0xB3; //Page1 -sfr P1M2 = 0xB4; -sfr P1SR = 0xB4; //Page1 -sfr P2S = 0xB5; -sfr IPH = 0xB7; -sfr PWMINTC = 0xB7; //Page1 - -sfr IP = 0xB8; -sfr SADEN = 0xB9; -sfr SADEN_1 = 0xBA; -sfr SADDR_1 = 0xBB; -sfr I2DAT = 0xBC; -sfr I2STAT = 0xBD; -sfr I2CLK = 0xBE; -sfr I2TOC = 0xBF; - -sfr I2CON = 0xC0; -sfr I2ADDR = 0xC1; -sfr ADCRL = 0xC2; -sfr ADCRH = 0xC3; -sfr T3CON = 0xC4; -sfr PWM4H = 0xC4; //Page1 -sfr RL3 = 0xC5; -sfr PWM5H = 0xC5; //Page1 -sfr RH3 = 0xC6; -sfr PIOCON1 = 0xC6; //Page1 -sfr TA = 0xC7; - -sfr T2CON = 0xC8; -sfr T2MOD = 0xC9; -sfr RCMP2L = 0xCA; -sfr RCMP2H = 0xCB; -sfr TL2 = 0xCC; -sfr PWM4L = 0xCC; //Page1 -sfr TH2 = 0xCD; -sfr PWM5L = 0xCD; //Page1 -sfr ADCMPL = 0xCE; -sfr ADCMPH = 0xCF; - -sfr PSW = 0xD0; -sfr PWMPH = 0xD1; -sfr PWM0H = 0xD2; -sfr PWM1H = 0xD3; -sfr PWM2H = 0xD4; -sfr PWM3H = 0xD5; -sfr PNP = 0xD6; -sfr FBD = 0xD7; - -sfr PWMCON0 = 0xD8; -sfr PWMPL = 0xD9; -sfr PWM0L = 0xDA; -sfr PWM1L = 0xDB; -sfr PWM2L = 0xDC; -sfr PWM3L = 0xDD; -sfr PIOCON0 = 0xDE; -sfr PWMCON1 = 0xDF; - -sfr ACC = 0xE0; -sfr ADCCON1 = 0xE1; -sfr ADCCON2 = 0xE2; -sfr ADCDLY = 0xE3; -sfr C0L = 0xE4; -sfr C0H = 0xE5; -sfr C1L = 0xE6; -sfr C1H = 0xE7; - -sfr ADCCON0 = 0xE8; -sfr PICON = 0xE9; -sfr PINEN = 0xEA; -sfr PIPEN = 0xEB; -sfr PIF = 0xEC; -sfr C2L = 0xED; -sfr C2H = 0xEE; -sfr EIP = 0xEF; - -sfr B = 0xF0; -sfr CAPCON3 = 0xF1; -sfr CAPCON4 = 0xF2; -sfr SPCR = 0xF3; -sfr SPCR2 = 0xF3; //Page1 -sfr SPSR = 0xF4; -sfr SPDR = 0xF5; -sfr AINDIDS = 0xF6; -sfr EIPH = 0xF7; - -sfr SCON_1 = 0xF8; -sfr PDTEN = 0xF9; //TA Protection -sfr PDTCNT = 0xFA; //TA Protection -sfr PMEN = 0xFB; -sfr PMD = 0xFC; -sfr EIP1 = 0xFE; -sfr EIPH1 = 0xFF; - -/* BIT Registers */ -/* SCON_1 */ -sbit SM0_1 = SCON_1^7; -sbit FE_1 = SCON_1^7; -sbit SM1_1 = SCON_1^6; -sbit SM2_1 = SCON_1^5; -sbit REN_1 = SCON_1^4; -sbit TB8_1 = SCON_1^3; -sbit RB8_1 = SCON_1^2; -sbit TI_1 = SCON_1^1; -sbit RI_1 = SCON_1^0; - -/* ADCCON0 */ -sbit ADCF = ADCCON0^7; -sbit ADCS = ADCCON0^6; -sbit ETGSEL1 = ADCCON0^5; -sbit ETGSEL0 = ADCCON0^4; -sbit ADCHS3 = ADCCON0^3; -sbit ADCHS2 = ADCCON0^2; -sbit ADCHS1 = ADCCON0^1; -sbit ADCHS0 = ADCCON0^0; - -/* PWMCON0 */ -sbit PWMRUN = PWMCON0^7; -sbit LOAD = PWMCON0^6; -sbit PWMF = PWMCON0^5; -sbit CLRPWM = PWMCON0^4; - - -/* PSW */ -sbit CY = PSW^7; -sbit AC = PSW^6; -sbit F0 = PSW^5; -sbit RS1 = PSW^4; -sbit RS0 = PSW^3; -sbit OV = PSW^2; -sbit P = PSW^0; - -/* T2CON */ -sbit TF2 = T2CON^7; -sbit TR2 = T2CON^2; -sbit CM_RL2 = T2CON^0; - -/* I2CON */ -sbit I2CEN = I2CON^6; -sbit STA = I2CON^5; -sbit STO = I2CON^4; -sbit SI = I2CON^3; -sbit AA = I2CON^2; -sbit I2CPX = I2CON^0; - -/* IP */ -sbit PADC = IP^6; -sbit PBOD = IP^5; -sbit PS = IP^4; -sbit PT1 = IP^3; -sbit PX1 = IP^2; -sbit PT0 = IP^1; -sbit PX0 = IP^0; - -/* P3 */ -sbit P30 = P3^0; - - -/* IE */ -sbit EA = IE^7; -sbit EADC = IE^6; -sbit EBOD = IE^5; -sbit ES = IE^4; -sbit ET1 = IE^3; -sbit EX1 = IE^2; -sbit ET0 = IE^1; -sbit EX0 = IE^0; - -/* P2 */ -sbit P20 = P2^0; - -/* SCON */ -sbit SM0 = SCON^7; -sbit FE = SCON^7; -sbit SM1 = SCON^6; -sbit SM2 = SCON^5; -sbit REN = SCON^4; -sbit TB8 = SCON^3; -sbit RB8 = SCON^2; -sbit TI = SCON^1; -sbit RI = SCON^0; - -/* P1 */ -sbit P17 = P1^7; -sbit P16 = P1^6; -sbit TXD_1 = P1^6; -sbit P15 = P1^5; -sbit P14 = P1^4; -sbit SDA = P1^4; -sbit P13 = P1^3; -sbit SCL = P1^3; -sbit P12 = P1^2; -sbit P11 = P1^1; -sbit P10 = P1^0; - -/* TCON */ -sbit TF1 = TCON^7; -sbit TR1 = TCON^6; -sbit TF0 = TCON^5; -sbit TR0 = TCON^4; -sbit IE1 = TCON^3; -sbit IT1 = TCON^2; -sbit IE0 = TCON^1; -sbit IT0 = TCON^0; - -/* P0 */ - -sbit P07 = P0^7; -sbit RXD = P0^7; -sbit P06 = P0^6; -sbit TXD = P0^6; -sbit P05 = P0^5; -sbit P04 = P0^4; -sbit STADC = P0^4; -sbit P03 = P0^3; -sbit P02 = P0^2; -sbit RXD_1 = P0^2; -sbit P01 = P0^1; -sbit MISO = P0^1; -sbit P00 = P0^0; -sbit MOSI = P0^0; - -//*/ - -typedef bit BIT; -typedef unsigned char UINT8; -typedef unsigned int UINT16; -typedef unsigned long UINT32; - -typedef unsigned char uint8_t; -typedef unsigned int uint16_t; -typedef unsigned long uint32_t; - -typedef unsigned char u8; -typedef unsigned int u16; -typedef unsigned long u32; - - -typedef enum {FALSE = 0, TRUE = !FALSE} PinStatus; -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction; - -typedef enum -{ - Bit_RESET = 0, - Bit_SET = !Bit_RESET -}bool; - -typedef enum -{ - OFF = 0, - ON = 1 -} -Fun_Status; - -typedef enum -{ - LOW = 0, - HIGH = !LOW -} -Pin_Status; - - -typedef enum -{ - Input = 0, - Output = !Input -} -GPIO_Status; - - - -#define CID_READ 0x0B -#define DID_READ 0x0C - -#define ERASE_APROM 0x22 -#define READ_APROM 0x00 -#define PROGRAM_APROM 0x21 -#define ERASE_LDROM -#define READ_LDROM -#define PROGRAM_LDROM -#define READ_CFG 0xC0 -#define PROGRAM_CFG 0xE1 -#define READ_UID 0x04 - - - - - - - - - - - - - - - - diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/SFR_Macro.h b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/SFR_Macro.h deleted file mode 100644 index 483a203af..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/SFR_Macro.h +++ /dev/null @@ -1,1161 +0,0 @@ - -#ifndef _SFR_H -#define _SFR_H - -/**** P0 80H *****/ -#define set_P00 P00 = 1 -#define set_P01 P01 = 1 -#define set_P02 P02 = 1 -#define set_P03 P03 = 1 -#define set_P04 P04 = 1 -#define set_P05 P05 = 1 -#define set_P06 P06 = 1 -#define set_P07 P07 = 1 - -#define clr_P00 P00 = 0 -#define clr_P01 P01 = 0 -#define clr_P02 P02 = 0 -#define clr_P03 P03 = 0 -#define clr_P04 P04 = 0 -#define clr_P05 P05 = 0 -#define clr_P06 P06 = 0 -#define clr_P07 P07 = 0 - -//**** SP 81H **** -//**** DPH 82H **** -//**** DPL 83H **** -//**** RWK 86H **** - -//**** PCON 87H ***** -#define set_SMOD PCON |= SET_BIT7 -#define set_SMOD0 PCON |= SET_BIT6 -#define set_POF PCON |= SET_BIT4 -#define set_GF1 PCON |= SET_BIT3 -#define set_GF0 PCON |= SET_BIT2 -#define set_PD PCON |= SET_BIT1 -#define set_IDL PCON |= SET_BIT0 - -#define clr_SMOD PCON &= ~SET_BIT7 -#define clr_SMOD0 PCON &= ~SET_BIT6 -#define clr_POF PCON &= ~SET_BIT4 -#define clr_GF1 PCON &= ~SET_BIT3 -#define clr_GF0 PCON &= ~SET_BIT2 -#define clr_PD PCON &= ~SET_BIT1 -#define clr_IDL PCON &= ~SET_BIT0 - -/**** TCON 88H ****/ -#define set_TF1 TF1 = 1 -#define set_TR1 TR1 = 1 -#define set_TF0 TF0 = 1 -#define set_TR0 TR0 = 1 -#define set_IE1 IE1 = 1 -#define set_IT1 IT1 = 1 -#define set_IE0 IE0 = 1 -#define set_IT0 IT0 = 1 - -#define clr_TF1 TF1 = 0 -#define clr_TR1 TR1 = 0 -#define clr_TF0 TF0 = 0 -#define clr_TR0 TR0 = 0 -#define clr_IE1 IE1 = 0 -#define clr_IT1 IT1 = 0 -#define clr_IE0 IE0 = 0 -#define clr_IT0 IT0 = 0 - -//**** TMOD 89H **** -#define set_GATE_T1 TMOD |= SET_BIT7 -#define set_CT_T1 TMOD |= SET_BIT6 -#define set_M1_T1 TMOD |= SET_BIT5 -#define set_M0_T1 TMOD |= SET_BIT4 -#define set_GATE_T0 TMOD |= SET_BIT3 -#define set_CT_T0 TMOD |= SET_BIT2 -#define set_M1_T0 TMOD |= SET_BIT1 -#define set_M0_T0 TMOD |= SET_BIT0 - -#define clr_GATE_T1 TMOD &= ~SET_BIT7 -#define clr_CT_T1 TMOD &= ~SET_BIT6 -#define clr_M1_T1 TMOD &= ~SET_BIT5 -#define clr_M0_T1 TMOD &= ~SET_BIT4 -#define clr_GATE_T0 TMOD &= ~SET_BIT3 -#define clr_CT_T0 TMOD &= ~SET_BIT2 -#define clr_M1_T0 TMOD &= ~SET_BIT1 -#define clr_M0_T0 TMOD &= ~SET_BIT0 - -//**** TH1 8AH **** -//**** TH0 8BH **** -//**** TL1 8CH **** -//**** TL0 8DH **** - -//**** CKCON 8EH **** -#define set_PWMCKS CKCON |= SET_BIT6 -#define set_T1M CKCON |= SET_BIT4 -#define set_T0M CKCON |= SET_BIT3 -#define set_CLOEN CKCON |= SET_BIT1 - -#define clr_PWMCKS CKCON &= ~SET_BIT6 -#define clr_T1M CKCON &= ~SET_BIT4 -#define clr_T0M CKCON &= ~SET_BIT3 -#define clr_CLOEN CKCON &= ~SET_BIT1 - -//**** WKCON 8FH **** -#define set_WKTCK WKCON |= SET_BIT5 -#define set_WKTF WKCON |= SET_BIT4 -#define set_WKTR WKCON |= SET_BIT3 -#define set_WKPS2 WKCON |= SET_BIT2 -#define set_WKPS1 WKCON |= SET_BIT1 -#define set_WKPS0 WKCON |= SET_BIT0 - -#define clr_WKTCK WKCON &= ~SET_BIT5 -#define clr_WKTF WKCON &= ~SET_BIT4 -#define clr_WKTR WKCON &= ~SET_BIT3 -#define clr_WKPS2 WKCON &= ~SET_BIT2 -#define clr_WKPS1 WKCON &= ~SET_BIT1 -#define clr_WKPS0 WKCON &= ~SET_BIT0 - -/**** P1 90H *****/ -#define set_P10 P10 = 1 -#define set_P11 P11 = 1 -#define set_P12 P12 = 1 -#define set_P13 P13 = 1 -#define set_P14 P14 = 1 -#define set_P15 P15 = 1 -#define set_P16 P16 = 1 -#define set_P17 P17 = 1 - -#define clr_P10 P10 = 0 -#define clr_P11 P11 = 0 -#define clr_P12 P12 = 0 -#define clr_P13 P13 = 0 -#define clr_P14 P14 = 0 -#define clr_P15 P15 = 0 -#define clr_P16 P16 = 0 -#define clr_P17 P17 = 0 - -//****SFRS 91H **** -#define set_SFRPAGE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=SET_BIT0;EA=BIT_TMP -#define clr_SFRPAGE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS&=~SET_BIT0;EA=BIT_TMP - -//****CAPCON0 92H **** -#define set_CAPEN2 CAPCON0 |= SET_BIT6 -#define set_CAPEN1 CAPCON0 |= SET_BIT5 -#define set_CAPEN0 CAPCON0 |= SET_BIT4 -#define set_CAPF2 CAPCON0 |= SET_BIT2 -#define set_CAPF1 CAPCON0 |= SET_BIT1 -#define set_CAPF0 CAPCON0 |= SET_BIT0 - -#define clr_CAPEN2 CAPCON0 &= ~SET_BIT6 -#define clr_CAPEN1 CAPCON0 &= ~SET_BIT5 -#define clr_CAPEN0 CAPCON0 &= ~SET_BIT4 -#define clr_CAPF2 CAPCON0 &= ~SET_BIT2 -#define clr_CAPF1 CAPCON0 &= ~SET_BIT1 -#define clr_CAPF0 CAPCON0 &= ~SET_BIT0 - -//**** CAPCON1 93H **** -#define set_CAP2LS1 CAPCON1 |= SET_BIT5 -#define set_CAP2LS0 CAPCON1 |= SET_BIT4 -#define set_CAP1LS1 CAPCON1 |= SET_BIT3 -#define set_CAP1LS0 CAPCON1 |= SET_BIT2 -#define set_CAP0LS1 CAPCON1 |= SET_BIT1 -#define set_CAP0LS0 CAPCON1 |= SET_BIT0 - -#define clr_CAP2LS1 CAPCON1 &= ~SET_BIT5 -#define clr_CAP2LS0 CAPCON1 &= ~SET_BIT4 -#define clr_CAP1LS1 CAPCON1 &= ~SET_BIT3 -#define clr_CAP1LS0 CAPCON1 &= ~SET_BIT2 -#define clr_CAP0LS1 CAPCON1 &= ~SET_BIT1 -#define clr_CAP0LS0 CAPCON1 &= ~SET_BIT0 - -//**** CAPCON2 94H **** -#define set_ENF2 CAPCON2 |= SET_BIT6 -#define set_ENF1 CAPCON2 |= SET_BIT5 -#define set_ENF0 CAPCON2 |= SET_BIT4 - -#define clr_ENF2 CAPCON2 &= ~SET_BIT6 -#define clr_ENF1 CAPCON2 &= ~SET_BIT5 -#define clr_ENF0 CAPCON2 &= ~SET_BIT4 - -//**** CKDIV 95H **** - -//**** CKSWT 96H **** TA protect register -#define set_HIRCST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT5;EA=BIT_TMP; -#define set_LIRCST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT4;EA=BIT_TMP; -#define set_ECLKST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT3;EA=BIT_TMP; -#define set_OSC1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT2;EA=BIT_TMP; -#define set_OSC0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT1;EA=BIT_TMP; - -#define clr_HIRCST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT5;EA=BIT_TMP; -#define clr_LIRCST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT4;EA=BIT_TMP; -#define clr_ECLKST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT3;EA=BIT_TMP; -#define clr_OSC1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT2;EA=BIT_TMP; -#define clr_OSC0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT1;EA=BIT_TMP; - -//**** CKEN 97H **** TA protect register -#define set_EXTEN1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT7;EA=BIT_TMP; -#define set_EXTEN0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT6;EA=BIT_TMP; -#define set_HIRCEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT5;EA=BIT_TMP; -#define set_CKSWTF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT0;EA=BIT_TMP; - -#define clr_EXTEN1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT7;EA=BIT_TMP; -#define clr_EXTEN0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT6;EA=BIT_TMP; -#define clr_HIRCEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT5;EA=BIT_TMP; -#define clr_CKSWTF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT0;EA=BIT_TMP; - -//**** SCON 98H **** -#define set_FE FE = 1 -#define set_SM1 SM1 = 1 -#define set_SM2 SM2 = 1 -#define set_REN REN = 1 -#define set_TB8 TB8 = 1 -#define set_RB8 RB8 = 1 -#define set_TI TI = 1 -#define set_RI RI = 1 - -#define clr_FE FE = 0 -#define clr_SM1 SM1 = 0 -#define clr_SM2 SM2 = 0 -#define clr_REN REN = 0 -#define clr_TB8 TB8 = 0 -#define clr_RB8 RB8 = 0 -#define clr_TI TI = 0 -#define clr_RI RI = 0 - -//**** SBUF 99H **** -//**** SBUF_1 9AH **** - -//**** EIE 9BH **** -#define set_ET2 EIE |= SET_BIT7 -#define set_ESPI EIE |= SET_BIT6 -#define set_EFB EIE |= SET_BIT5 -#define set_EWDT EIE |= SET_BIT4 -#define set_EPWM EIE |= SET_BIT3 -#define set_ECAP EIE |= SET_BIT2 -#define set_EPI EIE |= SET_BIT1 -#define set_EI2C EIE |= SET_BIT0 - -#define clr_ET2 EIE &= ~SET_BIT7 -#define clr_ESPI EIE &= ~SET_BIT6 -#define clr_EFB EIE &= ~SET_BIT5 -#define clr_EWDT EIE &= ~SET_BIT4 -#define clr_EPWM EIE &= ~SET_BIT3 -#define clr_ECAP EIE &= ~SET_BIT2 -#define clr_EPI EIE &= ~SET_BIT1 -#define clr_EI2C EIE &= ~SET_BIT0 - -//**** EIE1 9CH **** -#define set_EWKT EIE1 |= SET_BIT2 -#define set_ET3 EIE1 |= SET_BIT1 -#define set_ES_1 EIE1 |= SET_BIT0 - -#define clr_EWKT EIE1 &= ~SET_BIT2 -#define clr_ET3 EIE1 &= ~SET_BIT1 -#define clr_ES_1 EIE1 &= ~SET_BIT0 - -//**** CHPCON 9DH **** TA protect register -#define set_SWRST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT7 ;EA=BIT_TMP -#define set_IAPFF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT6 ;EA=BIT_TMP -#define set_BS BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT1 ;EA=BIT_TMP -#define set_IAPEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT0 ;EA=BIT_TMP - -#define clr_SWRST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT7;EA=BIT_TMP -#define clr_IAPFF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT6;EA=BIT_TMP -#define clr_BS BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT1;EA=BIT_TMP -#define clr_IAPEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT0;EA=BIT_TMP - -//**** P2 A0H **** - -//**** AUXR1 A2H **** -#define set_SWRF AUXR1 |= SET_BIT7 -#define set_RSTPINF AUXR1 |= SET_BIT6 -#define set_HARDF AUXR1 |= SET_BIT5 -#define set_GF2 AUXR1 |= SET_BIT3 -#define set_UART0PX AUXR1 |= SET_BIT2 -#define set_DPS AUXR1 |= SET_BIT0 - -#define clr_SWRF AUXR1 &= ~SET_BIT7 -#define clr_RSTPINF AUXR1 &= ~SET_BIT6 -#define clr_HARDF AUXR1 &= ~SET_BIT5 -#define clr_GF2 AUXR1 &= ~SET_BIT3 -#define clr_UART0PX AUXR1 &= ~SET_BIT2 -#define clr_DPS AUXR1 &= ~SET_BIT0 - -//**** BODCON0 A3H **** TA protect register -#define set_BODEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT7;EA=BIT_TMP -#define set_BOV2 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT6;EA=BIT_TMP -#define set_BOV1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT5;EA=BIT_TMP -#define set_BOV0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT4;EA=BIT_TMP -#define set_BOF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT3;EA=BIT_TMP -#define set_BORST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT2;EA=BIT_TMP -#define set_BORF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT1;EA=BIT_TMP -#define set_BOS BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT0;EA=BIT_TMP - -#define clr_BODEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT7;EA=BIT_TMP -#define clr_BOV2 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT6;EA=BIT_TMP -#define clr_BOV1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT5;EA=BIT_TMP -#define clr_BOV0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT4;EA=BIT_TMP -#define clr_BOF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT3;EA=BIT_TMP -#define clr_BORST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT2;EA=BIT_TMP -#define clr_BORF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT1;EA=BIT_TMP -#define clr_BOS BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT0;EA=BIT_TMP - -//**** IAPTRG A4H **** TA protect register -#define set_IAPGO BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPTRG|=SET_BIT0 ;EA=BIT_TMP -#define clr_IAPGO BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPTRG&=~SET_BIT0;EA=BIT_TMP - -//**** IAPUEN A5H **** TA protect register -#define set_CFUEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN|=SET_BIT2;EA=BIT_TMP -#define set_LDUEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN|=SET_BIT1;EA=BIT_TMP -#define set_APUEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN|=SET_BIT0;EA=BIT_TMP - -#define clr_CFUEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN&=~SET_BIT2;EA=BIT_TMP -#define clr_LDUEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN&=~SET_BIT1;EA=BIT_TMP -#define clr_APUEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN&=~SET_BIT0;EA=BIT_TMP - -//**** IAPAL A6H **** -//**** IAPAH A7H **** - -//**** IE A8H **** -#define set_EA EA = 1 -#define set_EADC EADC = 1 -#define set_EBOD EBOD = 1 -#define set_ES ES = 1 -#define set_ET1 ET1 = 1 -#define set_EX1 EX1 = 1 -#define set_ET0 ET0 = 1 -#define set_EX0 EX0 = 1 - -#define clr_EA EA = 0 -#define clr_EADC EADC = 0 -#define clr_EBOD EBOD = 0 -#define clr_ES ES = 0 -#define clr_ET1 ET1 = 0 -#define clr_EX1 EX1 = 0 -#define clr_ET0 ET0 = 0 -#define clr_EX0 EX0 = 0 - -//**** SADDR A9H **** - -//**** WDCON AAH **** TA protect register -#define set_WDTR BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT7;EA=BIT_TMP; -#define set_WDCLR BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT6;EA=BIT_TMP; -#define set_WDTF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT5;EA=BIT_TMP; -#define set_WIDPD BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT4;EA=BIT_TMP; -#define set_WDTRF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT3;EA=BIT_TMP; -#define set_WPS2 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT2;EA=BIT_TMP; -#define set_WPS1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT1;EA=BIT_TMP; -#define set_WPS0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT0;EA=BIT_TMP; - -#define clr_WDTEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT7;EA=BIT_TMP; -#define clr_WDCLR BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT6;EA=BIT_TMP; -#define clr_WDTF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT5;EA=BIT_TMP; -#define clr_WDTRF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT3;EA=BIT_TMP; -#define clr_WPS2 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT2;EA=BIT_TMP; -#define clr_WPS1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT1;EA=BIT_TMP; -#define clr_WPS0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT0;EA=BIT_TMP; - -//**** BODCON1 ABH **** TA protect register -#define set_LPBOD1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1|=SET_BIT2 ;EA=BIT_TMP; -#define set_LPBOD0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1|=SET_BIT1 ;EA=BIT_TMP; -#define set_BODFLT BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1|=SET_BIT0 ;EA=BIT_TMP; - -#define clr_LPBOD1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1&=~SET_BIT2;EA=BIT_TMP; -#define clr_LPBOD0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1&=~SET_BIT1;EA=BIT_TMP; -#define clr_BODFLT BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1&=~SET_BIT0;EA=BIT_TMP; - - -//**** P3M1 ACH PAGE0 **** -#define set_P3M1_0 P3M1 |= SET_BIT0 -#define clr_P3M1_0 P3M1 &= ~SET_BIT0 - -//**** P3S ACH PAGE1 **** SFRS must set as 1 to modify this register -#define set_P3S_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3S|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P3S_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3S&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -//**** P3M2 ADH PAGE0 **** -#define set_P3M2_0 P3M2 |= SET_BIT0 -#define clr_P3M2_0 P3M2 &= ~SET_BIT0 - -//**** P3SR ADH PAGE1 **** SFRS must set as 1 to modify this register -#define set_P3SR_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3SR|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P3SR_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3SR&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -//**** IAPFD AEH **** - -//**** IAPCN AFH **** -#define set_FOEN IAPN |= SET_BIT5 -#define set_FCEN IAPN |= SET_BIT4 -#define set_FCTRL3 IAPN |= SET_BIT3 -#define set_FCTRL2 IAPN |= SET_BIT2 -#define set_FCTRL1 IAPN |= SET_BIT1 -#define set_FCTRL0 IAPN |= SET_BIT0 - -#define clr_FOEN IAPN &= ~SET_BIT5 -#define clr_FCEN IAPN &= ~SET_BIT4 -#define clr_FCTRL3 IAPN &= ~SET_BIT3 -#define clr_FCTRL2 IAPN &= ~SET_BIT2 -#define clr_FCTRL1 IAPN &= ~SET_BIT1 -#define clr_FCTRL0 IAPN &= ~SET_BIT0 - -//**** P3 B0H **** -#define set_P30 P30 = 1 -#define clr_P30 P30 = 0 - -//**** P0M1 B1H PAGE0 **** -#define set_P0M1_7 P0M1 |= SET_BIT7 -#define set_P0M1_6 P0M1 |= SET_BIT6 -#define set_P0M1_5 P0M1 |= SET_BIT5 -#define set_P0M1_4 P0M1 |= SET_BIT4 -#define set_P0M1_3 P0M1 |= SET_BIT3 -#define set_P0M1_2 P0M1 |= SET_BIT2 -#define set_P0M1_1 P0M1 |= SET_BIT1 -#define set_P0M1_0 P0M1 |= SET_BIT0 - -#define clr_P0M1_7 P0M1 &= ~SET_BIT7 -#define clr_P0M1_6 P0M1 &= ~SET_BIT6 -#define clr_P0M1_5 P0M1 &= ~SET_BIT5 -#define clr_P0M1_4 P0M1 &= ~SET_BIT4 -#define clr_P0M1_3 P0M1 &= ~SET_BIT3 -#define clr_P0M1_2 P0M1 &= ~SET_BIT2 -#define clr_P0M1_1 P0M1 &= ~SET_BIT1 -#define clr_P0M1_0 P0M1 &= ~SET_BIT0 - -//**** P0S B2H PAGE1 **** SFRS must set as 1 to modify this register -#define set_P0S_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0S_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0S_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0S_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0S_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0S_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0S_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0S_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -#define clr_P0S_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0S_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0S_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0S_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0S_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0S_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0S_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0S_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -//**** P0M2 B2H PAGE0 **** -#define set_P0M2_7 P0M2 |= SET_BIT7 -#define set_P0M2_6 P0M2 |= SET_BIT6 -#define set_P0M2_5 P0M2 |= SET_BIT5 -#define set_P0M2_4 P0M2 |= SET_BIT4 -#define set_P0M2_3 P0M2 |= SET_BIT3 -#define set_P0M2_2 P0M2 |= SET_BIT2 -#define set_P0M2_1 P0M2 |= SET_BIT1 -#define set_P0M2_0 P0M2 |= SET_BIT0 - -#define clr_P0M2_7 P0M2 &= ~SET_BIT7 -#define clr_P0M2_6 P0M2 &= ~SET_BIT6 -#define clr_P0M2_5 P0M2 &= ~SET_BIT5 -#define clr_P0M2_4 P0M2 &= ~SET_BIT4 -#define clr_P0M2_3 P0M2 &= ~SET_BIT3 -#define clr_P0M2_2 P0M2 &= ~SET_BIT2 -#define clr_P0M2_1 P0M2 &= ~SET_BIT1 -#define clr_P0M2_0 P0M2 &= ~SET_BIT0 - - -//**** P0SR B0H PAGE1 **** SFRS must set as 1 to modify this register -#define set_P0SR_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0SR_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0SR_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0SR_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0SR_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0SR_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0SR_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P0SR_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -#define clr_P0SR_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0SR_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0SR_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0SR_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0SR_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0SR_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0SR_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P0SR_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - - -//**** P1M1 B3H PAGE0 **** -#define set_P1M1_7 P1M1 |= SET_BIT7 -#define set_P1M1_6 P1M1 |= SET_BIT6 -#define set_P1M1_5 P1M1 |= SET_BIT5 -#define set_P1M1_4 P1M1 |= SET_BIT4 -#define set_P1M1_3 P1M1 |= SET_BIT3 -#define set_P1M1_2 P1M1 |= SET_BIT2 -#define set_P1M1_1 P1M1 |= SET_BIT1 -#define set_P1M1_0 P1M1 |= SET_BIT0 - -#define clr_P1M1_7 P1M1 &= ~SET_BIT7 -#define clr_P1M1_6 P1M1 &= ~SET_BIT6 -#define clr_P1M1_5 P1M1 &= ~SET_BIT5 -#define clr_P1M1_4 P1M1 &= ~SET_BIT4 -#define clr_P1M1_3 P1M1 &= ~SET_BIT3 -#define clr_P1M1_2 P1M1 &= ~SET_BIT2 -#define clr_P1M1_1 P1M1 &= ~SET_BIT1 -#define clr_P1M1_0 P1M1 &= ~SET_BIT0 - -//**** P1S B3H PAGE1 **** SFRS must set as 1 to modify this register -#define set_P1S_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1S_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1S_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1S_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1S_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1S_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1S_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1S_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -#define clr_P1S_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1S_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1S_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1S_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1S_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1S_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1S_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1S_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -//**** P1M2 B4H PAGE0 **** -#define set_P12UP P1M2 |= SET_BIT2 -#define set_P1M2_1 P1M2 |= SET_BIT1 -#define set_P1M2_0 P1M2 |= SET_BIT0 - -#define clr_P12UP P1M2 &= ~SET_BIT2 -#define clr_P1M2_1 P1M2 &= ~SET_BIT1 -#define clr_P1M2_0 P1M2 &= ~SET_BIT0 - -//**** P1SR B4H PAGE1 **** SFRS must set as 1 to modify this register -#define set_P1SR_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1SR_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1SR_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1SR_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1SR_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1SR_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1SR_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_P1SR_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -#define clr_P1SR_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1SR_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1SR_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1SR_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1SR_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1SR_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1SR_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_P1SR_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - - -//**** P2S B5H **** -#define set_P2S_0 P2S |= SET_BIT0 -#define clr_P2S_0 P2S &= ~SET_BIT0 - -//**** IPH B7H PAGE0 **** -#define set_PADCH IPH |= SET_BIT6 -#define set_PBODH IPH |= SET_BIT5 -#define set_PSH IPH |= SET_BIT4 -#define set_PT1H IPH |= SET_BIT3 -#define set_PX11 IPH |= SET_BIT2 -#define set_PT0H IPH |= SET_BIT1 -#define set_PX0H IPH |= SET_BIT0 - -#define clr_PADCH IPH &= ~SET_BIT6 -#define clr_PBODH IPH &= ~SET_BIT5 -#define clr_PSH IPH &= ~SET_BIT4 -#define clr_PT1H IPH &= ~SET_BIT3 -#define clr_PX11 IPH &= ~SET_BIT2 -#define clr_PT0H IPH &= ~SET_BIT1 -#define clr_PX0H IPH &= ~SET_BIT0 - -//**** PWMINTC B7H PAGE1 **** SFRS must set as 1 to modify this register -#define set_INTTYP1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_INTTYP0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_INTSEL2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_INTSEL1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_INTSEL0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -#define clr_INTTYP1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_INTTYP0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_INTSEL2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_INTSEL1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_INTSEL0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -//**** IP B8H **** -#define set_PADC PADC = 1 -#define set_PBOD PBOD = 1 -#define set_PS PS = 1 -#define set_PT1 PT1 = 1 -#define set_PX1 PX1 = 1 -#define set_PT0 PT0 = 1 -#define set_PX0 PX0 = 1 - -#define clr_PADC PADC = 0 -#define clr_PBOD PBOD = 0 -#define clr_PS PS = 0 -#define clr_PT1 PT1 = 0 -#define clr_PX1 PX1 = 0 -#define clr_PT0 PT0 = 0 -#define clr_PX0 PX0 = 0 - -//**** SADEN B9H **** -//**** SADEN_1 8AH **** -//**** SADDR_1 BBH **** -//**** I2DAT BCH **** -//**** I2STAT BDH **** -//**** I2CLK BEH **** - -//**** I2TOC BFH **** -#define set_I2TOCEN I2TOC |= SET_BIT2 -#define set_DIV I2TOC |= SET_BIT1 -#define set_I2TOF I2TOC |= SET_BIT0 - -#define clr_I2TOCEN I2TOC &= ~SET_BIT2 -#define clr_DIV I2TOC &= ~SET_BIT1 -#define clr_I2TOF I2TOC &= ~SET_BIT0 - -//**** I2CON C0H **** -#define set_I2CEN I2CEN = 1 -#define set_STA STA = 1 -#define set_STO STO = 1 -#define set_SI SI = 1 -#define set_AA AA = 1 -#define set_I2CPX I2CPX = 1 - -#define clr_I2CEN I2CEN = 0 -#define clr_STA STA = 0 -#define clr_STO STO = 0 -#define clr_SI SI = 0 -#define clr_AA AA = 0 -#define clr_I2CPX I2CPX = 0 - -//**** I2ADDR C1H **** -#define set_GC I2ADDR |= SET_BIT0 -#define clr_GC I2ADDR &= ~SET_BIT0 - -//**** ADCRL C2H **** -//**** ADCRH C3H **** - -//**** T3CON C4H PAGE0 **** -#define set_SMOD_1 T3CON |= SET_BIT7 -#define set_SMOD0_1 T3CON |= SET_BIT6 -#define set_BRCK T3CON |= SET_BIT5 -#define set_TF3 T3CON |= SET_BIT4 -#define set_TR3 T3CON |= SET_BIT3 -#define set_T3PS2 T3CON |= SET_BIT2 -#define set_T3PS1 T3CON |= SET_BIT1 -#define set_T3PS0 T3CON |= SET_BIT0 - -#define clr_SMOD_1 T3CON &= ~SET_BIT7 -#define clr_SMOD0_1 T3CON &= ~SET_BIT6 -#define clr_BRCK T3CON &= ~SET_BIT5 -#define clr_TF3 T3CON &= ~SET_BIT4 -#define clr_TR3 T3CON &= ~SET_BIT3 -#define clr_T3PS2 T3CON &= ~SET_BIT2 -#define clr_T3PS1 T3CON &= ~SET_BIT1 -#define clr_T3PS0 T3CON &= ~SET_BIT0 - -//**** PWM4H C4H PAGE1 **** SFRS must set as 1 to modify this register -//**** RL3 C5H PAGE0 **** -//**** PWM5H C5H PAGE1 **** SFRS must set as 1 to modify this register -//**** RH3 C6H PAGE0 **** - -//**** PIOCON1 C6H PAGE1 **** SFRS must set as 1 to modify this register -#define set_PIO15 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_PIO13 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_PIO12 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_PIO11 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -#define clr_PIO15 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_PIO13 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_PIO12 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_PIO11 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -//**** T2CON C8H **** -#define set_TF2 TF2 = 1 -#define set_TR2 TR2 = 1 -#define set_CMRL2 CMRL2 = 1 - -#define clr_TF2 TF2 = 0 -#define clr_TR2 TR2 = 0 -#define clr_CMRL2 CMRL2 = 0 - -//**** T2MOD C9H **** -#define set_LDEN T2MOD |= SET_BIT7 -#define set_T2DIV2 T2MOD |= SET_BIT6 -#define set_T2DIV1 T2MOD |= SET_BIT5 -#define set_T2DIV0 T2MOD |= SET_BIT4 -#define set_CAPCR T2MOD |= SET_BIT3 -#define set_CMPCR T2MOD |= SET_BIT2 -#define set_LDTS1 T2MOD |= SET_BIT1 -#define set_LDTS0 T2MOD |= SET_BIT0 - -#define clr_LDEN T2MOD &= ~SET_BIT7 -#define clr_T2DIV2 T2MOD &= ~SET_BIT6 -#define clr_T2DIV1 T2MOD &= ~SET_BIT5 -#define clr_T2DIV0 T2MOD &= ~SET_BIT4 -#define clr_CAPCR T2MOD &= ~SET_BIT3 -#define clr_CMPCR T2MOD &= ~SET_BIT2 -#define clr_LDTS1 T2MOD &= ~SET_BIT1 -#define clr_LDTS0 T2MOD &= ~SET_BIT0 - -//**** RCMP2H CAH **** -//**** RCMP2L CBH **** -//**** TL2 CCH PAGE0 **** -//**** PWM4L CCH PAGE1 **** SFRS must set as 1 to modify this register -//**** TH2 CDH PAGE0 **** -//**** PWM5L CDH PAGE1 **** SFRS must set as 1 to modify this register -//**** ADCMPL CEH **** -//**** ADCMPH CFH **** - -/**** PSW D0H ****/ -#define set_CY CY = 1 -#define set_AC AC = 1 -#define set_F0 F0 = 1 -#define set_RS1 RS1 = 1 -#define set_RS0 RS0 = 1 -#define set_OV OV = 1 -#define set_P P = 1 - -#define clr_CY CY = 0 -#define clr_AC AC = 0 -#define clr_F0 F0 = 0 -#define clr_RS1 RS1 = 0 -#define clr_RS0 RS0 = 0 -#define clr_OV OV = 0 -#define clr_P P = 0 - -//**** PWMPH D1H **** -//**** PWM0H D2H **** -//**** PWM1H D3H **** -//**** PWM2H D4H **** -//**** PWM3H D5H **** - -//**** PNP D6H **** -#define set_PNP5 PNP |= SET_BIT5 -#define set_PNP4 PNP |= SET_BIT4 -#define set_PNP3 PNP |= SET_BIT3 -#define set_PNP2 PNP |= SET_BIT2 -#define set_PNP1 PNP |= SET_BIT1 -#define set_PNP0 PNP |= SET_BIT0 - -#define clr_PNP5 PNP &= ~SET_BIT5 -#define clr_PNP4 PNP &= ~SET_BIT4 -#define clr_PNP3 PNP &= ~SET_BIT3 -#define clr_PNP2 PNP &= ~SET_BIT2 -#define clr_PNP1 PNP &= ~SET_BIT1 -#define clr_PNP0 PNP &= ~SET_BIT0 - -//**** FBD D7H **** -#define set_FBF FBD |= SET_BIT7 -#define set_FBINLS FBD |= SET_BIT6 -#define set_FBD5 FBD |= SET_BIT5 -#define set_FBD4 FBD |= SET_BIT4 -#define set_FBD3 FBD |= SET_BIT3 -#define set_FBD2 FBD |= SET_BIT2 -#define set_FBD1 FBD |= SET_BIT1 -#define set_FBD0 FBD |= SET_BIT0 - -#define clr_FBF FBD &= ~SET_BIT7 -#define clr_FBINLS FBD &= ~SET_BIT6 -#define clr_FBD5 FBD &= ~SET_BIT5 -#define clr_FBD4 FBD &= ~SET_BIT4 -#define clr_FBD3 FBD &= ~SET_BIT3 -#define clr_FBD2 FBD &= ~SET_BIT2 -#define clr_FBD1 FBD &= ~SET_BIT1 -#define clr_FBD0 FBD &= ~SET_BIT0 - -/**** PWMCON0 D8H ****/ -#define set_PWMRUN PWMRUN = 1 -#define set_LOAD LOAD = 1 -#define set_PWMF PWMF = 1 -#define set_CLRPWM CLRPWM = 1 - -#define clr_PWMRUN PWMRUN = 0 -#define clr_LOAD LOAD = 0 -#define clr_PWMF PWMF = 0 -#define clr_CLRPWM CLRPWM = 0 - -//**** PWMPL D9H **** -//**** PWM0L DAH **** -//**** PWM1L DBH **** -//**** PWM2L DCH **** -//**** PWM3L DDH **** - -//**** PIOCON0 DEH **** -#define set_PIO05 PIOCON0 |= SET_BIT5 -#define set_PIO04 PIOCON0 |= SET_BIT4 -#define set_PIO03 PIOCON0 |= SET_BIT3 -#define set_PIO02 PIOCON0 |= SET_BIT2 -#define set_PIO01 PIOCON0 |= SET_BIT1 -#define set_PIO00 PIOCON0 |= SET_BIT0 - -#define clr_PIO05 PIOCON0 &= ~SET_BIT5 -#define clr_PIO04 PIOCON0 &= ~SET_BIT4 -#define clr_PIO03 PIOCON0 &= ~SET_BIT3 -#define clr_PIO02 PIOCON0 &= ~SET_BIT2 -#define clr_PIO01 PIOCON0 &= ~SET_BIT1 -#define clr_PIO00 PIOCON0 &= ~SET_BIT0 - -//**** PWMCON1 DFH **** -#define set_PWMMOD1 PWMCON1 |= SET_BIT7 -#define set_PWMMOD0 PWMCON1 |= SET_BIT6 -#define set_GP PWMCON1 |= SET_BIT5 -#define set_PWMTYP PWMCON1 |= SET_BIT4 -#define set_FBINEN PWMCON1 |= SET_BIT3 -#define set_PWMDIV2 PWMCON1 |= SET_BIT2 -#define set_PWMDIV1 PWMCON1 |= SET_BIT1 -#define set_PWMDIV0 PWMCON1 |= SET_BIT0 - -#define clr_PWMMOD1 PWMCON1 &= ~SET_BIT7 -#define clr_PWMMOD0 PWMCON1 &= ~SET_BIT6 -#define clr_GP PWMCON1 &= ~SET_BIT5 -#define clr_PWMTYP PWMCON1 &= ~SET_BIT4 -#define clr_FBINEN PWMCON1 &= ~SET_BIT3 -#define clr_PWMDIV2 PWMCON1 &= ~SET_BIT2 -#define clr_PWMDIV1 PWMCON1 &= ~SET_BIT1 -#define clr_PWMDIV0 PWMCON1 &= ~SET_BIT0 - -//**** ACC E0H **** - -//**** ADCCON1 E1H **** -#define set_STADCPX ADCCON1 |= SET_BIT6 -#define set_ETGTYP1 ADCCON1 |= SET_BIT3 -#define set_ETGTYP0 ADCCON1 |= SET_BIT2 -#define set_ADCEX ADCCON1 |= SET_BIT1 -#define set_ADCEN ADCCON1 |= SET_BIT0 - -#define clr_STADCPX ADCCON1 &= ~SET_BIT6 -#define clr_ETGTYP1 ADCCON1 &= ~SET_BIT3 -#define clr_ETGTYP0 ADCCON1 &= ~SET_BIT2 -#define clr_ADCEX ADCCON1 &= ~SET_BIT1 -#define clr_ADCEN ADCCON1 &= ~SET_BIT0 - -//**** ADCON2 E2H **** -#define set_ADFBEN ADCCON2 |= SET_BIT7 -#define set_ADCMPOP ADCCON2 |= SET_BIT6 -#define set_ADCMPEN ADCCON2 |= SET_BIT5 -#define set_ADCMPO ADCCON2 |= SET_BIT4 - -#define clr_ADFBEN ADCCON2 &= ~SET_BIT7 -#define clr_ADCMPOP ADCCON2 &= ~SET_BIT6 -#define clr_ADCMPEN ADCCON2 &= ~SET_BIT5 -#define clr_ADCMPO ADCCON2 &= ~SET_BIT4 - -//**** ADCDLY E3H **** -//**** C0L E4H **** -//**** C0H E5H **** -//**** C1L E6H **** -//**** C1H E7H **** - -//**** ADCCON0 EAH **** -#define set_ADCF ADCF = 1 -#define set_ADCS ADCS = 1 -#define set_ETGSEL1 ETGSEL1 = 1 -#define set_ETGSEL0 ETGSEL0 = 1 -#define set_ADCHS3 ADCHS3 = 1 -#define set_ADCHS2 ADCHS2 = 1 -#define set_ADCHS1 ADCHS1 = 1 -#define set_ADCHS0 ADCHS0 = 1 - -#define clr_ADCF ADCF = 0 -#define clr_ADCS ADCS = 0 -#define clr_ETGSEL1 ETGSEL1 = 0 -#define clr_ETGSEL0 ETGSEL0 = 0 -#define clr_ADCHS3 ADCHS3 = 0 -#define clr_ADCHS2 ADCHS2 = 0 -#define clr_ADCHS1 ADCHS1 = 0 -#define clr_ADCHS0 ADCHS0 = 0 - -//**** PICON E9H **** -#define set_PIT67 PICON |= SET_BIT7 -#define set_PIT45 PICON |= SET_BIT6 -#define set_PIT3 PICON |= SET_BIT5 -#define set_PIT2 PICON |= SET_BIT4 -#define set_PIT1 PICON |= SET_BIT3 -#define set_PIT0 PICON |= SET_BIT2 -#define set_PIPS1 PICON |= SET_BIT1 -#define set_PIPS0 PICON |= SET_BIT0 - -#define clr_PIT67 PICON &= ~SET_BIT7 -#define clr_PIT45 PICON &= ~SET_BIT6 -#define clr_PIT3 PICON &= ~SET_BIT5 -#define clr_PIT2 PICON &= ~SET_BIT4 -#define clr_PIT1 PICON &= ~SET_BIT3 -#define clr_PIT0 PICON &= ~SET_BIT2 -#define clr_PIPS1 PICON &= ~SET_BIT1 -#define clr_PIPS0 PICON &= ~SET_BIT0 - -//**** PINEN EAH **** -#define set_PINEN7 PINEN |= SET_BIT7 -#define set_PINEN6 PINEN |= SET_BIT6 -#define set_PINEN5 PINEN |= SET_BIT5 -#define set_PINEN4 PINEN |= SET_BIT4 -#define set_PINEN3 PINEN |= SET_BIT3 -#define set_PINEN2 PINEN |= SET_BIT2 -#define set_PINEN1 PINEN |= SET_BIT1 -#define set_PINEN0 PINEN |= SET_BIT0 - -#define clr_PINEN7 PINEN &= ~SET_BIT7 -#define clr_PINEN6 PINEN &= ~SET_BIT6 -#define clr_PINEN5 PINEN &= ~SET_BIT5 -#define clr_PINEN4 PINEN &= ~SET_BIT4 -#define clr_PINEN3 PINEN &= ~SET_BIT3 -#define clr_PINEN2 PINEN &= ~SET_BIT2 -#define clr_PINEN1 PINEN &= ~SET_BIT1 -#define clr_PINEN0 PINEN &= ~SET_BIT0 - -//**** PIPEN EBH **** -#define set_PIPEN7 PIPEN |= SET_BIT7 -#define set_PIPEN6 PIPEN |= SET_BIT6 -#define set_PIPEN5 PIPEN |= SET_BIT5 -#define set_PIPEN4 PIPEN |= SET_BIT4 -#define set_PIPEN3 PIPEN |= SET_BIT3 -#define set_PIPEN2 PIPEN |= SET_BIT2 -#define set_PIPEN1 PIPEN |= SET_BIT1 -#define set_PIPEN0 PIPEN |= SET_BIT0 - -#define clr_PIPEN7 PIPEN &= ~SET_BIT7 -#define clr_PIPEN6 PIPEN &= ~SET_BIT6 -#define clr_PIPEN5 PIPEN &= ~SET_BIT5 -#define clr_PIPEN4 PIPEN &= ~SET_BIT4 -#define clr_PIPEN3 PIPEN &= ~SET_BIT3 -#define clr_PIPEN2 PIPEN &= ~SET_BIT2 -#define clr_PIPEN1 PIPEN &= ~SET_BIT1 -#define clr_PIPEN0 PIPEN &= ~SET_BIT0 - -//**** PIF ECH **** -#define set_PIF7 PIF |= SET_BIT7 -#define set_PIF6 PIF |= SET_BIT6 -#define set_PIF5 PIF |= SET_BIT5 -#define set_PIF4 PIF |= SET_BIT4 -#define set_PIF3 PIF |= SET_BIT3 -#define set_PIF2 PIF |= SET_BIT2 -#define set_PIF1 PIF |= SET_BIT1 -#define set_PIF0 PIF |= SET_BIT0 - -#define clr_PIF7 PIF &= ~SET_BIT7 -#define clr_PIF6 PIF &= ~SET_BIT6 -#define clr_PIF5 PIF &= ~SET_BIT5 -#define clr_PIF4 PIF &= ~SET_BIT4 -#define clr_PIF3 PIF &= ~SET_BIT3 -#define clr_PIF2 PIF &= ~SET_BIT2 -#define clr_PIF1 PIF &= ~SET_BIT1 -#define clr_PIF0 PIF &= ~SET_BIT0 - -//**** C2L EDH **** -//**** C2H EEH **** - -//**** EIP EFH **** -#define set_PT2 EIP |= SET_BIT7 -#define set_PSPI EIP |= SET_BIT6 -#define set_PFB EIP |= SET_BIT5 -#define set_PWDT EIP |= SET_BIT4 -#define set_PPWM EIP |= SET_BIT3 -#define set_PCAP EIP |= SET_BIT2 -#define set_PPI EIP |= SET_BIT1 -#define set_PI2C EIP |= SET_BIT0 - -#define clr_PT2 EIP &= ~SET_BIT7 -#define clr_PSPI EIP &= ~SET_BIT6 -#define clr_PFB EIP &= ~SET_BIT5 -#define clr_PWDT EIP &= ~SET_BIT4 -#define clr_PPWM EIP &= ~SET_BIT3 -#define clr_PCAP EIP &= ~SET_BIT2 -#define clr_PPI EIP &= ~SET_BIT1 -#define clr_PI2C EIP &= ~SET_BIT0 - -//**** B F0H **** - -//**** CAPCON3 F1H **** -#define set_CAP13 CAPCON3 |= SET_BIT7 -#define set_CAP12 CAPCON3 |= SET_BIT6 -#define set_CAP11 CAPCON3 |= SET_BIT5 -#define set_CAP10 CAPCON3 |= SET_BIT4 -#define set_CAP03 CAPCON3 |= SET_BIT3 -#define set_CAP02 CAPCON3 |= SET_BIT2 -#define set_CAP01 CAPCON3 |= SET_BIT1 -#define set_CAP00 CAPCON3 |= SET_BIT0 - -#define clr_CAP13 CAPCON3 &= ~SET_BIT7 -#define clr_CAP12 CAPCON3 &= ~SET_BIT6 -#define clr_CAP11 CAPCON3 &= ~SET_BIT5 -#define clr_CAP10 CAPCON3 &= ~SET_BIT4 -#define clr_CAP03 CAPCON3 &= ~SET_BIT3 -#define clr_CAP02 CAPCON3 &= ~SET_BIT2 -#define clr_CAP01 CAPCON3 &= ~SET_BIT1 -#define clr_CAP00 CAPCON3 &= ~SET_BIT0 - -//**** CAPCON4 F2H **** -#define set_CAP23 CAPCON4 |= SET_BIT3 -#define set_CAP22 CAPCON4 |= SET_BIT2 -#define set_CAP21 CAPCON4 |= SET_BIT1 -#define set_CAP20 CAPCON4 |= SET_BIT0 - -#define clr_CAP23 CAPCON4 &= ~SET_BIT3 -#define clr_CAP22 CAPCON4 &= ~SET_BIT2 -#define clr_CAP21 CAPCON4 &= ~SET_BIT1 -#define clr_CAP20 CAPCON4 &= ~SET_BIT0 - -//**** SPCR F3H PAGE0 **** -#define set_SSOE SPCR |= SET_BIT7 -#define set_SPIEN SPCR |= SET_BIT6 -#define set_LSBFE SPCR |= SET_BIT5 -#define set_MSTR SPCR |= SET_BIT4 -#define set_CPOL SPCR |= SET_BIT3 -#define set_CPHA SPCR |= SET_BIT2 -#define set_SPR1 SPCR |= SET_BIT1 -#define set_SPR0 SPCR |= SET_BIT0 - -#define clr_SSOE SPCR &= ~SET_BIT7 -#define clr_SPIEN SPCR &= ~SET_BIT6 -#define clr_LSBFE SPCR &= ~SET_BIT5 -#define clr_MSTR SPCR &= ~SET_BIT4 -#define clr_CPOL SPCR &= ~SET_BIT3 -#define clr_CPHA SPCR &= ~SET_BIT2 -#define clr_SPR1 SPCR &= ~SET_BIT1 -#define clr_SPR0 SPCR &= ~SET_BIT0 - -//**** SPCR2 F3H PAGE1 **** SFRS must set as 1 to modify this register -#define set_SPIS1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;SPCR2|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define set_SPIS0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x00;SPCR2|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -#define clr_SPIS1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x00;SPCR2&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP -#define clr_SPIS0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x00;SPCR2&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP - -//**** SPSR F4H **** -#define set_SPIF SPSR |= SET_BIT7 -#define set_WCOL SPSR |= SET_BIT6 -#define set_SPIOVF SPSR |= SET_BIT5 -#define set_MODF SPSR |= SET_BIT4 -#define set_DISMODF SPSR |= SET_BIT3 - -#define clr_SPIF SPSR &= ~SET_BIT7 -#define clr_WCOL SPSR &= ~SET_BIT6 -#define clr_SPIOVF SPSR &= ~SET_BIT5 -#define clr_MODF SPSR &= ~SET_BIT4 -#define clr_DISMODF SPSR &= ~SET_BIT3 - -//**** SPDR F5H **** - -//**** AINDIDS F6H **** -#define set_P11DIDS AINDIDS |= SET_BIT7 -#define set_P03DIDS AINDIDS |= SET_BIT6 -#define set_P04DIDS AINDIDS |= SET_BIT5 -#define set_P05DIDS AINDIDS |= SET_BIT4 -#define set_P06DIDS AINDIDS |= SET_BIT3 -#define set_P07DIDS AINDIDS |= SET_BIT2 -#define set_P30DIDS AINDIDS |= SET_BIT1 -#define set_P17DIDS AINDIDS |= SET_BIT0 - -#define clr_P11DIDS AINDIDS &= ~SET_BIT7 -#define clr_P03DIDS AINDIDS &= ~SET_BIT6 -#define clr_P04DIDS AINDIDS &= ~SET_BIT5 -#define clr_P05DIDS AINDIDS &= ~SET_BIT4 -#define clr_P06DIDS AINDIDS &= ~SET_BIT3 -#define clr_P07DIDS AINDIDS &= ~SET_BIT2 -#define clr_P30DIDS AINDIDS &= ~SET_BIT1 -#define clr_P17DIDS AINDIDS &= ~SET_BIT0 - -//**** EIPH F7H **** -#define set_PT2H EIPH |= SET_BIT7 -#define set_PSPIH EIPH |= SET_BIT6 -#define set_PFBH EIPH |= SET_BIT5 -#define set_PWDTH EIPH |= SET_BIT4 -#define set_PPWMH EIPH |= SET_BIT3 -#define set_PCAPH EIPH |= SET_BIT2 -#define set_PPIH EIPH |= SET_BIT1 -#define set_PI2CH EIPH |= SET_BIT0 - -#define clr_PT2H EIPH &= ~SET_BIT7 -#define clr_PSPIH EIPH &= ~SET_BIT6 -#define clr_PFBH EIPH &= ~SET_BIT5 -#define clr_PWDTH EIPH &= ~SET_BIT4 -#define clr_PPWMH EIPH &= ~SET_BIT3 -#define clr_PCAPH EIPH &= ~SET_BIT2 -#define clr_PPIH EIPH &= ~SET_BIT1 -#define clr_PI2CH EIPH &= ~SET_BIT0 - -/**** SCON_1 F8H ****/ -#define set_FE_1 FE_1 = 1 -#define set_SM1_1 SM1_1 = 1 -#define set_SM2_1 SM2_1 = 1 -#define set_REN_1 REN_1 = 1 -#define set_TB8_1 TB8_1 = 1 -#define set_RB8_1 RB8_1 = 1 -#define set_TI_1 TI_1 = 1 -#define set_RI_1 RI_1 = 1 - -#define clr_FE_1 FE_1 = 0 -#define clr_SM1_1 SM1_1 = 0 -#define clr_SM2_1 SM2_1 = 0 -#define clr_REN_1 REN_1 = 0 -#define clr_TB8_1 TB8_1 = 0 -#define clr_RB8_1 RB8_1 = 0 -#define clr_TI_1 TI_1 = 0 -#define clr_RI_1 RI_1 = 0 - -//**** PDTEN F9H **** -#define set_PDT45EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|= SET_BIT2 ;EA=BIT_TMP; -#define set_PDT23EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|= SET_BIT1 ;EA=BIT_TMP; -#define set_PDT01EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|= SET_BIT0 ;EA=BIT_TMP; - -#define clr_PDT45EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN &= ~SET_BIT2 ;EA=BIT_TMP; -#define clr_PDT23EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN &= ~SET_BIT1 ;EA=BIT_TMP; -#define clr_PDT01EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN &= ~SET_BIT0 ;EA=BIT_TMP; - -//**** PDTCNT FAH **** - -//**** PMEN FBH **** -#define set_PMEN5 PMEN |= SET_BIT5 -#define set_PMEN4 PMEN |= SET_BIT4 -#define set_PMEN3 PMEN |= SET_BIT3 -#define set_PMEN2 PMEN |= SET_BIT2 -#define set_PMEN1 PMEN |= SET_BIT1 -#define set_PMEN0 PMEN |= SET_BIT0 - -#define clr_PMEN5 PMEN &= ~SET_BIT5 -#define clr_PMEN4 PMEN &= ~SET_BIT4 -#define clr_PMEN3 PMEN &= ~SET_BIT3 -#define clr_PMEN2 PMEN &= ~SET_BIT2 -#define clr_PMEN1 PMEN &= ~SET_BIT1 -#define clr_PMEN0 PMEN &= ~SET_BIT0 - -//**** PMD FCH **** -#define set_PMD7 PMD |= SET_BIT7 -#define set_PMD6 PMD |= SET_BIT6 -#define set_PMD5 PMD |= SET_BIT5 -#define set_PMD4 PMD |= SET_BIT4 -#define set_PMD3 PMD |= SET_BIT3 -#define set_PMD2 PMD |= SET_BIT2 -#define set_PMD1 PMD |= SET_BIT1 -#define set_PMD0 PMD |= SET_BIT0 - -#define clr_PMD7 PMD &= ~SET_BIT7 -#define clr_PMD6 PMD &= ~SET_BIT6 -#define clr_PMD5 PMD &= ~SET_BIT5 -#define clr_PMD4 PMD &= ~SET_BIT4 -#define clr_PMD3 PMD &= ~SET_BIT3 -#define clr_PMD2 PMD &= ~SET_BIT2 -#define clr_PMD1 PMD &= ~SET_BIT1 -#define clr_PMD0 PMD &= ~SET_BIT0 - -//**** EIP1 FEH **** -#define set_PWKT EIP1 |= SET_BIT2 -#define set_PT3 EIP1 |= SET_BIT1 -#define set_PS_1 EIP1 |= SET_BIT0 - -#define clr_PWKT EIP1 &= ~SET_BIT2 -#define clr_PT3 EIP1 &= ~SET_BIT1 -#define clr_PS_1 EIP1 &= ~SET_BIT0 - -//**** EIPH1 FFH **** -#define set_PWKTH EIPH1 |= SET_BIT2 -#define set_PT3H EIPH1 |= SET_BIT1 -#define set_PSH_1 EIPH1 |= SET_BIT0 - -#define clr_PWKTH EIPH1 &= ~SET_BIT2 -#define clr_PT3H EIPH1 &= ~SET_BIT1 -#define clr_PSH_1 EIPH1 &= ~SET_BIT0 - - - -#endif - diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/include.h b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/include.h deleted file mode 100644 index 9106eac87..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/include.h +++ /dev/null @@ -1,33 +0,0 @@ -/************************************************************ -* ProjectName: LT8619C -* FileName: Include.h -* BuildData: 2014-03-27 -* Version£º V1.00 -* Company: Lontium -************************************************************/ - -#ifndef _INCLUDE_H -#define _INCLUDE_H - - -#define _N76E003_ - -#include -#include "N76E003.h" -#include "SFR_Macro.h" -#include "Function_define.h" -#include "string.h" -#include "Delay.h" -#include "stdio.h" -#include "type.h" -#include "Uart0.h" - -#include "main.h" -#include "i2c_master.h" -#include "LT8912B.h" -//#include "interrupt.h" - - - - -#endif \ No newline at end of file diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/main.h b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/main.h deleted file mode 100644 index 8d649075c..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/main.h +++ /dev/null @@ -1,61 +0,0 @@ -/************************************************************ -* ProjectName: LT86104EX -* FileName: main.h -* BuildData: 2013-01-05 -* Version£º V3.20 -* Company: Lontium -************************************************************/ - -#ifndef _MAIN_H -#define _MAIN_H - -#define _uart_debug_ - -//#define _LVDS_Output_ - -#ifdef _LVDS_Output_ - -//#define _LVDS_Bypass_ - -//extern bit LVDS_Output_En; // = 1; // - -extern u16 Panel_Pixel_CLK; // = 4925; // 49.25MHz - -extern u8 PLL_Devider; - -extern u8 LVDS_Map; // = _VESA_; - -extern u8 LVDS_mode; // = _Sync_Mode_; - -extern u8 Color_Depth; // = _8_Bit_Color_; - -extern const u16 Panel_Timing[8]; - -#endif - - -extern u8 MIPI_Lane; // = 2; // 2 lane ; 0 : 4 lane - -extern u8 MIPI_Lane_CH_Swap; - -extern u8 MIPI_Lane_PN_Swap; - - -extern u8 HDMI_DVI_Output; - -extern bit IIS_Format_En; // 1: IIS ; 0 : SPDIF - -extern bit Test_Pattern_En; - -extern bit SDA_Ack; - -extern const u16 MIPI_Timing[6][8]; - -extern void GPIO_Initial( void ); - - -//extern void CLK_Configuration( void ); - - -#endif -/************************************** The End Of File **************************************/ diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/type.h b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/type.h deleted file mode 100644 index 93b34def5..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/type.h +++ /dev/null @@ -1,38 +0,0 @@ - -#ifndef _TYPE_H -#define _TYPE_H - -//Variable Type Definition -typedef char CHAR, *PCHAR ; -typedef unsigned char uchar, *puchar ; -typedef unsigned char UCHAR, *PUCHAR ; -typedef unsigned char byte, *pbyte ; -typedef unsigned char BYTE, *PBYTE ; - -typedef short SHORT, *PSHORT ; -typedef unsigned short ushort, *pushort ; -typedef unsigned short USHORT, *PUSHORT ; -typedef unsigned short word, *pword ; -typedef unsigned short WORD, *PWORD ; - -typedef long LONG, *PLONG ; -typedef unsigned long ulong, *pulong ; -typedef unsigned long ULONG, *PULONG ; -typedef unsigned long dword, *pdword ; -typedef unsigned long DWORD, *PDWORD ; - -typedef unsigned int UINT, uint; -//Public Definition - - -#define HIGH 1 -#define LOW 0 - -#ifndef NULL -#define NULL (void *)0 -#endif - - - - -#endif \ No newline at end of file diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/uart0.h b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/uart0.h deleted file mode 100644 index 6d1138570..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/inc/uart0.h +++ /dev/null @@ -1,25 +0,0 @@ - -#ifndef _UART0_H -#define _UART0_H - -void InitialUART0_Timer1(UINT32 u32Baudrate); //T1M = 1, SMOD = 1 -void InitialUART0_Timer3(UINT32 u32Baudrate); //Timer3 as Baudrate, SMOD=1, Prescale=0 -//void Send_Data_To_UART0(UINT8 c); -//UINT8 Receive_Data_From_UART0(void); -// -//UINT8 UID_BYTE(UINT8 Addr); -//void READ_MCU_UID(void); -//void Debug_printf(unsigned char *str); -//void printByte(u8 U8Data); -//void printByteWithSpace(u8 U8Data); -//void printWord(u16 U16Data); - -extern void printdec_u32(u32 u32_dec); -extern void print(char* fmt, ...); -extern void printhex(int hex); - -#endif - - - - diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/main.c b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/main.c deleted file mode 100644 index c9419ad35..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/main.c +++ /dev/null @@ -1,293 +0,0 @@ -/************************************************************ -* ProjectName: LT8619C -* FileName: Main.c -* BuildData: 2017-04-20 -* Version£º V1.00 -* Company: Lontium -************************************************************/ -#include "include.h" - -u8 MIPI_Lane; // = 2; // 2 lane ; 0 : 4 lane - -u8 MIPI_Lane_CH_Swap; - -u8 MIPI_Lane_PN_Swap; - -u8 HDMI_DVI_Output; // _HDMI_Output_ ; _DVI_Output_ - -bit IIS_Format_En; // 1: IIS ; 0 : SPDIF - -bit Test_Pattern_En; - -// bit LT8912B_IIC_En; - -bit SDA_Ack; - -const u16 MIPI_Timing[6][8] = -{ - //H_act V_act H_total V_total H_BP H_sync V_sync V_BP - { 720, 480, 858, 525, 60, 62, 6, 30 }, // 480P Vesa Timing - { 1024, 768, 1344, 806, 160, 136, 6, 29 }, // 1024x768 - { 1280, 720, 1650, 750, 220, 40, 5, 20 }, // 720P Vesa Timing - - { 1280, 800, 1440, 823, 80, 32, 6, 14 }, // 1280x800 timing - - { 1024, 600, 1344, 635, 140, 20, 3, 20 }, // 1024x600 -// { 1024, 600, 1274, 645, 80, 10, 10, 23 }, // 1024x600 - { 1920, 1080, 2200, 1125, 148, 44, 5, 36 }, // 1080P Vesa Timing -// { 1920, 1200, 2080, 1235, 80, 32, 6, 26 }, // 1920x1200 154MHz Vesa Timing -// { 1280, 480, 1460, 530, 80, 20, 10, 20 }, // 1280x480 -}; - -#ifdef _LVDS_Output_ - -// bit LVDS_Output_En; // = 1; // - -u16 Panel_Pixel_CLK; // = 4925; // 49.25MHz - -u8 PLL_Devider; - -u8 LVDS_Map; // = _VESA_; - -u8 LVDS_mode; // = _Sync_Mode_; - -u8 Color_Depth; // = _8_Bit_Color_; - -// ¸ù¾ÝLVDSÆÁ¹æ¸ñÊéÉèÖÃLVDSÊä³ösµÄÆÁ²Î: -const u16 Panel_Timing[8] = -//H_act V_act H_total V_total H_BP H_sync V_sync V_BP -// {1920, 1080, 2200, 1125, 148, 44, 5, 36};// 1080P Vesa Timing -// {1280, 800, 1440, 823, 80, 32, 6, 14};// 1280x800 - { 1024, 600, 1344, 635, 140, 20, 3, 20 }; // 1024x600 -// { 1024, 600, 1274, 645, 80, 10, 10, 23 }; // 1024x600 -// { 1280, 480, 1460, 530, 80, 20, 10, 20 }; - -#endif - -#ifdef _LT8912B_EVB_ // for 8912B demo board - - -/*********************************************************** - -***********************************************************/ -void GPIO_Initial( void ) -{ - P03_OpenDrain_Mode; // OpenDrain_Mode // 8912 SDA - P04_OpenDrain_Mode; // OpenDrain_Mode // 8912 SCL - P00_OpenDrain_Mode; // 8912 Reset // P03_PushPull_Mode; P03_OpenDrain_Mode - -// P01_Input_Mode; // IRQ - - P13_Input_Mode; - P14_Input_Mode; - -// P11_PushPull_Mode; - -//EA=1; - InitialUART0_Timer1( 115200 ); //UART_INTI - -// Enable_INT_Port0; -// Enable_BIT1_FallEdge_Trig; -// set_EPI; - -//set_EX1; -//set_IT1; -//set_IE1; -// set_EA; -} - -#endif - -#define _LT8912B_RSTN_LOW P00 = 0 -#define _LT8912B_RSTN_High P00 = 1 - -#ifdef _LT8912B_EVB_ // for 8912B demo - - -/*********************************************************** - ****************************/ -void Initstate_LT8912B( void ) -{ -// LT8912_IIC_En = 1; - - I2CADR = 0x92; -} - -#endif - -#ifdef _LT8912B_EVB_ // for 8912B demo - - -/*********************************************************** - -***********************************************************/ -void LT8912B_Reset( void ) -{ - _LT8912B_RSTN_LOW; - Delay_ms( 100 ); - _LT8912B_RSTN_High; - Delay_ms( 100 ); -} - -#endif - - -/*********************************************************** - -***********************************************************/ -void LT8912B_Config( void ) -{ - HDMI_DVI_Output = _HDMI_Output_; // _HDMI_Output_ ; _DVI_Output_ - - IIS_Format_En = _IIS_Output_; // 1: IIS ; 0 : SPDIF - - MIPI_Lane = 4; // 4 lane ; 0 ~ 4 lane - - MIPI_Lane_CH_Swap = _Channel_0123; // _Channel_3210; _Channel_0123 - MIPI_Lane_PN_Swap = _PN_Swap_Dis; // _PN_Swap_En; _PN_Swap_Dis - - Test_Pattern_En = 1; // - -#ifdef _LVDS_Output_ - -// if( LVDS_Output_En ) - { - Panel_Pixel_CLK = 5125; // 51.25MHz - - PLL_Devider = _PLL_Devider_1; // _PLL_Devider_1;_PLL_Devider_2;_PLL_Devider_4;_PLL_Devider_8 - - LVDS_Map = _VESA_; // _VESA_ ; _JEIDA_ - - LVDS_mode = _Sync_Mode_; // _Sync_Mode_ ; _De_Mode_ - - Color_Depth = _8_Bit_Color_; // _8_Bit_Color_ ; _6_Bit_Color_ - } -#endif -} - -/*********************************************************** - -***********************************************************/ -void main( void ) -{ - u8 temp = 0x00; -// CLK_Configuration( ); - GPIO_Initial( ); - - Delay_ms( 200 ); - Delay_ms( 200 ); - Delay_ms( 200 ); - Delay_ms( 200 ); - Delay_ms( 200 ); - - print( "\r\n**********************start*************************" ); - Initstate_LT8912B( ); - LT8912B_Reset( ); - print( "\r\n " ); - print( "\r\n*****************LT8912B reset done*****************" ); - - LT8912B_Config( ); - - videoformat = VESA_1280x800_60; // VESA_1280x800_60 ; - LT812B_Config( ); - print( "\r\n " ); - print( "\r\n****************LT8912B Initial done****************" ); - print( "\r\n " ); - - -/* - if( Test_Pattern_En ) - { - GCMWindow1080P( ); - // GCMWindow1280x480P(); - // GCMWindow720P( ); - // GCMWindow480P( ); - // GCMWindow576P( ); - } - //*/ -#ifdef _LVDS_Output_ - -// if( LVDS_Output_En ) - { - Collpll_Config( ); - LVDS_ScaleRatioConfig( ); - Delay_ms( 300 ); - LvdsPowerUp( ); - } -#endif - - Delay_ms( 200 ); - - while( 1 ) - { -#if 1 - if( temp < 10 ) - { - // temp++; - MIPI_Input_det( ); - - if( Pre_videoformat != videoformat ) - { - Pre_videoformat = videoformat; - if( videoformat != 0xff ) - { -#ifdef _LVDS_Output_ - // if( LVDS_Output_En ) - { - LvdsPowerDown( ); - } -#endif -//* - MIPIDig_Format_Config( ); - DDSConfig( ); - AudioIIsEn( ); - MIPIRxLogicRes( ); - - I2CADR = 0x92; - HDMI_WriteI2C_Byte( 0x70, 0x00 ); // pattern disable - print( "\r\n " ); - print( "\r\nLT8912B HDMI config done..." ); - print( "\r\n " ); -//*/ - // LT812B_Config( ); -#ifdef _LVDS_Output_ -#ifdef _LVDS_Bypass_ - - LVDS_Bypass_Config( ); -#else - Collpll_Config( ); - LVDS_ScaleRatioConfig( ); -#endif - Delay_ms( 300 ); - LvdsPowerUp( ); -#endif - } - //* - else - if( Test_Pattern_En ) - { - GCMWindow1280x800P( ); - -#ifdef _LVDS_Output_ - - videoformat = VESA_1024x600_60; - Collpll_Config( ); - LVDS_ScaleRatioConfig( ); - Delay_ms( 300 ); - LvdsPowerUp( ); - videoformat = 0xff; - #endif - // GCMWindow1280x480P(); - // GCMWindow720P( ); - // GCMWindow480P( ); - // GCMWindow576P( ); - } //*/ - } - - Delay_ms( 1000 ); - } -#endif - } -} - -/************************************** The End Of File **************************************/ diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/LT8912B_EVB.uvgui.HUAWEI b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/LT8912B_EVB.uvgui.HUAWEI deleted file mode 100644 index a9a356299..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/LT8912B_EVB.uvgui.HUAWEI +++ /dev/null @@ -1,1923 +0,0 @@ - - - - -6.1 - -
### uVision Project, (C) Keil Software
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- - - - 0 - 1536 - 864 - - - - - - 1 - 0 - - 100 - 0 - - ..\main.c - 40 - 139 - 149 - 1 - 252 - 0 - - - ..\inc\main.h - 0 - 1 - 12 - 1 - - 0 - - - ..\src\LT8912B.c - 0 - 815 - 821 - 1 - - 0 - - - ..\inc\LT8912B.h - 26 - 73 - 79 - 1 - - 0 - - - ..\src\uart0.c - 0 - 356 - 402 - 1 - - 0 - - - ..\inc\uart0.h - 2 - 1 - 7 - 1 - - 0 - - - ..\inc\Function_Define.h - 21 - 290 - 294 - 1 - - 0 - - - - - diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/LT8912B_EVB.uvopt b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/LT8912B_EVB.uvopt deleted file mode 100644 index 985d23e15..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/LT8912B_EVB.uvopt +++ /dev/null @@ -1,386 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - Target 1 - 0x0 - MCS-51 - - 16000000 - - 1 - 1 - 1 - 0 - 0 - - - 0 - 65535 - 0 - 0 - 0 - - - 120 - 65 - 8 - .\Listings\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 0 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 10 - - - - - - - - - - - BIN\Nuvoton_8051_Keil_uVision_Driver.dll - - - - 0 - Nuvoton_8051_Keil_uVision_Driver - - - - - - 0 - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - Startup - 1 - 0 - 0 - 0 - - 1 - 1 - 2 - 0 - 0 - 0 - .\STARTUP.A51 - STARTUP.A51 - 0 - 0 - - - - - src - 1 - 0 - 0 - 0 - - 2 - 2 - 1 - 0 - 0 - 0 - ..\src\Delay.c - Delay.c - 0 - 0 - - - 2 - 3 - 1 - 0 - 0 - 0 - ..\src\I2C_MASTER.C - I2C_MASTER.C - 0 - 0 - - - 2 - 4 - 1 - 0 - 0 - 0 - ..\src\LT8912B.c - LT8912B.c - 0 - 0 - - - 2 - 5 - 1 - 0 - 0 - 0 - ..\main.c - main.c - 0 - 0 - - - 2 - 6 - 1 - 0 - 0 - 0 - ..\src\uart0.c - uart0.c - 0 - 0 - - - - - inc - 1 - 0 - 0 - 0 - - 3 - 7 - 5 - 0 - 0 - 0 - ..\inc\Delay.h - Delay.h - 0 - 0 - - - 3 - 8 - 5 - 0 - 0 - 0 - ..\inc\Function_Define.h - Function_Define.h - 0 - 0 - - - 3 - 9 - 5 - 0 - 0 - 0 - ..\inc\I2C_Master.h - I2C_Master.h - 0 - 0 - - - 3 - 10 - 5 - 0 - 0 - 0 - ..\inc\include.h - include.h - 0 - 0 - - - 3 - 11 - 5 - 0 - 0 - 0 - ..\inc\LT8912B.h - LT8912B.h - 0 - 0 - - - 3 - 12 - 5 - 0 - 0 - 0 - ..\inc\main.h - main.h - 0 - 0 - - - 3 - 13 - 5 - 0 - 0 - 0 - ..\inc\N76E003.h - N76E003.h - 0 - 0 - - - 3 - 14 - 5 - 0 - 0 - 0 - ..\inc\SFR_Macro.h - SFR_Macro.h - 0 - 0 - - - 3 - 15 - 5 - 0 - 0 - 0 - ..\inc\type.h - type.h - 0 - 0 - - - 3 - 16 - 5 - 0 - 0 - 0 - ..\inc\uart0.h - uart0.h - 0 - 0 - - - - diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/LT8912B_EVB.uvproj b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/LT8912B_EVB.uvproj deleted file mode 100644 index 84d248b2d..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/LT8912B_EVB.uvproj +++ /dev/null @@ -1,463 +0,0 @@ - - - - 1.1 - -
### uVision Project, (C) Keil Software
- - - - Target 1 - 0x0 - MCS-51 - 0 - - - N76E003 - Nuvoton - IRAM(0 - 0xFF) IROM(0 - 0x47FF) XRAM(0 - 0x2FF) CLOCK(16000000) - - "LIB\STARTUP.A51" ("Standard 8051 Startup Code") - - 0 - N76E003.H - - - - - - - - - - - 0 - 0 - - - - Nuvoton\ - Nuvoton\ - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - LT8912B_EVB - 1 - 0 - 1 - 1 - 1 - .\Listings\ - 0 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - 65535 - - - S8051.DLL - - DP51.DLL - - S8051.DLL - - TP51.DLL - - - - - 0 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 10 - - - - - - - - - - - - - - BIN\Nuvoton_8051_Keil_uVision_Driver.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4102 - - 0 - BIN\Nuvoton_8051_Keil_uVision_Driver.dll - "" () - - - src - - 0 - - - - 2 - 0 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0xffff - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x4800 - - - 0 - 0x0 - 0x100 - - - 0 - 0x0 - 0x300 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 1 - 0 - 1 - 3 - 8 - 2 - 1 - 1 - 0 - 0 - - - FOSC_160000 - - ..\inc - - - - 0 - 1 - 0 - 0 - - - - - - - - - 0 - 0 - 1 - 0 - 2 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Startup - - - STARTUP.A51 - 2 - .\STARTUP.A51 - - - - - src - - - Delay.c - 1 - ..\src\Delay.c - - - I2C_MASTER.C - 1 - ..\src\I2C_MASTER.C - - - LT8912B.c - 1 - ..\src\LT8912B.c - - - main.c - 1 - ..\main.c - - - uart0.c - 1 - ..\src\uart0.c - - - - - inc - - - Delay.h - 5 - ..\inc\Delay.h - - - Function_Define.h - 5 - ..\inc\Function_Define.h - - - I2C_Master.h - 5 - ..\inc\I2C_Master.h - - - include.h - 5 - ..\inc\include.h - - - LT8912B.h - 5 - ..\inc\LT8912B.h - - - main.h - 5 - ..\inc\main.h - - - N76E003.h - 5 - ..\inc\N76E003.h - - - SFR_Macro.h - 5 - ..\inc\SFR_Macro.h - - - type.h - 5 - ..\inc\type.h - - - uart0.h - 5 - ..\inc\uart0.h - - - - - - - - diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/Delay.lst b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/Delay.lst deleted file mode 100644 index 048d69dba..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/Delay.lst +++ /dev/null @@ -1,163 +0,0 @@ -C51 COMPILER V9.54 DELAY 06/12/2026 11:01:29 PAGE 1 - - -C51 COMPILER V9.54, COMPILATION OF MODULE DELAY -OBJECT MODULE PLACED IN .\Objects\Delay.obj -COMPILER INVOKED BY: D:\Keil\MDK\download\C51\BIN\C51.EXE ..\src\Delay.c LARGE OPTIMIZE(8,SPEED) BROWSE INCDIR(..\inc) D - -EFINE(FOSC_160000) DEBUG OBJECTEXTEND PRINT(.\Listings\Delay.lst) TABS(2) OBJECT(.\Objects\Delay.obj) - -line level source - - 1 /*-------------------------------------------------------------------------------------------------------- - --*/ - 2 /* - - */ - 3 /* Copyright(c) 2016 Nuvoton Technology Corp. All rights reserved. - - */ - 4 /* - - */ - 5 /*-------------------------------------------------------------------------------------------------------- - --*/ - 6 - 7 //******************************************************************************************************** - -*** - 8 // Nuvoton Technoledge Corp. - 9 // Website: http://www.nuvoton.com - 10 // E-Mail : MicroC-8bit@nuvoton.com - 11 // Date : Apr/21/2016 - 12 //******************************************************************************************************** - -*** - 13 - 14 #include "Include.h" - 15 - 16 bit BIT_TMP; - 17 - 18 - 19 /*********************************************************** - 20 - 21 ***********************************************************/ - 22 void Timer0_Delay100us( UINT32 u32CNT ) - 23 { - 24 1 clr_T0M; //T0M=0, Timer0 Clock = Fsys/12 - 25 1 TMOD |= 0x01; //Timer0 is 16-bit mode - 26 1 set_TR0; //Start Timer0 - 27 1 while( u32CNT != 0 ) - 28 1 { - 29 2 TL0 = LOBYTE( TIMER_DIV12_VALUE_100us ); //Find define in "Function_define.h" "TIMER VALUE" - 30 2 TH0 = HIBYTE( TIMER_DIV12_VALUE_100us ); - 31 2 while( TF0 != 1 ) - 32 2 { - 33 3 ; //Check Timer0 Time-Out Flag - 34 3 } - 35 2 clr_TF0; - 36 2 u32CNT--; - 37 2 } - 38 1 clr_TR0; //Stop Timer0 - 39 1 } - 40 - 41 /*********************************************************** - 42 - 43 ***********************************************************/ - 44 void Timer0_Delay1ms( UINT32 u32CNT ) - 45 { - 46 1 clr_T0M; //T0M=0, Timer0 Clock = Fsys/12 - 47 1 TMOD |= 0x01; //Timer0 is 16-bit mode - C51 COMPILER V9.54 DELAY 06/12/2026 11:01:29 PAGE 2 - - 48 1 set_TR0; //Start Timer0 - 49 1 while( u32CNT != 0 ) - 50 1 { - 51 2 TL0 = LOBYTE( TIMER_DIV12_VALUE_1ms ); //Find define in "Function_define.h" "TIMER VALUE" - 52 2 TH0 = HIBYTE( TIMER_DIV12_VALUE_1ms ); - 53 2 while( TF0 != 1 ) - 54 2 { - 55 3 ; //Check Timer0 Time-Out Flag - 56 3 } - 57 2 clr_TF0; - 58 2 u32CNT--; - 59 2 } - 60 1 clr_TR0; //Stop Timer0 - 61 1 } - 62 - 63 /* - 64 //------------------------------------------------------------------------------ - 65 void Timer1_Delay10ms(UINT32 u32CNT) - 66 { - 67 clr_T1M; //T1M=0, Timer1 Clock = Fsys/12 - 68 TMOD |= 0x10; //Timer1 is 16-bit mode - 69 set_TR1; //Start Timer1 - 70 while (u32CNT != 0) - 71 { - 72 TL1 = LOBYTE(TIMER_DIV12_VALUE_10ms); //Find define in "Function_define.h" "TIMER VALUE" - 73 TH1 = HIBYTE(TIMER_DIV12_VALUE_10ms); - 74 while (TF1 != 1); //Check Timer1 Time-Out Flag - 75 clr_TF1; - 76 u32CNT --; - 77 } - 78 clr_TR1; //Stop Timer1 - 79 } - 80 //------------------------------------------------------------------------------ - 81 void Timer2_Delay500us(UINT32 u32CNT) - 82 { - 83 clr_T2DIV2; //Timer2 Clock = Fsys/4 - 84 clr_T2DIV1; - 85 set_T2DIV0; - 86 set_TR2; //Start Timer2 - 87 while (u32CNT != 0) - 88 { - 89 TL2 = LOBYTE(TIMER_DIV4_VALUE_500us); //Find define in "Function_define.h" "TIMER VALUE" - 90 TH2 = HIBYTE(TIMER_DIV4_VALUE_500us); - 91 while (TF2 != 1); //Check Timer2 Time-Out Flag - 92 clr_TF2; - 93 u32CNT --; - 94 } - 95 clr_TR2; //Stop Timer2 - 96 } - 97 //------------------------------------------------------------------------------ - 98 void Timer3_Delay100ms(UINT32 u32CNT) - 99 { - 100 T3CON = 0x07; //Timer3 Clock = Fsys/128 - 101 set_TR3; //Trigger Timer3 - 102 while (u32CNT != 0) - 103 { - 104 RL3 = LOBYTE(TIMER_DIV128_VALUE_100ms); //Find define in "Function_define.h" "TIMER VALUE" - 105 RH3 = HIBYTE(TIMER_DIV128_VALUE_100ms); - 106 while ((T3CON&SET_BIT4) != SET_BIT4); //Check Timer3 Time-Out Flag - 107 clr_TF3; - 108 u32CNT --; - 109 } - C51 COMPILER V9.54 DELAY 06/12/2026 11:01:29 PAGE 3 - - 110 clr_TR3; //Stop Timer3 - 111 } - 112 //------------------------------------------------------------------------------ - 113 void Timer3_Delay10us(UINT32 u32CNT) - 114 { - 115 T3CON = 0x07; //Timer3 Clock = Fsys/128 - 116 set_TR3; //Trigger Timer3 - 117 while (u32CNT != 0) - 118 { - 119 RL3 = LOBYTE(TIMER_DIV4_VALUE_10us); //Find define in "Function_define.h" "TIMER VALUE" - 120 RH3 = HIBYTE(TIMER_DIV4_VALUE_10us); - 121 while ((T3CON&SET_BIT4) != SET_BIT4); //Check Timer3 Time-Out Flag - 122 clr_TF3; - 123 u32CNT --; - 124 } - 125 clr_TR3; //Stop Timer3 - 126 } - 127 //*/ - 128 - - -MODULE INFORMATION: STATIC OVERLAYABLE - CODE SIZE = 178 ---- - CONSTANT SIZE = ---- ---- - XDATA SIZE = ---- 8 - PDATA SIZE = ---- ---- - DATA SIZE = ---- ---- - IDATA SIZE = ---- ---- - BIT SIZE = 1 ---- -END OF MODULE INFORMATION. - - -C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/I2C_MASTER.lst b/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/I2C_MASTER.lst deleted file mode 100644 index be4e7626f..000000000 --- a/HDMI/LT8912B/LT8912B_MIPI_to_HDMI_V1.00_20200815_Ok_N76E003/sourcecode/pro/Listings/I2C_MASTER.lst +++ /dev/null @@ -1,294 +0,0 @@ -C51 COMPILER V9.54 I2C_MASTER 06/12/2026 11:01:29 PAGE 1 - - -C51 COMPILER V9.54, COMPILATION OF MODULE I2C_MASTER -OBJECT MODULE PLACED IN .\Objects\I2C_MASTER.obj -COMPILER INVOKED BY: D:\Keil\MDK\download\C51\BIN\C51.EXE ..\src\I2C_MASTER.C LARGE OPTIMIZE(8,SPEED) BROWSE INCDIR(..\i - -nc) DEFINE(FOSC_160000) DEBUG OBJECTEXTEND PRINT(.\Listings\I2C_MASTER.lst) TABS(2) OBJECT(.\Objects\I2C_MASTER.obj) - -line level source - - 1 /************************************************************ - 2 * ProjectName: LT8522EX - 3 * FileName: lt8522ex.c - 4 * BuildData: 2014-03-27 - 5 * Version£º V1.00 - 6 * Company: Lontium - 7 ************************************************************/ - 8 - 9 #include "include.h" - 10 - 11 //bit FLAG_I2C_ERROR; - 12 bit ack; - 13 u8 I2CADR = 0x90; - 14 - 15 void Delay_ms( u16 mscount ) - 16 { - 17 1 u16 i, x; - 18 1 for( i = 0; i < mscount; i++ ) - 19 1 { - 20 2 for( x = 0; x < 2000; x++ ) - 21 2 { - 22 3 ; - 23 3 } - 24 2 // IWDG_ReloadCounter(); - 25 2 } - 26 1 } - 27 - 28 #define SCL_H P04=1 - 29 #define SCL_L P04=0 - 30 - 31 #define SDA_H P03=1 - 32 #define SDA_L P03=0 - 33 - 34 #define I2C_SDA_READ P03 - 35 - 36 static void I2C_Delay_us(u8 uscount) - 37 { - 38 1 u8 x; - 39 1 for(x=0; x